diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v index 16f3d92..8f463ff 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v @@ -101,6 +101,7 @@ module mkAluDispToRegFifo(CLK, RDY_specUpdate_incorrectSpeculation; // inlined wires + wire [11 : 0] m_m_specBits_0_lat_1$wget; wire m_m_valid_0_lat_0$whas; // register m_m_row_0 @@ -161,12 +162,12 @@ module mkAluDispToRegFifo(CLK, wire MUX_m_m_valid_0_dummy2_0$write_1__SEL_1; // remaining internal signals - reg [20 : 0] CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q5, - CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q2; - reg [11 : 0] CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q6, - CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q3; - reg [2 : 0] CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q4, - CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q1; + reg [20 : 0] CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q2, + CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q5; + reg [11 : 0] CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q3, + CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q6; + reg [2 : 0] CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q1, + CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q4; wire [11 : 0] IF_m_m_specBits_0_dummy2_0_read__86_AND_m_m_sp_ETC___d289, IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13, sb__h10633, @@ -192,9 +193,9 @@ module mkAluDispToRegFifo(CLK, // value method first assign first = { m_m_row_0[145:141], - CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q2, + CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q5, m_m_row_0[119], - CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q3, + CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q6, m_m_row_0[106:0], IF_m_m_specBits_0_dummy2_0_read__86_AND_m_m_sp_ETC___d289 } ; assign RDY_first = RDY_deq ; @@ -264,13 +265,15 @@ module mkAluDispToRegFifo(CLK, // inlined wires assign m_m_valid_0_lat_0$whas = MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ; + assign m_m_specBits_0_lat_1$wget = + sb__h10633 & specUpdate_correctSpeculation_mask ; // register m_m_row_0 assign m_m_row_0$D_IN = { enq_x[157:153], - CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q5, + CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q2, enq_x[131], - CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q6, + CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q3, enq_x[118:12] } ; assign m_m_row_0$EN = EN_enq ; @@ -326,101 +329,30 @@ module mkAluDispToRegFifo(CLK, m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 : 12'd0 ; - assign upd__h2327 = sb__h10633 & specUpdate_correctSpeculation_mask ; - always@(m_m_row_0) - begin - case (m_m_row_0[123:121]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q1 = - m_m_row_0[123:121]; - default: CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q1 = 3'd7; - endcase - end - always@(m_m_row_0 or CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q1) - begin - case (m_m_row_0[140:138]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q2 = - m_m_row_0[140:120]; - 3'd4: - CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q2 = - { m_m_row_0[140:138], - 9'h0AA, - m_m_row_0[128:124], - CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q1, - m_m_row_0[120] }; - default: CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q2 = - 21'd1485482; - endcase - end - always@(m_m_row_0) - begin - case (m_m_row_0[118:107]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q3 = - m_m_row_0[118:107]; - default: CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q3 = - 12'd2303; - endcase - end + assign upd__h2327 = m_m_specBits_0_lat_1$wget ; always@(enq_x) begin case (enq_x[135:133]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q4 = + CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q1 = enq_x[135:133]; - default: CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q4 = 3'd7; + default: CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q1 = 3'd7; endcase end - always@(enq_x or CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q4) + always@(enq_x or CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q1) begin case (enq_x[152:150]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q5 = + CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q2 = enq_x[152:132]; 3'd4: - CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q5 = + CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q2 = { enq_x[152:150], 9'h0AA, enq_x[140:136], - CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q4, + CASE_enq_x_BITS_135_TO_133_0_enq_x_BITS_135_TO_ETC__q1, enq_x[132] }; - default: CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q5 = + default: CASE_enq_x_BITS_152_TO_150_0_enq_x_BITS_152_TO_ETC__q2 = 21'd1485482; endcase end @@ -463,9 +395,80 @@ module mkAluDispToRegFifo(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q6 = + CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q3 = enq_x[130:119]; - default: CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q6 = + default: CASE_enq_x_BITS_130_TO_119_1_enq_x_BITS_130_TO_ETC__q3 = + 12'd2303; + endcase + end + always@(m_m_row_0) + begin + case (m_m_row_0[123:121]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q4 = + m_m_row_0[123:121]; + default: CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q4 = 3'd7; + endcase + end + always@(m_m_row_0 or CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q4) + begin + case (m_m_row_0[140:138]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q5 = + m_m_row_0[140:120]; + 3'd4: + CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q5 = + { m_m_row_0[140:138], + 9'h0AA, + m_m_row_0[128:124], + CASE_m_m_row_0_BITS_123_TO_121_0_m_m_row_0_BIT_ETC__q4, + m_m_row_0[120] }; + default: CASE_m_m_row_0_BITS_140_TO_138_0_m_m_row_0_BIT_ETC__q5 = + 21'd1485482; + endcase + end + always@(m_m_row_0) + begin + case (m_m_row_0[118:107]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd2048, + 12'd2049, + 12'd2816, + 12'd2818, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q6 = + m_m_row_0[118:107]; + default: CASE_m_m_row_0_BITS_118_TO_107_1_m_m_row_0_BIT_ETC__q6 = 12'd2303; endcase end diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v index e4d7821..bbb6fa8 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v @@ -98,6 +98,7 @@ module mkAluExeToFinFifo(CLK, RDY_specUpdate_incorrectSpeculation; // inlined wires + wire [11 : 0] m_m_specBits_0_lat_1$wget; wire m_m_valid_0_lat_1$whas; // register m_m_row_0 @@ -162,7 +163,9 @@ module mkAluExeToFinFifo(CLK, IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13, sb__h6821, upd__h2327; - wire IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6; + wire IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6, + _dand1m_m_valid_0_dummy2_1$EN_write, + _dand1m_m_valid_0_lat_1$EN_wset; // action method enq assign RDY_enq = !m_m_valid_0_dummy2_1$Q_OUT || EN_deq || !m_m_valid_0_rl ; @@ -246,8 +249,9 @@ module mkAluExeToFinFifo(CLK, IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60[specUpdate_incorrectSpeculation_kill_tag]) ; // inlined wires - assign m_m_valid_0_lat_1$whas = - MUX_m_m_valid_0_dummy2_1$write_1__SEL_1 || EN_enq ; + assign m_m_valid_0_lat_1$whas = _dand1m_m_valid_0_lat_1$EN_wset || EN_enq ; + assign m_m_specBits_0_lat_1$wget = + sb__h6821 & specUpdate_correctSpeculation_mask ; // register m_m_row_0 assign m_m_row_0$D_IN = enq_x[325:12] ; @@ -290,7 +294,7 @@ module mkAluExeToFinFifo(CLK, // submodule m_m_valid_0_dummy2_1 assign m_m_valid_0_dummy2_1$D_IN = 1'd1 ; assign m_m_valid_0_dummy2_1$EN = - MUX_m_m_valid_0_dummy2_1$write_1__SEL_1 || EN_enq ; + _dand1m_m_valid_0_dummy2_1$EN_write || EN_enq ; // remaining internal signals assign IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60 = @@ -302,11 +306,19 @@ module mkAluExeToFinFifo(CLK, EN_enq ? enq_x[11:0] : m_m_specBits_0_rl ; assign IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 = !EN_deq && m_m_valid_0_rl ; + assign _dand1m_m_valid_0_dummy2_1$EN_write = + EN_specUpdate_incorrectSpeculation && + (specUpdate_incorrectSpeculation_kill_all || + IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60[specUpdate_incorrectSpeculation_kill_tag]) ; + assign _dand1m_m_valid_0_lat_1$EN_wset = + EN_specUpdate_incorrectSpeculation && + (specUpdate_incorrectSpeculation_kill_all || + IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60[specUpdate_incorrectSpeculation_kill_tag]) ; assign sb__h6821 = m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 : 12'd0 ; - assign upd__h2327 = sb__h6821 & specUpdate_correctSpeculation_mask ; + assign upd__h2327 = m_m_specBits_0_lat_1$wget ; // handling of inlined registers diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v index 39854c0..e5da22d 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v @@ -101,6 +101,7 @@ module mkAluRegToExeFifo(CLK, RDY_specUpdate_incorrectSpeculation; // inlined wires + wire [11 : 0] m_m_specBits_0_lat_1$wget; wire m_m_valid_0_lat_0$whas; // register m_m_row_0 @@ -264,6 +265,8 @@ module mkAluRegToExeFifo(CLK, // inlined wires assign m_m_valid_0_lat_0$whas = MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ; + assign m_m_specBits_0_lat_1$wget = + sb__h10270 & specUpdate_correctSpeculation_mask ; // register m_m_row_0 assign m_m_row_0$D_IN = @@ -326,7 +329,7 @@ module mkAluRegToExeFifo(CLK, m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 : 12'd0 ; - assign upd__h2327 = sb__h10270 & specUpdate_correctSpeculation_mask ; + assign upd__h2327 = m_m_specBits_0_lat_1$wget ; always@(enq_x) begin case (enq_x[399:397]) diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index ef618b7..8ca14e8 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -3990,7 +3990,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; - wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, + wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; wire MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, @@ -4038,27 +4038,21 @@ module mkCore(CLK, MUX_coreFix_trainBPQ_1$enq_1__SEL_1, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2, - MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_1, + MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2, MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1, MUX_csrf_debug_int_pend$write_1__SEL_1, MUX_csrf_external_int_pend_vec_1$write_1__SEL_1, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fs_reg$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_1, - MUX_csrf_ie_vec_1$write_1__SEL_2, - MUX_csrf_ie_vec_1$write_1__VAL_1, + MUX_csrf_ie_vec_1$write_1__VAL_2, MUX_csrf_ie_vec_3$write_1__SEL_1, - MUX_csrf_ie_vec_3$write_1__SEL_2, - MUX_csrf_ie_vec_3$write_1__VAL_1, - MUX_csrf_mpp_reg$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__VAL_1, - MUX_csrf_prev_ie_vec_3$write_1__SEL_1, - MUX_csrf_prev_ie_vec_3$write_1__VAL_1, + MUX_csrf_ie_vec_3$write_1__VAL_2, + MUX_csrf_prev_ie_vec_1$write_1__VAL_2, + MUX_csrf_prev_ie_vec_3$write_1__VAL_2, MUX_csrf_prv_reg$write_1__SEL_1, MUX_csrf_software_int_pend_vec_3$write_1__VAL_2, - MUX_csrf_spp_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__VAL_1, + MUX_csrf_spp_reg$write_1__VAL_2, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_flush_reservation$write_1__SEL_1, @@ -4102,33 +4096,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10043, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968, - addr__h293334, - curData__h194025, - rVal1__h614264, + addr__h293335, + curData__h194026, + rVal1__h614263, rVal1__h638559, - trap_val__h703302, - x__h199068; + trap_val__h705462, + x__h199069; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q209, - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q210, - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q211, - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q212, - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q197, - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q198, - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q199, - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q200, - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q201, - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q202, - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q213, - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q214, - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q215, - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q216, - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q217, - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q218, - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207, - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208, + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q209, + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q210, + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q211, + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q212, + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q197, + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q198, + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q201, + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q202, + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q199, + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q200, + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q213, + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q214, + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q215, + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q216, + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q217, + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q218, + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q207, + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10693, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10738, @@ -4140,45 +4134,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9975; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q75, - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q76, - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q79, - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q80, - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q81, - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q82, - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q112, - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q113, - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q42, - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q43, - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q110, - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q111, - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q40, - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q41, - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q114, - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q115, - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q44, - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q45, - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q117, - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q118, - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46, - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47, - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q77, - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q78, - _theResult___fst_sfd__h349436, - _theResult___fst_sfd__h358159, - _theResult___fst_sfd__h366741, - _theResult___fst_sfd__h375925, - _theResult___fst_sfd__h384561, - _theResult___fst_sfd__h395128, - _theResult___fst_sfd__h403849, - _theResult___fst_sfd__h412431, - _theResult___fst_sfd__h421615, - _theResult___fst_sfd__h430251, - _theResult___fst_sfd__h440816, - _theResult___fst_sfd__h449537, - _theResult___fst_sfd__h458119, - _theResult___fst_sfd__h467303, - _theResult___fst_sfd__h475939; + reg [22 : 0] CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q75, + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q76, + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q79, + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q80, + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q81, + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q82, + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q112, + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q113, + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q42, + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q43, + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q110, + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q111, + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q40, + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q41, + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q114, + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q115, + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q44, + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q45, + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q116, + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q117, + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q46, + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q47, + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q77, + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q78, + _theResult___fst_sfd__h349435, + _theResult___fst_sfd__h358158, + _theResult___fst_sfd__h366740, + _theResult___fst_sfd__h375924, + _theResult___fst_sfd__h384560, + _theResult___fst_sfd__h395127, + _theResult___fst_sfd__h403848, + _theResult___fst_sfd__h412430, + _theResult___fst_sfd__h421614, + _theResult___fst_sfd__h430250, + _theResult___fst_sfd__h440815, + _theResult___fst_sfd__h449536, + _theResult___fst_sfd__h458118, + _theResult___fst_sfd__h467302, + _theResult___fst_sfd__h475938; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, @@ -4188,7 +4182,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280, IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529; + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417; reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272, @@ -4197,29 +4191,29 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275, - CASE_fetchStagepipelines_0_first_BITS_172_TO__ETC__q225, - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228; + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228, + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035; reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q203, - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q204, - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205, - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206, - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q175, - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q176, - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q177, - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q178, - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q179, - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q180, - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q152, - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q153, - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181, - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182, - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183, - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184, - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q135, - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q136, + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q203, + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q204, + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q205, + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q206, + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q175, + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q176, + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q177, + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q178, + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q179, + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q180, + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q152, + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q153, + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q181, + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q182, + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q183, + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q184, + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q135, + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10598, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10636, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10667, @@ -4229,66 +4223,66 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9835, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904; - reg [7 : 0] CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q60, - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q61, - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q68, - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q69, - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q73, - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q74, - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q97, - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q98, - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q27, - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q28, - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q95, - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q96, - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q25, - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q26, - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q103, - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q104, - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q33, - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q34, - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q108, - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q109, - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q38, - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q39, - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q62, - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q63, + reg [7 : 0] CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q60, + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q61, + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q68, + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q69, + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q73, + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q74, + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q97, + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q98, + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q27, + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q28, + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q95, + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q96, + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q25, + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q26, + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q103, + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q104, + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q33, + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q34, + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q108, + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q109, + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q38, + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q39, + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q62, + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q63, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430, - _theResult___fst_exp__h349435, - _theResult___fst_exp__h358158, - _theResult___fst_exp__h366740, - _theResult___fst_exp__h375924, - _theResult___fst_exp__h384560, - _theResult___fst_exp__h395127, - _theResult___fst_exp__h403848, - _theResult___fst_exp__h412430, - _theResult___fst_exp__h421614, - _theResult___fst_exp__h430250, - _theResult___fst_exp__h440815, - _theResult___fst_exp__h449536, - _theResult___fst_exp__h458118, - _theResult___fst_exp__h467302, - _theResult___fst_exp__h475938; + _theResult___fst_exp__h349434, + _theResult___fst_exp__h358157, + _theResult___fst_exp__h366739, + _theResult___fst_exp__h375923, + _theResult___fst_exp__h384559, + _theResult___fst_exp__h395126, + _theResult___fst_exp__h403847, + _theResult___fst_exp__h412429, + _theResult___fst_exp__h421613, + _theResult___fst_exp__h430249, + _theResult___fst_exp__h440814, + _theResult___fst_exp__h449535, + _theResult___fst_exp__h458117, + _theResult___fst_exp__h467301, + _theResult___fst_exp__h475937; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263, - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14009, - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14168; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14101, + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14263; reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863__ETC__q227, + CASE_checkForException_3069_BITS_3_TO_0_0_chec_ETC__q226, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14, CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261, - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14012, - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139, - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14169, - i__h702286, - i__h702446; + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14104, + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174, + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14264, + i__h704446, + i__h704606; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4299,11 +4293,11 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q226, + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10809, - x__h289113, - x__h294883; + x__h289114, + x__h294884; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -4331,50 +4325,50 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, CASE_fetchStagepipelines_0_canDeq_AND_NOT_fet_ETC__q234, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard03862_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, - CASE_guard03862_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, - CASE_guard06911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard12792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, - CASE_guard12792_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, - CASE_guard15980_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard21628_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, - CASE_guard21628_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, - CASE_guard36400_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard36400_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard40843_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119, - CASE_guard40843_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q116, - CASE_guard45712_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard49463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard49550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, - CASE_guard49550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, - CASE_guard54781_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard58172_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, - CASE_guard58172_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, - CASE_guard58480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, - CASE_guard58480_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, - CASE_guard67102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard67102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard67316_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, - CASE_guard67316_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, - CASE_guard75601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard75601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard75938_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, - CASE_guard75938_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, - CASE_guard84913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard84913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard93982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard93982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard95155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, - CASE_guard95155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, - CASE_guard97599_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k69941_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_guard03861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, + CASE_guard03861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, + CASE_guard06910_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard12791_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, + CASE_guard12791_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, + CASE_guard15979_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard21627_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, + CASE_guard21627_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, + CASE_guard36399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard36399_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard40842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, + CASE_guard40842_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard45711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard45711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard49462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard49462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard49549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, + CASE_guard49549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, + CASE_guard54780_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard54780_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard58171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, + CASE_guard58171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, + CASE_guard58479_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, + CASE_guard58479_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, + CASE_guard67101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard67101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard67315_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, + CASE_guard67315_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, + CASE_guard75600_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard75600_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard75937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, + CASE_guard75937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, + CASE_guard84912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard84912_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard93981_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard93981_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard95154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, + CASE_guard95154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, + CASE_guard97598_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_k71298_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4412,31 +4406,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11114, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14003, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14006, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13414, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13469, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13730, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13751, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13768, + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469, + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524, + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14095, + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14098, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13473, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13529, IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13822, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13836, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13843, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13912, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13923, - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14166, - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14167, - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779, - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13909, - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13934, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13870, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398, - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13841, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13858, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13911, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13913, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13927, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13934, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14003, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14014, + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14261, + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14262, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14000, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14025, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13961, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457, + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2538, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549, @@ -4445,21 +4439,21 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15071; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15164; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15062; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15155; wire [321 : 0] basicExec___d12049, basicExec___d12686; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15053, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15146, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11168, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11181, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11174; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023; - wire [127 : 0] b__h606909, b__h606985, b__h607086, b__h607098, x__h607928; + wire [127 : 0] b__h606908, b__h606984, b__h607085, b__h607097, x__h607927; wire [68 : 0] execFpuSimple___d11148; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598; @@ -4492,162 +4486,162 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14868, - _theResult___fst__h607309, - _theResult___snd__h607310, - a___1__h606923, - a___1__h607314, - a__h606761, + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d14961, + _theResult___fst__h607308, + _theResult___snd__h607309, + a___1__h606922, + a___1__h607313, + a__h606760, amoExec___d882, - b___1__h606924, - b___1__h607375, - b__h606762, - base__h704873, - base__h705076, - data___1__h478473, - data___1__h479403, - data__h477961, - data__h478891, - fallthrough_pc__h666996, - fallthrough_pc__h681798, - fcsr_csr__read__h614542, - fflags_csr__read__h614517, - frm_csr__read__h614528, - mcause_csr__read__h616189, - mcounteren_csr__read__h615934, - medeleg_csr__read__h615534, - mideleg_csr__read__h615629, - mie_csr__read__h615760, - mip_csr__read__h616429, - mstatus_csr__read__h615386, - mtvec_csr__read__h615842, - n___1__h200471, - n__h195563, + b___1__h606923, + b___1__h607374, + b__h606761, + base__h707033, + base__h707236, + data___1__h478472, + data___1__h479402, + data__h477960, + data__h478890, + fallthrough_pc__h667687, + fallthrough_pc__h683150, + fcsr_csr__read__h614541, + fflags_csr__read__h614516, + frm_csr__read__h614527, + mcause_csr__read__h616188, + mcounteren_csr__read__h615933, + medeleg_csr__read__h615533, + mideleg_csr__read__h615628, + mie_csr__read__h615759, + mip_csr__read__h616428, + mstatus_csr__read__h615385, + mtvec_csr__read__h615841, + n___1__h200472, + n__h195564, n__read__h6134, - n__read__h616533, - n__read__h616724, - n__read__h713751, - next_pc__h712992, - q___1__h479478, - q__h607919, - rVal1__h485840, - rVal2__h485841, - r___1__h479505, - r__h607920, - res_data__h341240, - res_data__h341245, - res_data__h386935, - res_data__h386940, - res_data__h432623, - res_data__h432628, - resp_addr__h295349, - rob_deqPort_0_deq_data__4241_BITS_282_TO_219_4_ETC___d14727, + n__read__h616532, + n__read__h616723, + n__read__h715911, + next_pc__h715152, + q___1__h479477, + q__h607918, + rVal1__h485839, + rVal2__h485840, + r___1__h479504, + r__h607919, + res_data__h341239, + res_data__h341244, + res_data__h386934, + res_data__h386939, + res_data__h432622, + res_data__h432627, + resp_addr__h295350, + rob_deqPort_0_deq_data__4334_BITS_282_TO_219_4_ETC___d14820, robdeqPort_0_deq_data_BITS_95_TO_32__q262, - satp_csr__read__h615243, - scause_csr__read__h615041, - scounteren_csr__read__h614903, - shiftData__h184331, - sie_csr__read__h614807, - sip_csr__read__h615180, - sstatus_csr__read__h614738, - stvec_csr__read__h614850, + satp_csr__read__h615242, + scause_csr__read__h615040, + scounteren_csr__read__h614902, + shiftData__h184332, + sie_csr__read__h614806, + sip_csr__read__h615179, + sstatus_csr__read__h614737, + stvec_csr__read__h614849, upd__h3639, upd__h4956, - v__h613035, + v__h613034, v__h637485, - vaddr__h184326, - x__h154751, - x__h158298, - x__h161112, - x__h162960, + vaddr__h184327, + x__h154750, + x__h158297, + x__h161111, + x__h162959, x__h17672, - x__h184238, x__h184239, + x__h184240, x__h20210, - x__h290558, - x__h292412, + x__h290559, + x__h292413, x__h45579, x__h48115, + x__h485745, x__h485746, x__h485747, - x__h485748, - x__h607298, - x__h621537, + x__h607297, x__h621538, + x__h621539, x__h643521, x__h643522, - x__h698600, - x_addr__h317446, - x_quotient__h478657, - x_reg_ifc__read__h614647, - x_remainder__h478658, - y__h624307, + x__h700760, + x_addr__h317447, + x_quotient__h478656, + x_reg_ifc__read__h614646, + x_remainder__h478657, + y__h624308, y__h645998, - y__h716923, - y_avValue__h183366, - y_avValue__h184085, - y_avValue__h482809, - y_avValue__h483530, - y_avValue__h484245, - y_avValue__h614207, - y_avValue__h619579, + y__h719083, + y_avValue__h183367, + y_avValue__h184086, + y_avValue__h482808, + y_avValue__h483529, + y_avValue__h484244, + y_avValue__h614206, + y_avValue__h619580, y_avValue__h638504, y_avValue__h641573, - y_avValue__h703149, - y_avValue__h704910, - y_avValue_snd_snd_snd_snd_snd__h716323, - y_avValue_snd_snd_snd_snd_snd__h716976, - y_avValue_snd_snd_snd_snd_snd__h717005; + y_avValue__h705309, + y_avValue__h707070, + y_avValue_snd_snd_snd_snd_snd__h718483, + y_avValue_snd_snd_snd_snd_snd__h719136, + y_avValue_snd_snd_snd_snd_snd__h719165; wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10746, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9983, - r1__read__h617231, - r1__read__h617635, - r1__read__h618165, - r1__read__h618170, - r1__read__h618189, - r1__read__h618442, - r1__read__h618618, - r1__read__h618736, - r1__read__h618741, - r1__read__h618760; - wire [61 : 0] r1__read__h617233, - r1__read__h617637, - r1__read__h618172, - r1__read__h618191, - r1__read__h618444, - r1__read__h618594, - r1__read__h618620, - r1__read__h618743, - r1__read__h618762; - wire [60 : 0] r1__read__h618446, - r1__read__h618596, - r1__read__h618622, - r1__read__h618764; - wire [59 : 0] r1__read__h617235, - r1__read__h617639, - r1__read__h618183, - r1__read__h618193, - r1__read__h618448, - r1__read__h618624, - r1__read__h618754, - r1__read__h618766; - wire [58 : 0] r1__read__h617237, - r1__read__h617641, - r1__read__h618195, - r1__read__h618450, - r1__read__h618626, - r1__read__h618768; + r1__read__h617230, + r1__read__h617634, + r1__read__h618164, + r1__read__h618169, + r1__read__h618188, + r1__read__h618441, + r1__read__h618619, + r1__read__h618737, + r1__read__h618742, + r1__read__h618761; + wire [61 : 0] r1__read__h617232, + r1__read__h617636, + r1__read__h618171, + r1__read__h618190, + r1__read__h618443, + r1__read__h618595, + r1__read__h618621, + r1__read__h618744, + r1__read__h618763; + wire [60 : 0] r1__read__h618445, + r1__read__h618597, + r1__read__h618623, + r1__read__h618765; + wire [59 : 0] r1__read__h617234, + r1__read__h617638, + r1__read__h618182, + r1__read__h618192, + r1__read__h618447, + r1__read__h618625, + r1__read__h618755, + r1__read__h618767; + wire [58 : 0] r1__read__h617236, + r1__read__h617640, + r1__read__h618194, + r1__read__h618449, + r1__read__h618627, + r1__read__h618769; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, - r1__read__h617239, - r1__read__h617643, - r1__read__h618197, - r1__read__h618452, - r1__read__h618598, - r1__read__h618628, - r1__read__h618770, - y__h257156; + r1__read__h617238, + r1__read__h617642, + r1__read__h618196, + r1__read__h618451, + r1__read__h618599, + r1__read__h618629, + r1__read__h618771, + y__h257157; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91, @@ -4675,187 +4669,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10232, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8759, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9469, - _theResult____h349453, - _theResult____h367092, - _theResult____h395145, - _theResult____h412782, - _theResult____h440833, - _theResult____h458470, - _theResult____h506901, - _theResult____h545702, - _theResult____h584903, - _theResult___snd__h357575, - _theResult___snd__h357586, - _theResult___snd__h357588, - _theResult___snd__h357598, - _theResult___snd__h357604, - _theResult___snd__h357627, - _theResult___snd__h366171, - _theResult___snd__h366173, - _theResult___snd__h366180, - _theResult___snd__h366186, - _theResult___snd__h366209, - _theResult___snd__h375341, - _theResult___snd__h375352, - _theResult___snd__h375354, - _theResult___snd__h375364, - _theResult___snd__h375370, - _theResult___snd__h375393, - _theResult___snd__h383961, - _theResult___snd__h383975, - _theResult___snd__h383981, - _theResult___snd__h383999, - _theResult___snd__h403265, - _theResult___snd__h403276, - _theResult___snd__h403278, - _theResult___snd__h403288, - _theResult___snd__h403294, - _theResult___snd__h403317, - _theResult___snd__h411861, - _theResult___snd__h411863, - _theResult___snd__h411870, - _theResult___snd__h411876, - _theResult___snd__h411899, - _theResult___snd__h421031, - _theResult___snd__h421042, - _theResult___snd__h421044, - _theResult___snd__h421054, - _theResult___snd__h421060, - _theResult___snd__h421083, - _theResult___snd__h429651, - _theResult___snd__h429665, - _theResult___snd__h429671, - _theResult___snd__h429689, - _theResult___snd__h448953, - _theResult___snd__h448964, - _theResult___snd__h448966, - _theResult___snd__h448976, - _theResult___snd__h448982, - _theResult___snd__h449005, - _theResult___snd__h457549, - _theResult___snd__h457551, - _theResult___snd__h457558, - _theResult___snd__h457564, - _theResult___snd__h457587, - _theResult___snd__h466719, - _theResult___snd__h466730, - _theResult___snd__h466732, - _theResult___snd__h466742, - _theResult___snd__h466748, - _theResult___snd__h466771, - _theResult___snd__h475339, - _theResult___snd__h475353, - _theResult___snd__h475359, - _theResult___snd__h475377, - _theResult___snd__h505511, - _theResult___snd__h505513, - _theResult___snd__h505520, - _theResult___snd__h505526, - _theResult___snd__h505549, - _theResult___snd__h515148, - _theResult___snd__h515159, - _theResult___snd__h515161, - _theResult___snd__h515171, - _theResult___snd__h515177, - _theResult___snd__h515200, - _theResult___snd__h523916, - _theResult___snd__h523930, - _theResult___snd__h523936, - _theResult___snd__h523954, - _theResult___snd__h544312, - _theResult___snd__h544314, - _theResult___snd__h544321, - _theResult___snd__h544327, - _theResult___snd__h544350, - _theResult___snd__h553949, - _theResult___snd__h553960, - _theResult___snd__h553962, - _theResult___snd__h553972, - _theResult___snd__h553978, - _theResult___snd__h554001, - _theResult___snd__h562717, - _theResult___snd__h562731, - _theResult___snd__h562737, - _theResult___snd__h562755, - _theResult___snd__h583513, - _theResult___snd__h583515, - _theResult___snd__h583522, - _theResult___snd__h583528, - _theResult___snd__h583551, - _theResult___snd__h593150, - _theResult___snd__h593161, - _theResult___snd__h593163, - _theResult___snd__h593173, - _theResult___snd__h593179, - _theResult___snd__h593202, - _theResult___snd__h601918, - _theResult___snd__h601932, - _theResult___snd__h601938, - _theResult___snd__h601956, - r1__read__h618454, - r1__read__h618600, - r1__read__h618630, - r1__read__h618772, - result__h367705, - result__h413395, - result__h459083, - result__h507514, - result__h546315, - result__h585516, - sfd__h341848, - sfd__h387543, - sfd__h433231, - sfd__h486559, - sfd__h525501, - sfd__h564702, - sfdin__h357558, - sfdin__h375324, - sfdin__h403248, - sfdin__h421014, - sfdin__h448936, - sfdin__h466702, - sfdin__h515131, - sfdin__h553932, - sfdin__h593133, - x__h367802, - x__h413492, - x__h459180, - x__h507609, - x__h546410, - x__h585611; - wire [55 : 0] r1__read__h617241, - r1__read__h617645, - r1__read__h618199, - r1__read__h618456, - r1__read__h618632, - r1__read__h618774; - wire [54 : 0] r1__read__h617243, - r1__read__h617647, - r1__read__h618201, - r1__read__h618458, - r1__read__h618634, - r1__read__h618776; - wire [53 : 0] r1__read__h618577, - r1__read__h618602, - r1__read__h618636, - r1__read__h618778, - sfd__h505578, - sfd__h515229, - sfd__h523989, - sfd__h544379, - sfd__h554030, - sfd__h562790, - sfd__h583580, - sfd__h593231, - sfd__h601991, - value__h350075, - value__h395765, - value__h441453; - wire [52 : 0] r1__read__h618460, - r1__read__h618579, - r1__read__h618604, - r1__read__h618638, - r1__read__h618780; + _theResult____h349452, + _theResult____h367091, + _theResult____h395144, + _theResult____h412781, + _theResult____h440832, + _theResult____h458469, + _theResult____h506900, + _theResult____h545701, + _theResult____h584902, + _theResult___snd__h357574, + _theResult___snd__h357585, + _theResult___snd__h357587, + _theResult___snd__h357597, + _theResult___snd__h357603, + _theResult___snd__h357626, + _theResult___snd__h366170, + _theResult___snd__h366172, + _theResult___snd__h366179, + _theResult___snd__h366185, + _theResult___snd__h366208, + _theResult___snd__h375340, + _theResult___snd__h375351, + _theResult___snd__h375353, + _theResult___snd__h375363, + _theResult___snd__h375369, + _theResult___snd__h375392, + _theResult___snd__h383960, + _theResult___snd__h383974, + _theResult___snd__h383980, + _theResult___snd__h383998, + _theResult___snd__h403264, + _theResult___snd__h403275, + _theResult___snd__h403277, + _theResult___snd__h403287, + _theResult___snd__h403293, + _theResult___snd__h403316, + _theResult___snd__h411860, + _theResult___snd__h411862, + _theResult___snd__h411869, + _theResult___snd__h411875, + _theResult___snd__h411898, + _theResult___snd__h421030, + _theResult___snd__h421041, + _theResult___snd__h421043, + _theResult___snd__h421053, + _theResult___snd__h421059, + _theResult___snd__h421082, + _theResult___snd__h429650, + _theResult___snd__h429664, + _theResult___snd__h429670, + _theResult___snd__h429688, + _theResult___snd__h448952, + _theResult___snd__h448963, + _theResult___snd__h448965, + _theResult___snd__h448975, + _theResult___snd__h448981, + _theResult___snd__h449004, + _theResult___snd__h457548, + _theResult___snd__h457550, + _theResult___snd__h457557, + _theResult___snd__h457563, + _theResult___snd__h457586, + _theResult___snd__h466718, + _theResult___snd__h466729, + _theResult___snd__h466731, + _theResult___snd__h466741, + _theResult___snd__h466747, + _theResult___snd__h466770, + _theResult___snd__h475338, + _theResult___snd__h475352, + _theResult___snd__h475358, + _theResult___snd__h475376, + _theResult___snd__h505510, + _theResult___snd__h505512, + _theResult___snd__h505519, + _theResult___snd__h505525, + _theResult___snd__h505548, + _theResult___snd__h515147, + _theResult___snd__h515158, + _theResult___snd__h515160, + _theResult___snd__h515170, + _theResult___snd__h515176, + _theResult___snd__h515199, + _theResult___snd__h523915, + _theResult___snd__h523929, + _theResult___snd__h523935, + _theResult___snd__h523953, + _theResult___snd__h544311, + _theResult___snd__h544313, + _theResult___snd__h544320, + _theResult___snd__h544326, + _theResult___snd__h544349, + _theResult___snd__h553948, + _theResult___snd__h553959, + _theResult___snd__h553961, + _theResult___snd__h553971, + _theResult___snd__h553977, + _theResult___snd__h554000, + _theResult___snd__h562716, + _theResult___snd__h562730, + _theResult___snd__h562736, + _theResult___snd__h562754, + _theResult___snd__h583512, + _theResult___snd__h583514, + _theResult___snd__h583521, + _theResult___snd__h583527, + _theResult___snd__h583550, + _theResult___snd__h593149, + _theResult___snd__h593160, + _theResult___snd__h593162, + _theResult___snd__h593172, + _theResult___snd__h593178, + _theResult___snd__h593201, + _theResult___snd__h601917, + _theResult___snd__h601931, + _theResult___snd__h601937, + _theResult___snd__h601955, + r1__read__h618453, + r1__read__h618601, + r1__read__h618631, + r1__read__h618773, + result__h367704, + result__h413394, + result__h459082, + result__h507513, + result__h546314, + result__h585515, + sfd__h341847, + sfd__h387542, + sfd__h433230, + sfd__h486558, + sfd__h525500, + sfd__h564701, + sfdin__h357557, + sfdin__h375323, + sfdin__h403247, + sfdin__h421013, + sfdin__h448935, + sfdin__h466701, + sfdin__h515130, + sfdin__h553931, + sfdin__h593132, + x__h367801, + x__h413491, + x__h459179, + x__h507608, + x__h546409, + x__h585610; + wire [55 : 0] r1__read__h617240, + r1__read__h617644, + r1__read__h618198, + r1__read__h618455, + r1__read__h618633, + r1__read__h618775; + wire [54 : 0] r1__read__h617242, + r1__read__h617646, + r1__read__h618200, + r1__read__h618457, + r1__read__h618635, + r1__read__h618777; + wire [53 : 0] r1__read__h618578, + r1__read__h618603, + r1__read__h618637, + r1__read__h618779, + sfd__h505577, + sfd__h515228, + sfd__h523988, + sfd__h544378, + sfd__h554029, + sfd__h562789, + sfd__h583579, + sfd__h593230, + sfd__h601990, + value__h350074, + value__h395764, + value__h441452; + wire [52 : 0] r1__read__h618459, + r1__read__h618580, + r1__read__h618605, + r1__read__h618639, + r1__read__h618781; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10713, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10715, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9246, @@ -4874,109 +4868,110 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9926, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9969, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9971, - _theResult___fst_sfd__h490488, - _theResult___fst_sfd__h506316, - _theResult___fst_sfd__h506319, - _theResult___fst_sfd__h515967, - _theResult___fst_sfd__h515970, - _theResult___fst_sfd__h524751, - _theResult___fst_sfd__h524754, - _theResult___fst_sfd__h524763, - _theResult___fst_sfd__h524769, - _theResult___fst_sfd__h529289, - _theResult___fst_sfd__h545117, - _theResult___fst_sfd__h545120, - _theResult___fst_sfd__h554768, - _theResult___fst_sfd__h554771, - _theResult___fst_sfd__h563552, - _theResult___fst_sfd__h563555, - _theResult___fst_sfd__h563564, - _theResult___fst_sfd__h563570, - _theResult___fst_sfd__h568490, - _theResult___fst_sfd__h584318, - _theResult___fst_sfd__h584321, - _theResult___fst_sfd__h593969, - _theResult___fst_sfd__h593972, - _theResult___fst_sfd__h602753, - _theResult___fst_sfd__h602756, - _theResult___fst_sfd__h602765, - _theResult___fst_sfd__h602771, - _theResult___sfd__h506216, - _theResult___sfd__h515867, - _theResult___sfd__h524651, - _theResult___sfd__h545017, - _theResult___sfd__h554668, - _theResult___sfd__h563452, - _theResult___sfd__h584218, - _theResult___sfd__h593869, - _theResult___sfd__h602653, - _theResult___snd_fst_sfd__h486513, - _theResult___snd_fst_sfd__h506322, - _theResult___snd_fst_sfd__h524757, - _theResult___snd_fst_sfd__h525455, - _theResult___snd_fst_sfd__h545123, - _theResult___snd_fst_sfd__h563558, - _theResult___snd_fst_sfd__h564656, - _theResult___snd_fst_sfd__h584324, - _theResult___snd_fst_sfd__h602759, - out___1_sfd__h486262, - out___1_sfd__h525204, - out___1_sfd__h564405, - out_sfd__h506219, - out_sfd__h515870, - out_sfd__h524654, - out_sfd__h545020, - out_sfd__h554671, - out_sfd__h563455, - out_sfd__h584221, - out_sfd__h593872, - out_sfd__h602656, - r1__read__h618782; - wire [50 : 0] r1__read__h617245, r1__read__h618462; - wire [49 : 0] r1__read__h618581, r1__read__h618784; - wire [48 : 0] r1__read__h617247, r1__read__h618464, r1__read__h618583; - wire [46 : 0] r1__read__h617249, r1__read__h618466; - wire [45 : 0] r1__read__h617251, r1__read__h618468; - wire [44 : 0] r1__read__h617253, r1__read__h618470; - wire [43 : 0] r1__read__h617255, r1__read__h618472; - wire [42 : 0] r1__read__h618474; - wire [41 : 0] r1__read__h618476; - wire [40 : 0] r1__read__h618478; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2835_BIT_160__ETC___d14015, - IF_fetchStage_pipelines_1_first__2844_BIT_160__ETC___d14172; + _theResult___fst_sfd__h490487, + _theResult___fst_sfd__h506315, + _theResult___fst_sfd__h506318, + _theResult___fst_sfd__h515966, + _theResult___fst_sfd__h515969, + _theResult___fst_sfd__h524750, + _theResult___fst_sfd__h524753, + _theResult___fst_sfd__h524762, + _theResult___fst_sfd__h524768, + _theResult___fst_sfd__h529288, + _theResult___fst_sfd__h545116, + _theResult___fst_sfd__h545119, + _theResult___fst_sfd__h554767, + _theResult___fst_sfd__h554770, + _theResult___fst_sfd__h563551, + _theResult___fst_sfd__h563554, + _theResult___fst_sfd__h563563, + _theResult___fst_sfd__h563569, + _theResult___fst_sfd__h568489, + _theResult___fst_sfd__h584317, + _theResult___fst_sfd__h584320, + _theResult___fst_sfd__h593968, + _theResult___fst_sfd__h593971, + _theResult___fst_sfd__h602752, + _theResult___fst_sfd__h602755, + _theResult___fst_sfd__h602764, + _theResult___fst_sfd__h602770, + _theResult___sfd__h506215, + _theResult___sfd__h515866, + _theResult___sfd__h524650, + _theResult___sfd__h545016, + _theResult___sfd__h554667, + _theResult___sfd__h563451, + _theResult___sfd__h584217, + _theResult___sfd__h593868, + _theResult___sfd__h602652, + _theResult___snd_fst_sfd__h486512, + _theResult___snd_fst_sfd__h506321, + _theResult___snd_fst_sfd__h524756, + _theResult___snd_fst_sfd__h525454, + _theResult___snd_fst_sfd__h545122, + _theResult___snd_fst_sfd__h563557, + _theResult___snd_fst_sfd__h564655, + _theResult___snd_fst_sfd__h584323, + _theResult___snd_fst_sfd__h602758, + out___1_sfd__h486261, + out___1_sfd__h525203, + out___1_sfd__h564404, + out_sfd__h506218, + out_sfd__h515869, + out_sfd__h524653, + out_sfd__h545019, + out_sfd__h554670, + out_sfd__h563454, + out_sfd__h584220, + out_sfd__h593871, + out_sfd__h602655, + r1__read__h618783; + wire [50 : 0] r1__read__h617244, r1__read__h618461; + wire [49 : 0] r1__read__h618582, r1__read__h618785; + wire [48 : 0] r1__read__h617246, r1__read__h618463, r1__read__h618584; + wire [46 : 0] r1__read__h617248, r1__read__h618465; + wire [45 : 0] r1__read__h617250, r1__read__h618467; + wire [44 : 0] r1__read__h617252, r1__read__h618469; + wire [43 : 0] r1__read__h617254, r1__read__h618471; + wire [42 : 0] r1__read__h618473; + wire [41 : 0] r1__read__h618475; + wire [40 : 0] r1__read__h618477; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2835_BIT_160__ETC___d14107, + IF_fetchStage_pipelines_1_first__2844_BIT_160__ETC___d14267; wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5, - data77961_BITS_31_TO_0__q2, - data78891_BITS_31_TO_0__q6, - r1__read__h617257, - r1__read__h618480, - x__h194788, - x__h341252, - x__h386947, - x__h432635, + data77960_BITS_31_TO_0__q2, + data78890_BITS_31_TO_0__q6, + imm__h659256, + r1__read__h617256, + r1__read__h618479, + x__h194789, + x__h341251, + x__h386946, + x__h432634, x__h75524, x_data__h65373, - x_data_imm__h677222, - x_data_imm__h692182; - wire [29 : 0] r1__read__h617259, r1__read__h618482; - wire [27 : 0] r1__read__h618484; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14061, - sfd__h357656, - sfd__h366238, - sfd__h375422, - sfd__h384034, - sfd__h403346, - sfd__h411928, - sfd__h421112, - sfd__h429724, - sfd__h449034, - sfd__h457616, - sfd__h466800, - sfd__h475412, - value__h491117, - value__h529918, - value__h569119; + x_data_imm__h678579, + x_data_imm__h694200; + wire [29 : 0] r1__read__h617258, r1__read__h618481; + wire [27 : 0] r1__read__h618483; + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14153, + sfd__h357655, + sfd__h366237, + sfd__h375421, + sfd__h384033, + sfd__h403345, + sfd__h411927, + sfd__h421111, + sfd__h429723, + sfd__h449033, + sfd__h457615, + sfd__h466799, + sfd__h475411, + value__h491116, + value__h529917, + value__h569118; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445, @@ -5001,77 +4996,77 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904, - _theResult___fst_sfd__h358162, - _theResult___fst_sfd__h366744, - _theResult___fst_sfd__h375928, - _theResult___fst_sfd__h384564, - _theResult___fst_sfd__h384573, - _theResult___fst_sfd__h384579, - _theResult___fst_sfd__h403852, - _theResult___fst_sfd__h412434, - _theResult___fst_sfd__h421618, - _theResult___fst_sfd__h430254, - _theResult___fst_sfd__h430263, - _theResult___fst_sfd__h430269, - _theResult___fst_sfd__h449540, - _theResult___fst_sfd__h458122, - _theResult___fst_sfd__h467306, - _theResult___fst_sfd__h475942, - _theResult___fst_sfd__h475951, - _theResult___fst_sfd__h475957, - _theResult___sfd__h358081, - _theResult___sfd__h366663, - _theResult___sfd__h375847, - _theResult___sfd__h384483, - _theResult___sfd__h384585, - _theResult___sfd__h403771, - _theResult___sfd__h412353, - _theResult___sfd__h421537, - _theResult___sfd__h430173, - _theResult___sfd__h430275, - _theResult___sfd__h449459, - _theResult___sfd__h458041, - _theResult___sfd__h467225, - _theResult___sfd__h475861, - _theResult___sfd__h475963, - _theResult___snd_fst_sfd__h341798, - _theResult___snd_fst_sfd__h366747, - _theResult___snd_fst_sfd__h384567, - _theResult___snd_fst_sfd__h387493, - _theResult___snd_fst_sfd__h412437, - _theResult___snd_fst_sfd__h430257, - _theResult___snd_fst_sfd__h433181, - _theResult___snd_fst_sfd__h458125, - _theResult___snd_fst_sfd__h475945, - out_f_sfd__h384862, - out_f_sfd__h430552, - out_f_sfd__h476240, - out_sfd__h358084, - out_sfd__h366666, - out_sfd__h375850, - out_sfd__h384486, - out_sfd__h403774, - out_sfd__h412356, - out_sfd__h421540, - out_sfd__h430176, - out_sfd__h449462, - out_sfd__h458044, - out_sfd__h467228, - out_sfd__h475864; - wire [19 : 0] r1__read__h618419; + _theResult___fst_sfd__h358161, + _theResult___fst_sfd__h366743, + _theResult___fst_sfd__h375927, + _theResult___fst_sfd__h384563, + _theResult___fst_sfd__h384572, + _theResult___fst_sfd__h384578, + _theResult___fst_sfd__h403851, + _theResult___fst_sfd__h412433, + _theResult___fst_sfd__h421617, + _theResult___fst_sfd__h430253, + _theResult___fst_sfd__h430262, + _theResult___fst_sfd__h430268, + _theResult___fst_sfd__h449539, + _theResult___fst_sfd__h458121, + _theResult___fst_sfd__h467305, + _theResult___fst_sfd__h475941, + _theResult___fst_sfd__h475950, + _theResult___fst_sfd__h475956, + _theResult___sfd__h358080, + _theResult___sfd__h366662, + _theResult___sfd__h375846, + _theResult___sfd__h384482, + _theResult___sfd__h384584, + _theResult___sfd__h403770, + _theResult___sfd__h412352, + _theResult___sfd__h421536, + _theResult___sfd__h430172, + _theResult___sfd__h430274, + _theResult___sfd__h449458, + _theResult___sfd__h458040, + _theResult___sfd__h467224, + _theResult___sfd__h475860, + _theResult___sfd__h475962, + _theResult___snd_fst_sfd__h341797, + _theResult___snd_fst_sfd__h366746, + _theResult___snd_fst_sfd__h384566, + _theResult___snd_fst_sfd__h387492, + _theResult___snd_fst_sfd__h412436, + _theResult___snd_fst_sfd__h430256, + _theResult___snd_fst_sfd__h433180, + _theResult___snd_fst_sfd__h458124, + _theResult___snd_fst_sfd__h475944, + out_f_sfd__h384861, + out_f_sfd__h430551, + out_f_sfd__h476239, + out_sfd__h358083, + out_sfd__h366665, + out_sfd__h375849, + out_sfd__h384485, + out_sfd__h403773, + out_sfd__h412355, + out_sfd__h421539, + out_sfd__h430175, + out_sfd__h449461, + out_sfd__h458043, + out_sfd__h467227, + out_sfd__h475863; + wire [19 : 0] r1__read__h618418; wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904, - _theResult____h655195, - enabled_ints___1__h655692, - enabled_ints__h655739, - pend_ints__h655193, - y__h655704; - wire [12 : 0] fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, - fetchStage_pipelines_1_first__2844_BIT_173_353_ETC___d13605, - r1__read_BITS_12_TO_0___h655715; + _theResult____h655200, + enabled_ints___1__h655697, + enabled_ints__h655744, + pend_ints__h655198, + y__h655709; + wire [12 : 0] fetchStage_pipelines_1_first__2844_BIT_173_359_ETC___d13665, + r1__read_BITS_12_TO_0___h655720; wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10525, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9052, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9762, IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12776, + IF_fetchStage_pipelines_0_first__2835_BIT_173__ETC___d13096, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647, @@ -5096,24 +5091,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434, - renaming_spec_bits__h684461, + renaming_spec_bits__h686479, result__h650909, result__h650960, - spec_bits__h687556, + spec_bits__h689574, w__h650904, - x__h367835, - x__h413525, - x__h459213, - x__h507642, - x__h546443, - x__h585644, + x__h367834, + x__h413524, + x__h459212, + x__h507641, + x__h546442, + x__h585643, x__h650908, x__h650959, y__h650938, - y__h687569, - y_avValue_fst__h681648, - y_avValue_snd_fst__h681922, - y_avValue_snd_fst__h681957; + y__h689587, + y_avValue_fst__h683000, + y_avValue_snd_fst__h683274, + y_avValue_snd_fst__h683309; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10630, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10632, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9162, @@ -5135,103 +5130,103 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q132, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q149, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q172, - _theResult___exp__h506215, - _theResult___exp__h515866, - _theResult___exp__h524650, - _theResult___exp__h545016, - _theResult___exp__h554667, - _theResult___exp__h563451, - _theResult___exp__h584217, - _theResult___exp__h593868, - _theResult___exp__h602652, - _theResult___fst_exp__h490487, - _theResult___fst_exp__h505551, - _theResult___fst_exp__h505557, - _theResult___fst_exp__h505560, - _theResult___fst_exp__h506315, - _theResult___fst_exp__h506318, - _theResult___fst_exp__h515137, - _theResult___fst_exp__h515202, - _theResult___fst_exp__h515208, - _theResult___fst_exp__h515211, - _theResult___fst_exp__h515966, - _theResult___fst_exp__h515969, - _theResult___fst_exp__h523922, - _theResult___fst_exp__h523961, - _theResult___fst_exp__h523967, - _theResult___fst_exp__h523970, - _theResult___fst_exp__h524750, - _theResult___fst_exp__h524753, - _theResult___fst_exp__h524762, - _theResult___fst_exp__h524765, - _theResult___fst_exp__h529288, - _theResult___fst_exp__h544352, - _theResult___fst_exp__h544358, - _theResult___fst_exp__h544361, - _theResult___fst_exp__h545116, - _theResult___fst_exp__h545119, - _theResult___fst_exp__h553938, - _theResult___fst_exp__h554003, - _theResult___fst_exp__h554009, - _theResult___fst_exp__h554012, - _theResult___fst_exp__h554767, - _theResult___fst_exp__h554770, - _theResult___fst_exp__h562723, - _theResult___fst_exp__h562762, - _theResult___fst_exp__h562768, - _theResult___fst_exp__h562771, - _theResult___fst_exp__h563551, - _theResult___fst_exp__h563554, - _theResult___fst_exp__h563563, - _theResult___fst_exp__h563566, - _theResult___fst_exp__h568489, - _theResult___fst_exp__h583553, - _theResult___fst_exp__h583559, - _theResult___fst_exp__h583562, - _theResult___fst_exp__h584317, - _theResult___fst_exp__h584320, - _theResult___fst_exp__h593139, - _theResult___fst_exp__h593204, - _theResult___fst_exp__h593210, - _theResult___fst_exp__h593213, - _theResult___fst_exp__h593968, - _theResult___fst_exp__h593971, - _theResult___fst_exp__h601924, - _theResult___fst_exp__h601963, - _theResult___fst_exp__h601969, - _theResult___fst_exp__h601972, - _theResult___fst_exp__h602752, - _theResult___fst_exp__h602755, - _theResult___fst_exp__h602764, - _theResult___fst_exp__h602767, - _theResult___snd_fst_exp__h506321, - _theResult___snd_fst_exp__h524756, - _theResult___snd_fst_exp__h545122, - _theResult___snd_fst_exp__h563557, - _theResult___snd_fst_exp__h584323, - _theResult___snd_fst_exp__h602758, + _theResult___exp__h506214, + _theResult___exp__h515865, + _theResult___exp__h524649, + _theResult___exp__h545015, + _theResult___exp__h554666, + _theResult___exp__h563450, + _theResult___exp__h584216, + _theResult___exp__h593867, + _theResult___exp__h602651, + _theResult___fst_exp__h490486, + _theResult___fst_exp__h505550, + _theResult___fst_exp__h505556, + _theResult___fst_exp__h505559, + _theResult___fst_exp__h506314, + _theResult___fst_exp__h506317, + _theResult___fst_exp__h515136, + _theResult___fst_exp__h515201, + _theResult___fst_exp__h515207, + _theResult___fst_exp__h515210, + _theResult___fst_exp__h515965, + _theResult___fst_exp__h515968, + _theResult___fst_exp__h523921, + _theResult___fst_exp__h523960, + _theResult___fst_exp__h523966, + _theResult___fst_exp__h523969, + _theResult___fst_exp__h524749, + _theResult___fst_exp__h524752, + _theResult___fst_exp__h524761, + _theResult___fst_exp__h524764, + _theResult___fst_exp__h529287, + _theResult___fst_exp__h544351, + _theResult___fst_exp__h544357, + _theResult___fst_exp__h544360, + _theResult___fst_exp__h545115, + _theResult___fst_exp__h545118, + _theResult___fst_exp__h553937, + _theResult___fst_exp__h554002, + _theResult___fst_exp__h554008, + _theResult___fst_exp__h554011, + _theResult___fst_exp__h554766, + _theResult___fst_exp__h554769, + _theResult___fst_exp__h562722, + _theResult___fst_exp__h562761, + _theResult___fst_exp__h562767, + _theResult___fst_exp__h562770, + _theResult___fst_exp__h563550, + _theResult___fst_exp__h563553, + _theResult___fst_exp__h563562, + _theResult___fst_exp__h563565, + _theResult___fst_exp__h568488, + _theResult___fst_exp__h583552, + _theResult___fst_exp__h583558, + _theResult___fst_exp__h583561, + _theResult___fst_exp__h584316, + _theResult___fst_exp__h584319, + _theResult___fst_exp__h593138, + _theResult___fst_exp__h593203, + _theResult___fst_exp__h593209, + _theResult___fst_exp__h593212, + _theResult___fst_exp__h593967, + _theResult___fst_exp__h593970, + _theResult___fst_exp__h601923, + _theResult___fst_exp__h601962, + _theResult___fst_exp__h601968, + _theResult___fst_exp__h601971, + _theResult___fst_exp__h602751, + _theResult___fst_exp__h602754, + _theResult___fst_exp__h602763, + _theResult___fst_exp__h602766, + _theResult___snd_fst_exp__h506320, + _theResult___snd_fst_exp__h524755, + _theResult___snd_fst_exp__h545121, + _theResult___snd_fst_exp__h563556, + _theResult___snd_fst_exp__h584322, + _theResult___snd_fst_exp__h602757, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99, csrf_debug_int_pend_read__1844_CONCAT_0b0_2867_ETC___d12877, - din_inc___2_exp__h524810, - din_inc___2_exp__h524845, - din_inc___2_exp__h524871, - din_inc___2_exp__h563611, - din_inc___2_exp__h563646, - din_inc___2_exp__h563672, - din_inc___2_exp__h602812, - din_inc___2_exp__h602847, - din_inc___2_exp__h602873, - out_exp__h506218, - out_exp__h515869, - out_exp__h524653, - out_exp__h545019, - out_exp__h554670, - out_exp__h563454, - out_exp__h584220, - out_exp__h593871, - out_exp__h602655; + din_inc___2_exp__h524809, + din_inc___2_exp__h524844, + din_inc___2_exp__h524870, + din_inc___2_exp__h563610, + din_inc___2_exp__h563645, + din_inc___2_exp__h563671, + din_inc___2_exp__h602811, + din_inc___2_exp__h602846, + din_inc___2_exp__h602872, + out_exp__h506217, + out_exp__h515868, + out_exp__h524652, + out_exp__h545018, + out_exp__h554669, + out_exp__h563453, + out_exp__h584219, + out_exp__h593870, + out_exp__h602654; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752; @@ -5262,121 +5257,121 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105, - _theResult___exp__h358080, - _theResult___exp__h366662, - _theResult___exp__h375846, - _theResult___exp__h384482, - _theResult___exp__h384584, - _theResult___exp__h403770, - _theResult___exp__h412352, - _theResult___exp__h421536, - _theResult___exp__h430172, - _theResult___exp__h430274, - _theResult___exp__h449458, - _theResult___exp__h458040, - _theResult___exp__h467224, - _theResult___exp__h475860, - _theResult___exp__h475962, - _theResult___fst_exp__h357564, - _theResult___fst_exp__h357629, - _theResult___fst_exp__h357635, - _theResult___fst_exp__h357638, - _theResult___fst_exp__h358161, - _theResult___fst_exp__h366211, - _theResult___fst_exp__h366217, - _theResult___fst_exp__h366220, - _theResult___fst_exp__h366743, - _theResult___fst_exp__h375330, - _theResult___fst_exp__h375395, - _theResult___fst_exp__h375401, - _theResult___fst_exp__h375404, - _theResult___fst_exp__h375927, - _theResult___fst_exp__h383967, - _theResult___fst_exp__h384006, - _theResult___fst_exp__h384012, - _theResult___fst_exp__h384015, - _theResult___fst_exp__h384563, - _theResult___fst_exp__h384572, - _theResult___fst_exp__h384575, - _theResult___fst_exp__h403254, - _theResult___fst_exp__h403319, - _theResult___fst_exp__h403325, - _theResult___fst_exp__h403328, - _theResult___fst_exp__h403851, - _theResult___fst_exp__h411901, - _theResult___fst_exp__h411907, - _theResult___fst_exp__h411910, - _theResult___fst_exp__h412433, - _theResult___fst_exp__h421020, - _theResult___fst_exp__h421085, - _theResult___fst_exp__h421091, - _theResult___fst_exp__h421094, - _theResult___fst_exp__h421617, - _theResult___fst_exp__h429657, - _theResult___fst_exp__h429696, - _theResult___fst_exp__h429702, - _theResult___fst_exp__h429705, - _theResult___fst_exp__h430253, - _theResult___fst_exp__h430262, - _theResult___fst_exp__h430265, - _theResult___fst_exp__h448942, - _theResult___fst_exp__h449007, - _theResult___fst_exp__h449013, - _theResult___fst_exp__h449016, - _theResult___fst_exp__h449539, - _theResult___fst_exp__h457589, - _theResult___fst_exp__h457595, - _theResult___fst_exp__h457598, - _theResult___fst_exp__h458121, - _theResult___fst_exp__h466708, - _theResult___fst_exp__h466773, - _theResult___fst_exp__h466779, - _theResult___fst_exp__h466782, - _theResult___fst_exp__h467305, - _theResult___fst_exp__h475345, - _theResult___fst_exp__h475384, - _theResult___fst_exp__h475390, - _theResult___fst_exp__h475393, - _theResult___fst_exp__h475941, - _theResult___fst_exp__h475950, - _theResult___fst_exp__h475953, - _theResult___snd_fst_exp__h366746, - _theResult___snd_fst_exp__h384566, - _theResult___snd_fst_exp__h412436, - _theResult___snd_fst_exp__h430256, - _theResult___snd_fst_exp__h458124, - _theResult___snd_fst_exp__h475944, + _theResult___exp__h358079, + _theResult___exp__h366661, + _theResult___exp__h375845, + _theResult___exp__h384481, + _theResult___exp__h384583, + _theResult___exp__h403769, + _theResult___exp__h412351, + _theResult___exp__h421535, + _theResult___exp__h430171, + _theResult___exp__h430273, + _theResult___exp__h449457, + _theResult___exp__h458039, + _theResult___exp__h467223, + _theResult___exp__h475859, + _theResult___exp__h475961, + _theResult___fst_exp__h357563, + _theResult___fst_exp__h357628, + _theResult___fst_exp__h357634, + _theResult___fst_exp__h357637, + _theResult___fst_exp__h358160, + _theResult___fst_exp__h366210, + _theResult___fst_exp__h366216, + _theResult___fst_exp__h366219, + _theResult___fst_exp__h366742, + _theResult___fst_exp__h375329, + _theResult___fst_exp__h375394, + _theResult___fst_exp__h375400, + _theResult___fst_exp__h375403, + _theResult___fst_exp__h375926, + _theResult___fst_exp__h383966, + _theResult___fst_exp__h384005, + _theResult___fst_exp__h384011, + _theResult___fst_exp__h384014, + _theResult___fst_exp__h384562, + _theResult___fst_exp__h384571, + _theResult___fst_exp__h384574, + _theResult___fst_exp__h403253, + _theResult___fst_exp__h403318, + _theResult___fst_exp__h403324, + _theResult___fst_exp__h403327, + _theResult___fst_exp__h403850, + _theResult___fst_exp__h411900, + _theResult___fst_exp__h411906, + _theResult___fst_exp__h411909, + _theResult___fst_exp__h412432, + _theResult___fst_exp__h421019, + _theResult___fst_exp__h421084, + _theResult___fst_exp__h421090, + _theResult___fst_exp__h421093, + _theResult___fst_exp__h421616, + _theResult___fst_exp__h429656, + _theResult___fst_exp__h429695, + _theResult___fst_exp__h429701, + _theResult___fst_exp__h429704, + _theResult___fst_exp__h430252, + _theResult___fst_exp__h430261, + _theResult___fst_exp__h430264, + _theResult___fst_exp__h448941, + _theResult___fst_exp__h449006, + _theResult___fst_exp__h449012, + _theResult___fst_exp__h449015, + _theResult___fst_exp__h449538, + _theResult___fst_exp__h457588, + _theResult___fst_exp__h457594, + _theResult___fst_exp__h457597, + _theResult___fst_exp__h458120, + _theResult___fst_exp__h466707, + _theResult___fst_exp__h466772, + _theResult___fst_exp__h466778, + _theResult___fst_exp__h466781, + _theResult___fst_exp__h467304, + _theResult___fst_exp__h475344, + _theResult___fst_exp__h475383, + _theResult___fst_exp__h475389, + _theResult___fst_exp__h475392, + _theResult___fst_exp__h475940, + _theResult___fst_exp__h475949, + _theResult___fst_exp__h475952, + _theResult___snd_fst_exp__h366745, + _theResult___snd_fst_exp__h384565, + _theResult___snd_fst_exp__h412435, + _theResult___snd_fst_exp__h430255, + _theResult___snd_fst_exp__h458123, + _theResult___snd_fst_exp__h475943, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145, - din_inc___2_exp__h384597, - din_inc___2_exp__h384621, - din_inc___2_exp__h384651, - din_inc___2_exp__h384675, - din_inc___2_exp__h430287, - din_inc___2_exp__h430311, - din_inc___2_exp__h430341, - din_inc___2_exp__h430365, - din_inc___2_exp__h475975, - din_inc___2_exp__h475999, - din_inc___2_exp__h476029, - din_inc___2_exp__h476053, - out_exp__h358083, - out_exp__h366665, - out_exp__h375849, - out_exp__h384485, - out_exp__h403773, - out_exp__h412355, - out_exp__h421539, - out_exp__h430175, - out_exp__h449461, - out_exp__h458043, - out_exp__h467227, - out_exp__h475863, - out_f_exp__h384861, - out_f_exp__h430551, - out_f_exp__h476239, - x__h617216; + din_inc___2_exp__h384596, + din_inc___2_exp__h384620, + din_inc___2_exp__h384650, + din_inc___2_exp__h384674, + din_inc___2_exp__h430286, + din_inc___2_exp__h430310, + din_inc___2_exp__h430340, + din_inc___2_exp__h430364, + din_inc___2_exp__h475974, + din_inc___2_exp__h475998, + din_inc___2_exp__h476028, + din_inc___2_exp__h476052, + out_exp__h358082, + out_exp__h366664, + out_exp__h375848, + out_exp__h384484, + out_exp__h403772, + out_exp__h412354, + out_exp__h421538, + out_exp__h430174, + out_exp__h449460, + out_exp__h458042, + out_exp__h467226, + out_exp__h475862, + out_f_exp__h384860, + out_f_exp__h430550, + out_f_exp__h476238, + x__h617215; wire [6 : 0] csrf_debug_int_pend_read__1844_CONCAT_0b0_2867_ETC___d12872; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735, @@ -5397,11 +5392,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8689, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9414, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15097, - x__h184460, - x__h704888; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14227, - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14957, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15190, + x__h184461, + x__h707048; + wire [4 : 0] IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14320, + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15050, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049, @@ -5418,111 +5413,113 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10874, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10918, checkForException___d13069, - checkForException___d13626, - fflags__h716900, - res_fflags__h341241, - res_fflags__h386936, - res_fflags__h432624, - x__h154745, - x__h158292, - x__h161108, - x__h290546, - y_avValue_snd_fst__h716307, - y_avValue_snd_fst__h716960, - y_avValue_snd_fst__h716989; + checkForException___d13686, + fflags__h719060, + res_fflags__h341240, + res_fflags__h386935, + res_fflags__h432623, + rs1__h659255, + x__h154744, + x__h158291, + x__h161107, + x__h290547, + y_avValue_snd_fst__h718467, + y_avValue_snd_fst__h719120, + y_avValue_snd_fst__h719149; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1881, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1883, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1885, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13207, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13208, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13209, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13210, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13211, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13212, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13213, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13214, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13215, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13216, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13217, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13218, - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13219, - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13245, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13242, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13243, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13244, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13245, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13246, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13247, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13248, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13249, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13250, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13251, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13252, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13253, + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13254, + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13280, IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819, + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929, IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13264, - cause_code__h702271, - vm_mode_reg__read__h618425; + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13299, + cause_code__h704431, + vm_mode_reg__read__h618424; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, - _theResult_____2__h299893, - next_deqP___1__h300172, - v__h299313, - v__h299544, - x__h305523, - x_decodeInfo_frm__h658934; + _theResult_____2__h299894, + next_deqP___1__h300173, + v__h299314, + v__h299545, + x__h305524, + x_decodeInfo_frm__h658939; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14978, - IF_sfdin03248_BIT_33_THEN_2_ELSE_0__q57, - IF_sfdin15131_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin21014_BIT_33_THEN_2_ELSE_0__q67, - IF_sfdin48936_BIT_33_THEN_2_ELSE_0__q92, - IF_sfdin53932_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin57558_BIT_33_THEN_2_ELSE_0__q22, - IF_sfdin66702_BIT_33_THEN_2_ELSE_0__q102, - IF_sfdin75324_BIT_33_THEN_2_ELSE_0__q32, - IF_sfdin93133_BIT_4_THEN_2_ELSE_0__q148, - IF_theResult___snd01918_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd05511_BIT_4_THEN_2_ELSE_0__q127, - IF_theResult___snd11861_BIT_33_THEN_2_ELSE_0__q59, - IF_theResult___snd23916_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd29651_BIT_33_THEN_2_ELSE_0__q72, - IF_theResult___snd44312_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd57549_BIT_33_THEN_2_ELSE_0__q94, - IF_theResult___snd62717_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd66171_BIT_33_THEN_2_ELSE_0__q24, - IF_theResult___snd75339_BIT_33_THEN_2_ELSE_0__q107, - IF_theResult___snd83513_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd83961_BIT_33_THEN_2_ELSE_0__q37, - guard__h349463, - guard__h358172, - guard__h367102, - guard__h375938, - guard__h395155, - guard__h403862, - guard__h412792, - guard__h421628, - guard__h440843, - guard__h449550, - guard__h458480, - guard__h467316, - guard__h497599, - guard__h506911, - guard__h515980, - guard__h536400, - guard__h545712, - guard__h554781, - guard__h575601, - guard__h584913, - guard__h593982, - prv__h718414, - prv__h718458, - sbIdx__h158171, - v__h607990, - v__h608000, - v__h609058, - x__h617271, - x__h713161, - x__h717147, - y_avValue_snd_snd_snd_fst__h716317, - y_avValue_snd_snd_snd_fst__h716970, - y_avValue_snd_snd_snd_fst__h716999; + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15071, + IF_sfdin03247_BIT_33_THEN_2_ELSE_0__q57, + IF_sfdin15130_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin21013_BIT_33_THEN_2_ELSE_0__q67, + IF_sfdin48935_BIT_33_THEN_2_ELSE_0__q92, + IF_sfdin53931_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin57557_BIT_33_THEN_2_ELSE_0__q22, + IF_sfdin66701_BIT_33_THEN_2_ELSE_0__q102, + IF_sfdin75323_BIT_33_THEN_2_ELSE_0__q32, + IF_sfdin93132_BIT_4_THEN_2_ELSE_0__q148, + IF_theResult___snd01917_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd05510_BIT_4_THEN_2_ELSE_0__q127, + IF_theResult___snd11860_BIT_33_THEN_2_ELSE_0__q59, + IF_theResult___snd23915_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd29650_BIT_33_THEN_2_ELSE_0__q72, + IF_theResult___snd44311_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd57548_BIT_33_THEN_2_ELSE_0__q94, + IF_theResult___snd62716_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd66170_BIT_33_THEN_2_ELSE_0__q24, + IF_theResult___snd75338_BIT_33_THEN_2_ELSE_0__q107, + IF_theResult___snd83512_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd83960_BIT_33_THEN_2_ELSE_0__q37, + guard__h349462, + guard__h358171, + guard__h367101, + guard__h375937, + guard__h395154, + guard__h403861, + guard__h412791, + guard__h421627, + guard__h440842, + guard__h449549, + guard__h458479, + guard__h467315, + guard__h497598, + guard__h506910, + guard__h515979, + guard__h536399, + guard__h545711, + guard__h554780, + guard__h575600, + guard__h584912, + guard__h593981, + prv__h720574, + prv__h720618, + r1__read_BITS_13_TO_12___h659124, + sbIdx__h158170, + v__h607989, + v__h607999, + v__h609057, + x__h715321, + x__h719307, + y_avValue_snd_snd_snd_fst__h718477, + y_avValue_snd_snd_snd_fst__h719130, + y_avValue_snd_snd_snd_fst__h719159; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557, @@ -5536,6 +5533,7 @@ module mkCore(CLK, IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10783, IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9045, IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9755, + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d13106, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10006, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10033, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10564, @@ -5584,11 +5582,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1667, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2114, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2131, - IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13785, - IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13793, - IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13717, - IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13792, - IF_NOT_rob_deqPort_1_deq_data__4766_BIT_25_476_ETC___d14969, + IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13875, + IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13883, + IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13805, + IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13882, + IF_NOT_rob_deqPort_1_deq_data__4859_BIT_25_486_ETC___d15062, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323, @@ -5718,27 +5716,30 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3654, - IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13385, - IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13719, - IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13782, - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13829, - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13950, + IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13444, + IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13807, + IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13872, + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13920, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14041, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__4763_THEN_IF_NOT_rob__ETC___d14970, + IF_rob_deqPort_1_canDeq__4856_THEN_IF_NOT_rob__ETC___d15063, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5345, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6709, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6737, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8101, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8129, - NOT_IF_NOT_rob_deqPort_0_canDeq__4759_4760_OR__ETC___d14975, - NOT_IF_rob_deqPort_0_deq_data__4241_BITS_97_TO_ETC___d14730, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13433, + NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_286_ETC___d13348, + NOT_IF_NOT_rob_deqPort_0_canDeq__4852_4853_OR__ETC___d15068, + NOT_IF_rob_deqPort_0_deq_data__4334_BITS_97_TO_ETC___d14823, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13492, + NOT_checkForException_3069_BIT_4_3070_3322_AND_ETC___d13431, + NOT_checkForException_3686_BIT_4_3687_3688_AND_ETC___d13706, NOT_coreFix_aluExe_0_bypassWire_0_whas__2301_2_ETC___d12328, NOT_coreFix_aluExe_0_bypassWire_0_whas__2301_2_ETC___d12358, NOT_coreFix_aluExe_1_bypassWire_0_whas__1478_1_ETC___d11505, @@ -5763,6 +5764,7 @@ module mkCore(CLK, NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8540, NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8662, NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d9387, + NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13816, NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611, NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640, NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2554, @@ -5811,49 +5813,51 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3643, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3685, NOT_coreFix_memExe_respLrScAmoQ_full_977_978_A_ETC___d2110, - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13472, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13700, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13711, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13733, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13748, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13762, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13765, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13885, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13904, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13956, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14078, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14085, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14096, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14132, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14157, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160, - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14204, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13415, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13633, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13647, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13653, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13752, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13769, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13787, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13790, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13878, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961, - NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d13985, - NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13289, + NOT_coreFix_memExe_rsMem_canEnq__3460_3521_OR__ETC___d13817, + NOT_csrf_fs_reg_read__1686_EQ_0_3058_3059_OR_N_ETC___d13346, + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13532, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13788, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13799, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13823, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13838, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13852, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13855, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13976, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13995, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14047, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14180, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14191, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14227, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14252, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255, + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14299, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13342, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13474, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13711, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13725, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13731, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13842, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13859, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13877, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13880, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13969, + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053, + NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d14077, + NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13433, NOT_fetchStage_pipelines_1_canDeq__2841_2842_O_ETC___d12850, - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13638, - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13640, - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13736, - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13757, - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13774, - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091, - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14093, - NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14147, - NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13630, + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13716, + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13718, + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13826, + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13847, + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13864, + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186, + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14188, + NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14242, + NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13708, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -5869,16 +5873,16 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13742, - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796, - NOT_rob_deqPort_0_canDeq__4759_4760_OR_regRena_ETC___d14798, - NOT_rob_deqPort_0_canDeq__4759_4760_OR_rob_deq_ETC___d14951, - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14554, - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14740, - NOT_rob_deqPort_1_deq_data__4766_BIT_25_4767_4_ETC___d14795, - NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13875, - NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13940, - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13689, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13832, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887, + NOT_rob_deqPort_0_canDeq__4852_4853_OR_regRena_ETC___d14891, + NOT_rob_deqPort_0_canDeq__4852_4853_OR_rob_deq_ETC___d15044, + NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14647, + NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14833, + NOT_rob_deqPort_1_deq_data__4859_BIT_25_4860_4_ETC___d14888, + NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d13966, + NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d14031, + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13777, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648, @@ -5912,11 +5916,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9053, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9416, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9763, - _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13803, - _0_OR_NOT_fetchStage_pipelines_1_first__2844_BI_ETC___d13888, - _0_OR_fetchStage_RDY_pipelines_0_first__2832_37_ETC___d13714, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14420, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14402, + _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13894, + _0_OR_NOT_fetchStage_pipelines_1_first__2844_BI_ETC___d13979, + _0_OR_fetchStage_RDY_pipelines_0_first__2832_38_ETC___d13802, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14513, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14495, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5280, @@ -5939,10 +5943,9 @@ module mkCore(CLK, _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9341, _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9343, _dfoo12, - _dfoo16, _dfoo18, _dfoo2, - _dfoo20, + _dfoo22, _dfoo28, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, @@ -5969,11 +5972,13 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h307889, - _theResult_____2__h313883, - _theResult_____2__h321737, - _theResult_____2__h332081, - _theResult_____2__h335306, + _theResult_____2__h307890, + _theResult_____2__h313884, + _theResult_____2__h321738, + _theResult_____2__h332082, + _theResult_____2__h335307, + checkForException_3069_BIT_4_3070_OR_csrf_fs_r_ETC___d13509, + checkForException_3686_BIT_4_3687_OR_csrf_fs_r_ETC___d13767, coreFix_aluExe_0_bypassWire_0_wget__2302_BITS__ETC___d12304, coreFix_aluExe_0_bypassWire_0_wget__2302_BITS__ETC___d12345, coreFix_aluExe_0_bypassWire_1_wget__2315_BITS__ETC___d12317, @@ -5984,7 +5989,7 @@ module mkCore(CLK, coreFix_aluExe_0_bypassWire_3_wget__2330_BITS__ETC___d12359, coreFix_aluExe_0_dispToRegQ_RDY_first__2279_AN_ETC___d12370, coreFix_aluExe_0_exeToFinQ_RDY_first__2719_AND_ETC___d12758, - coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394, + coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453, coreFix_aluExe_1_bypassWire_0_wget__1479_BITS__ETC___d11481, coreFix_aluExe_1_bypassWire_0_wget__1479_BITS__ETC___d11522, coreFix_aluExe_1_bypassWire_1_wget__1492_BITS__ETC___d11494, @@ -6018,7 +6023,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11028, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11070, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11112, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13895, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13986, coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587, coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627, coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600, @@ -6090,95 +6095,99 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3670, - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14559, - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422, - csrf_prv_reg_read__2863_ULE_1___d14382, - fetchStage_RDY_pipelines_0_first__2832_AND_NOT_ETC___d13381, - fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13285, - fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13447, - fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964, - fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14069, - fetchStage_pipelines_0_canDeq__2833_AND_fetchS_ETC___d13954, - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13892, - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13898, - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13899, - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13920, - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14217, - fetchStage_pipelines_0_canDeq__2833_AND_specTa_ETC___d14047, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13646, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13665, + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14652, + csrf_fs_reg_read__1686_EQ_0_3058_AND_fetchStag_ETC___d13104, + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515, + csrf_prv_reg_read__2863_ULE_1___d14475, + csrf_prv_reg_read__2863_ULT_IF_fetchStage_pipe_ETC___d13101, + fetchStage_RDY_pipelines_0_first__2832_AND_NOT_ETC___d13440, + fetchStage_RDY_pipelines_0_first__2832_AND_epo_ETC___d13320, + fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13506, + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14056, + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14174, + fetchStage_pipelines_0_canDeq__2833_AND_fetchS_ETC___d14045, + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13983, + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13989, + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13990, + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14011, + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14310, + fetchStage_pipelines_0_canDeq__2833_AND_specTa_ETC___d14139, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13099, fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13831, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13837, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13859, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13866, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13913, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13924, - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14075, - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13454, - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13658, - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072, - fetchStage_pipelines_1_first__2844_BITS_194_TO_ETC___d13848, - fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13686, - fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13853, - fetchStage_pipelines_1_first__2844_BIT_68_3503_ETC___d13681, - guard__h367700, - guard__h413390, - guard__h459078, - guard__h507509, - guard__h546310, - guard__h585511, - idx__h684592, - k__h669941, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13745, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13814, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13922, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13928, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13950, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13957, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14004, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14015, + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14169, + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13514, + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13738, + fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13736, + fetchStage_pipelines_1_first__2844_BITS_194_TO_ETC___d13939, + fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13774, + fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13944, + fetchStage_pipelines_1_first__2844_BIT_68_3563_ETC___d13769, + guard__h367699, + guard__h413389, + guard__h459077, + guard__h507508, + guard__h546309, + guard__h585510, + idx__h686610, + k__h671298, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153, mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13308, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13958, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13110, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13367, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14050, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h75409, - next_deqP___1__h308168, - next_deqP___1__h314449, - next_deqP___1__h322303, - next_deqP___1__h332360, - next_deqP___1__h335585, - r__h617263, - regRenamingTable_RDY_rename_0_getRename__3276__ETC___d13816, - regRenamingTable_RDY_rename_1_getRename__3872__ETC___d13890, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13442, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13697, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13709, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13845, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13976, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13989, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13994, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13999, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14019, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14023, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14029, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14033, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14041, - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14215, - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14136, - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14151, - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14176, - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14180, - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14186, - rob_RDY_enqPort_1_enq__3936_AND_NOT_fetchStage_ETC___d13944, - v__h302658, - v__h303176, - v__h313172, - v__h313403, - v__h317048, - v__h317279, - v__h331649, - v__h331880, - v__h334874, - v__h335105, - x__h607324; + next_deqP___1__h308169, + next_deqP___1__h314450, + next_deqP___1__h322304, + next_deqP___1__h332361, + next_deqP___1__h335586, + r__h617262, + regRenamingTable_RDY_rename_0_getRename__3311__ETC___d13907, + regRenamingTable_RDY_rename_1_getRename__3963__ETC___d13981, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13501, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13785, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13797, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13936, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14068, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14081, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14086, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14091, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14111, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14115, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14121, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14125, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14308, + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14231, + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14246, + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14271, + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14275, + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14281, + rob_RDY_enqPort_1_enq__4027_AND_NOT_fetchStage_ETC___d14035, + v__h302659, + v__h303177, + v__h313173, + v__h313404, + v__h317049, + v__h317280, + v__h331650, + v__h331881, + v__h334875, + v__h335106, + x__h607323; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6219,7 +6228,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15071 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15164 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6239,7 +6248,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15097 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15190 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9146,16 +9155,16 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && - coreFix_memExe_dTlb$RDY_toParent_rqToP_first ; + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; @@ -9169,30 +9178,30 @@ module mkCore(CLK, // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = + fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && - fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = - l2Tlb$RDY_toChildren_dTlbReqFlush_put && - coreFix_memExe_dTlb$RDY_toParent_flush_request_get ; + coreFix_memExe_dTlb$RDY_toParent_flush_request_get && + l2Tlb$RDY_toChildren_dTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - l2Tlb$RDY_toChildren_flushDone_get && + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9231,9 +9240,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9619,7 +9628,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14559 && + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14652 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -9664,7 +9673,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4759_4760_OR_regRena_ETC___d14798 && + NOT_rob_deqPort_0_canDeq__4852_4853_OR_regRena_ETC___d14891 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -10292,8 +10301,8 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; @@ -10579,14 +10588,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && - mmio_pRqQ_empty && - epochManager$checkEpoch_0_check && - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072 && - rob$isEmpty ; + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13110 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -10594,9 +10600,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - epochManager$RDY_incrementEpoch && - fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13285 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13308 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2832_AND_epo_ETC___d13320 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13367 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -10637,11 +10643,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13385) && - IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13785 && - IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13793 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13956 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13958 ; + IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13444) && + IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13875 && + IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13883 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14047 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14050 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -10676,7 +10682,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -10853,7 +10860,7 @@ module mkCore(CLK, assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap[4] ; - assign MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_1 = + assign MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming_Trap && !fetchStage$pipelines_0_first[68] && (IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || @@ -10874,67 +10881,55 @@ module mkCore(CLK, assign MUX_csrf_debug_int_pend$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd29 ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd16 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd29) ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd2 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; - assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) ; - assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 ; + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14093 && - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 ; + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14188 && + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 ; assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = @@ -10981,7 +10976,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h698600, + x__h700760, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 : @@ -10989,13 +10984,26 @@ module mkCore(CLK, assign MUX_commitStage_rg_instret$write_1__VAL_1 = commitStage_rg_instret + 64'd1 ; assign MUX_commitStage_rg_instret$write_1__VAL_2 = - commitStage_rg_instret + y__h716923 ; + commitStage_rg_instret + y__h719083 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h669941 == 1'd0 && - fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964) ? + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + (k__h671298 == 1'd0 && + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14056) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, - fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -11005,27 +11013,16 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529, - fetchStage_pipelines_1_first__2844_BIT_173_353_ETC___d13605, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589, + fetchStage_pipelines_1_first__2844_BIT_173_359_ETC___d13665, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h684461, + renaming_spec_bits__h686479, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, - fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11113,7 +11110,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, @@ -11127,10 +11124,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h289113 } ; + x__h289114 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h290558, + x__h290559, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11138,7 +11135,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h293334, + addr__h293335, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11151,12 +11148,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h154745, x__h154751, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h154744, x__h154750, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h158292, x__h158298, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h158291, x__h158297, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h161108, - x__h161112, + { x__h161107, + x__h161111, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, @@ -11167,7 +11164,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255, - x__h162960, + x__h162959, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, @@ -11180,7 +11177,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h295349, + resp_addr__h295350, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11260,7 +11257,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h199068 } ; + x__h199069 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11295,8 +11292,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h194025 : - { {32{x__h194788[31]}}, x__h194788 } } ; + curData__h194026 : + { {32{x__h194789[31]}}, x__h194789 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[325:321], @@ -11325,62 +11322,62 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h716900 ; - always@(IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 or + csrf_fflags_reg | fflags__h719060 ; + always@(IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 or robdeqPort_0_deq_data_BITS_95_TO_32__q262) begin - case (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544) + case (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_1 = robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; endcase end - assign MUX_csrf_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; - assign MUX_csrf_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h713751 + 64'd1 ; + n__read__h715911 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h713751 + { 62'd0, x__h717147 } ; - assign MUX_csrf_mpp_reg$write_1__VAL_1 = + n__read__h715911 + { 62'd0, x__h719307 } ; + assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) ? MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h703302 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h705462 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 != 6'd8 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h713161 : + x__h715321 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ? + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 ? 2'd1 : 2'd3 ; assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; @@ -11388,24 +11385,24 @@ module mkCore(CLK, (mmio_pRqQ_data_0[37:36] == 2'd2) ? mmio_pRqQ_data_0[0] : amoExec___d882[0] ; - assign MUX_csrf_spp_reg$write_1__VAL_1 = + assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ? - y_avValue__h703149 : - y_avValue__h704910 ; + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 ? + y_avValue__h705309 : + y_avValue__h707070 ; always@(rob$deqPort_0_deq_data or - next_pc__h712992 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h715152 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h712992; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h715152; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11440,24 +11437,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h341245 : - res_data__h341240 ; + res_data__h341244 : + res_data__h341239 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h386940 : - res_data__h386935 ; + res_data__h386939 : + res_data__h386934 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h432628 : - res_data__h432623 ; + res_data__h432627 : + res_data__h432622 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h478473 : - data__h477961 ; + data___1__h478472 : + data__h477960 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h479403 : - data__h478891 ; + data___1__h479402 : + data__h478890 ; assign MUX_rf$write_3_wr_2__VAL_4 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -11470,8 +11467,9 @@ module mkCore(CLK, { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], - fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, - 73'h12AAAAAAAAAAAAAAAA8, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035, + 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, fetchStage$pipelines_0_first[75] && @@ -11481,12 +11479,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14061 } ; + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14153 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], - fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035, 2'd1, !fetchStage$pipelines_0_first[68] && (IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || @@ -11504,7 +11503,7 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14]), - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13264, + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13299, fetchStage$pipelines_0_first[63:0], 2'd0, fetchStage$pipelines_0_first[323:260], @@ -11514,8 +11513,9 @@ module mkCore(CLK, { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], - fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, - 73'h12AAAAAAAAAAAAAAAA8, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035, + 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, fetchStage$pipelines_0_first[75] && @@ -11532,21 +11532,21 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h341241 ; + res_fflags__h341240 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h386936 ; + res_fflags__h386935 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h432624 ; + res_fflags__h432623 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd31 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || @@ -11558,12 +11558,12 @@ module mkCore(CLK, assign csrf_mcycle_ehr_data_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd30 ; assign csrInstOrInterruptInflight_lat_1$whas = - MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_1 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[199:195] == 5'd13 ; + fetchStage$pipelines_0_first[199:195] == 5'd13 || + MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ; assign mmio_dataReqQ_enqReq_lat_0$wget = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ? MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 : @@ -11871,8 +11871,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h609058 : - v__h607990 ; + v__h609057 : + v__h607989 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -12018,7 +12018,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h299893 ; + _theResult_____2__h299894 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12040,7 +12040,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h299313 ; + v__h299314 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12086,7 +12086,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - _theResult_____2__h307889 ; + _theResult_____2__h307890 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12104,7 +12104,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - v__h302658 ; + v__h302659 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12204,7 +12204,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - _theResult_____2__h313883 ; + _theResult_____2__h313884 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12222,7 +12222,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - v__h313172 ; + v__h313173 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12243,7 +12243,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h317446, + { x_addr__h317447, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12273,7 +12273,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - _theResult_____2__h321737 ; + _theResult_____2__h321738 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12291,7 +12291,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - v__h317048 ; + v__h317049 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12368,7 +12368,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - _theResult_____2__h335306 ; + _theResult_____2__h335307 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12386,7 +12386,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - v__h334874 ; + v__h334875 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12429,7 +12429,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - _theResult_____2__h332081 ; + _theResult_____2__h332082 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12447,7 +12447,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - v__h331649 ; + v__h331650 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12610,7 +12610,7 @@ module mkCore(CLK, assign csrf_debug_int_pend$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd29 || EN_setDEIP ; @@ -12620,9 +12620,9 @@ module mkCore(CLK, assign csrf_external_int_en_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22) ; // register csrf_external_int_en_vec_1 @@ -12631,9 +12631,9 @@ module mkCore(CLK, assign csrf_external_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22) ; // register csrf_external_int_en_vec_3 @@ -12642,7 +12642,7 @@ module mkCore(CLK, assign csrf_external_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -12667,7 +12667,7 @@ module mkCore(CLK, assign csrf_external_int_pend_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd29 || EN_setMEIP ; @@ -12679,25 +12679,25 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4759_4760_OR__ETC___d14975 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__4852_4853_OR__ETC___d15068 ; // register csrf_frm_reg assign csrf_frm_reg$D_IN = - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd1) ? csrf_mcycle_ehr_data_lat_0$wget[2:0] : csrf_mcycle_ehr_data_lat_0$wget[7:5] ; assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd2) ; // register csrf_fs_reg @@ -12708,60 +12708,60 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_1 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4759_4760_OR__ETC___d14975 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__4852_4853_OR__ETC___d15068 ; // register csrf_ie_vec_0 assign csrf_ie_vec_0$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ; assign csrf_ie_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) ; // register csrf_ie_vec_1 assign csrf_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_1 ; + !MUX_csrf_ie_vec_1$write_1__SEL_1 && + MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; // register csrf_ie_vec_3 assign csrf_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_1 ; + !MUX_csrf_ie_vec_3$write_1__SEL_1 && + MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo22 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? - cause_code__h702271 : + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + cause_code__h704431 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 || + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd27 ; // register csrf_mcause_interrupt_reg assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[4] : csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 || + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -12769,7 +12769,7 @@ module mkCore(CLK, assign csrf_mcounteren_cy_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -12777,7 +12777,7 @@ module mkCore(CLK, assign csrf_mcounteren_ir_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -12785,7 +12785,7 @@ module mkCore(CLK, assign csrf_mcounteren_tm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -12798,7 +12798,7 @@ module mkCore(CLK, assign csrf_medeleg_13_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd20 ; // register csrf_medeleg_15_reg @@ -12806,7 +12806,7 @@ module mkCore(CLK, assign csrf_medeleg_15_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -12814,20 +12814,20 @@ module mkCore(CLK, assign csrf_medeleg_9_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd20 ; // register csrf_mepc_csr assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[132:69] : rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 || + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd26 ; // register csrf_mideleg_11_reg @@ -12835,7 +12835,7 @@ module mkCore(CLK, assign csrf_mideleg_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -12843,7 +12843,7 @@ module mkCore(CLK, assign csrf_mideleg_1_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -12851,7 +12851,7 @@ module mkCore(CLK, assign csrf_mideleg_5_3_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -12859,7 +12859,7 @@ module mkCore(CLK, assign csrf_mideleg_9_7_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -12871,20 +12871,20 @@ module mkCore(CLK, // register csrf_mpp_reg assign csrf_mpp_reg$D_IN = - MUX_csrf_mpp_reg$write_1__SEL_1 ? - MUX_csrf_mpp_reg$write_1__VAL_1 : - csrf_prv_reg ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_prv_reg : + MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo22 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ; assign csrf_mprv_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18 ; // register csrf_mscratch_csr @@ -12892,20 +12892,20 @@ module mkCore(CLK, assign csrf_mscratch_csr$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd25 ; // register csrf_mtval_csr assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 || + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -12913,7 +12913,7 @@ module mkCore(CLK, assign csrf_mtvec_base_hi_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -12921,7 +12921,7 @@ module mkCore(CLK, assign csrf_mtvec_mode_low_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd23 ; // register csrf_mxr_reg @@ -12929,9 +12929,9 @@ module mkCore(CLK, assign csrf_mxr_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) ; // register csrf_ppn_reg @@ -12939,7 +12939,7 @@ module mkCore(CLK, assign csrf_ppn_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -12947,30 +12947,30 @@ module mkCore(CLK, assign csrf_prev_ie_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) ; // register csrf_prev_ie_vec_1 assign csrf_prev_ie_vec_1$D_IN = - MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : - csrf_ie_vec_1 ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_ie_vec_1 : + MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; // register csrf_prev_ie_vec_3 assign csrf_prev_ie_vec_3$D_IN = - MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_3$write_1__VAL_1 : - csrf_ie_vec_3 ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_ie_vec_3 : + MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; + NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo22 ; // register csrf_prv_reg assign csrf_prv_reg$D_IN = @@ -12985,28 +12985,28 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? - cause_code__h702271 : + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + cause_code__h704431 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 || + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd14 ; // register csrf_scause_interrupt_reg assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[4] : csrf_mscratch_csr$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 || + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -13014,7 +13014,7 @@ module mkCore(CLK, assign csrf_scounteren_cy_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -13022,7 +13022,7 @@ module mkCore(CLK, assign csrf_scounteren_ir_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -13030,20 +13030,20 @@ module mkCore(CLK, assign csrf_scounteren_tm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd11 ; // register csrf_sepc_csr assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[132:69] : rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 || + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -13051,9 +13051,9 @@ module mkCore(CLK, assign csrf_software_int_en_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22) ; // register csrf_software_int_en_vec_1 @@ -13061,9 +13061,9 @@ module mkCore(CLK, assign csrf_software_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22) ; // register csrf_software_int_en_vec_3 @@ -13071,7 +13071,7 @@ module mkCore(CLK, assign csrf_software_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -13095,25 +13095,25 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd29 ; // register csrf_spp_reg assign csrf_spp_reg$D_IN = - MUX_csrf_spp_reg$write_1__SEL_1 ? - MUX_csrf_spp_reg$write_1__VAL_1 : - csrf_prv_reg[0] ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_prv_reg[0] : + MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; assign csrf_sscratch_csr$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd12 ; // register csrf_stats_module_doStats @@ -13122,15 +13122,15 @@ module mkCore(CLK, // register csrf_stval_csr assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 || + csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -13138,7 +13138,7 @@ module mkCore(CLK, assign csrf_stvec_base_hi_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -13146,7 +13146,7 @@ module mkCore(CLK, assign csrf_stvec_mode_low_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd10 ; // register csrf_sum_reg @@ -13154,9 +13154,9 @@ module mkCore(CLK, assign csrf_sum_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) ; // register csrf_time_reg @@ -13168,9 +13168,9 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22) ; // register csrf_timer_int_en_vec_1 @@ -13178,9 +13178,9 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22) ; // register csrf_timer_int_en_vec_3 @@ -13188,7 +13188,7 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -13212,7 +13212,7 @@ module mkCore(CLK, assign csrf_tsr_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18 ; // register csrf_tvm_reg @@ -13220,7 +13220,7 @@ module mkCore(CLK, assign csrf_tvm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18 ; // register csrf_tw_reg @@ -13228,7 +13228,7 @@ module mkCore(CLK, assign csrf_tw_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -13236,7 +13236,7 @@ module mkCore(CLK, assign csrf_vm_mode_sv39_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd17 ; // register flush_reservation @@ -13253,7 +13253,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd16 || rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -13782,9 +13782,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -13933,8 +13933,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h621537, x__h621538, + x__h621539, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -13976,11 +13976,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h669941 == 1'd1 && - fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964) ? + (k__h671298 == 1'd1 && + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14056) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, - fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -13990,13 +13991,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529, - fetchStage_pipelines_1_first__2844_BIT_173_353_ETC___d13605, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589, + fetchStage_pipelines_1_first__2844_BIT_173_359_ETC___d13665, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h684461, + renaming_spec_bits__h686479, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14093,7 +14094,12 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_1_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo16 ; + WILL_FIRE_RL_renameStage_doRenaming && + (k__h671298 == 1'd1 && + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14056 || + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14174 == + 1'd1 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14191) ; assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_1_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ; @@ -14474,12 +14480,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h607298, - b__h606762 == 64'd0, - a__h606761, + { x__h607297, + b__h606761 == 64'd0, + a__h606760, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h607324, - a__h606761[63], + x__h607323, + a__h606760[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -14494,8 +14500,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h607310 : - b__h606762 ; + _theResult___snd__h607309 : + b__h606761 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14508,7 +14514,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h607928, + { x__h607927, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -14589,9 +14595,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], + x__h485745, x__h485746, x__h485747, - x__h485748, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12776 ; @@ -14632,7 +14638,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13976) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14068) ? { IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, @@ -14640,10 +14646,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529, + { IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h684461, + renaming_spec_bits__h686479, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14742,9 +14748,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13976 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14136) ; + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14068 || + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14231) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ; @@ -14797,8 +14803,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h290546, - x__h290558, + { x__h290547, + x__h290559, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890, @@ -14809,13 +14815,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921, - x__h292412, + x__h292413, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h289113 ; + x__h289114 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -15452,13 +15458,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h184326[2:0], - vaddr__h184326, + coreFix_memExe_lsq$getOrigBE << vaddr__h184327[2:0], + vaddr__h184327, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h184326[2:0] != 3'd0 : + vaddr__h184327[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h184326[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184326[0]), + vaddr__h184327[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184327[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12776 ; @@ -15488,8 +15494,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h718458, - prv__h718458 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h720618, + prv__h720618 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15597,44 +15603,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14033) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14125) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14033) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14125) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14033) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14125) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14033) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14125) ? specTagManager$currentSpecBits : - renaming_spec_bits__h684461 ; + renaming_spec_bits__h686479 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14041) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14041) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14041) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14041) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133) ? specTagManager$currentSpecBits : - renaming_spec_bits__h684461 ; + renaming_spec_bits__h686479 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15714,7 +15720,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h184331 ; + shiftData__h184332 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -15814,8 +15820,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h184238, x__h184239, + x__h184240, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12776 ; @@ -16066,9 +16072,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13999) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14091) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2835_BIT_160__ETC___d14015, + IF_fetchStage_pipelines_0_first__2835_BIT_160__ETC___d14107, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -16076,10 +16082,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2844_BIT_160__ETC___d14172, + IF_fetchStage_pipelines_1_first__2844_BIT_160__ETC___d14267, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h684461, + renaming_spec_bits__h686479, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16297,9 +16303,9 @@ module mkCore(CLK, // submodule csrInstOrInterruptInflight_dummy2_1 assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ; assign csrInstOrInterruptInflight_dummy2_1$EN = - MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_1 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[199:195] == 5'd13 ; + fetchStage$pipelines_0_first[199:195] == 5'd13 || + MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ; // submodule csrf_mcycle_ehr_data_dummy2_0 assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ; @@ -16324,7 +16330,7 @@ module mkCore(CLK, assign csrf_stats_module_writeQ$ENQ = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -16333,7 +16339,7 @@ module mkCore(CLK, assign csrf_terminate_module_terminateQ$ENQ = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -16352,8 +16358,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -16361,9 +16367,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14093 && - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 ; + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14188 && + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -16452,8 +16458,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -16461,9 +16467,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14093 && - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 ; + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14188 && + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 ; assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ; assign fetchStage$EN_iTlbIfc_updateVMInfo = MUX_update_vm_info$write_1__SEL_1 ; @@ -16788,7 +16794,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h684461 ; + renaming_spec_bits__h686479 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -16818,8 +16824,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -17031,8 +17037,8 @@ module mkCore(CLK, { fetchStage$pipelines_1_first[387:324], fetchStage$pipelines_1_first[127:96], fetchStage$pipelines_1_first[199:195], - fetchStage_pipelines_1_first__2844_BIT_173_353_ETC___d13605, - 73'h12AAAAAAAAAAAAAAAA8, + fetchStage_pipelines_1_first__2844_BIT_173_359_ETC___d13665, + 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, fetchStage$pipelines_1_first[75] && @@ -17043,11 +17049,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14217 || - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14166, - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14227, + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14310 || + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14261, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14320, 7'd32, - renaming_spec_bits__h684461 } ; + renaming_spec_bits__h686479 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17236,8 +17242,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -17362,8 +17368,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -17475,8 +17481,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -17537,9 +17543,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2833_AND_specTa_ETC___d14047 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14204) ; + (fetchStage_pipelines_0_canDeq__2833_AND_specTa_ETC___d14139 || + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14299) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -17549,10 +17555,10 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h194025), + .amoExec_current_data(curData__h194026), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h195563)); + .amoExec(n__h195564)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, @@ -17586,9 +17592,10 @@ module mkCore(CLK, .basicExec(basicExec___d12686)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, - { fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, + { { fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035 }, fetchStage$pipelines_0_first[160], - x_data_imm__h677222 } }), + x_data_imm__h678579 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17597,10 +17604,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h658934, - x__h617271 != + .checkForException_csrState({ x_decodeInfo_frm__h658939, + r1__read_BITS_13_TO_12___h659124 != 2'd0, - { prv__h718414, + { prv__h720574, csrf_tvm_reg, { csrf_tw_reg, csrf_tsr_reg, @@ -17615,10 +17622,10 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13069)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529, - { fetchStage_pipelines_1_first__2844_BIT_173_353_ETC___d13605, + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589, + { fetchStage_pipelines_1_first__2844_BIT_173_359_ETC___d13665, fetchStage$pipelines_1_first[160], - x_data_imm__h692182 } }), + x_data_imm__h694200 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17627,10 +17634,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h658934, - x__h617271 != + .checkForException_csrState({ x_decodeInfo_frm__h658939, + r1__read_BITS_13_TO_12___h659124 != 2'd0, - { prv__h718414, + { prv__h720574, csrf_tvm_reg, { csrf_tw_reg, csrf_tsr_reg, @@ -17643,143 +17650,143 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13626)); + .checkForException(checkForException___d13686)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h485840), - .execFpuSimple_rVal2(rVal2__h485841), + .execFpuSimple_rVal1(rVal1__h485839), + .execFpuSimple_rVal2(rVal2__h485840), .execFpuSimple(execFpuSimple___d11148)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ? - _theResult___snd__h357627 : - _theResult____h349453 ; + _theResult___snd__h357626 : + _theResult____h349452 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 ? - _theResult___snd__h403317 : - _theResult____h395145 ; + _theResult___snd__h403316 : + _theResult____h395144 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 ? - _theResult___snd__h449005 : - _theResult____h440833 ; + _theResult___snd__h449004 : + _theResult____h440832 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9003 ? - _theResult___snd__h515200 : - _theResult____h506901 ; + _theResult___snd__h515199 : + _theResult____h506900 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9713 ? - _theResult___snd__h593202 : - _theResult____h584903 ; + _theResult___snd__h593201 : + _theResult____h584902 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10476 ? - _theResult___snd__h554001 : - _theResult____h545702 ; + _theResult___snd__h554000 : + _theResult____h545701 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 ? - _theResult___snd__h466771 : - _theResult____h458470 ; + _theResult___snd__h466770 : + _theResult____h458469 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896 ? - _theResult___snd__h375393 : - _theResult____h367092 ; + _theResult___snd__h375392 : + _theResult____h367091 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 ? - _theResult___snd__h421083 : - _theResult____h412782 ; + _theResult___snd__h421082 : + _theResult____h412781 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ? - _theResult___snd__h457587 : - _theResult___snd__h475377 ; + _theResult___snd__h457586 : + _theResult___snd__h475376 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ? - _theResult___snd__h366209 : + _theResult___snd__h366208 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969 ? - _theResult___snd__h366209 : - _theResult___snd__h383999 ; + _theResult___snd__h366208 : + _theResult___snd__h383998 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 ? - _theResult___snd__h411899 : + _theResult___snd__h411898 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361 ? - _theResult___snd__h411899 : - _theResult___snd__h429689 ; + _theResult___snd__h411898 : + _theResult___snd__h429688 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 ? - _theResult___snd__h457587 : + _theResult___snd__h457586 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8691 ? - _theResult___snd__h505549 : + _theResult___snd__h505548 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9053 ? - _theResult___snd__h505549 : - _theResult___snd__h523954 ; + _theResult___snd__h505548 : + _theResult___snd__h523953 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9416 ? - _theResult___snd__h583551 : + _theResult___snd__h583550 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9763 ? - _theResult___snd__h583551 : - _theResult___snd__h601956 ; + _theResult___snd__h583550 : + _theResult___snd__h601955 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10179 ? - _theResult___snd__h544350 : + _theResult___snd__h544349 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10526 ? - _theResult___snd__h544350 : - _theResult___snd__h562755 ; + _theResult___snd__h544349 : + _theResult___snd__h562754 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h357564 == 8'd255) ? + ((_theResult___fst_exp__h357563 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150) : - ((_theResult___fst_exp__h366220 == 8'd255) ? + ((_theResult___fst_exp__h366219 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h357564 == 8'd255) ? + ((_theResult___fst_exp__h357563 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206) : - ((_theResult___fst_exp__h366220 == 8'd255) ? + ((_theResult___fst_exp__h366219 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h403254 == 8'd255) ? + ((_theResult___fst_exp__h403253 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542) : - ((_theResult___fst_exp__h411910 == 8'd255) ? + ((_theResult___fst_exp__h411909 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h403254 == 8'd255) ? + ((_theResult___fst_exp__h403253 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598) : - ((_theResult___fst_exp__h411910 == 8'd255) ? + ((_theResult___fst_exp__h411909 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h448942 == 8'd255) ? + ((_theResult___fst_exp__h448941 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934) : - ((_theResult___fst_exp__h457598 == 8'd255) ? + ((_theResult___fst_exp__h457597 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h448942 == 8'd255) ? + ((_theResult___fst_exp__h448941 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990) : - ((_theResult___fst_exp__h457598 == 8'd255) ? + ((_theResult___fst_exp__h457597 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997) ; assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10009 = @@ -17795,1633 +17802,1651 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10768) : !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 = - (_theResult____h349453[56] ? + (_theResult____h349452[56] ? 6'd0 : - (_theResult____h349453[55] ? + (_theResult____h349452[55] ? 6'd1 : - (_theResult____h349453[54] ? + (_theResult____h349452[54] ? 6'd2 : - (_theResult____h349453[53] ? + (_theResult____h349452[53] ? 6'd3 : - (_theResult____h349453[52] ? + (_theResult____h349452[52] ? 6'd4 : - (_theResult____h349453[51] ? + (_theResult____h349452[51] ? 6'd5 : - (_theResult____h349453[50] ? + (_theResult____h349452[50] ? 6'd6 : - (_theResult____h349453[49] ? + (_theResult____h349452[49] ? 6'd7 : - (_theResult____h349453[48] ? + (_theResult____h349452[48] ? 6'd8 : - (_theResult____h349453[47] ? + (_theResult____h349452[47] ? 6'd9 : - (_theResult____h349453[46] ? + (_theResult____h349452[46] ? 6'd10 : - (_theResult____h349453[45] ? + (_theResult____h349452[45] ? 6'd11 : - (_theResult____h349453[44] ? + (_theResult____h349452[44] ? 6'd12 : - (_theResult____h349453[43] ? + (_theResult____h349452[43] ? 6'd13 : - (_theResult____h349453[42] ? + (_theResult____h349452[42] ? 6'd14 : - (_theResult____h349453[41] ? + (_theResult____h349452[41] ? 6'd15 : - (_theResult____h349453[40] ? + (_theResult____h349452[40] ? 6'd16 : - (_theResult____h349453[39] ? + (_theResult____h349452[39] ? 6'd17 : - (_theResult____h349453[38] ? + (_theResult____h349452[38] ? 6'd18 : - (_theResult____h349453[37] ? + (_theResult____h349452[37] ? 6'd19 : - (_theResult____h349453[36] ? + (_theResult____h349452[36] ? 6'd20 : - (_theResult____h349453[35] ? + (_theResult____h349452[35] ? 6'd21 : - (_theResult____h349453[34] ? + (_theResult____h349452[34] ? 6'd22 : - (_theResult____h349453[33] ? + (_theResult____h349452[33] ? 6'd23 : - (_theResult____h349453[32] ? + (_theResult____h349452[32] ? 6'd24 : - (_theResult____h349453[31] ? + (_theResult____h349452[31] ? 6'd25 : - (_theResult____h349453[30] ? + (_theResult____h349452[30] ? 6'd26 : - (_theResult____h349453[29] ? + (_theResult____h349452[29] ? 6'd27 : - (_theResult____h349453[28] ? + (_theResult____h349452[28] ? 6'd28 : - (_theResult____h349453[27] ? + (_theResult____h349452[27] ? 6'd29 : - (_theResult____h349453[26] ? + (_theResult____h349452[26] ? 6'd30 : - (_theResult____h349453[25] ? + (_theResult____h349452[25] ? 6'd31 : - (_theResult____h349453[24] ? + (_theResult____h349452[24] ? 6'd32 : - (_theResult____h349453[23] ? + (_theResult____h349452[23] ? 6'd33 : - (_theResult____h349453[22] ? + (_theResult____h349452[22] ? 6'd34 : - (_theResult____h349453[21] ? + (_theResult____h349452[21] ? 6'd35 : - (_theResult____h349453[20] ? + (_theResult____h349452[20] ? 6'd36 : - (_theResult____h349453[19] ? + (_theResult____h349452[19] ? 6'd37 : - (_theResult____h349453[18] ? + (_theResult____h349452[18] ? 6'd38 : - (_theResult____h349453[17] ? + (_theResult____h349452[17] ? 6'd39 : - (_theResult____h349453[16] ? + (_theResult____h349452[16] ? 6'd40 : - (_theResult____h349453[15] ? + (_theResult____h349452[15] ? 6'd41 : - (_theResult____h349453[14] ? + (_theResult____h349452[14] ? 6'd42 : - (_theResult____h349453[13] ? + (_theResult____h349452[13] ? 6'd43 : - (_theResult____h349453[12] ? + (_theResult____h349452[12] ? 6'd44 : - (_theResult____h349453[11] ? + (_theResult____h349452[11] ? 6'd45 : - (_theResult____h349453[10] ? + (_theResult____h349452[10] ? 6'd46 : - (_theResult____h349453[9] ? + (_theResult____h349452[9] ? 6'd47 : - (_theResult____h349453[8] ? + (_theResult____h349452[8] ? 6'd48 : - (_theResult____h349453[7] ? + (_theResult____h349452[7] ? 6'd49 : - (_theResult____h349453[6] ? + (_theResult____h349452[6] ? 6'd50 : - (_theResult____h349453[5] ? + (_theResult____h349452[5] ? 6'd51 : - (_theResult____h349453[4] ? + (_theResult____h349452[4] ? 6'd52 : - (_theResult____h349453[3] ? + (_theResult____h349452[3] ? 6'd53 : - (_theResult____h349453[2] ? + (_theResult____h349452[2] ? 6'd54 : - (_theResult____h349453[1] ? + (_theResult____h349452[1] ? 6'd55 : - (_theResult____h349453[0] ? + (_theResult____h349452[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 = - (_theResult____h395145[56] ? + (_theResult____h395144[56] ? 6'd0 : - (_theResult____h395145[55] ? + (_theResult____h395144[55] ? 6'd1 : - (_theResult____h395145[54] ? + (_theResult____h395144[54] ? 6'd2 : - (_theResult____h395145[53] ? + (_theResult____h395144[53] ? 6'd3 : - (_theResult____h395145[52] ? + (_theResult____h395144[52] ? 6'd4 : - (_theResult____h395145[51] ? + (_theResult____h395144[51] ? 6'd5 : - (_theResult____h395145[50] ? + (_theResult____h395144[50] ? 6'd6 : - (_theResult____h395145[49] ? + (_theResult____h395144[49] ? 6'd7 : - (_theResult____h395145[48] ? + (_theResult____h395144[48] ? 6'd8 : - (_theResult____h395145[47] ? + (_theResult____h395144[47] ? 6'd9 : - (_theResult____h395145[46] ? + (_theResult____h395144[46] ? 6'd10 : - (_theResult____h395145[45] ? + (_theResult____h395144[45] ? 6'd11 : - (_theResult____h395145[44] ? + (_theResult____h395144[44] ? 6'd12 : - (_theResult____h395145[43] ? + (_theResult____h395144[43] ? 6'd13 : - (_theResult____h395145[42] ? + (_theResult____h395144[42] ? 6'd14 : - (_theResult____h395145[41] ? + (_theResult____h395144[41] ? 6'd15 : - (_theResult____h395145[40] ? + (_theResult____h395144[40] ? 6'd16 : - (_theResult____h395145[39] ? + (_theResult____h395144[39] ? 6'd17 : - (_theResult____h395145[38] ? + (_theResult____h395144[38] ? 6'd18 : - (_theResult____h395145[37] ? + (_theResult____h395144[37] ? 6'd19 : - (_theResult____h395145[36] ? + (_theResult____h395144[36] ? 6'd20 : - (_theResult____h395145[35] ? + (_theResult____h395144[35] ? 6'd21 : - (_theResult____h395145[34] ? + (_theResult____h395144[34] ? 6'd22 : - (_theResult____h395145[33] ? + (_theResult____h395144[33] ? 6'd23 : - (_theResult____h395145[32] ? + (_theResult____h395144[32] ? 6'd24 : - (_theResult____h395145[31] ? + (_theResult____h395144[31] ? 6'd25 : - (_theResult____h395145[30] ? + (_theResult____h395144[30] ? 6'd26 : - (_theResult____h395145[29] ? + (_theResult____h395144[29] ? 6'd27 : - (_theResult____h395145[28] ? + (_theResult____h395144[28] ? 6'd28 : - (_theResult____h395145[27] ? + (_theResult____h395144[27] ? 6'd29 : - (_theResult____h395145[26] ? + (_theResult____h395144[26] ? 6'd30 : - (_theResult____h395145[25] ? + (_theResult____h395144[25] ? 6'd31 : - (_theResult____h395145[24] ? + (_theResult____h395144[24] ? 6'd32 : - (_theResult____h395145[23] ? + (_theResult____h395144[23] ? 6'd33 : - (_theResult____h395145[22] ? + (_theResult____h395144[22] ? 6'd34 : - (_theResult____h395145[21] ? + (_theResult____h395144[21] ? 6'd35 : - (_theResult____h395145[20] ? + (_theResult____h395144[20] ? 6'd36 : - (_theResult____h395145[19] ? + (_theResult____h395144[19] ? 6'd37 : - (_theResult____h395145[18] ? + (_theResult____h395144[18] ? 6'd38 : - (_theResult____h395145[17] ? + (_theResult____h395144[17] ? 6'd39 : - (_theResult____h395145[16] ? + (_theResult____h395144[16] ? 6'd40 : - (_theResult____h395145[15] ? + (_theResult____h395144[15] ? 6'd41 : - (_theResult____h395145[14] ? + (_theResult____h395144[14] ? 6'd42 : - (_theResult____h395145[13] ? + (_theResult____h395144[13] ? 6'd43 : - (_theResult____h395145[12] ? + (_theResult____h395144[12] ? 6'd44 : - (_theResult____h395145[11] ? + (_theResult____h395144[11] ? 6'd45 : - (_theResult____h395145[10] ? + (_theResult____h395144[10] ? 6'd46 : - (_theResult____h395145[9] ? + (_theResult____h395144[9] ? 6'd47 : - (_theResult____h395145[8] ? + (_theResult____h395144[8] ? 6'd48 : - (_theResult____h395145[7] ? + (_theResult____h395144[7] ? 6'd49 : - (_theResult____h395145[6] ? + (_theResult____h395144[6] ? 6'd50 : - (_theResult____h395145[5] ? + (_theResult____h395144[5] ? 6'd51 : - (_theResult____h395145[4] ? + (_theResult____h395144[4] ? 6'd52 : - (_theResult____h395145[3] ? + (_theResult____h395144[3] ? 6'd53 : - (_theResult____h395145[2] ? + (_theResult____h395144[2] ? 6'd54 : - (_theResult____h395145[1] ? + (_theResult____h395144[1] ? 6'd55 : - (_theResult____h395145[0] ? + (_theResult____h395144[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 = - (_theResult____h440833[56] ? + (_theResult____h440832[56] ? 6'd0 : - (_theResult____h440833[55] ? + (_theResult____h440832[55] ? 6'd1 : - (_theResult____h440833[54] ? + (_theResult____h440832[54] ? 6'd2 : - (_theResult____h440833[53] ? + (_theResult____h440832[53] ? 6'd3 : - (_theResult____h440833[52] ? + (_theResult____h440832[52] ? 6'd4 : - (_theResult____h440833[51] ? + (_theResult____h440832[51] ? 6'd5 : - (_theResult____h440833[50] ? + (_theResult____h440832[50] ? 6'd6 : - (_theResult____h440833[49] ? + (_theResult____h440832[49] ? 6'd7 : - (_theResult____h440833[48] ? + (_theResult____h440832[48] ? 6'd8 : - (_theResult____h440833[47] ? + (_theResult____h440832[47] ? 6'd9 : - (_theResult____h440833[46] ? + (_theResult____h440832[46] ? 6'd10 : - (_theResult____h440833[45] ? + (_theResult____h440832[45] ? 6'd11 : - (_theResult____h440833[44] ? + (_theResult____h440832[44] ? 6'd12 : - (_theResult____h440833[43] ? + (_theResult____h440832[43] ? 6'd13 : - (_theResult____h440833[42] ? + (_theResult____h440832[42] ? 6'd14 : - (_theResult____h440833[41] ? + (_theResult____h440832[41] ? 6'd15 : - (_theResult____h440833[40] ? + (_theResult____h440832[40] ? 6'd16 : - (_theResult____h440833[39] ? + (_theResult____h440832[39] ? 6'd17 : - (_theResult____h440833[38] ? + (_theResult____h440832[38] ? 6'd18 : - (_theResult____h440833[37] ? + (_theResult____h440832[37] ? 6'd19 : - (_theResult____h440833[36] ? + (_theResult____h440832[36] ? 6'd20 : - (_theResult____h440833[35] ? + (_theResult____h440832[35] ? 6'd21 : - (_theResult____h440833[34] ? + (_theResult____h440832[34] ? 6'd22 : - (_theResult____h440833[33] ? + (_theResult____h440832[33] ? 6'd23 : - (_theResult____h440833[32] ? + (_theResult____h440832[32] ? 6'd24 : - (_theResult____h440833[31] ? + (_theResult____h440832[31] ? 6'd25 : - (_theResult____h440833[30] ? + (_theResult____h440832[30] ? 6'd26 : - (_theResult____h440833[29] ? + (_theResult____h440832[29] ? 6'd27 : - (_theResult____h440833[28] ? + (_theResult____h440832[28] ? 6'd28 : - (_theResult____h440833[27] ? + (_theResult____h440832[27] ? 6'd29 : - (_theResult____h440833[26] ? + (_theResult____h440832[26] ? 6'd30 : - (_theResult____h440833[25] ? + (_theResult____h440832[25] ? 6'd31 : - (_theResult____h440833[24] ? + (_theResult____h440832[24] ? 6'd32 : - (_theResult____h440833[23] ? + (_theResult____h440832[23] ? 6'd33 : - (_theResult____h440833[22] ? + (_theResult____h440832[22] ? 6'd34 : - (_theResult____h440833[21] ? + (_theResult____h440832[21] ? 6'd35 : - (_theResult____h440833[20] ? + (_theResult____h440832[20] ? 6'd36 : - (_theResult____h440833[19] ? + (_theResult____h440832[19] ? 6'd37 : - (_theResult____h440833[18] ? + (_theResult____h440832[18] ? 6'd38 : - (_theResult____h440833[17] ? + (_theResult____h440832[17] ? 6'd39 : - (_theResult____h440833[16] ? + (_theResult____h440832[16] ? 6'd40 : - (_theResult____h440833[15] ? + (_theResult____h440832[15] ? 6'd41 : - (_theResult____h440833[14] ? + (_theResult____h440832[14] ? 6'd42 : - (_theResult____h440833[13] ? + (_theResult____h440832[13] ? 6'd43 : - (_theResult____h440833[12] ? + (_theResult____h440832[12] ? 6'd44 : - (_theResult____h440833[11] ? + (_theResult____h440832[11] ? 6'd45 : - (_theResult____h440833[10] ? + (_theResult____h440832[10] ? 6'd46 : - (_theResult____h440833[9] ? + (_theResult____h440832[9] ? 6'd47 : - (_theResult____h440833[8] ? + (_theResult____h440832[8] ? 6'd48 : - (_theResult____h440833[7] ? + (_theResult____h440832[7] ? 6'd49 : - (_theResult____h440833[6] ? + (_theResult____h440832[6] ? 6'd50 : - (_theResult____h440833[5] ? + (_theResult____h440832[5] ? 6'd51 : - (_theResult____h440833[4] ? + (_theResult____h440832[4] ? 6'd52 : - (_theResult____h440833[3] ? + (_theResult____h440832[3] ? 6'd53 : - (_theResult____h440833[2] ? + (_theResult____h440832[2] ? 6'd54 : - (_theResult____h440833[1] ? + (_theResult____h440832[1] ? 6'd55 : - (_theResult____h440833[0] ? + (_theResult____h440832[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10474 = - (_theResult____h545702[56] ? + (_theResult____h545701[56] ? 6'd0 : - (_theResult____h545702[55] ? + (_theResult____h545701[55] ? 6'd1 : - (_theResult____h545702[54] ? + (_theResult____h545701[54] ? 6'd2 : - (_theResult____h545702[53] ? + (_theResult____h545701[53] ? 6'd3 : - (_theResult____h545702[52] ? + (_theResult____h545701[52] ? 6'd4 : - (_theResult____h545702[51] ? + (_theResult____h545701[51] ? 6'd5 : - (_theResult____h545702[50] ? + (_theResult____h545701[50] ? 6'd6 : - (_theResult____h545702[49] ? + (_theResult____h545701[49] ? 6'd7 : - (_theResult____h545702[48] ? + (_theResult____h545701[48] ? 6'd8 : - (_theResult____h545702[47] ? + (_theResult____h545701[47] ? 6'd9 : - (_theResult____h545702[46] ? + (_theResult____h545701[46] ? 6'd10 : - (_theResult____h545702[45] ? + (_theResult____h545701[45] ? 6'd11 : - (_theResult____h545702[44] ? + (_theResult____h545701[44] ? 6'd12 : - (_theResult____h545702[43] ? + (_theResult____h545701[43] ? 6'd13 : - (_theResult____h545702[42] ? + (_theResult____h545701[42] ? 6'd14 : - (_theResult____h545702[41] ? + (_theResult____h545701[41] ? 6'd15 : - (_theResult____h545702[40] ? + (_theResult____h545701[40] ? 6'd16 : - (_theResult____h545702[39] ? + (_theResult____h545701[39] ? 6'd17 : - (_theResult____h545702[38] ? + (_theResult____h545701[38] ? 6'd18 : - (_theResult____h545702[37] ? + (_theResult____h545701[37] ? 6'd19 : - (_theResult____h545702[36] ? + (_theResult____h545701[36] ? 6'd20 : - (_theResult____h545702[35] ? + (_theResult____h545701[35] ? 6'd21 : - (_theResult____h545702[34] ? + (_theResult____h545701[34] ? 6'd22 : - (_theResult____h545702[33] ? + (_theResult____h545701[33] ? 6'd23 : - (_theResult____h545702[32] ? + (_theResult____h545701[32] ? 6'd24 : - (_theResult____h545702[31] ? + (_theResult____h545701[31] ? 6'd25 : - (_theResult____h545702[30] ? + (_theResult____h545701[30] ? 6'd26 : - (_theResult____h545702[29] ? + (_theResult____h545701[29] ? 6'd27 : - (_theResult____h545702[28] ? + (_theResult____h545701[28] ? 6'd28 : - (_theResult____h545702[27] ? + (_theResult____h545701[27] ? 6'd29 : - (_theResult____h545702[26] ? + (_theResult____h545701[26] ? 6'd30 : - (_theResult____h545702[25] ? + (_theResult____h545701[25] ? 6'd31 : - (_theResult____h545702[24] ? + (_theResult____h545701[24] ? 6'd32 : - (_theResult____h545702[23] ? + (_theResult____h545701[23] ? 6'd33 : - (_theResult____h545702[22] ? + (_theResult____h545701[22] ? 6'd34 : - (_theResult____h545702[21] ? + (_theResult____h545701[21] ? 6'd35 : - (_theResult____h545702[20] ? + (_theResult____h545701[20] ? 6'd36 : - (_theResult____h545702[19] ? + (_theResult____h545701[19] ? 6'd37 : - (_theResult____h545702[18] ? + (_theResult____h545701[18] ? 6'd38 : - (_theResult____h545702[17] ? + (_theResult____h545701[17] ? 6'd39 : - (_theResult____h545702[16] ? + (_theResult____h545701[16] ? 6'd40 : - (_theResult____h545702[15] ? + (_theResult____h545701[15] ? 6'd41 : - (_theResult____h545702[14] ? + (_theResult____h545701[14] ? 6'd42 : - (_theResult____h545702[13] ? + (_theResult____h545701[13] ? 6'd43 : - (_theResult____h545702[12] ? + (_theResult____h545701[12] ? 6'd44 : - (_theResult____h545702[11] ? + (_theResult____h545701[11] ? 6'd45 : - (_theResult____h545702[10] ? + (_theResult____h545701[10] ? 6'd46 : - (_theResult____h545702[9] ? + (_theResult____h545701[9] ? 6'd47 : - (_theResult____h545702[8] ? + (_theResult____h545701[8] ? 6'd48 : - (_theResult____h545702[7] ? + (_theResult____h545701[7] ? 6'd49 : - (_theResult____h545702[6] ? + (_theResult____h545701[6] ? 6'd50 : - (_theResult____h545702[5] ? + (_theResult____h545701[5] ? 6'd51 : - (_theResult____h545702[4] ? + (_theResult____h545701[4] ? 6'd52 : - (_theResult____h545702[3] ? + (_theResult____h545701[3] ? 6'd53 : - (_theResult____h545702[2] ? + (_theResult____h545701[2] ? 6'd54 : - (_theResult____h545702[1] ? + (_theResult____h545701[1] ? 6'd55 : - (_theResult____h545702[0] ? + (_theResult____h545701[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9001 = - (_theResult____h506901[56] ? + (_theResult____h506900[56] ? 6'd0 : - (_theResult____h506901[55] ? + (_theResult____h506900[55] ? 6'd1 : - (_theResult____h506901[54] ? + (_theResult____h506900[54] ? 6'd2 : - (_theResult____h506901[53] ? + (_theResult____h506900[53] ? 6'd3 : - (_theResult____h506901[52] ? + (_theResult____h506900[52] ? 6'd4 : - (_theResult____h506901[51] ? + (_theResult____h506900[51] ? 6'd5 : - (_theResult____h506901[50] ? + (_theResult____h506900[50] ? 6'd6 : - (_theResult____h506901[49] ? + (_theResult____h506900[49] ? 6'd7 : - (_theResult____h506901[48] ? + (_theResult____h506900[48] ? 6'd8 : - (_theResult____h506901[47] ? + (_theResult____h506900[47] ? 6'd9 : - (_theResult____h506901[46] ? + (_theResult____h506900[46] ? 6'd10 : - (_theResult____h506901[45] ? + (_theResult____h506900[45] ? 6'd11 : - (_theResult____h506901[44] ? + (_theResult____h506900[44] ? 6'd12 : - (_theResult____h506901[43] ? + (_theResult____h506900[43] ? 6'd13 : - (_theResult____h506901[42] ? + (_theResult____h506900[42] ? 6'd14 : - (_theResult____h506901[41] ? + (_theResult____h506900[41] ? 6'd15 : - (_theResult____h506901[40] ? + (_theResult____h506900[40] ? 6'd16 : - (_theResult____h506901[39] ? + (_theResult____h506900[39] ? 6'd17 : - (_theResult____h506901[38] ? + (_theResult____h506900[38] ? 6'd18 : - (_theResult____h506901[37] ? + (_theResult____h506900[37] ? 6'd19 : - (_theResult____h506901[36] ? + (_theResult____h506900[36] ? 6'd20 : - (_theResult____h506901[35] ? + (_theResult____h506900[35] ? 6'd21 : - (_theResult____h506901[34] ? + (_theResult____h506900[34] ? 6'd22 : - (_theResult____h506901[33] ? + (_theResult____h506900[33] ? 6'd23 : - (_theResult____h506901[32] ? + (_theResult____h506900[32] ? 6'd24 : - (_theResult____h506901[31] ? + (_theResult____h506900[31] ? 6'd25 : - (_theResult____h506901[30] ? + (_theResult____h506900[30] ? 6'd26 : - (_theResult____h506901[29] ? + (_theResult____h506900[29] ? 6'd27 : - (_theResult____h506901[28] ? + (_theResult____h506900[28] ? 6'd28 : - (_theResult____h506901[27] ? + (_theResult____h506900[27] ? 6'd29 : - (_theResult____h506901[26] ? + (_theResult____h506900[26] ? 6'd30 : - (_theResult____h506901[25] ? + (_theResult____h506900[25] ? 6'd31 : - (_theResult____h506901[24] ? + (_theResult____h506900[24] ? 6'd32 : - (_theResult____h506901[23] ? + (_theResult____h506900[23] ? 6'd33 : - (_theResult____h506901[22] ? + (_theResult____h506900[22] ? 6'd34 : - (_theResult____h506901[21] ? + (_theResult____h506900[21] ? 6'd35 : - (_theResult____h506901[20] ? + (_theResult____h506900[20] ? 6'd36 : - (_theResult____h506901[19] ? + (_theResult____h506900[19] ? 6'd37 : - (_theResult____h506901[18] ? + (_theResult____h506900[18] ? 6'd38 : - (_theResult____h506901[17] ? + (_theResult____h506900[17] ? 6'd39 : - (_theResult____h506901[16] ? + (_theResult____h506900[16] ? 6'd40 : - (_theResult____h506901[15] ? + (_theResult____h506900[15] ? 6'd41 : - (_theResult____h506901[14] ? + (_theResult____h506900[14] ? 6'd42 : - (_theResult____h506901[13] ? + (_theResult____h506900[13] ? 6'd43 : - (_theResult____h506901[12] ? + (_theResult____h506900[12] ? 6'd44 : - (_theResult____h506901[11] ? + (_theResult____h506900[11] ? 6'd45 : - (_theResult____h506901[10] ? + (_theResult____h506900[10] ? 6'd46 : - (_theResult____h506901[9] ? + (_theResult____h506900[9] ? 6'd47 : - (_theResult____h506901[8] ? + (_theResult____h506900[8] ? 6'd48 : - (_theResult____h506901[7] ? + (_theResult____h506900[7] ? 6'd49 : - (_theResult____h506901[6] ? + (_theResult____h506900[6] ? 6'd50 : - (_theResult____h506901[5] ? + (_theResult____h506900[5] ? 6'd51 : - (_theResult____h506901[4] ? + (_theResult____h506900[4] ? 6'd52 : - (_theResult____h506901[3] ? + (_theResult____h506900[3] ? 6'd53 : - (_theResult____h506901[2] ? + (_theResult____h506900[2] ? 6'd54 : - (_theResult____h506901[1] ? + (_theResult____h506900[1] ? 6'd55 : - (_theResult____h506901[0] ? + (_theResult____h506900[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9711 = - (_theResult____h584903[56] ? + (_theResult____h584902[56] ? 6'd0 : - (_theResult____h584903[55] ? + (_theResult____h584902[55] ? 6'd1 : - (_theResult____h584903[54] ? + (_theResult____h584902[54] ? 6'd2 : - (_theResult____h584903[53] ? + (_theResult____h584902[53] ? 6'd3 : - (_theResult____h584903[52] ? + (_theResult____h584902[52] ? 6'd4 : - (_theResult____h584903[51] ? + (_theResult____h584902[51] ? 6'd5 : - (_theResult____h584903[50] ? + (_theResult____h584902[50] ? 6'd6 : - (_theResult____h584903[49] ? + (_theResult____h584902[49] ? 6'd7 : - (_theResult____h584903[48] ? + (_theResult____h584902[48] ? 6'd8 : - (_theResult____h584903[47] ? + (_theResult____h584902[47] ? 6'd9 : - (_theResult____h584903[46] ? + (_theResult____h584902[46] ? 6'd10 : - (_theResult____h584903[45] ? + (_theResult____h584902[45] ? 6'd11 : - (_theResult____h584903[44] ? + (_theResult____h584902[44] ? 6'd12 : - (_theResult____h584903[43] ? + (_theResult____h584902[43] ? 6'd13 : - (_theResult____h584903[42] ? + (_theResult____h584902[42] ? 6'd14 : - (_theResult____h584903[41] ? + (_theResult____h584902[41] ? 6'd15 : - (_theResult____h584903[40] ? + (_theResult____h584902[40] ? 6'd16 : - (_theResult____h584903[39] ? + (_theResult____h584902[39] ? 6'd17 : - (_theResult____h584903[38] ? + (_theResult____h584902[38] ? 6'd18 : - (_theResult____h584903[37] ? + (_theResult____h584902[37] ? 6'd19 : - (_theResult____h584903[36] ? + (_theResult____h584902[36] ? 6'd20 : - (_theResult____h584903[35] ? + (_theResult____h584902[35] ? 6'd21 : - (_theResult____h584903[34] ? + (_theResult____h584902[34] ? 6'd22 : - (_theResult____h584903[33] ? + (_theResult____h584902[33] ? 6'd23 : - (_theResult____h584903[32] ? + (_theResult____h584902[32] ? 6'd24 : - (_theResult____h584903[31] ? + (_theResult____h584902[31] ? 6'd25 : - (_theResult____h584903[30] ? + (_theResult____h584902[30] ? 6'd26 : - (_theResult____h584903[29] ? + (_theResult____h584902[29] ? 6'd27 : - (_theResult____h584903[28] ? + (_theResult____h584902[28] ? 6'd28 : - (_theResult____h584903[27] ? + (_theResult____h584902[27] ? 6'd29 : - (_theResult____h584903[26] ? + (_theResult____h584902[26] ? 6'd30 : - (_theResult____h584903[25] ? + (_theResult____h584902[25] ? 6'd31 : - (_theResult____h584903[24] ? + (_theResult____h584902[24] ? 6'd32 : - (_theResult____h584903[23] ? + (_theResult____h584902[23] ? 6'd33 : - (_theResult____h584903[22] ? + (_theResult____h584902[22] ? 6'd34 : - (_theResult____h584903[21] ? + (_theResult____h584902[21] ? 6'd35 : - (_theResult____h584903[20] ? + (_theResult____h584902[20] ? 6'd36 : - (_theResult____h584903[19] ? + (_theResult____h584902[19] ? 6'd37 : - (_theResult____h584903[18] ? + (_theResult____h584902[18] ? 6'd38 : - (_theResult____h584903[17] ? + (_theResult____h584902[17] ? 6'd39 : - (_theResult____h584903[16] ? + (_theResult____h584902[16] ? 6'd40 : - (_theResult____h584903[15] ? + (_theResult____h584902[15] ? 6'd41 : - (_theResult____h584903[14] ? + (_theResult____h584902[14] ? 6'd42 : - (_theResult____h584903[13] ? + (_theResult____h584902[13] ? 6'd43 : - (_theResult____h584903[12] ? + (_theResult____h584902[12] ? 6'd44 : - (_theResult____h584903[11] ? + (_theResult____h584902[11] ? 6'd45 : - (_theResult____h584903[10] ? + (_theResult____h584902[10] ? 6'd46 : - (_theResult____h584903[9] ? + (_theResult____h584902[9] ? 6'd47 : - (_theResult____h584903[8] ? + (_theResult____h584902[8] ? 6'd48 : - (_theResult____h584903[7] ? + (_theResult____h584902[7] ? 6'd49 : - (_theResult____h584903[6] ? + (_theResult____h584902[6] ? 6'd50 : - (_theResult____h584903[5] ? + (_theResult____h584902[5] ? 6'd51 : - (_theResult____h584903[4] ? + (_theResult____h584902[4] ? 6'd52 : - (_theResult____h584903[3] ? + (_theResult____h584902[3] ? 6'd53 : - (_theResult____h584903[2] ? + (_theResult____h584902[2] ? 6'd54 : - (_theResult____h584903[1] ? + (_theResult____h584902[1] ? 6'd55 : - (_theResult____h584903[0] ? + (_theResult____h584902[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 = - (_theResult____h367092[56] ? + (_theResult____h367091[56] ? 6'd0 : - (_theResult____h367092[55] ? + (_theResult____h367091[55] ? 6'd1 : - (_theResult____h367092[54] ? + (_theResult____h367091[54] ? 6'd2 : - (_theResult____h367092[53] ? + (_theResult____h367091[53] ? 6'd3 : - (_theResult____h367092[52] ? + (_theResult____h367091[52] ? 6'd4 : - (_theResult____h367092[51] ? + (_theResult____h367091[51] ? 6'd5 : - (_theResult____h367092[50] ? + (_theResult____h367091[50] ? 6'd6 : - (_theResult____h367092[49] ? + (_theResult____h367091[49] ? 6'd7 : - (_theResult____h367092[48] ? + (_theResult____h367091[48] ? 6'd8 : - (_theResult____h367092[47] ? + (_theResult____h367091[47] ? 6'd9 : - (_theResult____h367092[46] ? + (_theResult____h367091[46] ? 6'd10 : - (_theResult____h367092[45] ? + (_theResult____h367091[45] ? 6'd11 : - (_theResult____h367092[44] ? + (_theResult____h367091[44] ? 6'd12 : - (_theResult____h367092[43] ? + (_theResult____h367091[43] ? 6'd13 : - (_theResult____h367092[42] ? + (_theResult____h367091[42] ? 6'd14 : - (_theResult____h367092[41] ? + (_theResult____h367091[41] ? 6'd15 : - (_theResult____h367092[40] ? + (_theResult____h367091[40] ? 6'd16 : - (_theResult____h367092[39] ? + (_theResult____h367091[39] ? 6'd17 : - (_theResult____h367092[38] ? + (_theResult____h367091[38] ? 6'd18 : - (_theResult____h367092[37] ? + (_theResult____h367091[37] ? 6'd19 : - (_theResult____h367092[36] ? + (_theResult____h367091[36] ? 6'd20 : - (_theResult____h367092[35] ? + (_theResult____h367091[35] ? 6'd21 : - (_theResult____h367092[34] ? + (_theResult____h367091[34] ? 6'd22 : - (_theResult____h367092[33] ? + (_theResult____h367091[33] ? 6'd23 : - (_theResult____h367092[32] ? + (_theResult____h367091[32] ? 6'd24 : - (_theResult____h367092[31] ? + (_theResult____h367091[31] ? 6'd25 : - (_theResult____h367092[30] ? + (_theResult____h367091[30] ? 6'd26 : - (_theResult____h367092[29] ? + (_theResult____h367091[29] ? 6'd27 : - (_theResult____h367092[28] ? + (_theResult____h367091[28] ? 6'd28 : - (_theResult____h367092[27] ? + (_theResult____h367091[27] ? 6'd29 : - (_theResult____h367092[26] ? + (_theResult____h367091[26] ? 6'd30 : - (_theResult____h367092[25] ? + (_theResult____h367091[25] ? 6'd31 : - (_theResult____h367092[24] ? + (_theResult____h367091[24] ? 6'd32 : - (_theResult____h367092[23] ? + (_theResult____h367091[23] ? 6'd33 : - (_theResult____h367092[22] ? + (_theResult____h367091[22] ? 6'd34 : - (_theResult____h367092[21] ? + (_theResult____h367091[21] ? 6'd35 : - (_theResult____h367092[20] ? + (_theResult____h367091[20] ? 6'd36 : - (_theResult____h367092[19] ? + (_theResult____h367091[19] ? 6'd37 : - (_theResult____h367092[18] ? + (_theResult____h367091[18] ? 6'd38 : - (_theResult____h367092[17] ? + (_theResult____h367091[17] ? 6'd39 : - (_theResult____h367092[16] ? + (_theResult____h367091[16] ? 6'd40 : - (_theResult____h367092[15] ? + (_theResult____h367091[15] ? 6'd41 : - (_theResult____h367092[14] ? + (_theResult____h367091[14] ? 6'd42 : - (_theResult____h367092[13] ? + (_theResult____h367091[13] ? 6'd43 : - (_theResult____h367092[12] ? + (_theResult____h367091[12] ? 6'd44 : - (_theResult____h367092[11] ? + (_theResult____h367091[11] ? 6'd45 : - (_theResult____h367092[10] ? + (_theResult____h367091[10] ? 6'd46 : - (_theResult____h367092[9] ? + (_theResult____h367091[9] ? 6'd47 : - (_theResult____h367092[8] ? + (_theResult____h367091[8] ? 6'd48 : - (_theResult____h367092[7] ? + (_theResult____h367091[7] ? 6'd49 : - (_theResult____h367092[6] ? + (_theResult____h367091[6] ? 6'd50 : - (_theResult____h367092[5] ? + (_theResult____h367091[5] ? 6'd51 : - (_theResult____h367092[4] ? + (_theResult____h367091[4] ? 6'd52 : - (_theResult____h367092[3] ? + (_theResult____h367091[3] ? 6'd53 : - (_theResult____h367092[2] ? + (_theResult____h367091[2] ? 6'd54 : - (_theResult____h367092[1] ? + (_theResult____h367091[1] ? 6'd55 : - (_theResult____h367092[0] ? + (_theResult____h367091[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 = - (_theResult____h412782[56] ? + (_theResult____h412781[56] ? 6'd0 : - (_theResult____h412782[55] ? + (_theResult____h412781[55] ? 6'd1 : - (_theResult____h412782[54] ? + (_theResult____h412781[54] ? 6'd2 : - (_theResult____h412782[53] ? + (_theResult____h412781[53] ? 6'd3 : - (_theResult____h412782[52] ? + (_theResult____h412781[52] ? 6'd4 : - (_theResult____h412782[51] ? + (_theResult____h412781[51] ? 6'd5 : - (_theResult____h412782[50] ? + (_theResult____h412781[50] ? 6'd6 : - (_theResult____h412782[49] ? + (_theResult____h412781[49] ? 6'd7 : - (_theResult____h412782[48] ? + (_theResult____h412781[48] ? 6'd8 : - (_theResult____h412782[47] ? + (_theResult____h412781[47] ? 6'd9 : - (_theResult____h412782[46] ? + (_theResult____h412781[46] ? 6'd10 : - (_theResult____h412782[45] ? + (_theResult____h412781[45] ? 6'd11 : - (_theResult____h412782[44] ? + (_theResult____h412781[44] ? 6'd12 : - (_theResult____h412782[43] ? + (_theResult____h412781[43] ? 6'd13 : - (_theResult____h412782[42] ? + (_theResult____h412781[42] ? 6'd14 : - (_theResult____h412782[41] ? + (_theResult____h412781[41] ? 6'd15 : - (_theResult____h412782[40] ? + (_theResult____h412781[40] ? 6'd16 : - (_theResult____h412782[39] ? + (_theResult____h412781[39] ? 6'd17 : - (_theResult____h412782[38] ? + (_theResult____h412781[38] ? 6'd18 : - (_theResult____h412782[37] ? + (_theResult____h412781[37] ? 6'd19 : - (_theResult____h412782[36] ? + (_theResult____h412781[36] ? 6'd20 : - (_theResult____h412782[35] ? + (_theResult____h412781[35] ? 6'd21 : - (_theResult____h412782[34] ? + (_theResult____h412781[34] ? 6'd22 : - (_theResult____h412782[33] ? + (_theResult____h412781[33] ? 6'd23 : - (_theResult____h412782[32] ? + (_theResult____h412781[32] ? 6'd24 : - (_theResult____h412782[31] ? + (_theResult____h412781[31] ? 6'd25 : - (_theResult____h412782[30] ? + (_theResult____h412781[30] ? 6'd26 : - (_theResult____h412782[29] ? + (_theResult____h412781[29] ? 6'd27 : - (_theResult____h412782[28] ? + (_theResult____h412781[28] ? 6'd28 : - (_theResult____h412782[27] ? + (_theResult____h412781[27] ? 6'd29 : - (_theResult____h412782[26] ? + (_theResult____h412781[26] ? 6'd30 : - (_theResult____h412782[25] ? + (_theResult____h412781[25] ? 6'd31 : - (_theResult____h412782[24] ? + (_theResult____h412781[24] ? 6'd32 : - (_theResult____h412782[23] ? + (_theResult____h412781[23] ? 6'd33 : - (_theResult____h412782[22] ? + (_theResult____h412781[22] ? 6'd34 : - (_theResult____h412782[21] ? + (_theResult____h412781[21] ? 6'd35 : - (_theResult____h412782[20] ? + (_theResult____h412781[20] ? 6'd36 : - (_theResult____h412782[19] ? + (_theResult____h412781[19] ? 6'd37 : - (_theResult____h412782[18] ? + (_theResult____h412781[18] ? 6'd38 : - (_theResult____h412782[17] ? + (_theResult____h412781[17] ? 6'd39 : - (_theResult____h412782[16] ? + (_theResult____h412781[16] ? 6'd40 : - (_theResult____h412782[15] ? + (_theResult____h412781[15] ? 6'd41 : - (_theResult____h412782[14] ? + (_theResult____h412781[14] ? 6'd42 : - (_theResult____h412782[13] ? + (_theResult____h412781[13] ? 6'd43 : - (_theResult____h412782[12] ? + (_theResult____h412781[12] ? 6'd44 : - (_theResult____h412782[11] ? + (_theResult____h412781[11] ? 6'd45 : - (_theResult____h412782[10] ? + (_theResult____h412781[10] ? 6'd46 : - (_theResult____h412782[9] ? + (_theResult____h412781[9] ? 6'd47 : - (_theResult____h412782[8] ? + (_theResult____h412781[8] ? 6'd48 : - (_theResult____h412782[7] ? + (_theResult____h412781[7] ? 6'd49 : - (_theResult____h412782[6] ? + (_theResult____h412781[6] ? 6'd50 : - (_theResult____h412782[5] ? + (_theResult____h412781[5] ? 6'd51 : - (_theResult____h412782[4] ? + (_theResult____h412781[4] ? 6'd52 : - (_theResult____h412782[3] ? + (_theResult____h412781[3] ? 6'd53 : - (_theResult____h412782[2] ? + (_theResult____h412781[2] ? 6'd54 : - (_theResult____h412782[1] ? + (_theResult____h412781[1] ? 6'd55 : - (_theResult____h412782[0] ? + (_theResult____h412781[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 = - (_theResult____h458470[56] ? + (_theResult____h458469[56] ? 6'd0 : - (_theResult____h458470[55] ? + (_theResult____h458469[55] ? 6'd1 : - (_theResult____h458470[54] ? + (_theResult____h458469[54] ? 6'd2 : - (_theResult____h458470[53] ? + (_theResult____h458469[53] ? 6'd3 : - (_theResult____h458470[52] ? + (_theResult____h458469[52] ? 6'd4 : - (_theResult____h458470[51] ? + (_theResult____h458469[51] ? 6'd5 : - (_theResult____h458470[50] ? + (_theResult____h458469[50] ? 6'd6 : - (_theResult____h458470[49] ? + (_theResult____h458469[49] ? 6'd7 : - (_theResult____h458470[48] ? + (_theResult____h458469[48] ? 6'd8 : - (_theResult____h458470[47] ? + (_theResult____h458469[47] ? 6'd9 : - (_theResult____h458470[46] ? + (_theResult____h458469[46] ? 6'd10 : - (_theResult____h458470[45] ? + (_theResult____h458469[45] ? 6'd11 : - (_theResult____h458470[44] ? + (_theResult____h458469[44] ? 6'd12 : - (_theResult____h458470[43] ? + (_theResult____h458469[43] ? 6'd13 : - (_theResult____h458470[42] ? + (_theResult____h458469[42] ? 6'd14 : - (_theResult____h458470[41] ? + (_theResult____h458469[41] ? 6'd15 : - (_theResult____h458470[40] ? + (_theResult____h458469[40] ? 6'd16 : - (_theResult____h458470[39] ? + (_theResult____h458469[39] ? 6'd17 : - (_theResult____h458470[38] ? + (_theResult____h458469[38] ? 6'd18 : - (_theResult____h458470[37] ? + (_theResult____h458469[37] ? 6'd19 : - (_theResult____h458470[36] ? + (_theResult____h458469[36] ? 6'd20 : - (_theResult____h458470[35] ? + (_theResult____h458469[35] ? 6'd21 : - (_theResult____h458470[34] ? + (_theResult____h458469[34] ? 6'd22 : - (_theResult____h458470[33] ? + (_theResult____h458469[33] ? 6'd23 : - (_theResult____h458470[32] ? + (_theResult____h458469[32] ? 6'd24 : - (_theResult____h458470[31] ? + (_theResult____h458469[31] ? 6'd25 : - (_theResult____h458470[30] ? + (_theResult____h458469[30] ? 6'd26 : - (_theResult____h458470[29] ? + (_theResult____h458469[29] ? 6'd27 : - (_theResult____h458470[28] ? + (_theResult____h458469[28] ? 6'd28 : - (_theResult____h458470[27] ? + (_theResult____h458469[27] ? 6'd29 : - (_theResult____h458470[26] ? + (_theResult____h458469[26] ? 6'd30 : - (_theResult____h458470[25] ? + (_theResult____h458469[25] ? 6'd31 : - (_theResult____h458470[24] ? + (_theResult____h458469[24] ? 6'd32 : - (_theResult____h458470[23] ? + (_theResult____h458469[23] ? 6'd33 : - (_theResult____h458470[22] ? + (_theResult____h458469[22] ? 6'd34 : - (_theResult____h458470[21] ? + (_theResult____h458469[21] ? 6'd35 : - (_theResult____h458470[20] ? + (_theResult____h458469[20] ? 6'd36 : - (_theResult____h458470[19] ? + (_theResult____h458469[19] ? 6'd37 : - (_theResult____h458470[18] ? + (_theResult____h458469[18] ? 6'd38 : - (_theResult____h458470[17] ? + (_theResult____h458469[17] ? 6'd39 : - (_theResult____h458470[16] ? + (_theResult____h458469[16] ? 6'd40 : - (_theResult____h458470[15] ? + (_theResult____h458469[15] ? 6'd41 : - (_theResult____h458470[14] ? + (_theResult____h458469[14] ? 6'd42 : - (_theResult____h458470[13] ? + (_theResult____h458469[13] ? 6'd43 : - (_theResult____h458470[12] ? + (_theResult____h458469[12] ? 6'd44 : - (_theResult____h458470[11] ? + (_theResult____h458469[11] ? 6'd45 : - (_theResult____h458470[10] ? + (_theResult____h458469[10] ? 6'd46 : - (_theResult____h458470[9] ? + (_theResult____h458469[9] ? 6'd47 : - (_theResult____h458470[8] ? + (_theResult____h458469[8] ? 6'd48 : - (_theResult____h458470[7] ? + (_theResult____h458469[7] ? 6'd49 : - (_theResult____h458470[6] ? + (_theResult____h458469[6] ? 6'd50 : - (_theResult____h458470[5] ? + (_theResult____h458469[5] ? 6'd51 : - (_theResult____h458470[4] ? + (_theResult____h458469[4] ? 6'd52 : - (_theResult____h458470[3] ? + (_theResult____h458469[3] ? 6'd53 : - (_theResult____h458470[2] ? + (_theResult____h458469[2] ? 6'd54 : - (_theResult____h458470[1] ? + (_theResult____h458469[1] ? 6'd55 : - (_theResult____h458470[0] ? + (_theResult____h458469[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10021 = - (_theResult___fst_exp__h593139 == 11'd2047) ? + (_theResult___fst_exp__h593138 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard84913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard84912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10518 = - (_theResult___fst_exp__h553938 == 11'd2047) ? + (_theResult___fst_exp__h553937 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; + CASE_guard45711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10783 = - (_theResult___fst_exp__h553938 == 11'd2047) ? + (_theResult___fst_exp__h553937 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard45712_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard45711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9045 = - (_theResult___fst_exp__h515137 == 11'd2047) ? + (_theResult___fst_exp__h515136 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard06911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard06910_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9755 = - (_theResult___fst_exp__h593139 == 11'd2047) ? + (_theResult___fst_exp__h593138 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard84913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard84912_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 = - (guard__h349463 == 2'b0 || + (guard__h349462 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h357564 : - _theResult___exp__h358080 ; + _theResult___fst_exp__h357563 : + _theResult___exp__h358079 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 = - (guard__h349463 == 2'b0) ? - _theResult___fst_exp__h357564 : + (guard__h349462 == 2'b0) ? + _theResult___fst_exp__h357563 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h358080 : - _theResult___fst_exp__h357564) ; + _theResult___exp__h358079 : + _theResult___fst_exp__h357563) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 = - (guard__h349463 == 2'b0 || + (guard__h349462 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h357558[56:34] : - _theResult___sfd__h358081 ; + sfdin__h357557[56:34] : + _theResult___sfd__h358080 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 = - (guard__h349463 == 2'b0) ? - sfdin__h357558[56:34] : + (guard__h349462 == 2'b0) ? + sfdin__h357557[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h358081 : - sfdin__h357558[56:34]) ; + _theResult___sfd__h358080 : + sfdin__h357557[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 = - (guard__h395155 == 2'b0 || + (guard__h395154 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h403254 : - _theResult___exp__h403770 ; + _theResult___fst_exp__h403253 : + _theResult___exp__h403769 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 = - (guard__h395155 == 2'b0) ? - _theResult___fst_exp__h403254 : + (guard__h395154 == 2'b0) ? + _theResult___fst_exp__h403253 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h403770 : - _theResult___fst_exp__h403254) ; + _theResult___exp__h403769 : + _theResult___fst_exp__h403253) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 = - (guard__h395155 == 2'b0 || + (guard__h395154 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h403248[56:34] : - _theResult___sfd__h403771 ; + sfdin__h403247[56:34] : + _theResult___sfd__h403770 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 = - (guard__h395155 == 2'b0) ? - sfdin__h403248[56:34] : + (guard__h395154 == 2'b0) ? + sfdin__h403247[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h403771 : - sfdin__h403248[56:34]) ; + _theResult___sfd__h403770 : + sfdin__h403247[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 = - (guard__h440843 == 2'b0 || + (guard__h440842 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h448942 : - _theResult___exp__h449458 ; + _theResult___fst_exp__h448941 : + _theResult___exp__h449457 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 = - (guard__h440843 == 2'b0) ? - _theResult___fst_exp__h448942 : + (guard__h440842 == 2'b0) ? + _theResult___fst_exp__h448941 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h449458 : - _theResult___fst_exp__h448942) ; + _theResult___exp__h449457 : + _theResult___fst_exp__h448941) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 = - (guard__h440843 == 2'b0 || + (guard__h440842 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h448936[56:34] : - _theResult___sfd__h449459 ; + sfdin__h448935[56:34] : + _theResult___sfd__h449458 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 = - (guard__h440843 == 2'b0) ? - sfdin__h448936[56:34] : + (guard__h440842 == 2'b0) ? + sfdin__h448935[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h449459 : - sfdin__h448936[56:34]) ; + _theResult___sfd__h449458 : + sfdin__h448935[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10630 = - (guard__h545712 == 2'b0 || + (guard__h545711 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h553938 : - _theResult___exp__h554667 ; + _theResult___fst_exp__h553937 : + _theResult___exp__h554666 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10632 = - (guard__h545712 == 2'b0) ? - _theResult___fst_exp__h553938 : + (guard__h545711 == 2'b0) ? + _theResult___fst_exp__h553937 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h554667 : - _theResult___fst_exp__h553938) ; + _theResult___exp__h554666 : + _theResult___fst_exp__h553937) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10713 = - (guard__h545712 == 2'b0 || + (guard__h545711 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h553932[56:5] : - _theResult___sfd__h554668 ; + sfdin__h553931[56:5] : + _theResult___sfd__h554667 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10715 = - (guard__h545712 == 2'b0) ? - sfdin__h553932[56:5] : + (guard__h545711 == 2'b0) ? + sfdin__h553931[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h554668 : - sfdin__h553932[56:5]) ; + _theResult___sfd__h554667 : + sfdin__h553931[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9162 = - (guard__h506911 == 2'b0 || + (guard__h506910 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h515137 : - _theResult___exp__h515866 ; + _theResult___fst_exp__h515136 : + _theResult___exp__h515865 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9164 = - (guard__h506911 == 2'b0) ? - _theResult___fst_exp__h515137 : + (guard__h506910 == 2'b0) ? + _theResult___fst_exp__h515136 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h515866 : - _theResult___fst_exp__h515137) ; + _theResult___exp__h515865 : + _theResult___fst_exp__h515136) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9246 = - (guard__h506911 == 2'b0 || + (guard__h506910 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h515131[56:5] : - _theResult___sfd__h515867 ; + sfdin__h515130[56:5] : + _theResult___sfd__h515866 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9248 = - (guard__h506911 == 2'b0) ? - sfdin__h515131[56:5] : + (guard__h506910 == 2'b0) ? + sfdin__h515130[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h515867 : - sfdin__h515131[56:5]) ; + _theResult___sfd__h515866 : + sfdin__h515130[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9867 = - (guard__h584913 == 2'b0 || + (guard__h584912 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h593139 : - _theResult___exp__h593868 ; + _theResult___fst_exp__h593138 : + _theResult___exp__h593867 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9869 = - (guard__h584913 == 2'b0) ? - _theResult___fst_exp__h593139 : + (guard__h584912 == 2'b0) ? + _theResult___fst_exp__h593138 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h593868 : - _theResult___fst_exp__h593139) ; + _theResult___exp__h593867 : + _theResult___fst_exp__h593138) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9950 = - (guard__h584913 == 2'b0 || + (guard__h584912 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h593133[56:5] : - _theResult___sfd__h593869 ; + sfdin__h593132[56:5] : + _theResult___sfd__h593868 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9952 = - (guard__h584913 == 2'b0) ? - sfdin__h593133[56:5] : + (guard__h584912 == 2'b0) ? + sfdin__h593132[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h593869 : - sfdin__h593133[56:5]) ; + _theResult___sfd__h593868 : + sfdin__h593132[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 = - (guard__h367102 == 2'b0 || + (guard__h367101 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h375330 : - _theResult___exp__h375846 ; + _theResult___fst_exp__h375329 : + _theResult___exp__h375845 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 = - (guard__h367102 == 2'b0) ? - _theResult___fst_exp__h375330 : + (guard__h367101 == 2'b0) ? + _theResult___fst_exp__h375329 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h375846 : - _theResult___fst_exp__h375330) ; + _theResult___exp__h375845 : + _theResult___fst_exp__h375329) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 = - (guard__h367102 == 2'b0 || + (guard__h367101 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h375324[56:34] : - _theResult___sfd__h375847 ; + sfdin__h375323[56:34] : + _theResult___sfd__h375846 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 = - (guard__h367102 == 2'b0) ? - sfdin__h375324[56:34] : + (guard__h367101 == 2'b0) ? + sfdin__h375323[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h375847 : - sfdin__h375324[56:34]) ; + _theResult___sfd__h375846 : + sfdin__h375323[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 = - (guard__h412792 == 2'b0 || + (guard__h412791 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h421020 : - _theResult___exp__h421536 ; + _theResult___fst_exp__h421019 : + _theResult___exp__h421535 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 = - (guard__h412792 == 2'b0) ? - _theResult___fst_exp__h421020 : + (guard__h412791 == 2'b0) ? + _theResult___fst_exp__h421019 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h421536 : - _theResult___fst_exp__h421020) ; + _theResult___exp__h421535 : + _theResult___fst_exp__h421019) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 = - (guard__h412792 == 2'b0 || + (guard__h412791 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h421014[56:34] : - _theResult___sfd__h421537 ; + sfdin__h421013[56:34] : + _theResult___sfd__h421536 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 = - (guard__h412792 == 2'b0) ? - sfdin__h421014[56:34] : + (guard__h412791 == 2'b0) ? + sfdin__h421013[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h421537 : - sfdin__h421014[56:34]) ; + _theResult___sfd__h421536 : + sfdin__h421013[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 = - (guard__h458480 == 2'b0 || + (guard__h458479 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h466708 : - _theResult___exp__h467224 ; + _theResult___fst_exp__h466707 : + _theResult___exp__h467223 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 = - (guard__h458480 == 2'b0) ? - _theResult___fst_exp__h466708 : + (guard__h458479 == 2'b0) ? + _theResult___fst_exp__h466707 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h467224 : - _theResult___fst_exp__h466708) ; + _theResult___exp__h467223 : + _theResult___fst_exp__h466707) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 = - (guard__h458480 == 2'b0 || + (guard__h458479 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h466702[56:34] : - _theResult___sfd__h467225 ; + sfdin__h466701[56:34] : + _theResult___sfd__h467224 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 = - (guard__h458480 == 2'b0) ? - sfdin__h466702[56:34] : + (guard__h458479 == 2'b0) ? + sfdin__h466701[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h467225 : - sfdin__h466702[56:34]) ; + _theResult___sfd__h467224 : + sfdin__h466701[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 = - (guard__h358172 == 2'b0 || + (guard__h358171 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h366220 : - _theResult___exp__h366662 ; + _theResult___fst_exp__h366219 : + _theResult___exp__h366661 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 = - (guard__h358172 == 2'b0) ? - _theResult___fst_exp__h366220 : + (guard__h358171 == 2'b0) ? + _theResult___fst_exp__h366219 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h366662 : - _theResult___fst_exp__h366220) ; + _theResult___exp__h366661 : + _theResult___fst_exp__h366219) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h375938 == 2'b0 || + (guard__h375937 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h384015 : - _theResult___exp__h384482 ; + _theResult___fst_exp__h384014 : + _theResult___exp__h384481 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h375938 == 2'b0) ? - _theResult___fst_exp__h384015 : + (guard__h375937 == 2'b0) ? + _theResult___fst_exp__h384014 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h384482 : - _theResult___fst_exp__h384015) ; + _theResult___exp__h384481 : + _theResult___fst_exp__h384014) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 = - (guard__h358172 == 2'b0 || + (guard__h358171 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h366171[56:34] : - _theResult___sfd__h366663 ; + _theResult___snd__h366170[56:34] : + _theResult___sfd__h366662 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 = - (guard__h358172 == 2'b0) ? - _theResult___snd__h366171[56:34] : + (guard__h358171 == 2'b0) ? + _theResult___snd__h366170[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h366663 : - _theResult___snd__h366171[56:34]) ; + _theResult___sfd__h366662 : + _theResult___snd__h366170[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 = - (guard__h375938 == 2'b0 || + (guard__h375937 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h383961[56:34] : - _theResult___sfd__h384483 ; + _theResult___snd__h383960[56:34] : + _theResult___sfd__h384482 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 = - (guard__h375938 == 2'b0) ? - _theResult___snd__h383961[56:34] : + (guard__h375937 == 2'b0) ? + _theResult___snd__h383960[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h384483 : - _theResult___snd__h383961[56:34]) ; + _theResult___sfd__h384482 : + _theResult___snd__h383960[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 = - (guard__h403862 == 2'b0 || + (guard__h403861 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h411910 : - _theResult___exp__h412352 ; + _theResult___fst_exp__h411909 : + _theResult___exp__h412351 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 = - (guard__h403862 == 2'b0) ? - _theResult___fst_exp__h411910 : + (guard__h403861 == 2'b0) ? + _theResult___fst_exp__h411909 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h412352 : - _theResult___fst_exp__h411910) ; + _theResult___exp__h412351 : + _theResult___fst_exp__h411909) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h421628 == 2'b0 || + (guard__h421627 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h429705 : - _theResult___exp__h430172 ; + _theResult___fst_exp__h429704 : + _theResult___exp__h430171 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h421628 == 2'b0) ? - _theResult___fst_exp__h429705 : + (guard__h421627 == 2'b0) ? + _theResult___fst_exp__h429704 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h430172 : - _theResult___fst_exp__h429705) ; + _theResult___exp__h430171 : + _theResult___fst_exp__h429704) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 = - (guard__h403862 == 2'b0 || + (guard__h403861 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h411861[56:34] : - _theResult___sfd__h412353 ; + _theResult___snd__h411860[56:34] : + _theResult___sfd__h412352 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 = - (guard__h403862 == 2'b0) ? - _theResult___snd__h411861[56:34] : + (guard__h403861 == 2'b0) ? + _theResult___snd__h411860[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h412353 : - _theResult___snd__h411861[56:34]) ; + _theResult___sfd__h412352 : + _theResult___snd__h411860[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 = - (guard__h421628 == 2'b0 || + (guard__h421627 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h429651[56:34] : - _theResult___sfd__h430173 ; + _theResult___snd__h429650[56:34] : + _theResult___sfd__h430172 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 = - (guard__h421628 == 2'b0) ? - _theResult___snd__h429651[56:34] : + (guard__h421627 == 2'b0) ? + _theResult___snd__h429650[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h430173 : - _theResult___snd__h429651[56:34]) ; + _theResult___sfd__h430172 : + _theResult___snd__h429650[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 = - (guard__h449550 == 2'b0 || + (guard__h449549 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h457598 : - _theResult___exp__h458040 ; + _theResult___fst_exp__h457597 : + _theResult___exp__h458039 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 = - (guard__h449550 == 2'b0) ? - _theResult___fst_exp__h457598 : + (guard__h449549 == 2'b0) ? + _theResult___fst_exp__h457597 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h458040 : - _theResult___fst_exp__h457598) ; + _theResult___exp__h458039 : + _theResult___fst_exp__h457597) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h467316 == 2'b0 || + (guard__h467315 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h475393 : - _theResult___exp__h475860 ; + _theResult___fst_exp__h475392 : + _theResult___exp__h475859 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h467316 == 2'b0) ? - _theResult___fst_exp__h475393 : + (guard__h467315 == 2'b0) ? + _theResult___fst_exp__h475392 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h475860 : - _theResult___fst_exp__h475393) ; + _theResult___exp__h475859 : + _theResult___fst_exp__h475392) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 = - (guard__h449550 == 2'b0 || + (guard__h449549 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h457549[56:34] : - _theResult___sfd__h458041 ; + _theResult___snd__h457548[56:34] : + _theResult___sfd__h458040 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 = - (guard__h449550 == 2'b0) ? - _theResult___snd__h457549[56:34] : + (guard__h449549 == 2'b0) ? + _theResult___snd__h457548[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h458041 : - _theResult___snd__h457549[56:34]) ; + _theResult___sfd__h458040 : + _theResult___snd__h457548[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 = - (guard__h467316 == 2'b0 || + (guard__h467315 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h475339[56:34] : - _theResult___sfd__h475861 ; + _theResult___snd__h475338[56:34] : + _theResult___sfd__h475860 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 = - (guard__h467316 == 2'b0) ? - _theResult___snd__h475339[56:34] : + (guard__h467315 == 2'b0) ? + _theResult___snd__h475338[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h475861 : - _theResult___snd__h475339[56:34]) ; + _theResult___sfd__h475860 : + _theResult___snd__h475338[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10592 = - (guard__h536400 == 2'b0 || + (guard__h536399 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h544361 : - _theResult___exp__h545016 ; + _theResult___fst_exp__h544360 : + _theResult___exp__h545015 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10594 = - (guard__h536400 == 2'b0) ? - _theResult___fst_exp__h544361 : + (guard__h536399 == 2'b0) ? + _theResult___fst_exp__h544360 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h545016 : - _theResult___fst_exp__h544361) ; + _theResult___exp__h545015 : + _theResult___fst_exp__h544360) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10661 = - (guard__h554781 == 2'b0 || + (guard__h554780 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h562771 : - _theResult___exp__h563451 ; + _theResult___fst_exp__h562770 : + _theResult___exp__h563450 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10663 = - (guard__h554781 == 2'b0) ? - _theResult___fst_exp__h562771 : + (guard__h554780 == 2'b0) ? + _theResult___fst_exp__h562770 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h563451 : - _theResult___fst_exp__h562771) ; + _theResult___exp__h563450 : + _theResult___fst_exp__h562770) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10687 = - (guard__h536400 == 2'b0 || + (guard__h536399 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h544312[56:5] : - _theResult___sfd__h545017 ; + _theResult___snd__h544311[56:5] : + _theResult___sfd__h545016 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10689 = - (guard__h536400 == 2'b0) ? - _theResult___snd__h544312[56:5] : + (guard__h536399 == 2'b0) ? + _theResult___snd__h544311[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h545017 : - _theResult___snd__h544312[56:5]) ; + _theResult___sfd__h545016 : + _theResult___snd__h544311[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10732 = - (guard__h554781 == 2'b0 || + (guard__h554780 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h562717[56:5] : - _theResult___sfd__h563452 ; + _theResult___snd__h562716[56:5] : + _theResult___sfd__h563451 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10734 = - (guard__h554781 == 2'b0) ? - _theResult___snd__h562717[56:5] : + (guard__h554780 == 2'b0) ? + _theResult___snd__h562716[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h563452 : - _theResult___snd__h562717[56:5]) ; + _theResult___sfd__h563451 : + _theResult___snd__h562716[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9119 = - (guard__h497599 == 2'b0 || + (guard__h497598 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h505560 : - _theResult___exp__h506215 ; + _theResult___fst_exp__h505559 : + _theResult___exp__h506214 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9121 = - (guard__h497599 == 2'b0) ? - _theResult___fst_exp__h505560 : + (guard__h497598 == 2'b0) ? + _theResult___fst_exp__h505559 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h506215 : - _theResult___fst_exp__h505560) ; + _theResult___exp__h506214 : + _theResult___fst_exp__h505559) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9193 = - (guard__h515980 == 2'b0 || + (guard__h515979 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h523970 : - _theResult___exp__h524650 ; + _theResult___fst_exp__h523969 : + _theResult___exp__h524649 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9195 = - (guard__h515980 == 2'b0) ? - _theResult___fst_exp__h523970 : + (guard__h515979 == 2'b0) ? + _theResult___fst_exp__h523969 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h524650 : - _theResult___fst_exp__h523970) ; + _theResult___exp__h524649 : + _theResult___fst_exp__h523969) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9219 = - (guard__h497599 == 2'b0 || + (guard__h497598 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h505511[56:5] : - _theResult___sfd__h506216 ; + _theResult___snd__h505510[56:5] : + _theResult___sfd__h506215 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9221 = - (guard__h497599 == 2'b0) ? - _theResult___snd__h505511[56:5] : + (guard__h497598 == 2'b0) ? + _theResult___snd__h505510[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h506216 : - _theResult___snd__h505511[56:5]) ; + _theResult___sfd__h506215 : + _theResult___snd__h505510[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9265 = - (guard__h515980 == 2'b0 || + (guard__h515979 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h523916[56:5] : - _theResult___sfd__h524651 ; + _theResult___snd__h523915[56:5] : + _theResult___sfd__h524650 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9267 = - (guard__h515980 == 2'b0) ? - _theResult___snd__h523916[56:5] : + (guard__h515979 == 2'b0) ? + _theResult___snd__h523915[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h524651 : - _theResult___snd__h523916[56:5]) ; + _theResult___sfd__h524650 : + _theResult___snd__h523915[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9829 = - (guard__h575601 == 2'b0 || + (guard__h575600 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h583562 : - _theResult___exp__h584217 ; + _theResult___fst_exp__h583561 : + _theResult___exp__h584216 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9831 = - (guard__h575601 == 2'b0) ? - _theResult___fst_exp__h583562 : + (guard__h575600 == 2'b0) ? + _theResult___fst_exp__h583561 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h584217 : - _theResult___fst_exp__h583562) ; + _theResult___exp__h584216 : + _theResult___fst_exp__h583561) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9898 = - (guard__h593982 == 2'b0 || + (guard__h593981 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h601972 : - _theResult___exp__h602652 ; + _theResult___fst_exp__h601971 : + _theResult___exp__h602651 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9900 = - (guard__h593982 == 2'b0) ? - _theResult___fst_exp__h601972 : + (guard__h593981 == 2'b0) ? + _theResult___fst_exp__h601971 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h602652 : - _theResult___fst_exp__h601972) ; + _theResult___exp__h602651 : + _theResult___fst_exp__h601971) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9924 = - (guard__h575601 == 2'b0 || + (guard__h575600 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h583513[56:5] : - _theResult___sfd__h584218 ; + _theResult___snd__h583512[56:5] : + _theResult___sfd__h584217 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9926 = - (guard__h575601 == 2'b0) ? - _theResult___snd__h583513[56:5] : + (guard__h575600 == 2'b0) ? + _theResult___snd__h583512[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h584218 : - _theResult___snd__h583513[56:5]) ; + _theResult___sfd__h584217 : + _theResult___snd__h583512[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9969 = - (guard__h593982 == 2'b0 || + (guard__h593981 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h601918[56:5] : - _theResult___sfd__h602653 ; + _theResult___snd__h601917[56:5] : + _theResult___sfd__h602652 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9971 = - (guard__h593982 == 2'b0) ? - _theResult___snd__h601918[56:5] : + (guard__h593981 == 2'b0) ? + _theResult___snd__h601917[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h602653 : - _theResult___snd__h601918[56:5]) ; + _theResult___sfd__h602652 : + _theResult___snd__h601917[56:5]) ; assign IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904 = - (_theResult____h655195 == 15'd0 && + (_theResult____h655200 == 15'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h655739 : - _theResult____h655195 ; + enabled_ints__h655744 : + _theResult____h655200 ; + assign IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d13106 = + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[2] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[3] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[4] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[5] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[6] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[7] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[8] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[9] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[10] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[11] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] || + checkForException___d13069[4] || + csrf_fs_reg_read__1686_EQ_0_3058_AND_fetchStag_ETC___d13104 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10006 = - (_theResult___fst_exp__h583562 == 11'd2047) ? + (_theResult___fst_exp__h583561 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard75601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard75600_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10033 = - (_theResult___fst_exp__h601972 == 11'd2047) ? + (_theResult___fst_exp__h601971 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard93981_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10564 = - (_theResult___fst_exp__h562771 == 11'd2047) ? + (_theResult___fst_exp__h562770 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_guard54780_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10768 = - (_theResult___fst_exp__h544361 == 11'd2047) ? + (_theResult___fst_exp__h544360 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36400_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; - assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10795 = - (_theResult___fst_exp__h562771 == 11'd2047) ? - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard54781_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard36399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; + assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10795 = + (_theResult___fst_exp__h562770 == 11'd2047) ? + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard54780_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9091 = - (_theResult___fst_exp__h523970 == 11'd2047) ? + (_theResult___fst_exp__h523969 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard15980_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard15979_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9801 = - (_theResult___fst_exp__h601972 == 11'd2047) ? + (_theResult___fst_exp__h601971 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard93981_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875 = IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864 ? @@ -19461,110 +19486,110 @@ module mkCore(CLK, (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1828 ? 4'd1 : IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1883) ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13207 = + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13242 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd12 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd12) ? 4'd13 : 4'd15 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13208 = + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13243 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd11 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd11) ? 4'd12 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13207 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13209 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13242 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13244 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd10 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd10) ? 4'd11 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13208 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13210 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13243 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13245 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd9 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd9) ? 4'd9 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13209 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13211 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13244 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13246 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd8 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd8) ? 4'd8 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13210 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13212 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13245 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13247 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd7 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd7) ? 4'd7 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13211 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13213 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13246 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13248 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd6 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd6) ? 4'd6 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13212 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13214 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13247 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13249 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd5 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd5) ? 4'd5 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13213 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13215 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13248 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13250 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd4 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd4) ? 4'd4 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13214 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13216 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13249 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13251 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd3 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd3) ? 4'd3 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13215 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13217 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13250 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13252 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd2 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd2) ? 4'd2 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13216 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13218 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13251 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13253 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd1 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd1) ? 4'd1 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13217 ; - assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13219 = + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13252 ; + assign IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13254 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 == + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 == 4'd0 : - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 == + IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 == 4'd0) ? 4'd0 : - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13218 ; + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13253 ; assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 = { (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 : @@ -19627,37 +19652,37 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10223 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10104 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10106 || - _theResult___fst_exp__h544361 == 11'd2047) ? + _theResult___fst_exp__h544360 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36400_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; + CASE_guard36399_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8750 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8616 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8618 || - _theResult___fst_exp__h505560 == 11'd2047) ? + _theResult___fst_exp__h505559 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard97599_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard97598_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9460 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9341 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9343 || - _theResult___fst_exp__h583562 == 11'd2047) ? + _theResult___fst_exp__h583561 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard75601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard75600_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; - assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13245 = + assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13280 = IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] ? 4'd0 : (IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] ? @@ -20067,42 +20092,42 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[12]) ? CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 : CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13785 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13875 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13415) && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13474) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13782 : + IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13872 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13793 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2833_283_ETC___d13883 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13415) && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13474) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13792 : + IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13882 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13790 ; - assign IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13717 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13880 ; + assign IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13805 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13700 : + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13788 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13711 : + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13799 : (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - _0_OR_fetchStage_RDY_pipelines_0_first__2832_37_ETC___d13714) ; - assign IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13792 = - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13640 ? - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 || + _0_OR_fetchStage_RDY_pipelines_0_first__2832_38_ETC___d13802) ; + assign IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13882 = + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13718 ? + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 || fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13787 : + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13877 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13790 ; - assign IF_NOT_rob_deqPort_1_deq_data__4766_BIT_25_476_ETC___d14969 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13880 ; + assign IF_NOT_rob_deqPort_1_deq_data__4859_BIT_25_486_ETC___d15062 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -20126,35 +20151,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h375330 == 8'd255) ? + ((_theResult___fst_exp__h375329 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180) : - ((_theResult___fst_exp__h384015 == 8'd255) ? + ((_theResult___fst_exp__h384014 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h375330 == 8'd255) ? + ((_theResult___fst_exp__h375329 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223) : - ((_theResult___fst_exp__h384015 == 8'd255) ? + ((_theResult___fst_exp__h384014 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[2] : - _theResult___fst_exp__h384563 == 8'd255 && - _theResult___fst_sfd__h384564 == 23'd0 ; + _theResult___fst_exp__h384562 == 8'd255 && + _theResult___fst_sfd__h384563 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[1] : - _theResult___fst_exp__h384015 == 8'd0 && - guard__h375938 != 2'b0 ; + _theResult___fst_exp__h384014 == 8'd0 && + guard__h375937 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[0] : - _theResult___fst_exp__h384015 != 8'd255 && - guard__h375938 != 2'b0 ; + _theResult___fst_exp__h384014 != 8'd255 && + guard__h375937 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? @@ -20164,35 +20189,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h421020 == 8'd255) ? + ((_theResult___fst_exp__h421019 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572) : - ((_theResult___fst_exp__h429705 == 8'd255) ? + ((_theResult___fst_exp__h429704 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h421020 == 8'd255) ? + ((_theResult___fst_exp__h421019 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615) : - ((_theResult___fst_exp__h429705 == 8'd255) ? + ((_theResult___fst_exp__h429704 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[2] : - _theResult___fst_exp__h430253 == 8'd255 && - _theResult___fst_sfd__h430254 == 23'd0 ; + _theResult___fst_exp__h430252 == 8'd255 && + _theResult___fst_sfd__h430253 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[1] : - _theResult___fst_exp__h429705 == 8'd0 && - guard__h421628 != 2'b0 ; + _theResult___fst_exp__h429704 == 8'd0 && + guard__h421627 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[0] : - _theResult___fst_exp__h429705 != 8'd255 && - guard__h421628 != 2'b0 ; + _theResult___fst_exp__h429704 != 8'd255 && + guard__h421627 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? @@ -20202,35 +20227,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h466708 == 8'd255) ? + ((_theResult___fst_exp__h466707 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964) : - ((_theResult___fst_exp__h475393 == 8'd255) ? + ((_theResult___fst_exp__h475392 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h466708 == 8'd255) ? + ((_theResult___fst_exp__h466707 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007) : - ((_theResult___fst_exp__h475393 == 8'd255) ? + ((_theResult___fst_exp__h475392 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[2] : - _theResult___fst_exp__h475941 == 8'd255 && - _theResult___fst_sfd__h475942 == 23'd0 ; + _theResult___fst_exp__h475940 == 8'd255 && + _theResult___fst_sfd__h475941 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[1] : - _theResult___fst_exp__h475393 == 8'd0 && - guard__h467316 != 2'b0 ; + _theResult___fst_exp__h475392 == 8'd0 && + guard__h467315 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[0] : - _theResult___fst_exp__h475393 != 8'd255 && - guard__h467316 != 2'b0 ; + _theResult___fst_exp__h475392 != 8'd255 && + guard__h467315 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10035 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9463 ? (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9464 ? @@ -20259,48 +20284,48 @@ module mkCore(CLK, assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10992 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d8754 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10850[2] : - _theResult___fst_exp__h524753 == 11'd2047 && - _theResult___fst_sfd__h524754 == 52'd0 ; + _theResult___fst_exp__h524752 == 11'd2047 && + _theResult___fst_sfd__h524753 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11006 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d10227 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10891[2] : - _theResult___fst_exp__h563554 == 11'd2047 && - _theResult___fst_sfd__h563555 == 52'd0 ; + _theResult___fst_exp__h563553 == 11'd2047 && + _theResult___fst_sfd__h563554 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11021 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9464 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10935[2] : - _theResult___fst_exp__h602755 == 11'd2047 && - _theResult___fst_sfd__h602756 == 52'd0 ; + _theResult___fst_exp__h602754 == 11'd2047 && + _theResult___fst_sfd__h602755 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11038 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d8754 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10850[1] : - _theResult___fst_exp__h523970 == 11'd0 && - guard__h515980 != 2'b0 ; + _theResult___fst_exp__h523969 == 11'd0 && + guard__h515979 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11050 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d10227 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10891[1] : - _theResult___fst_exp__h562771 == 11'd0 && - guard__h554781 != 2'b0 ; + _theResult___fst_exp__h562770 == 11'd0 && + guard__h554780 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11063 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9464 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10935[1] : - _theResult___fst_exp__h601972 == 11'd0 && - guard__h593982 != 2'b0 ; + _theResult___fst_exp__h601971 == 11'd0 && + guard__h593981 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11080 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d8754 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10850[0] : - _theResult___fst_exp__h523970 != 11'd2047 && - guard__h515980 != 2'b0 ; + _theResult___fst_exp__h523969 != 11'd2047 && + guard__h515979 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11092 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d10227 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10891[0] : - _theResult___fst_exp__h562771 != 11'd2047 && - guard__h554781 != 2'b0 ; + _theResult___fst_exp__h562770 != 11'd2047 && + guard__h554780 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11105 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9464 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10935[0] : - _theResult___fst_exp__h601972 != 11'd2047 && - guard__h593982 != 2'b0 ; + _theResult___fst_exp__h601971 != 11'd2047 && + guard__h593981 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9052 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q129[10:0] == 11'd0) ? @@ -20327,6 +20352,10 @@ module mkCore(CLK, IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9755 : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9801) : coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; + assign IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13203 = + checkForException___d13069[4] ? + CASE_checkForException_3069_BITS_3_TO_0_0_chec_ETC__q226 : + 4'd2 ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2279_ETC___d12312 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && @@ -21021,11 +21050,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10746 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h563566, + _theResult___fst_exp__h563565, (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ? - _theResult___snd_fst_sfd__h525455 : - _theResult___fst_sfd__h563570 } ; + _theResult___snd_fst_sfd__h525454 : + _theResult___fst_sfd__h563569 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10748 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] : @@ -21222,11 +21251,11 @@ module mkCore(CLK, { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9095, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h524765, + _theResult___fst_exp__h524764, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ? - _theResult___snd_fst_sfd__h486513 : - _theResult___fst_sfd__h524769 } ; + _theResult___snd_fst_sfd__h486512 : + _theResult___fst_sfd__h524768 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9280 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] : @@ -21295,11 +21324,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9983 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h602767, + _theResult___fst_exp__h602766, (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ? - _theResult___snd_fst_sfd__h564656 : - _theResult___fst_sfd__h602771 } ; + _theResult___snd_fst_sfd__h564655 : + _theResult___fst_sfd__h602770 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] : @@ -21330,39 +21359,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h200471 : + n___1__h200472 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21415,7 +21444,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h199068 : + x__h199069 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 ? 64'd0 : 64'd1) ; @@ -21427,7 +21456,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 = - _theResult_____2__h299893 == v__h299313 ; + _theResult_____2__h299894 == v__h299314 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21436,7 +21465,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 = - _theResult_____2__h307889 == v__h302658 ; + _theResult_____2__h307890 == v__h302659 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21465,7 +21494,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h305523 } ; + x__h305524 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -21563,35 +21592,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h195563 : + n__h195564 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -21619,7 +21648,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 = - _theResult_____2__h313883 == v__h313172 ; + _theResult_____2__h313884 == v__h313173 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21628,7 +21657,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 = - _theResult_____2__h321737 == v__h317048 ; + _theResult_____2__h321738 == v__h317049 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21780,7 +21809,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 = - _theResult_____2__h335306 == v__h334874 ; + _theResult_____2__h335307 == v__h334875 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -21829,7 +21858,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) : IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 = - _theResult_____2__h332081 == v__h331649 ; + _theResult_____2__h332082 == v__h331650 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -21863,49 +21892,53 @@ module mkCore(CLK, csrf_minstret_ehr_data_lat_0$whas ? rob$deqPort_0_deq_data[95:32] : csrf_minstret_ehr_data_rl ; - assign IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13385 = - fetchStage_RDY_pipelines_0_first__2832_AND_NOT_ETC___d13381 ? + assign IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13444 = + fetchStage_RDY_pipelines_0_first__2832_AND_NOT_ETC___d13440 ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13719 = + assign IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13807 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13689 : + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13777 : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13717 ; - assign IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13782 = + IF_NOT_fetchStage_pipelines_1_first__2844_BITS_ETC___d13805 ; + assign IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13872 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13447 && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13640) ? - IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13719 && - (IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 || + fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13506 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13718) ? + IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13807 && + (IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13829 = - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13822 || + assign IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13920 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13913 || fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2835_BIT_160__ETC___d14015 = + assign IF_fetchStage_pipelines_0_first__2835_BIT_160__ETC___d14107 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14003, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14006 ? - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14009 : + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14095, + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14098 ? + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14101 : { 1'h0, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14012 } } ; - assign IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13264 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14104 } } ; + assign IF_fetchStage_pipelines_0_first__2835_BIT_173__ETC___d13096 = + fetchStage$pipelines_0_first[173] ? + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035 : + 12'hCFF ; + assign IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13299 = (fetchStage$pipelines_0_first[68] || !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] && @@ -21922,30 +21955,30 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14]) ? - IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13219 : + IF_IF_fetchStage_pipelines_0_first__2835_BIT_6_ETC___d13254 : CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863__ETC__q227 ; - assign IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13950 = - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13909 && - IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13719 && - (IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13934 || + assign IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14041 = + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14000 && + IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13807 && + (IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14025 || fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - rob_RDY_enqPort_1_enq__3936_AND_NOT_fetchStage_ETC___d13944) ; - assign IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14227 = + rob_RDY_enqPort_1_enq__4027_AND_NOT_fetchStage_ETC___d14035) ; + assign IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14320 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 && - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14167) ? - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14168 : + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 && + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14262) ? + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14263 : { 1'h0, - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14169 } ; - assign IF_fetchStage_pipelines_1_first__2844_BIT_160__ETC___d14172 = + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14264 } ; + assign IF_fetchStage_pipelines_1_first__2844_BIT_160__ETC___d14267 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14166, - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14167 ? - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14168 : + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14261, + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14262 ? + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14263 : { 1'h0, - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14169 } } ; + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14264 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -21970,62 +22003,62 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14868 = + assign IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d14961 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h716323 : + y_avValue_snd_snd_snd_snd_snd__h718483 : 64'd0 ; - assign IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14957 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h716307 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14978 = + assign IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15050 = + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h718467 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15071 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h716317 : + y_avValue_snd_snd_snd_fst__h718477 : 2'd0 ; - assign IF_rob_deqPort_1_canDeq__4763_THEN_IF_NOT_rob__ETC___d14970 = + assign IF_rob_deqPort_1_canDeq__4856_THEN_IF_NOT_rob__ETC___d15063 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__4766_BIT_25_476_ETC___d14969 : + IF_NOT_rob_deqPort_1_deq_data__4859_BIT_25_486_ETC___d15062 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin03248_BIT_33_THEN_2_ELSE_0__q57 = - sfdin__h403248[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin15131_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h515131[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin21014_BIT_33_THEN_2_ELSE_0__q67 = - sfdin__h421014[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin48936_BIT_33_THEN_2_ELSE_0__q92 = - sfdin__h448936[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin53932_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h553932[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin57558_BIT_33_THEN_2_ELSE_0__q22 = - sfdin__h357558[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin66702_BIT_33_THEN_2_ELSE_0__q102 = - sfdin__h466702[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin75324_BIT_33_THEN_2_ELSE_0__q32 = - sfdin__h375324[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin93133_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h593133[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01918_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h601918[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd05511_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h505511[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd11861_BIT_33_THEN_2_ELSE_0__q59 = - _theResult___snd__h411861[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd23916_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h523916[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd29651_BIT_33_THEN_2_ELSE_0__q72 = - _theResult___snd__h429651[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd44312_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h544312[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd57549_BIT_33_THEN_2_ELSE_0__q94 = - _theResult___snd__h457549[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd62717_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h562717[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd66171_BIT_33_THEN_2_ELSE_0__q24 = - _theResult___snd__h366171[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd75339_BIT_33_THEN_2_ELSE_0__q107 = - _theResult___snd__h475339[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd83513_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h583513[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd83961_BIT_33_THEN_2_ELSE_0__q37 = - _theResult___snd__h383961[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin03247_BIT_33_THEN_2_ELSE_0__q57 = + sfdin__h403247[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin15130_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h515130[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin21013_BIT_33_THEN_2_ELSE_0__q67 = + sfdin__h421013[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin48935_BIT_33_THEN_2_ELSE_0__q92 = + sfdin__h448935[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin53931_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h553931[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin57557_BIT_33_THEN_2_ELSE_0__q22 = + sfdin__h357557[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin66701_BIT_33_THEN_2_ELSE_0__q102 = + sfdin__h466701[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin75323_BIT_33_THEN_2_ELSE_0__q32 = + sfdin__h375323[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin93132_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h593132[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd01917_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h601917[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd05510_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h505510[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd11860_BIT_33_THEN_2_ELSE_0__q59 = + _theResult___snd__h411860[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd23915_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h523915[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd29650_BIT_33_THEN_2_ELSE_0__q72 = + _theResult___snd__h429650[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd44311_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h544311[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd57548_BIT_33_THEN_2_ELSE_0__q94 = + _theResult___snd__h457548[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd62716_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h562716[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd66170_BIT_33_THEN_2_ELSE_0__q24 = + _theResult___snd__h366170[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd75338_BIT_33_THEN_2_ELSE_0__q107 = + _theResult___snd__h475338[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd83512_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h583512[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd83960_BIT_33_THEN_2_ELSE_0__q37 = + _theResult___snd__h383960[33] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? @@ -22056,20 +22089,58 @@ module mkCore(CLK, (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049[0] : _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061[0]) ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__4759_4760_OR__ETC___d14975 = - (fflags__h716900 & csrf_fflags_reg) != fflags__h716900 || - !r__h617263 && - (IF_rob_deqPort_1_canDeq__4763_THEN_IF_NOT_rob__ETC___d14970 || - fflags__h716900 != 5'd0) ; - assign NOT_IF_rob_deqPort_0_deq_data__4241_BITS_97_TO_ETC___d14730 = - next_pc__h712992 != - rob_deqPort_0_deq_data__4241_BITS_282_TO_219_4_ETC___d14727 ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13433 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 && + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_286_ETC___d13348 = + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[2] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[3] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[4] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[5] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[6] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[7] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[8] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[9] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[10] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[11] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] && + !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] && + !checkForException___d13069[4] && + NOT_csrf_fs_reg_read__1686_EQ_0_3058_3059_OR_N_ETC___d13346 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__4852_4853_OR__ETC___d15068 = + (fflags__h719060 & csrf_fflags_reg) != fflags__h719060 || + !r__h617262 && + (IF_rob_deqPort_1_canDeq__4856_THEN_IF_NOT_rob__ETC___d15063 || + fflags__h719060 != 5'd0) ; + assign NOT_IF_rob_deqPort_0_deq_data__4334_BITS_97_TO_ETC___d14823 = + next_pc__h715152 != + rob_deqPort_0_deq_data__4334_BITS_282_TO_219_4_ETC___d14820 ; + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13492 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 ; + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 ; + assign NOT_checkForException_3069_BIT_4_3070_3322_AND_ETC___d13431 = + !checkForException___d13069[4] && + (csrf_fs_reg != 2'd0 || + (!fetchStage$pipelines_0_first[95] || + !fetchStage$pipelines_0_first[94]) && + (!fetchStage$pipelines_0_first[88] || + !fetchStage$pipelines_0_first[87]) && + !fetchStage$pipelines_0_first[81] && + (!fetchStage$pipelines_0_first[75] || + !fetchStage$pipelines_0_first[74])) ; + assign NOT_checkForException_3686_BIT_4_3687_3688_AND_ETC___d13706 = + !checkForException___d13686[4] && + (csrf_fs_reg != 2'd0 || + (!fetchStage$pipelines_1_first[95] || + !fetchStage$pipelines_1_first[94]) && + (!fetchStage$pipelines_1_first[88] || + !fetchStage$pipelines_1_first[87]) && + !fetchStage$pipelines_1_first[81] && + (!fetchStage$pipelines_1_first[75] || + !fetchStage$pipelines_1_first[74])) ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2301_2_ETC___d12328 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2302_BITS__ETC___d12304) && @@ -22435,6 +22506,24 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[14] && !coreFix_fpuMulDivExe_0_regToExeQ$first[13] && !coreFix_fpuMulDivExe_0_regToExeQ$first[12] ; + assign NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13816 = + !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || + fetchStage$pipelines_0_first[68] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[2] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[3] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[4] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[5] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[6] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[7] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[8] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[9] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[10] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[11] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] ; assign NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) && @@ -22776,122 +22865,155 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] || !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ; - assign NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 = - !csrf_prv_reg_read__2863_ULE_1___d14382 || + assign NOT_coreFix_memExe_rsMem_canEnq__3460_3521_OR__ETC___d13817 = + !coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 || + fetchStage$pipelines_0_first[68] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[2] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[3] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[4] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[5] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[6] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[7] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[8] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[9] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[10] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[11] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] ; + assign NOT_csrf_fs_reg_read__1686_EQ_0_3058_3059_OR_N_ETC___d13346 = + (csrf_fs_reg != 2'd0 || + (!fetchStage$pipelines_0_first[95] || + !fetchStage$pipelines_0_first[94]) && + (!fetchStage$pipelines_0_first[88] || + !fetchStage$pipelines_0_first[87]) && + !fetchStage$pipelines_0_first[81] && + (!fetchStage$pipelines_0_first[75] || + !fetchStage$pipelines_0_first[74])) && + (fetchStage$pipelines_0_first[199:195] != 5'd13 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13342 && + !csrf_prv_reg_read__2863_ULT_IF_fetchStage_pipe_ETC___d13101) ; + assign NOT_csrf_prv_reg_read__2863_ULE_1_4475_4539_OR_ETC___d14543 = + !csrf_prv_reg_read__2863_ULE_1___d14475 || (commitStage_commitTrap[4] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14402 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14420) ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13472 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14495 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14513) ; + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13532 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13454 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13469 || + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13514 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13529 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13700 = + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13788 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3362_AND__ETC___d13697 || + (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13785 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13686) ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13711 = + fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13774) ; + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13799 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3362_AND__ETC___d13709 || + (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13797 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13686) ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13733 = + fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13774) ; + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13823 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13454 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13730 || + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13514 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13748 = + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13838 = !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13742 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13832 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13762 = + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13852 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13454 || + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13514 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13765 = - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13762 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 ; + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13855 = + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13852 && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13885 = + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13976 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13742 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13832 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13904 = + !coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453 ; + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13995 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13875) && + NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d13966) && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13956 = + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14047 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13831 && - IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13385) && + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13922 && + IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13444) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2833_AND_fetchS_ETC___d13954 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14078 = + fetchStage_pipelines_0_canDeq__2833_AND_fetchS_ETC___d14045 ; + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14075) && - coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 = - (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13414) && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13473) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14085 = + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14180 = !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13469 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13529 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14096 = - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14093 && + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14191 = + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14188 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13870 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14132 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13961 ; + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14227 = !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14157 = - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14252 = + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14132 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14227 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_1_first[173] ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 = + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464) && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ; - assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14204 = - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14085 && + assign NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14299 = + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14180 && specTagManager$canClaim && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 = + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13342 = + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + fetchStage$pipelines_0_first[178:174] != 5'd15) && + rs1__h659255 == 5'd0 && + imm__h659256 == 32'd0 || + IF_fetchStage_pipelines_0_first__2835_BIT_173__ETC___d13096[11:10] != + 2'b11 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 = fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -22901,16 +23023,16 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13289 && + NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13433 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13415 = + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13474 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13414 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13473 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 = fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -22921,85 +23043,85 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && !fetchStage$pipelines_0_first[68] && - !checkForException___d13069[4] && + NOT_checkForException_3069_BIT_4_3070_3322_AND_ETC___d13431 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13633 = + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13711 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13414 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13647 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13473 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13725 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 && - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13646 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13653 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 && + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13731 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394) ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13752 = + !coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453) ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13842 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13751 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13769 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13841 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13859 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13768 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13787 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13858 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13877 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13790 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13880 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13878 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13969 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13646 ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724 ; + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14061 = + assign NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14153 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14003, + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 || + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14095, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14006) ? - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14009 : + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14098) ? + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14101 : { 1'h0, - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14012 }, + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14104 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d13985 = + assign NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d14077 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h666996 ; - assign NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13289 = + fallthrough_pc__h667687 ; + assign NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13433 = !fetchStage$pipelines_0_first[68] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] && @@ -23016,13 +23138,13 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] && - !checkForException___d13069[4] ; + NOT_checkForException_3069_BIT_4_3070_3322_AND_ETC___d13431 ; assign NOT_fetchStage_pipelines_1_canDeq__2841_2842_O_ETC___d12850 = !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13638 = + assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13716 = fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && fetchStage$pipelines_1_first[199:195] != 5'd17 && @@ -23032,24 +23154,24 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13630 && + NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13708 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13633) ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13640 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13711) ; + assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13718 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13472 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13532 && specTagManager$canClaim) && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13638 ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13736 = + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13716 ; + assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13826 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13733 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13823 && specTagManager$canClaim) && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13638 ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13757 = + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13716 ; + assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13847 = fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && fetchStage$pipelines_1_first[199:195] != 5'd17 && @@ -23059,12 +23181,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13630 && + NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13708 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13752) ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13774 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13842) ; + assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13864 = fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && fetchStage$pipelines_1_first[199:195] != 5'd17 && @@ -23074,12 +23196,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13630 && + NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13708 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13769) ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13859) ; + assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 = fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && fetchStage$pipelines_1_first[199:195] != 5'd17 && @@ -23090,19 +23212,19 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && !fetchStage$pipelines_1_first[68] && - !checkForException___d13626[4] && + NOT_checkForException_3686_BIT_4_3687_3688_AND_ETC___d13706 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14093 = + assign NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14188 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14085 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14180 && specTagManager$canClaim) && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 ; - assign NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14147 = + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 ; + assign NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14242 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h681798 ; - assign NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13630 = + fallthrough_pc__h683150 ; + assign NOT_fetchStage_pipelines_1_first__2844_BIT_68__ETC___d13708 = !fetchStage$pipelines_1_first[68] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] && @@ -23119,7 +23241,7 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] && !IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] && - !checkForException___d13626[4] ; + NOT_checkForException_3686_BIT_4_3687_3688_AND_ETC___d13706 ; assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 = !mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ; assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 = @@ -23199,7 +23321,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13742 = + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13832 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -23211,22 +23333,22 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || fetchStage$pipelines_0_first[68] || - checkForException___d13069[4] || + checkForException_3069_BIT_4_3070_OR_csrf_fs_r_ETC___d13509 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796 = + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || checkForException___d13069[4] || !rob$enqPort_0_canEnq ; - assign NOT_rob_deqPort_0_canDeq__4759_4760_OR_regRena_ETC___d14798 = + assign NOT_rob_deqPort_0_canDeq__4852_4853_OR_regRena_ETC___d14891 = (!rob$deqPort_0_canDeq || regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__4766_BIT_25_4767_4_ETC___d14795) ; - assign NOT_rob_deqPort_0_canDeq__4759_4760_OR_rob_deq_ETC___d14951 = + NOT_rob_deqPort_1_deq_data__4859_BIT_25_4860_4_ETC___d14888) ; + assign NOT_rob_deqPort_0_canDeq__4852_4853_OR_rob_deq_ETC___d15044 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -23240,18 +23362,18 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] != 5'd19 && rob$deqPort_0_deq_data[186:182] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14554 = + assign NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14647 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14740 = + assign NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14833 = (rob$deqPort_0_deq_data[186:182] == 5'd13) != rob$deqPort_0_deq_data[181] ; - assign NOT_rob_deqPort_1_deq_data__4766_BIT_25_4767_4_ETC___d14795 = + assign NOT_rob_deqPort_1_deq_data__4859_BIT_25_4860_4_ETC___d14888 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -23264,16 +23386,16 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20 || regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; - assign NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13875 = + assign NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d13966 = !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13742 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13822 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13832 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13913 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13940 = + assign NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d14031 = !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13822 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13913 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013 = @@ -23293,34 +23415,34 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - x__h294883 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15097 = + x__h294884 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15190 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15053 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15146 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15062 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15053, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15155 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15146, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15071 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15062, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15164 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15155, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 } ; - assign SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13689 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670 || + assign SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13777 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13442 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13501 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13686 ; + fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13774 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11168 = - b__h606909 * b__h606985 ; + b__h606908 * b__h606984 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11181 = - b__h606909 * b__h607098 ; + b__h606908 * b__h607097 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64 } ; @@ -23430,15 +23552,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265 = { 3'd0, - _theResult___fst_exp__h357564 == 8'd0 && - (sfdin__h357558[56:34] == 23'd0 || guard__h349463 != 2'b0), + _theResult___fst_exp__h357563 == 8'd0 && + (sfdin__h357557[56:34] == 23'd0 || guard__h349462 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h358161 == 8'd255 && - _theResult___fst_sfd__h358162 == 23'd0, + _theResult___fst_exp__h358160 == 8'd255 && + _theResult___fst_sfd__h358161 == 23'd0, 1'd0, - _theResult___fst_exp__h357564 != 8'd255 && - guard__h349463 != 2'b0 } ; + _theResult___fst_exp__h357563 != 8'd255 && + guard__h349462 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ^ @@ -23446,15 +23568,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657 = { 3'd0, - _theResult___fst_exp__h403254 == 8'd0 && - (sfdin__h403248[56:34] == 23'd0 || guard__h395155 != 2'b0), + _theResult___fst_exp__h403253 == 8'd0 && + (sfdin__h403247[56:34] == 23'd0 || guard__h395154 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h403851 == 8'd255 && - _theResult___fst_sfd__h403852 == 23'd0, + _theResult___fst_exp__h403850 == 8'd255 && + _theResult___fst_sfd__h403851 == 23'd0, 1'd0, - _theResult___fst_exp__h403254 != 8'd255 && - guard__h395155 != 2'b0 } ; + _theResult___fst_exp__h403253 != 8'd255 && + guard__h395154 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ^ @@ -23462,15 +23584,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049 = { 3'd0, - _theResult___fst_exp__h448942 == 8'd0 && - (sfdin__h448936[56:34] == 23'd0 || guard__h440843 != 2'b0), + _theResult___fst_exp__h448941 == 8'd0 && + (sfdin__h448935[56:34] == 23'd0 || guard__h440842 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h449539 == 8'd255 && - _theResult___fst_sfd__h449540 == 23'd0, + _theResult___fst_exp__h449538 == 8'd255 && + _theResult___fst_sfd__h449539 == 23'd0, 1'd0, - _theResult___fst_exp__h448942 != 8'd255 && - guard__h440843 != 2'b0 } ; + _theResult___fst_exp__h448941 != 8'd255 && + guard__h440842 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10476 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10474 } ^ @@ -23478,37 +23600,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10850 = { 3'd0, - _theResult___fst_exp__h515137 == 11'd0 && - (sfdin__h515131[56:5] == 52'd0 || guard__h506911 != 2'b0), + _theResult___fst_exp__h515136 == 11'd0 && + (sfdin__h515130[56:5] == 52'd0 || guard__h506910 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h515969 == 11'd2047 && - _theResult___fst_sfd__h515970 == 52'd0, + _theResult___fst_exp__h515968 == 11'd2047 && + _theResult___fst_sfd__h515969 == 52'd0, 1'd0, - _theResult___fst_exp__h515137 != 11'd2047 && - guard__h506911 != 2'b0 } ; + _theResult___fst_exp__h515136 != 11'd2047 && + guard__h506910 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10891 = { 3'd0, - _theResult___fst_exp__h553938 == 11'd0 && - (sfdin__h553932[56:5] == 52'd0 || guard__h545712 != 2'b0), + _theResult___fst_exp__h553937 == 11'd0 && + (sfdin__h553931[56:5] == 52'd0 || guard__h545711 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h554770 == 11'd2047 && - _theResult___fst_sfd__h554771 == 52'd0, + _theResult___fst_exp__h554769 == 11'd2047 && + _theResult___fst_sfd__h554770 == 52'd0, 1'd0, - _theResult___fst_exp__h553938 != 11'd2047 && - guard__h545712 != 2'b0 } ; + _theResult___fst_exp__h553937 != 11'd2047 && + guard__h545711 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10935 = { 3'd0, - _theResult___fst_exp__h593139 == 11'd0 && - (sfdin__h593133[56:5] == 52'd0 || guard__h584913 != 2'b0), + _theResult___fst_exp__h593138 == 11'd0 && + (sfdin__h593132[56:5] == 52'd0 || guard__h584912 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h593971 == 11'd2047 && - _theResult___fst_sfd__h593972 == 52'd0, + _theResult___fst_exp__h593970 == 11'd2047 && + _theResult___fst_sfd__h593971 == 52'd0, 1'd0, - _theResult___fst_exp__h593139 != 11'd2047 && - guard__h584913 != 2'b0 } ; + _theResult___fst_exp__h593138 != 11'd2047 && + guard__h584912 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9003 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9001 } ^ @@ -23526,15 +23648,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294 = { 3'd0, - _theResult___fst_exp__h375330 == 8'd0 && - (sfdin__h375324[56:34] == 23'd0 || guard__h367102 != 2'b0), + _theResult___fst_exp__h375329 == 8'd0 && + (sfdin__h375323[56:34] == 23'd0 || guard__h367101 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h375927 == 8'd255 && - _theResult___fst_sfd__h375928 == 23'd0, + _theResult___fst_exp__h375926 == 8'd255 && + _theResult___fst_sfd__h375927 == 23'd0, 1'd0, - _theResult___fst_exp__h375330 != 8'd255 && - guard__h367102 != 2'b0 } ; + _theResult___fst_exp__h375329 != 8'd255 && + guard__h367101 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ^ @@ -23542,15 +23664,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686 = { 3'd0, - _theResult___fst_exp__h421020 == 8'd0 && - (sfdin__h421014[56:34] == 23'd0 || guard__h412792 != 2'b0), + _theResult___fst_exp__h421019 == 8'd0 && + (sfdin__h421013[56:34] == 23'd0 || guard__h412791 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h421617 == 8'd255 && - _theResult___fst_sfd__h421618 == 23'd0, + _theResult___fst_exp__h421616 == 8'd255 && + _theResult___fst_sfd__h421617 == 23'd0, 1'd0, - _theResult___fst_exp__h421020 != 8'd255 && - guard__h412792 != 2'b0 } ; + _theResult___fst_exp__h421019 != 8'd255 && + guard__h412791 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ^ @@ -23558,15 +23680,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078 = { 3'd0, - _theResult___fst_exp__h466708 == 8'd0 && - (sfdin__h466702[56:34] == 23'd0 || guard__h458480 != 2'b0), + _theResult___fst_exp__h466707 == 8'd0 && + (sfdin__h466701[56:34] == 23'd0 || guard__h458479 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h467305 == 8'd255 && - _theResult___fst_sfd__h467306 == 23'd0, + _theResult___fst_exp__h467304 == 8'd255 && + _theResult___fst_sfd__h467305 == 23'd0, 1'd0, - _theResult___fst_exp__h466708 != 8'd255 && - guard__h458480 != 2'b0 } ; + _theResult___fst_exp__h466707 != 8'd255 && + guard__h458479 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ^ @@ -23580,15 +23702,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277 = { 3'd0, - _theResult___fst_exp__h366220 == 8'd0 && - guard__h358172 != 2'b0, + _theResult___fst_exp__h366219 == 8'd0 && + guard__h358171 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h366743 == 8'd255 && - _theResult___fst_sfd__h366744 == 23'd0, + _theResult___fst_exp__h366742 == 8'd255 && + _theResult___fst_sfd__h366743 == 23'd0, 1'd0, - _theResult___fst_exp__h366220 != 8'd255 && - guard__h358172 != 2'b0 } ; + _theResult___fst_exp__h366219 != 8'd255 && + guard__h358171 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ^ @@ -23602,15 +23724,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669 = { 3'd0, - _theResult___fst_exp__h411910 == 8'd0 && - guard__h403862 != 2'b0, + _theResult___fst_exp__h411909 == 8'd0 && + guard__h403861 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h412433 == 8'd255 && - _theResult___fst_sfd__h412434 == 23'd0, + _theResult___fst_exp__h412432 == 8'd255 && + _theResult___fst_sfd__h412433 == 23'd0, 1'd0, - _theResult___fst_exp__h411910 != 8'd255 && - guard__h403862 != 2'b0 } ; + _theResult___fst_exp__h411909 != 8'd255 && + guard__h403861 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ^ @@ -23624,15 +23746,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061 = { 3'd0, - _theResult___fst_exp__h457598 == 8'd0 && - guard__h449550 != 2'b0, + _theResult___fst_exp__h457597 == 8'd0 && + guard__h449549 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h458121 == 8'd255 && - _theResult___fst_sfd__h458122 == 23'd0, + _theResult___fst_exp__h458120 == 8'd255 && + _theResult___fst_sfd__h458121 == 23'd0, 1'd0, - _theResult___fst_exp__h457598 != 8'd255 && - guard__h449550 != 2'b0 } ; + _theResult___fst_exp__h457597 != 8'd255 && + guard__h449549 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10179 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10177 } ^ @@ -23646,39 +23768,39 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10833 = { 3'd0, - _theResult___fst_exp__h505560 == 11'd0 && - guard__h497599 != 2'b0, + _theResult___fst_exp__h505559 == 11'd0 && + guard__h497598 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h506318 == 11'd2047 && - _theResult___fst_sfd__h506319 == 52'd0, + _theResult___fst_exp__h506317 == 11'd2047 && + _theResult___fst_sfd__h506318 == 52'd0, 1'd0, - _theResult___fst_exp__h505560 != 11'd2047 && - guard__h497599 != 2'b0 } ; + _theResult___fst_exp__h505559 != 11'd2047 && + guard__h497598 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10874 = { 3'd0, - _theResult___fst_exp__h544361 == 11'd0 && - guard__h536400 != 2'b0, + _theResult___fst_exp__h544360 == 11'd0 && + guard__h536399 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h545119 == 11'd2047 && - _theResult___fst_sfd__h545120 == 52'd0, + _theResult___fst_exp__h545118 == 11'd2047 && + _theResult___fst_sfd__h545119 == 52'd0, 1'd0, - _theResult___fst_exp__h544361 != 11'd2047 && - guard__h536400 != 2'b0 } ; + _theResult___fst_exp__h544360 != 11'd2047 && + guard__h536399 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10918 = { 3'd0, - _theResult___fst_exp__h583562 == 11'd0 && - guard__h575601 != 2'b0, + _theResult___fst_exp__h583561 == 11'd0 && + guard__h575600 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h584320 == 11'd2047 && - _theResult___fst_sfd__h584321 == 52'd0, + _theResult___fst_exp__h584319 == 11'd2047 && + _theResult___fst_sfd__h584320 == 52'd0, 1'd0, - _theResult___fst_exp__h583562 != 11'd2047 && - guard__h575601 != 2'b0 } ; + _theResult___fst_exp__h583561 != 11'd2047 && + guard__h575600 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11174 = - b__h607086 * b__h607098 ; + b__h607085 * b__h607097 ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8691 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8689 } ^ @@ -23701,48 +23823,48 @@ module mkCore(CLK, 12'h800) <= (IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9762 ^ 12'h800) ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13803 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13894 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k69941_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2844_BI_ETC___d13888 = + CASE_k71298_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2844_BI_ETC___d13979 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && CASE_fetchStagepipelines_0_canDeq_AND_NOT_fet_ETC__q234 ; - assign _0_OR_fetchStage_RDY_pipelines_0_first__2832_37_ETC___d13714 = + assign _0_OR_fetchStage_RDY_pipelines_0_first__2832_38_ETC___d13802 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13442 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13501 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13686 ; + fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13774 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654 = - sfd__h341848 >> + sfd__h341847 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046 = - sfd__h387543 >> + sfd__h387542 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438 = - sfd__h433231 >> + sfd__h433230 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10232 = - sfd__h525501 >> + sfd__h525500 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10228 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8759 = - sfd__h486559 >> + sfd__h486558 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8755 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9469 = - sfd__h564702 >> + sfd__h564701 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9465 ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14420 = - medeleg_csr__read__h615534[i__h702286] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14402 = - mideleg_csr__read__h615629[i__h702446] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14513 = + medeleg_csr__read__h615533[i__h704446] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14495 = + mideleg_csr__read__h615628[i__h704606] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 = 12'd3074 - { 6'd0, @@ -24330,57 +24452,49 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13999 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14091 || + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; - assign _dfoo16 = - k__h669941 == 1'd1 && - fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964 || - (fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14069 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14078) == - 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14096 ; assign _dfoo18 = - k__h669941 == 1'd0 && - fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964 || - (fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14069 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14078) == + k__h671298 == 1'd0 && + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14056 || + fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14174 == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14096 ; + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14191 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14041 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 || + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo20 = + assign _dfoo22 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; assign _dfoo28 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + (IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd18) || rob$deqPort_0_deq_data[186:182] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14033 || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14125 || + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -24455,1430 +24569,1430 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h299893 = + assign _theResult_____2__h299894 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142) ? - next_deqP___1__h300172 : + next_deqP___1__h300173 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h307889 = + assign _theResult_____2__h307890 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249) ? - next_deqP___1__h308168 : + next_deqP___1__h308169 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h313883 = + assign _theResult_____2__h313884 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420) ? - next_deqP___1__h314449 : + next_deqP___1__h314450 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h321737 = + assign _theResult_____2__h321738 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516) ? - next_deqP___1__h322303 : + next_deqP___1__h322304 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h332081 = + assign _theResult_____2__h332082 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745) ? - next_deqP___1__h332360 : + next_deqP___1__h332361 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h335306 = + assign _theResult_____2__h335307 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839) ? - next_deqP___1__h335585 : + next_deqP___1__h335586 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h349453 = - (value__h350075 == 54'd0) ? sfd__h341848 : 57'd1 ; - assign _theResult____h367092 = + assign _theResult____h349452 = + (value__h350074 == 54'd0) ? sfd__h341847 : 57'd1 ; + assign _theResult____h367091 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ^ 12'h800) < 12'd2105) ? - result__h367705 : - _theResult____h349453 ; - assign _theResult____h395145 = - (value__h395765 == 54'd0) ? sfd__h387543 : 57'd1 ; - assign _theResult____h412782 = + result__h367704 : + _theResult____h349452 ; + assign _theResult____h395144 = + (value__h395764 == 54'd0) ? sfd__h387542 : 57'd1 ; + assign _theResult____h412781 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ^ 12'h800) < 12'd2105) ? - result__h413395 : - _theResult____h395145 ; - assign _theResult____h440833 = - (value__h441453 == 54'd0) ? sfd__h433231 : 57'd1 ; - assign _theResult____h458470 = + result__h413394 : + _theResult____h395144 ; + assign _theResult____h440832 = + (value__h441452 == 54'd0) ? sfd__h433230 : 57'd1 ; + assign _theResult____h458469 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ^ 12'h800) < 12'd2105) ? - result__h459083 : - _theResult____h440833 ; - assign _theResult____h506901 = + result__h459082 : + _theResult____h440832 ; + assign _theResult____h506900 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8755 ^ 12'h800) < 12'd2105) ? - result__h507514 : - ((value__h491117 == 25'd0) ? sfd__h486559 : 57'd1) ; - assign _theResult____h545702 = + result__h507513 : + ((value__h491116 == 25'd0) ? sfd__h486558 : 57'd1) ; + assign _theResult____h545701 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10228 ^ 12'h800) < 12'd2105) ? - result__h546315 : - ((value__h529918 == 25'd0) ? sfd__h525501 : 57'd1) ; - assign _theResult____h584903 = + result__h546314 : + ((value__h529917 == 25'd0) ? sfd__h525500 : 57'd1) ; + assign _theResult____h584902 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9465 ^ 12'h800) < 12'd2105) ? - result__h585516 : - ((value__h569119 == 25'd0) ? sfd__h564702 : 57'd1) ; - assign _theResult____h655195 = + result__h585515 : + ((value__h569118 == 25'd0) ? sfd__h564701 : 57'd1) ; + assign _theResult____h655200 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h655692 : + enabled_ints___1__h655697 : 15'd0 ; - assign _theResult___exp__h358080 = - sfd__h357656[24] ? - ((_theResult___fst_exp__h357564 == 8'd254) ? + assign _theResult___exp__h358079 = + sfd__h357655[24] ? + ((_theResult___fst_exp__h357563 == 8'd254) ? 8'd255 : - din_inc___2_exp__h384597) : - ((_theResult___fst_exp__h357564 == 8'd0 && - sfd__h357656[24:23] == 2'b01) ? + din_inc___2_exp__h384596) : + ((_theResult___fst_exp__h357563 == 8'd0 && + sfd__h357655[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h357564) ; - assign _theResult___exp__h366662 = - sfd__h366238[24] ? - ((_theResult___fst_exp__h366220 == 8'd254) ? + _theResult___fst_exp__h357563) ; + assign _theResult___exp__h366661 = + sfd__h366237[24] ? + ((_theResult___fst_exp__h366219 == 8'd254) ? 8'd255 : - din_inc___2_exp__h384621) : - ((_theResult___fst_exp__h366220 == 8'd0 && - sfd__h366238[24:23] == 2'b01) ? + din_inc___2_exp__h384620) : + ((_theResult___fst_exp__h366219 == 8'd0 && + sfd__h366237[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h366220) ; - assign _theResult___exp__h375846 = - sfd__h375422[24] ? - ((_theResult___fst_exp__h375330 == 8'd254) ? + _theResult___fst_exp__h366219) ; + assign _theResult___exp__h375845 = + sfd__h375421[24] ? + ((_theResult___fst_exp__h375329 == 8'd254) ? 8'd255 : - din_inc___2_exp__h384651) : - ((_theResult___fst_exp__h375330 == 8'd0 && - sfd__h375422[24:23] == 2'b01) ? + din_inc___2_exp__h384650) : + ((_theResult___fst_exp__h375329 == 8'd0 && + sfd__h375421[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h375330) ; - assign _theResult___exp__h384482 = - sfd__h384034[24] ? - ((_theResult___fst_exp__h384015 == 8'd254) ? + _theResult___fst_exp__h375329) ; + assign _theResult___exp__h384481 = + sfd__h384033[24] ? + ((_theResult___fst_exp__h384014 == 8'd254) ? 8'd255 : - din_inc___2_exp__h384675) : - ((_theResult___fst_exp__h384015 == 8'd0 && - sfd__h384034[24:23] == 2'b01) ? + din_inc___2_exp__h384674) : + ((_theResult___fst_exp__h384014 == 8'd0 && + sfd__h384033[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h384015) ; - assign _theResult___exp__h384584 = + _theResult___fst_exp__h384014) ; + assign _theResult___exp__h384583 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h384575 ; - assign _theResult___exp__h403770 = - sfd__h403346[24] ? - ((_theResult___fst_exp__h403254 == 8'd254) ? + _theResult___fst_exp__h384574 ; + assign _theResult___exp__h403769 = + sfd__h403345[24] ? + ((_theResult___fst_exp__h403253 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430287) : - ((_theResult___fst_exp__h403254 == 8'd0 && - sfd__h403346[24:23] == 2'b01) ? + din_inc___2_exp__h430286) : + ((_theResult___fst_exp__h403253 == 8'd0 && + sfd__h403345[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h403254) ; - assign _theResult___exp__h412352 = - sfd__h411928[24] ? - ((_theResult___fst_exp__h411910 == 8'd254) ? + _theResult___fst_exp__h403253) ; + assign _theResult___exp__h412351 = + sfd__h411927[24] ? + ((_theResult___fst_exp__h411909 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430311) : - ((_theResult___fst_exp__h411910 == 8'd0 && - sfd__h411928[24:23] == 2'b01) ? + din_inc___2_exp__h430310) : + ((_theResult___fst_exp__h411909 == 8'd0 && + sfd__h411927[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h411910) ; - assign _theResult___exp__h421536 = - sfd__h421112[24] ? - ((_theResult___fst_exp__h421020 == 8'd254) ? + _theResult___fst_exp__h411909) ; + assign _theResult___exp__h421535 = + sfd__h421111[24] ? + ((_theResult___fst_exp__h421019 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430341) : - ((_theResult___fst_exp__h421020 == 8'd0 && - sfd__h421112[24:23] == 2'b01) ? + din_inc___2_exp__h430340) : + ((_theResult___fst_exp__h421019 == 8'd0 && + sfd__h421111[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h421020) ; - assign _theResult___exp__h430172 = - sfd__h429724[24] ? - ((_theResult___fst_exp__h429705 == 8'd254) ? + _theResult___fst_exp__h421019) ; + assign _theResult___exp__h430171 = + sfd__h429723[24] ? + ((_theResult___fst_exp__h429704 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430365) : - ((_theResult___fst_exp__h429705 == 8'd0 && - sfd__h429724[24:23] == 2'b01) ? + din_inc___2_exp__h430364) : + ((_theResult___fst_exp__h429704 == 8'd0 && + sfd__h429723[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h429705) ; - assign _theResult___exp__h430274 = + _theResult___fst_exp__h429704) ; + assign _theResult___exp__h430273 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h430265 ; - assign _theResult___exp__h449458 = - sfd__h449034[24] ? - ((_theResult___fst_exp__h448942 == 8'd254) ? + _theResult___fst_exp__h430264 ; + assign _theResult___exp__h449457 = + sfd__h449033[24] ? + ((_theResult___fst_exp__h448941 == 8'd254) ? 8'd255 : - din_inc___2_exp__h475975) : - ((_theResult___fst_exp__h448942 == 8'd0 && - sfd__h449034[24:23] == 2'b01) ? + din_inc___2_exp__h475974) : + ((_theResult___fst_exp__h448941 == 8'd0 && + sfd__h449033[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h448942) ; - assign _theResult___exp__h458040 = - sfd__h457616[24] ? - ((_theResult___fst_exp__h457598 == 8'd254) ? + _theResult___fst_exp__h448941) ; + assign _theResult___exp__h458039 = + sfd__h457615[24] ? + ((_theResult___fst_exp__h457597 == 8'd254) ? 8'd255 : - din_inc___2_exp__h475999) : - ((_theResult___fst_exp__h457598 == 8'd0 && - sfd__h457616[24:23] == 2'b01) ? + din_inc___2_exp__h475998) : + ((_theResult___fst_exp__h457597 == 8'd0 && + sfd__h457615[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h457598) ; - assign _theResult___exp__h467224 = - sfd__h466800[24] ? - ((_theResult___fst_exp__h466708 == 8'd254) ? + _theResult___fst_exp__h457597) ; + assign _theResult___exp__h467223 = + sfd__h466799[24] ? + ((_theResult___fst_exp__h466707 == 8'd254) ? 8'd255 : - din_inc___2_exp__h476029) : - ((_theResult___fst_exp__h466708 == 8'd0 && - sfd__h466800[24:23] == 2'b01) ? + din_inc___2_exp__h476028) : + ((_theResult___fst_exp__h466707 == 8'd0 && + sfd__h466799[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h466708) ; - assign _theResult___exp__h475860 = - sfd__h475412[24] ? - ((_theResult___fst_exp__h475393 == 8'd254) ? + _theResult___fst_exp__h466707) ; + assign _theResult___exp__h475859 = + sfd__h475411[24] ? + ((_theResult___fst_exp__h475392 == 8'd254) ? 8'd255 : - din_inc___2_exp__h476053) : - ((_theResult___fst_exp__h475393 == 8'd0 && - sfd__h475412[24:23] == 2'b01) ? + din_inc___2_exp__h476052) : + ((_theResult___fst_exp__h475392 == 8'd0 && + sfd__h475411[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h475393) ; - assign _theResult___exp__h475962 = + _theResult___fst_exp__h475392) ; + assign _theResult___exp__h475961 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h475953 ; - assign _theResult___exp__h506215 = - sfd__h505578[53] ? - ((_theResult___fst_exp__h505560 == 11'd2046) ? + _theResult___fst_exp__h475952 ; + assign _theResult___exp__h506214 = + sfd__h505577[53] ? + ((_theResult___fst_exp__h505559 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h524810) : - ((_theResult___fst_exp__h505560 == 11'd0 && - sfd__h505578[53:52] == 2'b01) ? + din_inc___2_exp__h524809) : + ((_theResult___fst_exp__h505559 == 11'd0 && + sfd__h505577[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h505560) ; - assign _theResult___exp__h515866 = - sfd__h515229[53] ? - ((_theResult___fst_exp__h515137 == 11'd2046) ? + _theResult___fst_exp__h505559) ; + assign _theResult___exp__h515865 = + sfd__h515228[53] ? + ((_theResult___fst_exp__h515136 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h524845) : - ((_theResult___fst_exp__h515137 == 11'd0 && - sfd__h515229[53:52] == 2'b01) ? + din_inc___2_exp__h524844) : + ((_theResult___fst_exp__h515136 == 11'd0 && + sfd__h515228[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h515137) ; - assign _theResult___exp__h524650 = - sfd__h523989[53] ? - ((_theResult___fst_exp__h523970 == 11'd2046) ? + _theResult___fst_exp__h515136) ; + assign _theResult___exp__h524649 = + sfd__h523988[53] ? + ((_theResult___fst_exp__h523969 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h524871) : - ((_theResult___fst_exp__h523970 == 11'd0 && - sfd__h523989[53:52] == 2'b01) ? + din_inc___2_exp__h524870) : + ((_theResult___fst_exp__h523969 == 11'd0 && + sfd__h523988[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h523970) ; - assign _theResult___exp__h545016 = - sfd__h544379[53] ? - ((_theResult___fst_exp__h544361 == 11'd2046) ? + _theResult___fst_exp__h523969) ; + assign _theResult___exp__h545015 = + sfd__h544378[53] ? + ((_theResult___fst_exp__h544360 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h563611) : - ((_theResult___fst_exp__h544361 == 11'd0 && - sfd__h544379[53:52] == 2'b01) ? + din_inc___2_exp__h563610) : + ((_theResult___fst_exp__h544360 == 11'd0 && + sfd__h544378[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h544361) ; - assign _theResult___exp__h554667 = - sfd__h554030[53] ? - ((_theResult___fst_exp__h553938 == 11'd2046) ? + _theResult___fst_exp__h544360) ; + assign _theResult___exp__h554666 = + sfd__h554029[53] ? + ((_theResult___fst_exp__h553937 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h563646) : - ((_theResult___fst_exp__h553938 == 11'd0 && - sfd__h554030[53:52] == 2'b01) ? + din_inc___2_exp__h563645) : + ((_theResult___fst_exp__h553937 == 11'd0 && + sfd__h554029[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h553938) ; - assign _theResult___exp__h563451 = - sfd__h562790[53] ? - ((_theResult___fst_exp__h562771 == 11'd2046) ? + _theResult___fst_exp__h553937) ; + assign _theResult___exp__h563450 = + sfd__h562789[53] ? + ((_theResult___fst_exp__h562770 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h563672) : - ((_theResult___fst_exp__h562771 == 11'd0 && - sfd__h562790[53:52] == 2'b01) ? + din_inc___2_exp__h563671) : + ((_theResult___fst_exp__h562770 == 11'd0 && + sfd__h562789[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h562771) ; - assign _theResult___exp__h584217 = - sfd__h583580[53] ? - ((_theResult___fst_exp__h583562 == 11'd2046) ? + _theResult___fst_exp__h562770) ; + assign _theResult___exp__h584216 = + sfd__h583579[53] ? + ((_theResult___fst_exp__h583561 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h602812) : - ((_theResult___fst_exp__h583562 == 11'd0 && - sfd__h583580[53:52] == 2'b01) ? + din_inc___2_exp__h602811) : + ((_theResult___fst_exp__h583561 == 11'd0 && + sfd__h583579[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h583562) ; - assign _theResult___exp__h593868 = - sfd__h593231[53] ? - ((_theResult___fst_exp__h593139 == 11'd2046) ? + _theResult___fst_exp__h583561) ; + assign _theResult___exp__h593867 = + sfd__h593230[53] ? + ((_theResult___fst_exp__h593138 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h602847) : - ((_theResult___fst_exp__h593139 == 11'd0 && - sfd__h593231[53:52] == 2'b01) ? + din_inc___2_exp__h602846) : + ((_theResult___fst_exp__h593138 == 11'd0 && + sfd__h593230[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h593139) ; - assign _theResult___exp__h602652 = - sfd__h601991[53] ? - ((_theResult___fst_exp__h601972 == 11'd2046) ? + _theResult___fst_exp__h593138) ; + assign _theResult___exp__h602651 = + sfd__h601990[53] ? + ((_theResult___fst_exp__h601971 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h602873) : - ((_theResult___fst_exp__h601972 == 11'd0 && - sfd__h601991[53:52] == 2'b01) ? + din_inc___2_exp__h602872) : + ((_theResult___fst_exp__h601971 == 11'd0 && + sfd__h601990[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h601972) ; - assign _theResult___fst__h607309 = - a__h606761[63] ? a___1__h607314 : a__h606761 ; - assign _theResult___fst_exp__h357564 = - _theResult____h349453[56] ? + _theResult___fst_exp__h601971) ; + assign _theResult___fst__h607308 = + a__h606760[63] ? a___1__h607313 : a__h606760 ; + assign _theResult___fst_exp__h357563 = + _theResult____h349452[56] ? 8'd2 : - _theResult___fst_exp__h357638 ; - assign _theResult___fst_exp__h357629 = + _theResult___fst_exp__h357637 ; + assign _theResult___fst_exp__h357628 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 } ; - assign _theResult___fst_exp__h357635 = - (!_theResult____h349453[56] && !_theResult____h349453[55] && - !_theResult____h349453[54] && - !_theResult____h349453[53] && - !_theResult____h349453[52] && - !_theResult____h349453[51] && - !_theResult____h349453[50] && - !_theResult____h349453[49] && - !_theResult____h349453[48] && - !_theResult____h349453[47] && - !_theResult____h349453[46] && - !_theResult____h349453[45] && - !_theResult____h349453[44] && - !_theResult____h349453[43] && - !_theResult____h349453[42] && - !_theResult____h349453[41] && - !_theResult____h349453[40] && - !_theResult____h349453[39] && - !_theResult____h349453[38] && - !_theResult____h349453[37] && - !_theResult____h349453[36] && - !_theResult____h349453[35] && - !_theResult____h349453[34] && - !_theResult____h349453[33] && - !_theResult____h349453[32] && - !_theResult____h349453[31] && - !_theResult____h349453[30] && - !_theResult____h349453[29] && - !_theResult____h349453[28] && - !_theResult____h349453[27] && - !_theResult____h349453[26] && - !_theResult____h349453[25] && - !_theResult____h349453[24] && - !_theResult____h349453[23] && - !_theResult____h349453[22] && - !_theResult____h349453[21] && - !_theResult____h349453[20] && - !_theResult____h349453[19] && - !_theResult____h349453[18] && - !_theResult____h349453[17] && - !_theResult____h349453[16] && - !_theResult____h349453[15] && - !_theResult____h349453[14] && - !_theResult____h349453[13] && - !_theResult____h349453[12] && - !_theResult____h349453[11] && - !_theResult____h349453[10] && - !_theResult____h349453[9] && - !_theResult____h349453[8] && - !_theResult____h349453[7] && - !_theResult____h349453[6] && - !_theResult____h349453[5] && - !_theResult____h349453[4] && - !_theResult____h349453[3] && - !_theResult____h349453[2] && - !_theResult____h349453[1] && - !_theResult____h349453[0] || + assign _theResult___fst_exp__h357634 = + (!_theResult____h349452[56] && !_theResult____h349452[55] && + !_theResult____h349452[54] && + !_theResult____h349452[53] && + !_theResult____h349452[52] && + !_theResult____h349452[51] && + !_theResult____h349452[50] && + !_theResult____h349452[49] && + !_theResult____h349452[48] && + !_theResult____h349452[47] && + !_theResult____h349452[46] && + !_theResult____h349452[45] && + !_theResult____h349452[44] && + !_theResult____h349452[43] && + !_theResult____h349452[42] && + !_theResult____h349452[41] && + !_theResult____h349452[40] && + !_theResult____h349452[39] && + !_theResult____h349452[38] && + !_theResult____h349452[37] && + !_theResult____h349452[36] && + !_theResult____h349452[35] && + !_theResult____h349452[34] && + !_theResult____h349452[33] && + !_theResult____h349452[32] && + !_theResult____h349452[31] && + !_theResult____h349452[30] && + !_theResult____h349452[29] && + !_theResult____h349452[28] && + !_theResult____h349452[27] && + !_theResult____h349452[26] && + !_theResult____h349452[25] && + !_theResult____h349452[24] && + !_theResult____h349452[23] && + !_theResult____h349452[22] && + !_theResult____h349452[21] && + !_theResult____h349452[20] && + !_theResult____h349452[19] && + !_theResult____h349452[18] && + !_theResult____h349452[17] && + !_theResult____h349452[16] && + !_theResult____h349452[15] && + !_theResult____h349452[14] && + !_theResult____h349452[13] && + !_theResult____h349452[12] && + !_theResult____h349452[11] && + !_theResult____h349452[10] && + !_theResult____h349452[9] && + !_theResult____h349452[8] && + !_theResult____h349452[7] && + !_theResult____h349452[6] && + !_theResult____h349452[5] && + !_theResult____h349452[4] && + !_theResult____h349452[3] && + !_theResult____h349452[2] && + !_theResult____h349452[1] && + !_theResult____h349452[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345) ? 8'd0 : - _theResult___fst_exp__h357629 ; - assign _theResult___fst_exp__h357638 = - (!_theResult____h349453[56] && _theResult____h349453[55]) ? + _theResult___fst_exp__h357628 ; + assign _theResult___fst_exp__h357637 = + (!_theResult____h349452[56] && _theResult____h349452[55]) ? 8'd1 : - _theResult___fst_exp__h357635 ; - assign _theResult___fst_exp__h358161 = - (_theResult___fst_exp__h357564 == 8'd255) ? - _theResult___fst_exp__h357564 : - _theResult___fst_exp__h358158 ; - assign _theResult___fst_exp__h366211 = + _theResult___fst_exp__h357634 ; + assign _theResult___fst_exp__h358160 = + (_theResult___fst_exp__h357563 == 8'd255) ? + _theResult___fst_exp__h357563 : + _theResult___fst_exp__h358157 ; + assign _theResult___fst_exp__h366210 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h366217 = + assign _theResult___fst_exp__h366216 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576) ? 8'd0 : - _theResult___fst_exp__h366211 ; - assign _theResult___fst_exp__h366220 = + _theResult___fst_exp__h366210 ; + assign _theResult___fst_exp__h366219 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h366217 : + _theResult___fst_exp__h366216 : 8'd129 ; - assign _theResult___fst_exp__h366743 = - (_theResult___fst_exp__h366220 == 8'd255) ? - _theResult___fst_exp__h366220 : - _theResult___fst_exp__h366740 ; - assign _theResult___fst_exp__h375330 = - _theResult____h367092[56] ? + assign _theResult___fst_exp__h366742 = + (_theResult___fst_exp__h366219 == 8'd255) ? + _theResult___fst_exp__h366219 : + _theResult___fst_exp__h366739 ; + assign _theResult___fst_exp__h375329 = + _theResult____h367091[56] ? 8'd2 : - _theResult___fst_exp__h375404 ; - assign _theResult___fst_exp__h375395 = + _theResult___fst_exp__h375403 ; + assign _theResult___fst_exp__h375394 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 } ; - assign _theResult___fst_exp__h375401 = - (!_theResult____h367092[56] && !_theResult____h367092[55] && - !_theResult____h367092[54] && - !_theResult____h367092[53] && - !_theResult____h367092[52] && - !_theResult____h367092[51] && - !_theResult____h367092[50] && - !_theResult____h367092[49] && - !_theResult____h367092[48] && - !_theResult____h367092[47] && - !_theResult____h367092[46] && - !_theResult____h367092[45] && - !_theResult____h367092[44] && - !_theResult____h367092[43] && - !_theResult____h367092[42] && - !_theResult____h367092[41] && - !_theResult____h367092[40] && - !_theResult____h367092[39] && - !_theResult____h367092[38] && - !_theResult____h367092[37] && - !_theResult____h367092[36] && - !_theResult____h367092[35] && - !_theResult____h367092[34] && - !_theResult____h367092[33] && - !_theResult____h367092[32] && - !_theResult____h367092[31] && - !_theResult____h367092[30] && - !_theResult____h367092[29] && - !_theResult____h367092[28] && - !_theResult____h367092[27] && - !_theResult____h367092[26] && - !_theResult____h367092[25] && - !_theResult____h367092[24] && - !_theResult____h367092[23] && - !_theResult____h367092[22] && - !_theResult____h367092[21] && - !_theResult____h367092[20] && - !_theResult____h367092[19] && - !_theResult____h367092[18] && - !_theResult____h367092[17] && - !_theResult____h367092[16] && - !_theResult____h367092[15] && - !_theResult____h367092[14] && - !_theResult____h367092[13] && - !_theResult____h367092[12] && - !_theResult____h367092[11] && - !_theResult____h367092[10] && - !_theResult____h367092[9] && - !_theResult____h367092[8] && - !_theResult____h367092[7] && - !_theResult____h367092[6] && - !_theResult____h367092[5] && - !_theResult____h367092[4] && - !_theResult____h367092[3] && - !_theResult____h367092[2] && - !_theResult____h367092[1] && - !_theResult____h367092[0] || + assign _theResult___fst_exp__h375400 = + (!_theResult____h367091[56] && !_theResult____h367091[55] && + !_theResult____h367091[54] && + !_theResult____h367091[53] && + !_theResult____h367091[52] && + !_theResult____h367091[51] && + !_theResult____h367091[50] && + !_theResult____h367091[49] && + !_theResult____h367091[48] && + !_theResult____h367091[47] && + !_theResult____h367091[46] && + !_theResult____h367091[45] && + !_theResult____h367091[44] && + !_theResult____h367091[43] && + !_theResult____h367091[42] && + !_theResult____h367091[41] && + !_theResult____h367091[40] && + !_theResult____h367091[39] && + !_theResult____h367091[38] && + !_theResult____h367091[37] && + !_theResult____h367091[36] && + !_theResult____h367091[35] && + !_theResult____h367091[34] && + !_theResult____h367091[33] && + !_theResult____h367091[32] && + !_theResult____h367091[31] && + !_theResult____h367091[30] && + !_theResult____h367091[29] && + !_theResult____h367091[28] && + !_theResult____h367091[27] && + !_theResult____h367091[26] && + !_theResult____h367091[25] && + !_theResult____h367091[24] && + !_theResult____h367091[23] && + !_theResult____h367091[22] && + !_theResult____h367091[21] && + !_theResult____h367091[20] && + !_theResult____h367091[19] && + !_theResult____h367091[18] && + !_theResult____h367091[17] && + !_theResult____h367091[16] && + !_theResult____h367091[15] && + !_theResult____h367091[14] && + !_theResult____h367091[13] && + !_theResult____h367091[12] && + !_theResult____h367091[11] && + !_theResult____h367091[10] && + !_theResult____h367091[9] && + !_theResult____h367091[8] && + !_theResult____h367091[7] && + !_theResult____h367091[6] && + !_theResult____h367091[5] && + !_theResult____h367091[4] && + !_theResult____h367091[3] && + !_theResult____h367091[2] && + !_theResult____h367091[1] && + !_theResult____h367091[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896) ? 8'd0 : - _theResult___fst_exp__h375395 ; - assign _theResult___fst_exp__h375404 = - (!_theResult____h367092[56] && _theResult____h367092[55]) ? + _theResult___fst_exp__h375394 ; + assign _theResult___fst_exp__h375403 = + (!_theResult____h367091[56] && _theResult____h367091[55]) ? 8'd1 : - _theResult___fst_exp__h375401 ; - assign _theResult___fst_exp__h375927 = - (_theResult___fst_exp__h375330 == 8'd255) ? - _theResult___fst_exp__h375330 : - _theResult___fst_exp__h375924 ; - assign _theResult___fst_exp__h383967 = + _theResult___fst_exp__h375400 ; + assign _theResult___fst_exp__h375926 = + (_theResult___fst_exp__h375329 == 8'd255) ? + _theResult___fst_exp__h375329 : + _theResult___fst_exp__h375923 ; + assign _theResult___fst_exp__h383966 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ; - assign _theResult___fst_exp__h384006 = + assign _theResult___fst_exp__h384005 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h384012 = + assign _theResult___fst_exp__h384011 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969) ? 8'd0 : - _theResult___fst_exp__h384006 ; - assign _theResult___fst_exp__h384015 = + _theResult___fst_exp__h384005 ; + assign _theResult___fst_exp__h384014 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h384012 : - _theResult___fst_exp__h383967 ; - assign _theResult___fst_exp__h384563 = - (_theResult___fst_exp__h384015 == 8'd255) ? - _theResult___fst_exp__h384015 : - _theResult___fst_exp__h384560 ; - assign _theResult___fst_exp__h384572 = + _theResult___fst_exp__h384011 : + _theResult___fst_exp__h383966 ; + assign _theResult___fst_exp__h384562 = + (_theResult___fst_exp__h384014 == 8'd255) ? + _theResult___fst_exp__h384014 : + _theResult___fst_exp__h384559 ; + assign _theResult___fst_exp__h384571 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_exp__h366746 : - _theResult___fst_exp__h349435) : + _theResult___snd_fst_exp__h366745 : + _theResult___fst_exp__h349434) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_exp__h384566 : - _theResult___fst_exp__h349435) ; - assign _theResult___fst_exp__h384575 = + _theResult___snd_fst_exp__h384565 : + _theResult___fst_exp__h349434) ; + assign _theResult___fst_exp__h384574 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h384572 ; - assign _theResult___fst_exp__h403254 = - _theResult____h395145[56] ? + _theResult___fst_exp__h384571 ; + assign _theResult___fst_exp__h403253 = + _theResult____h395144[56] ? 8'd2 : - _theResult___fst_exp__h403328 ; - assign _theResult___fst_exp__h403319 = + _theResult___fst_exp__h403327 ; + assign _theResult___fst_exp__h403318 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ; - assign _theResult___fst_exp__h403325 = - (!_theResult____h395145[56] && !_theResult____h395145[55] && - !_theResult____h395145[54] && - !_theResult____h395145[53] && - !_theResult____h395145[52] && - !_theResult____h395145[51] && - !_theResult____h395145[50] && - !_theResult____h395145[49] && - !_theResult____h395145[48] && - !_theResult____h395145[47] && - !_theResult____h395145[46] && - !_theResult____h395145[45] && - !_theResult____h395145[44] && - !_theResult____h395145[43] && - !_theResult____h395145[42] && - !_theResult____h395145[41] && - !_theResult____h395145[40] && - !_theResult____h395145[39] && - !_theResult____h395145[38] && - !_theResult____h395145[37] && - !_theResult____h395145[36] && - !_theResult____h395145[35] && - !_theResult____h395145[34] && - !_theResult____h395145[33] && - !_theResult____h395145[32] && - !_theResult____h395145[31] && - !_theResult____h395145[30] && - !_theResult____h395145[29] && - !_theResult____h395145[28] && - !_theResult____h395145[27] && - !_theResult____h395145[26] && - !_theResult____h395145[25] && - !_theResult____h395145[24] && - !_theResult____h395145[23] && - !_theResult____h395145[22] && - !_theResult____h395145[21] && - !_theResult____h395145[20] && - !_theResult____h395145[19] && - !_theResult____h395145[18] && - !_theResult____h395145[17] && - !_theResult____h395145[16] && - !_theResult____h395145[15] && - !_theResult____h395145[14] && - !_theResult____h395145[13] && - !_theResult____h395145[12] && - !_theResult____h395145[11] && - !_theResult____h395145[10] && - !_theResult____h395145[9] && - !_theResult____h395145[8] && - !_theResult____h395145[7] && - !_theResult____h395145[6] && - !_theResult____h395145[5] && - !_theResult____h395145[4] && - !_theResult____h395145[3] && - !_theResult____h395145[2] && - !_theResult____h395145[1] && - !_theResult____h395145[0] || + assign _theResult___fst_exp__h403324 = + (!_theResult____h395144[56] && !_theResult____h395144[55] && + !_theResult____h395144[54] && + !_theResult____h395144[53] && + !_theResult____h395144[52] && + !_theResult____h395144[51] && + !_theResult____h395144[50] && + !_theResult____h395144[49] && + !_theResult____h395144[48] && + !_theResult____h395144[47] && + !_theResult____h395144[46] && + !_theResult____h395144[45] && + !_theResult____h395144[44] && + !_theResult____h395144[43] && + !_theResult____h395144[42] && + !_theResult____h395144[41] && + !_theResult____h395144[40] && + !_theResult____h395144[39] && + !_theResult____h395144[38] && + !_theResult____h395144[37] && + !_theResult____h395144[36] && + !_theResult____h395144[35] && + !_theResult____h395144[34] && + !_theResult____h395144[33] && + !_theResult____h395144[32] && + !_theResult____h395144[31] && + !_theResult____h395144[30] && + !_theResult____h395144[29] && + !_theResult____h395144[28] && + !_theResult____h395144[27] && + !_theResult____h395144[26] && + !_theResult____h395144[25] && + !_theResult____h395144[24] && + !_theResult____h395144[23] && + !_theResult____h395144[22] && + !_theResult____h395144[21] && + !_theResult____h395144[20] && + !_theResult____h395144[19] && + !_theResult____h395144[18] && + !_theResult____h395144[17] && + !_theResult____h395144[16] && + !_theResult____h395144[15] && + !_theResult____h395144[14] && + !_theResult____h395144[13] && + !_theResult____h395144[12] && + !_theResult____h395144[11] && + !_theResult____h395144[10] && + !_theResult____h395144[9] && + !_theResult____h395144[8] && + !_theResult____h395144[7] && + !_theResult____h395144[6] && + !_theResult____h395144[5] && + !_theResult____h395144[4] && + !_theResult____h395144[3] && + !_theResult____h395144[2] && + !_theResult____h395144[1] && + !_theResult____h395144[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737) ? 8'd0 : - _theResult___fst_exp__h403319 ; - assign _theResult___fst_exp__h403328 = - (!_theResult____h395145[56] && _theResult____h395145[55]) ? + _theResult___fst_exp__h403318 ; + assign _theResult___fst_exp__h403327 = + (!_theResult____h395144[56] && _theResult____h395144[55]) ? 8'd1 : - _theResult___fst_exp__h403325 ; - assign _theResult___fst_exp__h403851 = - (_theResult___fst_exp__h403254 == 8'd255) ? - _theResult___fst_exp__h403254 : - _theResult___fst_exp__h403848 ; - assign _theResult___fst_exp__h411901 = + _theResult___fst_exp__h403324 ; + assign _theResult___fst_exp__h403850 = + (_theResult___fst_exp__h403253 == 8'd255) ? + _theResult___fst_exp__h403253 : + _theResult___fst_exp__h403847 ; + assign _theResult___fst_exp__h411900 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h411907 = + assign _theResult___fst_exp__h411906 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968) ? 8'd0 : - _theResult___fst_exp__h411901 ; - assign _theResult___fst_exp__h411910 = + _theResult___fst_exp__h411900 ; + assign _theResult___fst_exp__h411909 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h411907 : + _theResult___fst_exp__h411906 : 8'd129 ; - assign _theResult___fst_exp__h412433 = - (_theResult___fst_exp__h411910 == 8'd255) ? - _theResult___fst_exp__h411910 : - _theResult___fst_exp__h412430 ; - assign _theResult___fst_exp__h421020 = - _theResult____h412782[56] ? + assign _theResult___fst_exp__h412432 = + (_theResult___fst_exp__h411909 == 8'd255) ? + _theResult___fst_exp__h411909 : + _theResult___fst_exp__h412429 ; + assign _theResult___fst_exp__h421019 = + _theResult____h412781[56] ? 8'd2 : - _theResult___fst_exp__h421094 ; - assign _theResult___fst_exp__h421085 = + _theResult___fst_exp__h421093 ; + assign _theResult___fst_exp__h421084 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ; - assign _theResult___fst_exp__h421091 = - (!_theResult____h412782[56] && !_theResult____h412782[55] && - !_theResult____h412782[54] && - !_theResult____h412782[53] && - !_theResult____h412782[52] && - !_theResult____h412782[51] && - !_theResult____h412782[50] && - !_theResult____h412782[49] && - !_theResult____h412782[48] && - !_theResult____h412782[47] && - !_theResult____h412782[46] && - !_theResult____h412782[45] && - !_theResult____h412782[44] && - !_theResult____h412782[43] && - !_theResult____h412782[42] && - !_theResult____h412782[41] && - !_theResult____h412782[40] && - !_theResult____h412782[39] && - !_theResult____h412782[38] && - !_theResult____h412782[37] && - !_theResult____h412782[36] && - !_theResult____h412782[35] && - !_theResult____h412782[34] && - !_theResult____h412782[33] && - !_theResult____h412782[32] && - !_theResult____h412782[31] && - !_theResult____h412782[30] && - !_theResult____h412782[29] && - !_theResult____h412782[28] && - !_theResult____h412782[27] && - !_theResult____h412782[26] && - !_theResult____h412782[25] && - !_theResult____h412782[24] && - !_theResult____h412782[23] && - !_theResult____h412782[22] && - !_theResult____h412782[21] && - !_theResult____h412782[20] && - !_theResult____h412782[19] && - !_theResult____h412782[18] && - !_theResult____h412782[17] && - !_theResult____h412782[16] && - !_theResult____h412782[15] && - !_theResult____h412782[14] && - !_theResult____h412782[13] && - !_theResult____h412782[12] && - !_theResult____h412782[11] && - !_theResult____h412782[10] && - !_theResult____h412782[9] && - !_theResult____h412782[8] && - !_theResult____h412782[7] && - !_theResult____h412782[6] && - !_theResult____h412782[5] && - !_theResult____h412782[4] && - !_theResult____h412782[3] && - !_theResult____h412782[2] && - !_theResult____h412782[1] && - !_theResult____h412782[0] || + assign _theResult___fst_exp__h421090 = + (!_theResult____h412781[56] && !_theResult____h412781[55] && + !_theResult____h412781[54] && + !_theResult____h412781[53] && + !_theResult____h412781[52] && + !_theResult____h412781[51] && + !_theResult____h412781[50] && + !_theResult____h412781[49] && + !_theResult____h412781[48] && + !_theResult____h412781[47] && + !_theResult____h412781[46] && + !_theResult____h412781[45] && + !_theResult____h412781[44] && + !_theResult____h412781[43] && + !_theResult____h412781[42] && + !_theResult____h412781[41] && + !_theResult____h412781[40] && + !_theResult____h412781[39] && + !_theResult____h412781[38] && + !_theResult____h412781[37] && + !_theResult____h412781[36] && + !_theResult____h412781[35] && + !_theResult____h412781[34] && + !_theResult____h412781[33] && + !_theResult____h412781[32] && + !_theResult____h412781[31] && + !_theResult____h412781[30] && + !_theResult____h412781[29] && + !_theResult____h412781[28] && + !_theResult____h412781[27] && + !_theResult____h412781[26] && + !_theResult____h412781[25] && + !_theResult____h412781[24] && + !_theResult____h412781[23] && + !_theResult____h412781[22] && + !_theResult____h412781[21] && + !_theResult____h412781[20] && + !_theResult____h412781[19] && + !_theResult____h412781[18] && + !_theResult____h412781[17] && + !_theResult____h412781[16] && + !_theResult____h412781[15] && + !_theResult____h412781[14] && + !_theResult____h412781[13] && + !_theResult____h412781[12] && + !_theResult____h412781[11] && + !_theResult____h412781[10] && + !_theResult____h412781[9] && + !_theResult____h412781[8] && + !_theResult____h412781[7] && + !_theResult____h412781[6] && + !_theResult____h412781[5] && + !_theResult____h412781[4] && + !_theResult____h412781[3] && + !_theResult____h412781[2] && + !_theResult____h412781[1] && + !_theResult____h412781[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288) ? 8'd0 : - _theResult___fst_exp__h421085 ; - assign _theResult___fst_exp__h421094 = - (!_theResult____h412782[56] && _theResult____h412782[55]) ? + _theResult___fst_exp__h421084 ; + assign _theResult___fst_exp__h421093 = + (!_theResult____h412781[56] && _theResult____h412781[55]) ? 8'd1 : - _theResult___fst_exp__h421091 ; - assign _theResult___fst_exp__h421617 = - (_theResult___fst_exp__h421020 == 8'd255) ? - _theResult___fst_exp__h421020 : - _theResult___fst_exp__h421614 ; - assign _theResult___fst_exp__h429657 = + _theResult___fst_exp__h421090 ; + assign _theResult___fst_exp__h421616 = + (_theResult___fst_exp__h421019 == 8'd255) ? + _theResult___fst_exp__h421019 : + _theResult___fst_exp__h421613 ; + assign _theResult___fst_exp__h429656 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ; - assign _theResult___fst_exp__h429696 = + assign _theResult___fst_exp__h429695 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h429702 = + assign _theResult___fst_exp__h429701 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361) ? 8'd0 : - _theResult___fst_exp__h429696 ; - assign _theResult___fst_exp__h429705 = + _theResult___fst_exp__h429695 ; + assign _theResult___fst_exp__h429704 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h429702 : - _theResult___fst_exp__h429657 ; - assign _theResult___fst_exp__h430253 = - (_theResult___fst_exp__h429705 == 8'd255) ? - _theResult___fst_exp__h429705 : - _theResult___fst_exp__h430250 ; - assign _theResult___fst_exp__h430262 = + _theResult___fst_exp__h429701 : + _theResult___fst_exp__h429656 ; + assign _theResult___fst_exp__h430252 = + (_theResult___fst_exp__h429704 == 8'd255) ? + _theResult___fst_exp__h429704 : + _theResult___fst_exp__h430249 ; + assign _theResult___fst_exp__h430261 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_exp__h412436 : - _theResult___fst_exp__h395127) : + _theResult___snd_fst_exp__h412435 : + _theResult___fst_exp__h395126) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_exp__h430256 : - _theResult___fst_exp__h395127) ; - assign _theResult___fst_exp__h430265 = + _theResult___snd_fst_exp__h430255 : + _theResult___fst_exp__h395126) ; + assign _theResult___fst_exp__h430264 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h430262 ; - assign _theResult___fst_exp__h448942 = - _theResult____h440833[56] ? + _theResult___fst_exp__h430261 ; + assign _theResult___fst_exp__h448941 = + _theResult____h440832[56] ? 8'd2 : - _theResult___fst_exp__h449016 ; - assign _theResult___fst_exp__h449007 = + _theResult___fst_exp__h449015 ; + assign _theResult___fst_exp__h449006 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ; - assign _theResult___fst_exp__h449013 = - (!_theResult____h440833[56] && !_theResult____h440833[55] && - !_theResult____h440833[54] && - !_theResult____h440833[53] && - !_theResult____h440833[52] && - !_theResult____h440833[51] && - !_theResult____h440833[50] && - !_theResult____h440833[49] && - !_theResult____h440833[48] && - !_theResult____h440833[47] && - !_theResult____h440833[46] && - !_theResult____h440833[45] && - !_theResult____h440833[44] && - !_theResult____h440833[43] && - !_theResult____h440833[42] && - !_theResult____h440833[41] && - !_theResult____h440833[40] && - !_theResult____h440833[39] && - !_theResult____h440833[38] && - !_theResult____h440833[37] && - !_theResult____h440833[36] && - !_theResult____h440833[35] && - !_theResult____h440833[34] && - !_theResult____h440833[33] && - !_theResult____h440833[32] && - !_theResult____h440833[31] && - !_theResult____h440833[30] && - !_theResult____h440833[29] && - !_theResult____h440833[28] && - !_theResult____h440833[27] && - !_theResult____h440833[26] && - !_theResult____h440833[25] && - !_theResult____h440833[24] && - !_theResult____h440833[23] && - !_theResult____h440833[22] && - !_theResult____h440833[21] && - !_theResult____h440833[20] && - !_theResult____h440833[19] && - !_theResult____h440833[18] && - !_theResult____h440833[17] && - !_theResult____h440833[16] && - !_theResult____h440833[15] && - !_theResult____h440833[14] && - !_theResult____h440833[13] && - !_theResult____h440833[12] && - !_theResult____h440833[11] && - !_theResult____h440833[10] && - !_theResult____h440833[9] && - !_theResult____h440833[8] && - !_theResult____h440833[7] && - !_theResult____h440833[6] && - !_theResult____h440833[5] && - !_theResult____h440833[4] && - !_theResult____h440833[3] && - !_theResult____h440833[2] && - !_theResult____h440833[1] && - !_theResult____h440833[0] || + assign _theResult___fst_exp__h449012 = + (!_theResult____h440832[56] && !_theResult____h440832[55] && + !_theResult____h440832[54] && + !_theResult____h440832[53] && + !_theResult____h440832[52] && + !_theResult____h440832[51] && + !_theResult____h440832[50] && + !_theResult____h440832[49] && + !_theResult____h440832[48] && + !_theResult____h440832[47] && + !_theResult____h440832[46] && + !_theResult____h440832[45] && + !_theResult____h440832[44] && + !_theResult____h440832[43] && + !_theResult____h440832[42] && + !_theResult____h440832[41] && + !_theResult____h440832[40] && + !_theResult____h440832[39] && + !_theResult____h440832[38] && + !_theResult____h440832[37] && + !_theResult____h440832[36] && + !_theResult____h440832[35] && + !_theResult____h440832[34] && + !_theResult____h440832[33] && + !_theResult____h440832[32] && + !_theResult____h440832[31] && + !_theResult____h440832[30] && + !_theResult____h440832[29] && + !_theResult____h440832[28] && + !_theResult____h440832[27] && + !_theResult____h440832[26] && + !_theResult____h440832[25] && + !_theResult____h440832[24] && + !_theResult____h440832[23] && + !_theResult____h440832[22] && + !_theResult____h440832[21] && + !_theResult____h440832[20] && + !_theResult____h440832[19] && + !_theResult____h440832[18] && + !_theResult____h440832[17] && + !_theResult____h440832[16] && + !_theResult____h440832[15] && + !_theResult____h440832[14] && + !_theResult____h440832[13] && + !_theResult____h440832[12] && + !_theResult____h440832[11] && + !_theResult____h440832[10] && + !_theResult____h440832[9] && + !_theResult____h440832[8] && + !_theResult____h440832[7] && + !_theResult____h440832[6] && + !_theResult____h440832[5] && + !_theResult____h440832[4] && + !_theResult____h440832[3] && + !_theResult____h440832[2] && + !_theResult____h440832[1] && + !_theResult____h440832[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129) ? 8'd0 : - _theResult___fst_exp__h449007 ; - assign _theResult___fst_exp__h449016 = - (!_theResult____h440833[56] && _theResult____h440833[55]) ? + _theResult___fst_exp__h449006 ; + assign _theResult___fst_exp__h449015 = + (!_theResult____h440832[56] && _theResult____h440832[55]) ? 8'd1 : - _theResult___fst_exp__h449013 ; - assign _theResult___fst_exp__h449539 = - (_theResult___fst_exp__h448942 == 8'd255) ? - _theResult___fst_exp__h448942 : - _theResult___fst_exp__h449536 ; - assign _theResult___fst_exp__h457589 = + _theResult___fst_exp__h449012 ; + assign _theResult___fst_exp__h449538 = + (_theResult___fst_exp__h448941 == 8'd255) ? + _theResult___fst_exp__h448941 : + _theResult___fst_exp__h449535 ; + assign _theResult___fst_exp__h457588 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h457595 = + assign _theResult___fst_exp__h457594 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360) ? 8'd0 : - _theResult___fst_exp__h457589 ; - assign _theResult___fst_exp__h457598 = + _theResult___fst_exp__h457588 ; + assign _theResult___fst_exp__h457597 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h457595 : + _theResult___fst_exp__h457594 : 8'd129 ; - assign _theResult___fst_exp__h458121 = - (_theResult___fst_exp__h457598 == 8'd255) ? - _theResult___fst_exp__h457598 : - _theResult___fst_exp__h458118 ; - assign _theResult___fst_exp__h466708 = - _theResult____h458470[56] ? + assign _theResult___fst_exp__h458120 = + (_theResult___fst_exp__h457597 == 8'd255) ? + _theResult___fst_exp__h457597 : + _theResult___fst_exp__h458117 ; + assign _theResult___fst_exp__h466707 = + _theResult____h458469[56] ? 8'd2 : - _theResult___fst_exp__h466782 ; - assign _theResult___fst_exp__h466773 = + _theResult___fst_exp__h466781 ; + assign _theResult___fst_exp__h466772 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ; - assign _theResult___fst_exp__h466779 = - (!_theResult____h458470[56] && !_theResult____h458470[55] && - !_theResult____h458470[54] && - !_theResult____h458470[53] && - !_theResult____h458470[52] && - !_theResult____h458470[51] && - !_theResult____h458470[50] && - !_theResult____h458470[49] && - !_theResult____h458470[48] && - !_theResult____h458470[47] && - !_theResult____h458470[46] && - !_theResult____h458470[45] && - !_theResult____h458470[44] && - !_theResult____h458470[43] && - !_theResult____h458470[42] && - !_theResult____h458470[41] && - !_theResult____h458470[40] && - !_theResult____h458470[39] && - !_theResult____h458470[38] && - !_theResult____h458470[37] && - !_theResult____h458470[36] && - !_theResult____h458470[35] && - !_theResult____h458470[34] && - !_theResult____h458470[33] && - !_theResult____h458470[32] && - !_theResult____h458470[31] && - !_theResult____h458470[30] && - !_theResult____h458470[29] && - !_theResult____h458470[28] && - !_theResult____h458470[27] && - !_theResult____h458470[26] && - !_theResult____h458470[25] && - !_theResult____h458470[24] && - !_theResult____h458470[23] && - !_theResult____h458470[22] && - !_theResult____h458470[21] && - !_theResult____h458470[20] && - !_theResult____h458470[19] && - !_theResult____h458470[18] && - !_theResult____h458470[17] && - !_theResult____h458470[16] && - !_theResult____h458470[15] && - !_theResult____h458470[14] && - !_theResult____h458470[13] && - !_theResult____h458470[12] && - !_theResult____h458470[11] && - !_theResult____h458470[10] && - !_theResult____h458470[9] && - !_theResult____h458470[8] && - !_theResult____h458470[7] && - !_theResult____h458470[6] && - !_theResult____h458470[5] && - !_theResult____h458470[4] && - !_theResult____h458470[3] && - !_theResult____h458470[2] && - !_theResult____h458470[1] && - !_theResult____h458470[0] || + assign _theResult___fst_exp__h466778 = + (!_theResult____h458469[56] && !_theResult____h458469[55] && + !_theResult____h458469[54] && + !_theResult____h458469[53] && + !_theResult____h458469[52] && + !_theResult____h458469[51] && + !_theResult____h458469[50] && + !_theResult____h458469[49] && + !_theResult____h458469[48] && + !_theResult____h458469[47] && + !_theResult____h458469[46] && + !_theResult____h458469[45] && + !_theResult____h458469[44] && + !_theResult____h458469[43] && + !_theResult____h458469[42] && + !_theResult____h458469[41] && + !_theResult____h458469[40] && + !_theResult____h458469[39] && + !_theResult____h458469[38] && + !_theResult____h458469[37] && + !_theResult____h458469[36] && + !_theResult____h458469[35] && + !_theResult____h458469[34] && + !_theResult____h458469[33] && + !_theResult____h458469[32] && + !_theResult____h458469[31] && + !_theResult____h458469[30] && + !_theResult____h458469[29] && + !_theResult____h458469[28] && + !_theResult____h458469[27] && + !_theResult____h458469[26] && + !_theResult____h458469[25] && + !_theResult____h458469[24] && + !_theResult____h458469[23] && + !_theResult____h458469[22] && + !_theResult____h458469[21] && + !_theResult____h458469[20] && + !_theResult____h458469[19] && + !_theResult____h458469[18] && + !_theResult____h458469[17] && + !_theResult____h458469[16] && + !_theResult____h458469[15] && + !_theResult____h458469[14] && + !_theResult____h458469[13] && + !_theResult____h458469[12] && + !_theResult____h458469[11] && + !_theResult____h458469[10] && + !_theResult____h458469[9] && + !_theResult____h458469[8] && + !_theResult____h458469[7] && + !_theResult____h458469[6] && + !_theResult____h458469[5] && + !_theResult____h458469[4] && + !_theResult____h458469[3] && + !_theResult____h458469[2] && + !_theResult____h458469[1] && + !_theResult____h458469[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680) ? 8'd0 : - _theResult___fst_exp__h466773 ; - assign _theResult___fst_exp__h466782 = - (!_theResult____h458470[56] && _theResult____h458470[55]) ? + _theResult___fst_exp__h466772 ; + assign _theResult___fst_exp__h466781 = + (!_theResult____h458469[56] && _theResult____h458469[55]) ? 8'd1 : - _theResult___fst_exp__h466779 ; - assign _theResult___fst_exp__h467305 = - (_theResult___fst_exp__h466708 == 8'd255) ? - _theResult___fst_exp__h466708 : - _theResult___fst_exp__h467302 ; - assign _theResult___fst_exp__h475345 = + _theResult___fst_exp__h466778 ; + assign _theResult___fst_exp__h467304 = + (_theResult___fst_exp__h466707 == 8'd255) ? + _theResult___fst_exp__h466707 : + _theResult___fst_exp__h467301 ; + assign _theResult___fst_exp__h475344 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ; - assign _theResult___fst_exp__h475384 = + assign _theResult___fst_exp__h475383 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h475390 = + assign _theResult___fst_exp__h475389 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753) ? 8'd0 : - _theResult___fst_exp__h475384 ; - assign _theResult___fst_exp__h475393 = + _theResult___fst_exp__h475383 ; + assign _theResult___fst_exp__h475392 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h475390 : - _theResult___fst_exp__h475345 ; - assign _theResult___fst_exp__h475941 = - (_theResult___fst_exp__h475393 == 8'd255) ? - _theResult___fst_exp__h475393 : - _theResult___fst_exp__h475938 ; - assign _theResult___fst_exp__h475950 = + _theResult___fst_exp__h475389 : + _theResult___fst_exp__h475344 ; + assign _theResult___fst_exp__h475940 = + (_theResult___fst_exp__h475392 == 8'd255) ? + _theResult___fst_exp__h475392 : + _theResult___fst_exp__h475937 ; + assign _theResult___fst_exp__h475949 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_exp__h458124 : - _theResult___fst_exp__h440815) : + _theResult___snd_fst_exp__h458123 : + _theResult___fst_exp__h440814) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_exp__h475944 : - _theResult___fst_exp__h440815) ; - assign _theResult___fst_exp__h475953 = + _theResult___snd_fst_exp__h475943 : + _theResult___fst_exp__h440814) ; + assign _theResult___fst_exp__h475952 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h475950 ; - assign _theResult___fst_exp__h490487 = + _theResult___fst_exp__h475949 ; + assign _theResult___fst_exp__h490486 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_exp__h505551 = + assign _theResult___fst_exp__h505550 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8689 } ; - assign _theResult___fst_exp__h505557 = + assign _theResult___fst_exp__h505556 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8662 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8691) ? 11'd0 : - _theResult___fst_exp__h505551 ; - assign _theResult___fst_exp__h505560 = + _theResult___fst_exp__h505550 ; + assign _theResult___fst_exp__h505559 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h505557 : + _theResult___fst_exp__h505556 : 11'd897 ; - assign _theResult___fst_exp__h506315 = + assign _theResult___fst_exp__h506314 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q136 : + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9125 ; - assign _theResult___fst_exp__h506318 = - (_theResult___fst_exp__h505560 == 11'd2047) ? - _theResult___fst_exp__h505560 : - _theResult___fst_exp__h506315 ; - assign _theResult___fst_exp__h515137 = - _theResult____h506901[56] ? + assign _theResult___fst_exp__h506317 = + (_theResult___fst_exp__h505559 == 11'd2047) ? + _theResult___fst_exp__h505559 : + _theResult___fst_exp__h506314 ; + assign _theResult___fst_exp__h515136 = + _theResult____h506900[56] ? 11'd2 : - _theResult___fst_exp__h515211 ; - assign _theResult___fst_exp__h515202 = + _theResult___fst_exp__h515210 ; + assign _theResult___fst_exp__h515201 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9001 } ; - assign _theResult___fst_exp__h515208 = - (!_theResult____h506901[56] && !_theResult____h506901[55] && - !_theResult____h506901[54] && - !_theResult____h506901[53] && - !_theResult____h506901[52] && - !_theResult____h506901[51] && - !_theResult____h506901[50] && - !_theResult____h506901[49] && - !_theResult____h506901[48] && - !_theResult____h506901[47] && - !_theResult____h506901[46] && - !_theResult____h506901[45] && - !_theResult____h506901[44] && - !_theResult____h506901[43] && - !_theResult____h506901[42] && - !_theResult____h506901[41] && - !_theResult____h506901[40] && - !_theResult____h506901[39] && - !_theResult____h506901[38] && - !_theResult____h506901[37] && - !_theResult____h506901[36] && - !_theResult____h506901[35] && - !_theResult____h506901[34] && - !_theResult____h506901[33] && - !_theResult____h506901[32] && - !_theResult____h506901[31] && - !_theResult____h506901[30] && - !_theResult____h506901[29] && - !_theResult____h506901[28] && - !_theResult____h506901[27] && - !_theResult____h506901[26] && - !_theResult____h506901[25] && - !_theResult____h506901[24] && - !_theResult____h506901[23] && - !_theResult____h506901[22] && - !_theResult____h506901[21] && - !_theResult____h506901[20] && - !_theResult____h506901[19] && - !_theResult____h506901[18] && - !_theResult____h506901[17] && - !_theResult____h506901[16] && - !_theResult____h506901[15] && - !_theResult____h506901[14] && - !_theResult____h506901[13] && - !_theResult____h506901[12] && - !_theResult____h506901[11] && - !_theResult____h506901[10] && - !_theResult____h506901[9] && - !_theResult____h506901[8] && - !_theResult____h506901[7] && - !_theResult____h506901[6] && - !_theResult____h506901[5] && - !_theResult____h506901[4] && - !_theResult____h506901[3] && - !_theResult____h506901[2] && - !_theResult____h506901[1] && - !_theResult____h506901[0] || + assign _theResult___fst_exp__h515207 = + (!_theResult____h506900[56] && !_theResult____h506900[55] && + !_theResult____h506900[54] && + !_theResult____h506900[53] && + !_theResult____h506900[52] && + !_theResult____h506900[51] && + !_theResult____h506900[50] && + !_theResult____h506900[49] && + !_theResult____h506900[48] && + !_theResult____h506900[47] && + !_theResult____h506900[46] && + !_theResult____h506900[45] && + !_theResult____h506900[44] && + !_theResult____h506900[43] && + !_theResult____h506900[42] && + !_theResult____h506900[41] && + !_theResult____h506900[40] && + !_theResult____h506900[39] && + !_theResult____h506900[38] && + !_theResult____h506900[37] && + !_theResult____h506900[36] && + !_theResult____h506900[35] && + !_theResult____h506900[34] && + !_theResult____h506900[33] && + !_theResult____h506900[32] && + !_theResult____h506900[31] && + !_theResult____h506900[30] && + !_theResult____h506900[29] && + !_theResult____h506900[28] && + !_theResult____h506900[27] && + !_theResult____h506900[26] && + !_theResult____h506900[25] && + !_theResult____h506900[24] && + !_theResult____h506900[23] && + !_theResult____h506900[22] && + !_theResult____h506900[21] && + !_theResult____h506900[20] && + !_theResult____h506900[19] && + !_theResult____h506900[18] && + !_theResult____h506900[17] && + !_theResult____h506900[16] && + !_theResult____h506900[15] && + !_theResult____h506900[14] && + !_theResult____h506900[13] && + !_theResult____h506900[12] && + !_theResult____h506900[11] && + !_theResult____h506900[10] && + !_theResult____h506900[9] && + !_theResult____h506900[8] && + !_theResult____h506900[7] && + !_theResult____h506900[6] && + !_theResult____h506900[5] && + !_theResult____h506900[4] && + !_theResult____h506900[3] && + !_theResult____h506900[2] && + !_theResult____h506900[1] && + !_theResult____h506900[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9003) ? 11'd0 : - _theResult___fst_exp__h515202 ; - assign _theResult___fst_exp__h515211 = - (!_theResult____h506901[56] && _theResult____h506901[55]) ? + _theResult___fst_exp__h515201 ; + assign _theResult___fst_exp__h515210 = + (!_theResult____h506900[56] && _theResult____h506900[55]) ? 11'd1 : - _theResult___fst_exp__h515208 ; - assign _theResult___fst_exp__h515966 = + _theResult___fst_exp__h515207 ; + assign _theResult___fst_exp__h515965 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q204 : + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9168 ; - assign _theResult___fst_exp__h515969 = - (_theResult___fst_exp__h515137 == 11'd2047) ? - _theResult___fst_exp__h515137 : - _theResult___fst_exp__h515966 ; - assign _theResult___fst_exp__h523922 = + assign _theResult___fst_exp__h515968 = + (_theResult___fst_exp__h515136 == 11'd2047) ? + _theResult___fst_exp__h515136 : + _theResult___fst_exp__h515965 ; + assign _theResult___fst_exp__h523921 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q129[10:0] ; - assign _theResult___fst_exp__h523961 = + assign _theResult___fst_exp__h523960 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q129[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8689 } ; - assign _theResult___fst_exp__h523967 = + assign _theResult___fst_exp__h523966 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8662 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9053) ? 11'd0 : - _theResult___fst_exp__h523961 ; - assign _theResult___fst_exp__h523970 = + _theResult___fst_exp__h523960 ; + assign _theResult___fst_exp__h523969 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h523967 : - _theResult___fst_exp__h523922 ; - assign _theResult___fst_exp__h524750 = + _theResult___fst_exp__h523966 : + _theResult___fst_exp__h523921 ; + assign _theResult___fst_exp__h524749 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 : + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 ; - assign _theResult___fst_exp__h524753 = - (_theResult___fst_exp__h523970 == 11'd2047) ? - _theResult___fst_exp__h523970 : - _theResult___fst_exp__h524750 ; - assign _theResult___fst_exp__h524762 = + assign _theResult___fst_exp__h524752 = + (_theResult___fst_exp__h523969 == 11'd2047) ? + _theResult___fst_exp__h523969 : + _theResult___fst_exp__h524749 ; + assign _theResult___fst_exp__h524761 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8616 ? - _theResult___snd_fst_exp__h506321 : - _theResult___fst_exp__h490487) : + _theResult___snd_fst_exp__h506320 : + _theResult___fst_exp__h490486) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d8753 ? - _theResult___snd_fst_exp__h524756 : - _theResult___fst_exp__h490487) ; - assign _theResult___fst_exp__h524765 = + _theResult___snd_fst_exp__h524755 : + _theResult___fst_exp__h490486) ; + assign _theResult___fst_exp__h524764 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h524762 ; - assign _theResult___fst_exp__h529288 = + _theResult___fst_exp__h524761 ; + assign _theResult___fst_exp__h529287 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_exp__h544352 = + assign _theResult___fst_exp__h544351 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10177 } ; - assign _theResult___fst_exp__h544358 = + assign _theResult___fst_exp__h544357 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d10150 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10179) ? 11'd0 : - _theResult___fst_exp__h544352 ; - assign _theResult___fst_exp__h544361 = + _theResult___fst_exp__h544351 ; + assign _theResult___fst_exp__h544360 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h544358 : + _theResult___fst_exp__h544357 : 11'd897 ; - assign _theResult___fst_exp__h545116 = + assign _theResult___fst_exp__h545115 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q176 : + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10598 ; - assign _theResult___fst_exp__h545119 = - (_theResult___fst_exp__h544361 == 11'd2047) ? - _theResult___fst_exp__h544361 : - _theResult___fst_exp__h545116 ; - assign _theResult___fst_exp__h553938 = - _theResult____h545702[56] ? + assign _theResult___fst_exp__h545118 = + (_theResult___fst_exp__h544360 == 11'd2047) ? + _theResult___fst_exp__h544360 : + _theResult___fst_exp__h545115 ; + assign _theResult___fst_exp__h553937 = + _theResult____h545701[56] ? 11'd2 : - _theResult___fst_exp__h554012 ; - assign _theResult___fst_exp__h554003 = + _theResult___fst_exp__h554011 ; + assign _theResult___fst_exp__h554002 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10474 } ; - assign _theResult___fst_exp__h554009 = - (!_theResult____h545702[56] && !_theResult____h545702[55] && - !_theResult____h545702[54] && - !_theResult____h545702[53] && - !_theResult____h545702[52] && - !_theResult____h545702[51] && - !_theResult____h545702[50] && - !_theResult____h545702[49] && - !_theResult____h545702[48] && - !_theResult____h545702[47] && - !_theResult____h545702[46] && - !_theResult____h545702[45] && - !_theResult____h545702[44] && - !_theResult____h545702[43] && - !_theResult____h545702[42] && - !_theResult____h545702[41] && - !_theResult____h545702[40] && - !_theResult____h545702[39] && - !_theResult____h545702[38] && - !_theResult____h545702[37] && - !_theResult____h545702[36] && - !_theResult____h545702[35] && - !_theResult____h545702[34] && - !_theResult____h545702[33] && - !_theResult____h545702[32] && - !_theResult____h545702[31] && - !_theResult____h545702[30] && - !_theResult____h545702[29] && - !_theResult____h545702[28] && - !_theResult____h545702[27] && - !_theResult____h545702[26] && - !_theResult____h545702[25] && - !_theResult____h545702[24] && - !_theResult____h545702[23] && - !_theResult____h545702[22] && - !_theResult____h545702[21] && - !_theResult____h545702[20] && - !_theResult____h545702[19] && - !_theResult____h545702[18] && - !_theResult____h545702[17] && - !_theResult____h545702[16] && - !_theResult____h545702[15] && - !_theResult____h545702[14] && - !_theResult____h545702[13] && - !_theResult____h545702[12] && - !_theResult____h545702[11] && - !_theResult____h545702[10] && - !_theResult____h545702[9] && - !_theResult____h545702[8] && - !_theResult____h545702[7] && - !_theResult____h545702[6] && - !_theResult____h545702[5] && - !_theResult____h545702[4] && - !_theResult____h545702[3] && - !_theResult____h545702[2] && - !_theResult____h545702[1] && - !_theResult____h545702[0] || + assign _theResult___fst_exp__h554008 = + (!_theResult____h545701[56] && !_theResult____h545701[55] && + !_theResult____h545701[54] && + !_theResult____h545701[53] && + !_theResult____h545701[52] && + !_theResult____h545701[51] && + !_theResult____h545701[50] && + !_theResult____h545701[49] && + !_theResult____h545701[48] && + !_theResult____h545701[47] && + !_theResult____h545701[46] && + !_theResult____h545701[45] && + !_theResult____h545701[44] && + !_theResult____h545701[43] && + !_theResult____h545701[42] && + !_theResult____h545701[41] && + !_theResult____h545701[40] && + !_theResult____h545701[39] && + !_theResult____h545701[38] && + !_theResult____h545701[37] && + !_theResult____h545701[36] && + !_theResult____h545701[35] && + !_theResult____h545701[34] && + !_theResult____h545701[33] && + !_theResult____h545701[32] && + !_theResult____h545701[31] && + !_theResult____h545701[30] && + !_theResult____h545701[29] && + !_theResult____h545701[28] && + !_theResult____h545701[27] && + !_theResult____h545701[26] && + !_theResult____h545701[25] && + !_theResult____h545701[24] && + !_theResult____h545701[23] && + !_theResult____h545701[22] && + !_theResult____h545701[21] && + !_theResult____h545701[20] && + !_theResult____h545701[19] && + !_theResult____h545701[18] && + !_theResult____h545701[17] && + !_theResult____h545701[16] && + !_theResult____h545701[15] && + !_theResult____h545701[14] && + !_theResult____h545701[13] && + !_theResult____h545701[12] && + !_theResult____h545701[11] && + !_theResult____h545701[10] && + !_theResult____h545701[9] && + !_theResult____h545701[8] && + !_theResult____h545701[7] && + !_theResult____h545701[6] && + !_theResult____h545701[5] && + !_theResult____h545701[4] && + !_theResult____h545701[3] && + !_theResult____h545701[2] && + !_theResult____h545701[1] && + !_theResult____h545701[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10476) ? 11'd0 : - _theResult___fst_exp__h554003 ; - assign _theResult___fst_exp__h554012 = - (!_theResult____h545702[56] && _theResult____h545702[55]) ? + _theResult___fst_exp__h554002 ; + assign _theResult___fst_exp__h554011 = + (!_theResult____h545701[56] && _theResult____h545701[55]) ? 11'd1 : - _theResult___fst_exp__h554009 ; - assign _theResult___fst_exp__h554767 = + _theResult___fst_exp__h554008 ; + assign _theResult___fst_exp__h554766 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q178 : + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10636 ; - assign _theResult___fst_exp__h554770 = - (_theResult___fst_exp__h553938 == 11'd2047) ? - _theResult___fst_exp__h553938 : - _theResult___fst_exp__h554767 ; - assign _theResult___fst_exp__h562723 = + assign _theResult___fst_exp__h554769 = + (_theResult___fst_exp__h553937 == 11'd2047) ? + _theResult___fst_exp__h553937 : + _theResult___fst_exp__h554766 ; + assign _theResult___fst_exp__h562722 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q169[10:0] ; - assign _theResult___fst_exp__h562762 = + assign _theResult___fst_exp__h562761 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q169[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10177 } ; - assign _theResult___fst_exp__h562768 = + assign _theResult___fst_exp__h562767 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d10150 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10526) ? 11'd0 : - _theResult___fst_exp__h562762 ; - assign _theResult___fst_exp__h562771 = + _theResult___fst_exp__h562761 ; + assign _theResult___fst_exp__h562770 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h562768 : - _theResult___fst_exp__h562723 ; - assign _theResult___fst_exp__h563551 = + _theResult___fst_exp__h562767 : + _theResult___fst_exp__h562722 ; + assign _theResult___fst_exp__h563550 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q180 : + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10667 ; - assign _theResult___fst_exp__h563554 = - (_theResult___fst_exp__h562771 == 11'd2047) ? - _theResult___fst_exp__h562771 : - _theResult___fst_exp__h563551 ; - assign _theResult___fst_exp__h563563 = + assign _theResult___fst_exp__h563553 = + (_theResult___fst_exp__h562770 == 11'd2047) ? + _theResult___fst_exp__h562770 : + _theResult___fst_exp__h563550 ; + assign _theResult___fst_exp__h563562 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10104 ? - _theResult___snd_fst_exp__h545122 : - _theResult___fst_exp__h529288) : + _theResult___snd_fst_exp__h545121 : + _theResult___fst_exp__h529287) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d10226 ? - _theResult___snd_fst_exp__h563557 : - _theResult___fst_exp__h529288) ; - assign _theResult___fst_exp__h563566 = + _theResult___snd_fst_exp__h563556 : + _theResult___fst_exp__h529287) ; + assign _theResult___fst_exp__h563565 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h563563 ; - assign _theResult___fst_exp__h568489 = + _theResult___fst_exp__h563562 ; + assign _theResult___fst_exp__h568488 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_exp__h583553 = + assign _theResult___fst_exp__h583552 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9414 } ; - assign _theResult___fst_exp__h583559 = + assign _theResult___fst_exp__h583558 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d9387 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9416) ? 11'd0 : - _theResult___fst_exp__h583553 ; - assign _theResult___fst_exp__h583562 = + _theResult___fst_exp__h583552 ; + assign _theResult___fst_exp__h583561 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h583559 : + _theResult___fst_exp__h583558 : 11'd897 ; - assign _theResult___fst_exp__h584317 = + assign _theResult___fst_exp__h584316 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q153 : + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9835 ; - assign _theResult___fst_exp__h584320 = - (_theResult___fst_exp__h583562 == 11'd2047) ? - _theResult___fst_exp__h583562 : - _theResult___fst_exp__h584317 ; - assign _theResult___fst_exp__h593139 = - _theResult____h584903[56] ? + assign _theResult___fst_exp__h584319 = + (_theResult___fst_exp__h583561 == 11'd2047) ? + _theResult___fst_exp__h583561 : + _theResult___fst_exp__h584316 ; + assign _theResult___fst_exp__h593138 = + _theResult____h584902[56] ? 11'd2 : - _theResult___fst_exp__h593213 ; - assign _theResult___fst_exp__h593204 = + _theResult___fst_exp__h593212 ; + assign _theResult___fst_exp__h593203 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9711 } ; - assign _theResult___fst_exp__h593210 = - (!_theResult____h584903[56] && !_theResult____h584903[55] && - !_theResult____h584903[54] && - !_theResult____h584903[53] && - !_theResult____h584903[52] && - !_theResult____h584903[51] && - !_theResult____h584903[50] && - !_theResult____h584903[49] && - !_theResult____h584903[48] && - !_theResult____h584903[47] && - !_theResult____h584903[46] && - !_theResult____h584903[45] && - !_theResult____h584903[44] && - !_theResult____h584903[43] && - !_theResult____h584903[42] && - !_theResult____h584903[41] && - !_theResult____h584903[40] && - !_theResult____h584903[39] && - !_theResult____h584903[38] && - !_theResult____h584903[37] && - !_theResult____h584903[36] && - !_theResult____h584903[35] && - !_theResult____h584903[34] && - !_theResult____h584903[33] && - !_theResult____h584903[32] && - !_theResult____h584903[31] && - !_theResult____h584903[30] && - !_theResult____h584903[29] && - !_theResult____h584903[28] && - !_theResult____h584903[27] && - !_theResult____h584903[26] && - !_theResult____h584903[25] && - !_theResult____h584903[24] && - !_theResult____h584903[23] && - !_theResult____h584903[22] && - !_theResult____h584903[21] && - !_theResult____h584903[20] && - !_theResult____h584903[19] && - !_theResult____h584903[18] && - !_theResult____h584903[17] && - !_theResult____h584903[16] && - !_theResult____h584903[15] && - !_theResult____h584903[14] && - !_theResult____h584903[13] && - !_theResult____h584903[12] && - !_theResult____h584903[11] && - !_theResult____h584903[10] && - !_theResult____h584903[9] && - !_theResult____h584903[8] && - !_theResult____h584903[7] && - !_theResult____h584903[6] && - !_theResult____h584903[5] && - !_theResult____h584903[4] && - !_theResult____h584903[3] && - !_theResult____h584903[2] && - !_theResult____h584903[1] && - !_theResult____h584903[0] || + assign _theResult___fst_exp__h593209 = + (!_theResult____h584902[56] && !_theResult____h584902[55] && + !_theResult____h584902[54] && + !_theResult____h584902[53] && + !_theResult____h584902[52] && + !_theResult____h584902[51] && + !_theResult____h584902[50] && + !_theResult____h584902[49] && + !_theResult____h584902[48] && + !_theResult____h584902[47] && + !_theResult____h584902[46] && + !_theResult____h584902[45] && + !_theResult____h584902[44] && + !_theResult____h584902[43] && + !_theResult____h584902[42] && + !_theResult____h584902[41] && + !_theResult____h584902[40] && + !_theResult____h584902[39] && + !_theResult____h584902[38] && + !_theResult____h584902[37] && + !_theResult____h584902[36] && + !_theResult____h584902[35] && + !_theResult____h584902[34] && + !_theResult____h584902[33] && + !_theResult____h584902[32] && + !_theResult____h584902[31] && + !_theResult____h584902[30] && + !_theResult____h584902[29] && + !_theResult____h584902[28] && + !_theResult____h584902[27] && + !_theResult____h584902[26] && + !_theResult____h584902[25] && + !_theResult____h584902[24] && + !_theResult____h584902[23] && + !_theResult____h584902[22] && + !_theResult____h584902[21] && + !_theResult____h584902[20] && + !_theResult____h584902[19] && + !_theResult____h584902[18] && + !_theResult____h584902[17] && + !_theResult____h584902[16] && + !_theResult____h584902[15] && + !_theResult____h584902[14] && + !_theResult____h584902[13] && + !_theResult____h584902[12] && + !_theResult____h584902[11] && + !_theResult____h584902[10] && + !_theResult____h584902[9] && + !_theResult____h584902[8] && + !_theResult____h584902[7] && + !_theResult____h584902[6] && + !_theResult____h584902[5] && + !_theResult____h584902[4] && + !_theResult____h584902[3] && + !_theResult____h584902[2] && + !_theResult____h584902[1] && + !_theResult____h584902[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9713) ? 11'd0 : - _theResult___fst_exp__h593204 ; - assign _theResult___fst_exp__h593213 = - (!_theResult____h584903[56] && _theResult____h584903[55]) ? + _theResult___fst_exp__h593203 ; + assign _theResult___fst_exp__h593212 = + (!_theResult____h584902[56] && _theResult____h584902[55]) ? 11'd1 : - _theResult___fst_exp__h593210 ; - assign _theResult___fst_exp__h593968 = + _theResult___fst_exp__h593209 ; + assign _theResult___fst_exp__h593967 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 : + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 ; - assign _theResult___fst_exp__h593971 = - (_theResult___fst_exp__h593139 == 11'd2047) ? - _theResult___fst_exp__h593139 : - _theResult___fst_exp__h593968 ; - assign _theResult___fst_exp__h601924 = + assign _theResult___fst_exp__h593970 = + (_theResult___fst_exp__h593138 == 11'd2047) ? + _theResult___fst_exp__h593138 : + _theResult___fst_exp__h593967 ; + assign _theResult___fst_exp__h601923 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q146[10:0] ; - assign _theResult___fst_exp__h601963 = + assign _theResult___fst_exp__h601962 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC__q146[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9414 } ; - assign _theResult___fst_exp__h601969 = + assign _theResult___fst_exp__h601968 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d9387 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9763) ? 11'd0 : - _theResult___fst_exp__h601963 ; - assign _theResult___fst_exp__h601972 = + _theResult___fst_exp__h601962 ; + assign _theResult___fst_exp__h601971 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h601969 : - _theResult___fst_exp__h601924 ; - assign _theResult___fst_exp__h602752 = + _theResult___fst_exp__h601968 : + _theResult___fst_exp__h601923 ; + assign _theResult___fst_exp__h602751 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 : + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 ; - assign _theResult___fst_exp__h602755 = - (_theResult___fst_exp__h601972 == 11'd2047) ? - _theResult___fst_exp__h601972 : - _theResult___fst_exp__h602752 ; - assign _theResult___fst_exp__h602764 = + assign _theResult___fst_exp__h602754 = + (_theResult___fst_exp__h601971 == 11'd2047) ? + _theResult___fst_exp__h601971 : + _theResult___fst_exp__h602751 ; + assign _theResult___fst_exp__h602763 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9341 ? - _theResult___snd_fst_exp__h584323 : - _theResult___fst_exp__h568489) : + _theResult___snd_fst_exp__h584322 : + _theResult___fst_exp__h568488) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9463 ? - _theResult___snd_fst_exp__h602758 : - _theResult___fst_exp__h568489) ; - assign _theResult___fst_exp__h602767 = + _theResult___snd_fst_exp__h602757 : + _theResult___fst_exp__h568488) ; + assign _theResult___fst_exp__h602766 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h602764 ; - assign _theResult___fst_sfd__h358162 = - (_theResult___fst_exp__h357564 == 8'd255) ? - sfdin__h357558[56:34] : - _theResult___fst_sfd__h358159 ; - assign _theResult___fst_sfd__h366744 = - (_theResult___fst_exp__h366220 == 8'd255) ? - _theResult___snd__h366171[56:34] : - _theResult___fst_sfd__h366741 ; - assign _theResult___fst_sfd__h375928 = - (_theResult___fst_exp__h375330 == 8'd255) ? - sfdin__h375324[56:34] : - _theResult___fst_sfd__h375925 ; - assign _theResult___fst_sfd__h384564 = - (_theResult___fst_exp__h384015 == 8'd255) ? - _theResult___snd__h383961[56:34] : - _theResult___fst_sfd__h384561 ; - assign _theResult___fst_sfd__h384573 = + _theResult___fst_exp__h602763 ; + assign _theResult___fst_sfd__h358161 = + (_theResult___fst_exp__h357563 == 8'd255) ? + sfdin__h357557[56:34] : + _theResult___fst_sfd__h358158 ; + assign _theResult___fst_sfd__h366743 = + (_theResult___fst_exp__h366219 == 8'd255) ? + _theResult___snd__h366170[56:34] : + _theResult___fst_sfd__h366740 ; + assign _theResult___fst_sfd__h375927 = + (_theResult___fst_exp__h375329 == 8'd255) ? + sfdin__h375323[56:34] : + _theResult___fst_sfd__h375924 ; + assign _theResult___fst_sfd__h384563 = + (_theResult___fst_exp__h384014 == 8'd255) ? + _theResult___snd__h383960[56:34] : + _theResult___fst_sfd__h384560 ; + assign _theResult___fst_sfd__h384572 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_sfd__h366747 : - _theResult___fst_sfd__h349436) : + _theResult___snd_fst_sfd__h366746 : + _theResult___fst_sfd__h349435) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_sfd__h384567 : - _theResult___fst_sfd__h349436) ; - assign _theResult___fst_sfd__h384579 = + _theResult___snd_fst_sfd__h384566 : + _theResult___fst_sfd__h349435) ; + assign _theResult___fst_sfd__h384578 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -25886,33 +26000,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h384573 ; - assign _theResult___fst_sfd__h403852 = - (_theResult___fst_exp__h403254 == 8'd255) ? - sfdin__h403248[56:34] : - _theResult___fst_sfd__h403849 ; - assign _theResult___fst_sfd__h412434 = - (_theResult___fst_exp__h411910 == 8'd255) ? - _theResult___snd__h411861[56:34] : - _theResult___fst_sfd__h412431 ; - assign _theResult___fst_sfd__h421618 = - (_theResult___fst_exp__h421020 == 8'd255) ? - sfdin__h421014[56:34] : - _theResult___fst_sfd__h421615 ; - assign _theResult___fst_sfd__h430254 = - (_theResult___fst_exp__h429705 == 8'd255) ? - _theResult___snd__h429651[56:34] : - _theResult___fst_sfd__h430251 ; - assign _theResult___fst_sfd__h430263 = + _theResult___fst_sfd__h384572 ; + assign _theResult___fst_sfd__h403851 = + (_theResult___fst_exp__h403253 == 8'd255) ? + sfdin__h403247[56:34] : + _theResult___fst_sfd__h403848 ; + assign _theResult___fst_sfd__h412433 = + (_theResult___fst_exp__h411909 == 8'd255) ? + _theResult___snd__h411860[56:34] : + _theResult___fst_sfd__h412430 ; + assign _theResult___fst_sfd__h421617 = + (_theResult___fst_exp__h421019 == 8'd255) ? + sfdin__h421013[56:34] : + _theResult___fst_sfd__h421614 ; + assign _theResult___fst_sfd__h430253 = + (_theResult___fst_exp__h429704 == 8'd255) ? + _theResult___snd__h429650[56:34] : + _theResult___fst_sfd__h430250 ; + assign _theResult___fst_sfd__h430262 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_sfd__h412437 : - _theResult___fst_sfd__h395128) : + _theResult___snd_fst_sfd__h412436 : + _theResult___fst_sfd__h395127) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_sfd__h430257 : - _theResult___fst_sfd__h395128) ; - assign _theResult___fst_sfd__h430269 = + _theResult___snd_fst_sfd__h430256 : + _theResult___fst_sfd__h395127) ; + assign _theResult___fst_sfd__h430268 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -25920,33 +26034,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h430263 ; - assign _theResult___fst_sfd__h449540 = - (_theResult___fst_exp__h448942 == 8'd255) ? - sfdin__h448936[56:34] : - _theResult___fst_sfd__h449537 ; - assign _theResult___fst_sfd__h458122 = - (_theResult___fst_exp__h457598 == 8'd255) ? - _theResult___snd__h457549[56:34] : - _theResult___fst_sfd__h458119 ; - assign _theResult___fst_sfd__h467306 = - (_theResult___fst_exp__h466708 == 8'd255) ? - sfdin__h466702[56:34] : - _theResult___fst_sfd__h467303 ; - assign _theResult___fst_sfd__h475942 = - (_theResult___fst_exp__h475393 == 8'd255) ? - _theResult___snd__h475339[56:34] : - _theResult___fst_sfd__h475939 ; - assign _theResult___fst_sfd__h475951 = + _theResult___fst_sfd__h430262 ; + assign _theResult___fst_sfd__h449539 = + (_theResult___fst_exp__h448941 == 8'd255) ? + sfdin__h448935[56:34] : + _theResult___fst_sfd__h449536 ; + assign _theResult___fst_sfd__h458121 = + (_theResult___fst_exp__h457597 == 8'd255) ? + _theResult___snd__h457548[56:34] : + _theResult___fst_sfd__h458118 ; + assign _theResult___fst_sfd__h467305 = + (_theResult___fst_exp__h466707 == 8'd255) ? + sfdin__h466701[56:34] : + _theResult___fst_sfd__h467302 ; + assign _theResult___fst_sfd__h475941 = + (_theResult___fst_exp__h475392 == 8'd255) ? + _theResult___snd__h475338[56:34] : + _theResult___fst_sfd__h475938 ; + assign _theResult___fst_sfd__h475950 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_sfd__h458125 : - _theResult___fst_sfd__h440816) : + _theResult___snd_fst_sfd__h458124 : + _theResult___fst_sfd__h440815) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_sfd__h475945 : - _theResult___fst_sfd__h440816) ; - assign _theResult___fst_sfd__h475957 = + _theResult___snd_fst_sfd__h475944 : + _theResult___fst_sfd__h440815) ; + assign _theResult___fst_sfd__h475956 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -25954,1324 +26068,1344 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h475951 ; - assign _theResult___fst_sfd__h490488 = + _theResult___fst_sfd__h475950 ; + assign _theResult___fst_sfd__h490487 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_sfd__h506316 = + assign _theResult___fst_sfd__h506315 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 : + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 ; - assign _theResult___fst_sfd__h506319 = - (_theResult___fst_exp__h505560 == 11'd2047) ? - _theResult___snd__h505511[56:5] : - _theResult___fst_sfd__h506316 ; - assign _theResult___fst_sfd__h515967 = + assign _theResult___fst_sfd__h506318 = + (_theResult___fst_exp__h505559 == 11'd2047) ? + _theResult___snd__h505510[56:5] : + _theResult___fst_sfd__h506315 ; + assign _theResult___fst_sfd__h515966 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q210 : + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9252 ; - assign _theResult___fst_sfd__h515970 = - (_theResult___fst_exp__h515137 == 11'd2047) ? - sfdin__h515131[56:5] : - _theResult___fst_sfd__h515967 ; - assign _theResult___fst_sfd__h524751 = + assign _theResult___fst_sfd__h515969 = + (_theResult___fst_exp__h515136 == 11'd2047) ? + sfdin__h515130[56:5] : + _theResult___fst_sfd__h515966 ; + assign _theResult___fst_sfd__h524750 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q212 : + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9271 ; - assign _theResult___fst_sfd__h524754 = - (_theResult___fst_exp__h523970 == 11'd2047) ? - _theResult___snd__h523916[56:5] : - _theResult___fst_sfd__h524751 ; - assign _theResult___fst_sfd__h524763 = + assign _theResult___fst_sfd__h524753 = + (_theResult___fst_exp__h523969 == 11'd2047) ? + _theResult___snd__h523915[56:5] : + _theResult___fst_sfd__h524750 ; + assign _theResult___fst_sfd__h524762 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8616 ? - _theResult___snd_fst_sfd__h506322 : - _theResult___fst_sfd__h490488) : + _theResult___snd_fst_sfd__h506321 : + _theResult___fst_sfd__h490487) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d8753 ? - _theResult___snd_fst_sfd__h524757 : - _theResult___fst_sfd__h490488) ; - assign _theResult___fst_sfd__h524769 = + _theResult___snd_fst_sfd__h524756 : + _theResult___fst_sfd__h490487) ; + assign _theResult___fst_sfd__h524768 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h524763 ; - assign _theResult___fst_sfd__h529289 = + _theResult___fst_sfd__h524762 ; + assign _theResult___fst_sfd__h529288 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_sfd__h545117 = + assign _theResult___fst_sfd__h545116 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q198 : + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10693 ; - assign _theResult___fst_sfd__h545120 = - (_theResult___fst_exp__h544361 == 11'd2047) ? - _theResult___snd__h544312[56:5] : - _theResult___fst_sfd__h545117 ; - assign _theResult___fst_sfd__h554768 = + assign _theResult___fst_sfd__h545119 = + (_theResult___fst_exp__h544360 == 11'd2047) ? + _theResult___snd__h544311[56:5] : + _theResult___fst_sfd__h545116 ; + assign _theResult___fst_sfd__h554767 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 ; - assign _theResult___fst_sfd__h554771 = - (_theResult___fst_exp__h553938 == 11'd2047) ? - sfdin__h553932[56:5] : - _theResult___fst_sfd__h554768 ; - assign _theResult___fst_sfd__h563552 = + assign _theResult___fst_sfd__h554770 = + (_theResult___fst_exp__h553937 == 11'd2047) ? + sfdin__h553931[56:5] : + _theResult___fst_sfd__h554767 ; + assign _theResult___fst_sfd__h563551 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q202 : + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10738 ; - assign _theResult___fst_sfd__h563555 = - (_theResult___fst_exp__h562771 == 11'd2047) ? - _theResult___snd__h562717[56:5] : - _theResult___fst_sfd__h563552 ; - assign _theResult___fst_sfd__h563564 = + assign _theResult___fst_sfd__h563554 = + (_theResult___fst_exp__h562770 == 11'd2047) ? + _theResult___snd__h562716[56:5] : + _theResult___fst_sfd__h563551 ; + assign _theResult___fst_sfd__h563563 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10104 ? - _theResult___snd_fst_sfd__h545123 : - _theResult___fst_sfd__h529289) : + _theResult___snd_fst_sfd__h545122 : + _theResult___fst_sfd__h529288) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d10226 ? - _theResult___snd_fst_sfd__h563558 : - _theResult___fst_sfd__h529289) ; - assign _theResult___fst_sfd__h563570 = + _theResult___snd_fst_sfd__h563557 : + _theResult___fst_sfd__h529288) ; + assign _theResult___fst_sfd__h563569 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h563564 ; - assign _theResult___fst_sfd__h568490 = + _theResult___fst_sfd__h563563 ; + assign _theResult___fst_sfd__h568489 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 ; - assign _theResult___fst_sfd__h584318 = + assign _theResult___fst_sfd__h584317 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q214 : + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9930 ; - assign _theResult___fst_sfd__h584321 = - (_theResult___fst_exp__h583562 == 11'd2047) ? - _theResult___snd__h583513[56:5] : - _theResult___fst_sfd__h584318 ; - assign _theResult___fst_sfd__h593969 = + assign _theResult___fst_sfd__h584320 = + (_theResult___fst_exp__h583561 == 11'd2047) ? + _theResult___snd__h583512[56:5] : + _theResult___fst_sfd__h584317 ; + assign _theResult___fst_sfd__h593968 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9956 ; - assign _theResult___fst_sfd__h593972 = - (_theResult___fst_exp__h593139 == 11'd2047) ? - sfdin__h593133[56:5] : - _theResult___fst_sfd__h593969 ; - assign _theResult___fst_sfd__h602753 = + assign _theResult___fst_sfd__h593971 = + (_theResult___fst_exp__h593138 == 11'd2047) ? + sfdin__h593132[56:5] : + _theResult___fst_sfd__h593968 ; + assign _theResult___fst_sfd__h602752 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q218 : + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9975 ; - assign _theResult___fst_sfd__h602756 = - (_theResult___fst_exp__h601972 == 11'd2047) ? - _theResult___snd__h601918[56:5] : - _theResult___fst_sfd__h602753 ; - assign _theResult___fst_sfd__h602765 = + assign _theResult___fst_sfd__h602755 = + (_theResult___fst_exp__h601971 == 11'd2047) ? + _theResult___snd__h601917[56:5] : + _theResult___fst_sfd__h602752 ; + assign _theResult___fst_sfd__h602764 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9341 ? - _theResult___snd_fst_sfd__h584324 : - _theResult___fst_sfd__h568490) : + _theResult___snd_fst_sfd__h584323 : + _theResult___fst_sfd__h568489) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9463 ? - _theResult___snd_fst_sfd__h602759 : - _theResult___fst_sfd__h568490) ; - assign _theResult___fst_sfd__h602771 = + _theResult___snd_fst_sfd__h602758 : + _theResult___fst_sfd__h568489) ; + assign _theResult___fst_sfd__h602770 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h602765 ; - assign _theResult___sfd__h358081 = - sfd__h357656[24] ? - ((_theResult___fst_exp__h357564 == 8'd254) ? + _theResult___fst_sfd__h602764 ; + assign _theResult___sfd__h358080 = + sfd__h357655[24] ? + ((_theResult___fst_exp__h357563 == 8'd254) ? 23'd0 : - sfd__h357656[23:1]) : - sfd__h357656[22:0] ; - assign _theResult___sfd__h366663 = - sfd__h366238[24] ? - ((_theResult___fst_exp__h366220 == 8'd254) ? + sfd__h357655[23:1]) : + sfd__h357655[22:0] ; + assign _theResult___sfd__h366662 = + sfd__h366237[24] ? + ((_theResult___fst_exp__h366219 == 8'd254) ? 23'd0 : - sfd__h366238[23:1]) : - sfd__h366238[22:0] ; - assign _theResult___sfd__h375847 = - sfd__h375422[24] ? - ((_theResult___fst_exp__h375330 == 8'd254) ? + sfd__h366237[23:1]) : + sfd__h366237[22:0] ; + assign _theResult___sfd__h375846 = + sfd__h375421[24] ? + ((_theResult___fst_exp__h375329 == 8'd254) ? 23'd0 : - sfd__h375422[23:1]) : - sfd__h375422[22:0] ; - assign _theResult___sfd__h384483 = - sfd__h384034[24] ? - ((_theResult___fst_exp__h384015 == 8'd254) ? + sfd__h375421[23:1]) : + sfd__h375421[22:0] ; + assign _theResult___sfd__h384482 = + sfd__h384033[24] ? + ((_theResult___fst_exp__h384014 == 8'd254) ? 23'd0 : - sfd__h384034[23:1]) : - sfd__h384034[22:0] ; - assign _theResult___sfd__h384585 = + sfd__h384033[23:1]) : + sfd__h384033[22:0] ; + assign _theResult___sfd__h384584 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h341798 : - _theResult___fst_sfd__h384579 ; - assign _theResult___sfd__h403771 = - sfd__h403346[24] ? - ((_theResult___fst_exp__h403254 == 8'd254) ? + _theResult___snd_fst_sfd__h341797 : + _theResult___fst_sfd__h384578 ; + assign _theResult___sfd__h403770 = + sfd__h403345[24] ? + ((_theResult___fst_exp__h403253 == 8'd254) ? 23'd0 : - sfd__h403346[23:1]) : - sfd__h403346[22:0] ; - assign _theResult___sfd__h412353 = - sfd__h411928[24] ? - ((_theResult___fst_exp__h411910 == 8'd254) ? + sfd__h403345[23:1]) : + sfd__h403345[22:0] ; + assign _theResult___sfd__h412352 = + sfd__h411927[24] ? + ((_theResult___fst_exp__h411909 == 8'd254) ? 23'd0 : - sfd__h411928[23:1]) : - sfd__h411928[22:0] ; - assign _theResult___sfd__h421537 = - sfd__h421112[24] ? - ((_theResult___fst_exp__h421020 == 8'd254) ? + sfd__h411927[23:1]) : + sfd__h411927[22:0] ; + assign _theResult___sfd__h421536 = + sfd__h421111[24] ? + ((_theResult___fst_exp__h421019 == 8'd254) ? 23'd0 : - sfd__h421112[23:1]) : - sfd__h421112[22:0] ; - assign _theResult___sfd__h430173 = - sfd__h429724[24] ? - ((_theResult___fst_exp__h429705 == 8'd254) ? + sfd__h421111[23:1]) : + sfd__h421111[22:0] ; + assign _theResult___sfd__h430172 = + sfd__h429723[24] ? + ((_theResult___fst_exp__h429704 == 8'd254) ? 23'd0 : - sfd__h429724[23:1]) : - sfd__h429724[22:0] ; - assign _theResult___sfd__h430275 = + sfd__h429723[23:1]) : + sfd__h429723[22:0] ; + assign _theResult___sfd__h430274 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h387493 : - _theResult___fst_sfd__h430269 ; - assign _theResult___sfd__h449459 = - sfd__h449034[24] ? - ((_theResult___fst_exp__h448942 == 8'd254) ? + _theResult___snd_fst_sfd__h387492 : + _theResult___fst_sfd__h430268 ; + assign _theResult___sfd__h449458 = + sfd__h449033[24] ? + ((_theResult___fst_exp__h448941 == 8'd254) ? 23'd0 : - sfd__h449034[23:1]) : - sfd__h449034[22:0] ; - assign _theResult___sfd__h458041 = - sfd__h457616[24] ? - ((_theResult___fst_exp__h457598 == 8'd254) ? + sfd__h449033[23:1]) : + sfd__h449033[22:0] ; + assign _theResult___sfd__h458040 = + sfd__h457615[24] ? + ((_theResult___fst_exp__h457597 == 8'd254) ? 23'd0 : - sfd__h457616[23:1]) : - sfd__h457616[22:0] ; - assign _theResult___sfd__h467225 = - sfd__h466800[24] ? - ((_theResult___fst_exp__h466708 == 8'd254) ? + sfd__h457615[23:1]) : + sfd__h457615[22:0] ; + assign _theResult___sfd__h467224 = + sfd__h466799[24] ? + ((_theResult___fst_exp__h466707 == 8'd254) ? 23'd0 : - sfd__h466800[23:1]) : - sfd__h466800[22:0] ; - assign _theResult___sfd__h475861 = - sfd__h475412[24] ? - ((_theResult___fst_exp__h475393 == 8'd254) ? + sfd__h466799[23:1]) : + sfd__h466799[22:0] ; + assign _theResult___sfd__h475860 = + sfd__h475411[24] ? + ((_theResult___fst_exp__h475392 == 8'd254) ? 23'd0 : - sfd__h475412[23:1]) : - sfd__h475412[22:0] ; - assign _theResult___sfd__h475963 = + sfd__h475411[23:1]) : + sfd__h475411[22:0] ; + assign _theResult___sfd__h475962 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h433181 : - _theResult___fst_sfd__h475957 ; - assign _theResult___sfd__h506216 = - sfd__h505578[53] ? - ((_theResult___fst_exp__h505560 == 11'd2046) ? + _theResult___snd_fst_sfd__h433180 : + _theResult___fst_sfd__h475956 ; + assign _theResult___sfd__h506215 = + sfd__h505577[53] ? + ((_theResult___fst_exp__h505559 == 11'd2046) ? 52'd0 : - sfd__h505578[52:1]) : - sfd__h505578[51:0] ; - assign _theResult___sfd__h515867 = - sfd__h515229[53] ? - ((_theResult___fst_exp__h515137 == 11'd2046) ? + sfd__h505577[52:1]) : + sfd__h505577[51:0] ; + assign _theResult___sfd__h515866 = + sfd__h515228[53] ? + ((_theResult___fst_exp__h515136 == 11'd2046) ? 52'd0 : - sfd__h515229[52:1]) : - sfd__h515229[51:0] ; - assign _theResult___sfd__h524651 = - sfd__h523989[53] ? - ((_theResult___fst_exp__h523970 == 11'd2046) ? + sfd__h515228[52:1]) : + sfd__h515228[51:0] ; + assign _theResult___sfd__h524650 = + sfd__h523988[53] ? + ((_theResult___fst_exp__h523969 == 11'd2046) ? 52'd0 : - sfd__h523989[52:1]) : - sfd__h523989[51:0] ; - assign _theResult___sfd__h545017 = - sfd__h544379[53] ? - ((_theResult___fst_exp__h544361 == 11'd2046) ? + sfd__h523988[52:1]) : + sfd__h523988[51:0] ; + assign _theResult___sfd__h545016 = + sfd__h544378[53] ? + ((_theResult___fst_exp__h544360 == 11'd2046) ? 52'd0 : - sfd__h544379[52:1]) : - sfd__h544379[51:0] ; - assign _theResult___sfd__h554668 = - sfd__h554030[53] ? - ((_theResult___fst_exp__h553938 == 11'd2046) ? + sfd__h544378[52:1]) : + sfd__h544378[51:0] ; + assign _theResult___sfd__h554667 = + sfd__h554029[53] ? + ((_theResult___fst_exp__h553937 == 11'd2046) ? 52'd0 : - sfd__h554030[52:1]) : - sfd__h554030[51:0] ; - assign _theResult___sfd__h563452 = - sfd__h562790[53] ? - ((_theResult___fst_exp__h562771 == 11'd2046) ? + sfd__h554029[52:1]) : + sfd__h554029[51:0] ; + assign _theResult___sfd__h563451 = + sfd__h562789[53] ? + ((_theResult___fst_exp__h562770 == 11'd2046) ? 52'd0 : - sfd__h562790[52:1]) : - sfd__h562790[51:0] ; - assign _theResult___sfd__h584218 = - sfd__h583580[53] ? - ((_theResult___fst_exp__h583562 == 11'd2046) ? + sfd__h562789[52:1]) : + sfd__h562789[51:0] ; + assign _theResult___sfd__h584217 = + sfd__h583579[53] ? + ((_theResult___fst_exp__h583561 == 11'd2046) ? 52'd0 : - sfd__h583580[52:1]) : - sfd__h583580[51:0] ; - assign _theResult___sfd__h593869 = - sfd__h593231[53] ? - ((_theResult___fst_exp__h593139 == 11'd2046) ? + sfd__h583579[52:1]) : + sfd__h583579[51:0] ; + assign _theResult___sfd__h593868 = + sfd__h593230[53] ? + ((_theResult___fst_exp__h593138 == 11'd2046) ? 52'd0 : - sfd__h593231[52:1]) : - sfd__h593231[51:0] ; - assign _theResult___sfd__h602653 = - sfd__h601991[53] ? - ((_theResult___fst_exp__h601972 == 11'd2046) ? + sfd__h593230[52:1]) : + sfd__h593230[51:0] ; + assign _theResult___sfd__h602652 = + sfd__h601990[53] ? + ((_theResult___fst_exp__h601971 == 11'd2046) ? 52'd0 : - sfd__h601991[52:1]) : - sfd__h601991[51:0] ; - assign _theResult___snd__h357575 = { _theResult____h349453[55:0], 1'd0 } ; - assign _theResult___snd__h357586 = - (!_theResult____h349453[56] && _theResult____h349453[55]) ? - _theResult___snd__h357588 : - _theResult___snd__h357598 ; - assign _theResult___snd__h357588 = { _theResult____h349453[54:0], 2'd0 } ; - assign _theResult___snd__h357598 = - (!_theResult____h349453[56] && !_theResult____h349453[55] && - !_theResult____h349453[54] && - !_theResult____h349453[53] && - !_theResult____h349453[52] && - !_theResult____h349453[51] && - !_theResult____h349453[50] && - !_theResult____h349453[49] && - !_theResult____h349453[48] && - !_theResult____h349453[47] && - !_theResult____h349453[46] && - !_theResult____h349453[45] && - !_theResult____h349453[44] && - !_theResult____h349453[43] && - !_theResult____h349453[42] && - !_theResult____h349453[41] && - !_theResult____h349453[40] && - !_theResult____h349453[39] && - !_theResult____h349453[38] && - !_theResult____h349453[37] && - !_theResult____h349453[36] && - !_theResult____h349453[35] && - !_theResult____h349453[34] && - !_theResult____h349453[33] && - !_theResult____h349453[32] && - !_theResult____h349453[31] && - !_theResult____h349453[30] && - !_theResult____h349453[29] && - !_theResult____h349453[28] && - !_theResult____h349453[27] && - !_theResult____h349453[26] && - !_theResult____h349453[25] && - !_theResult____h349453[24] && - !_theResult____h349453[23] && - !_theResult____h349453[22] && - !_theResult____h349453[21] && - !_theResult____h349453[20] && - !_theResult____h349453[19] && - !_theResult____h349453[18] && - !_theResult____h349453[17] && - !_theResult____h349453[16] && - !_theResult____h349453[15] && - !_theResult____h349453[14] && - !_theResult____h349453[13] && - !_theResult____h349453[12] && - !_theResult____h349453[11] && - !_theResult____h349453[10] && - !_theResult____h349453[9] && - !_theResult____h349453[8] && - !_theResult____h349453[7] && - !_theResult____h349453[6] && - !_theResult____h349453[5] && - !_theResult____h349453[4] && - !_theResult____h349453[3] && - !_theResult____h349453[2] && - !_theResult____h349453[1] && - !_theResult____h349453[0]) ? - _theResult____h349453 : - _theResult___snd__h357604 ; - assign _theResult___snd__h357604 = + sfd__h601990[52:1]) : + sfd__h601990[51:0] ; + assign _theResult___snd__h357574 = { _theResult____h349452[55:0], 1'd0 } ; + assign _theResult___snd__h357585 = + (!_theResult____h349452[56] && _theResult____h349452[55]) ? + _theResult___snd__h357587 : + _theResult___snd__h357597 ; + assign _theResult___snd__h357587 = { _theResult____h349452[54:0], 2'd0 } ; + assign _theResult___snd__h357597 = + (!_theResult____h349452[56] && !_theResult____h349452[55] && + !_theResult____h349452[54] && + !_theResult____h349452[53] && + !_theResult____h349452[52] && + !_theResult____h349452[51] && + !_theResult____h349452[50] && + !_theResult____h349452[49] && + !_theResult____h349452[48] && + !_theResult____h349452[47] && + !_theResult____h349452[46] && + !_theResult____h349452[45] && + !_theResult____h349452[44] && + !_theResult____h349452[43] && + !_theResult____h349452[42] && + !_theResult____h349452[41] && + !_theResult____h349452[40] && + !_theResult____h349452[39] && + !_theResult____h349452[38] && + !_theResult____h349452[37] && + !_theResult____h349452[36] && + !_theResult____h349452[35] && + !_theResult____h349452[34] && + !_theResult____h349452[33] && + !_theResult____h349452[32] && + !_theResult____h349452[31] && + !_theResult____h349452[30] && + !_theResult____h349452[29] && + !_theResult____h349452[28] && + !_theResult____h349452[27] && + !_theResult____h349452[26] && + !_theResult____h349452[25] && + !_theResult____h349452[24] && + !_theResult____h349452[23] && + !_theResult____h349452[22] && + !_theResult____h349452[21] && + !_theResult____h349452[20] && + !_theResult____h349452[19] && + !_theResult____h349452[18] && + !_theResult____h349452[17] && + !_theResult____h349452[16] && + !_theResult____h349452[15] && + !_theResult____h349452[14] && + !_theResult____h349452[13] && + !_theResult____h349452[12] && + !_theResult____h349452[11] && + !_theResult____h349452[10] && + !_theResult____h349452[9] && + !_theResult____h349452[8] && + !_theResult____h349452[7] && + !_theResult____h349452[6] && + !_theResult____h349452[5] && + !_theResult____h349452[4] && + !_theResult____h349452[3] && + !_theResult____h349452[2] && + !_theResult____h349452[1] && + !_theResult____h349452[0]) ? + _theResult____h349452 : + _theResult___snd__h357603 ; + assign _theResult___snd__h357603 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0], 2'd0 } ; - assign _theResult___snd__h357627 = - _theResult____h349453 << + assign _theResult___snd__h357626 = + _theResult____h349452 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 ; - assign _theResult___snd__h366171 = + assign _theResult___snd__h366170 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h366180 : - _theResult___snd__h366173 ; - assign _theResult___snd__h366173 = + _theResult___snd__h366179 : + _theResult___snd__h366172 ; + assign _theResult___snd__h366172 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h366180 = + assign _theResult___snd__h366179 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h341848 : - _theResult___snd__h366186 ; - assign _theResult___snd__h366186 = + sfd__h341847 : + _theResult___snd__h366185 ; + assign _theResult___snd__h366185 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0], 2'd0 } ; - assign _theResult___snd__h366209 = - sfd__h341848 << + assign _theResult___snd__h366208 = + sfd__h341847 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 ; - assign _theResult___snd__h375341 = { _theResult____h367092[55:0], 1'd0 } ; - assign _theResult___snd__h375352 = - (!_theResult____h367092[56] && _theResult____h367092[55]) ? - _theResult___snd__h375354 : - _theResult___snd__h375364 ; - assign _theResult___snd__h375354 = { _theResult____h367092[54:0], 2'd0 } ; - assign _theResult___snd__h375364 = - (!_theResult____h367092[56] && !_theResult____h367092[55] && - !_theResult____h367092[54] && - !_theResult____h367092[53] && - !_theResult____h367092[52] && - !_theResult____h367092[51] && - !_theResult____h367092[50] && - !_theResult____h367092[49] && - !_theResult____h367092[48] && - !_theResult____h367092[47] && - !_theResult____h367092[46] && - !_theResult____h367092[45] && - !_theResult____h367092[44] && - !_theResult____h367092[43] && - !_theResult____h367092[42] && - !_theResult____h367092[41] && - !_theResult____h367092[40] && - !_theResult____h367092[39] && - !_theResult____h367092[38] && - !_theResult____h367092[37] && - !_theResult____h367092[36] && - !_theResult____h367092[35] && - !_theResult____h367092[34] && - !_theResult____h367092[33] && - !_theResult____h367092[32] && - !_theResult____h367092[31] && - !_theResult____h367092[30] && - !_theResult____h367092[29] && - !_theResult____h367092[28] && - !_theResult____h367092[27] && - !_theResult____h367092[26] && - !_theResult____h367092[25] && - !_theResult____h367092[24] && - !_theResult____h367092[23] && - !_theResult____h367092[22] && - !_theResult____h367092[21] && - !_theResult____h367092[20] && - !_theResult____h367092[19] && - !_theResult____h367092[18] && - !_theResult____h367092[17] && - !_theResult____h367092[16] && - !_theResult____h367092[15] && - !_theResult____h367092[14] && - !_theResult____h367092[13] && - !_theResult____h367092[12] && - !_theResult____h367092[11] && - !_theResult____h367092[10] && - !_theResult____h367092[9] && - !_theResult____h367092[8] && - !_theResult____h367092[7] && - !_theResult____h367092[6] && - !_theResult____h367092[5] && - !_theResult____h367092[4] && - !_theResult____h367092[3] && - !_theResult____h367092[2] && - !_theResult____h367092[1] && - !_theResult____h367092[0]) ? - _theResult____h367092 : - _theResult___snd__h375370 ; - assign _theResult___snd__h375370 = + assign _theResult___snd__h375340 = { _theResult____h367091[55:0], 1'd0 } ; + assign _theResult___snd__h375351 = + (!_theResult____h367091[56] && _theResult____h367091[55]) ? + _theResult___snd__h375353 : + _theResult___snd__h375363 ; + assign _theResult___snd__h375353 = { _theResult____h367091[54:0], 2'd0 } ; + assign _theResult___snd__h375363 = + (!_theResult____h367091[56] && !_theResult____h367091[55] && + !_theResult____h367091[54] && + !_theResult____h367091[53] && + !_theResult____h367091[52] && + !_theResult____h367091[51] && + !_theResult____h367091[50] && + !_theResult____h367091[49] && + !_theResult____h367091[48] && + !_theResult____h367091[47] && + !_theResult____h367091[46] && + !_theResult____h367091[45] && + !_theResult____h367091[44] && + !_theResult____h367091[43] && + !_theResult____h367091[42] && + !_theResult____h367091[41] && + !_theResult____h367091[40] && + !_theResult____h367091[39] && + !_theResult____h367091[38] && + !_theResult____h367091[37] && + !_theResult____h367091[36] && + !_theResult____h367091[35] && + !_theResult____h367091[34] && + !_theResult____h367091[33] && + !_theResult____h367091[32] && + !_theResult____h367091[31] && + !_theResult____h367091[30] && + !_theResult____h367091[29] && + !_theResult____h367091[28] && + !_theResult____h367091[27] && + !_theResult____h367091[26] && + !_theResult____h367091[25] && + !_theResult____h367091[24] && + !_theResult____h367091[23] && + !_theResult____h367091[22] && + !_theResult____h367091[21] && + !_theResult____h367091[20] && + !_theResult____h367091[19] && + !_theResult____h367091[18] && + !_theResult____h367091[17] && + !_theResult____h367091[16] && + !_theResult____h367091[15] && + !_theResult____h367091[14] && + !_theResult____h367091[13] && + !_theResult____h367091[12] && + !_theResult____h367091[11] && + !_theResult____h367091[10] && + !_theResult____h367091[9] && + !_theResult____h367091[8] && + !_theResult____h367091[7] && + !_theResult____h367091[6] && + !_theResult____h367091[5] && + !_theResult____h367091[4] && + !_theResult____h367091[3] && + !_theResult____h367091[2] && + !_theResult____h367091[1] && + !_theResult____h367091[0]) ? + _theResult____h367091 : + _theResult___snd__h375369 ; + assign _theResult___snd__h375369 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31[54:0], 2'd0 } ; - assign _theResult___snd__h375393 = - _theResult____h367092 << + assign _theResult___snd__h375392 = + _theResult____h367091 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 ; - assign _theResult___snd__h383961 = + assign _theResult___snd__h383960 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h383975 : - _theResult___snd__h366173 ; - assign _theResult___snd__h383975 = + _theResult___snd__h383974 : + _theResult___snd__h366172 ; + assign _theResult___snd__h383974 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h341848 : - _theResult___snd__h383981 ; - assign _theResult___snd__h383981 = + sfd__h341847 : + _theResult___snd__h383980 ; + assign _theResult___snd__h383980 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36[54:0], 2'd0 } ; - assign _theResult___snd__h383999 = - sfd__h341848 << + assign _theResult___snd__h383998 = + sfd__h341847 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968) ; - assign _theResult___snd__h403265 = { _theResult____h395145[55:0], 1'd0 } ; - assign _theResult___snd__h403276 = - (!_theResult____h395145[56] && _theResult____h395145[55]) ? - _theResult___snd__h403278 : - _theResult___snd__h403288 ; - assign _theResult___snd__h403278 = { _theResult____h395145[54:0], 2'd0 } ; - assign _theResult___snd__h403288 = - (!_theResult____h395145[56] && !_theResult____h395145[55] && - !_theResult____h395145[54] && - !_theResult____h395145[53] && - !_theResult____h395145[52] && - !_theResult____h395145[51] && - !_theResult____h395145[50] && - !_theResult____h395145[49] && - !_theResult____h395145[48] && - !_theResult____h395145[47] && - !_theResult____h395145[46] && - !_theResult____h395145[45] && - !_theResult____h395145[44] && - !_theResult____h395145[43] && - !_theResult____h395145[42] && - !_theResult____h395145[41] && - !_theResult____h395145[40] && - !_theResult____h395145[39] && - !_theResult____h395145[38] && - !_theResult____h395145[37] && - !_theResult____h395145[36] && - !_theResult____h395145[35] && - !_theResult____h395145[34] && - !_theResult____h395145[33] && - !_theResult____h395145[32] && - !_theResult____h395145[31] && - !_theResult____h395145[30] && - !_theResult____h395145[29] && - !_theResult____h395145[28] && - !_theResult____h395145[27] && - !_theResult____h395145[26] && - !_theResult____h395145[25] && - !_theResult____h395145[24] && - !_theResult____h395145[23] && - !_theResult____h395145[22] && - !_theResult____h395145[21] && - !_theResult____h395145[20] && - !_theResult____h395145[19] && - !_theResult____h395145[18] && - !_theResult____h395145[17] && - !_theResult____h395145[16] && - !_theResult____h395145[15] && - !_theResult____h395145[14] && - !_theResult____h395145[13] && - !_theResult____h395145[12] && - !_theResult____h395145[11] && - !_theResult____h395145[10] && - !_theResult____h395145[9] && - !_theResult____h395145[8] && - !_theResult____h395145[7] && - !_theResult____h395145[6] && - !_theResult____h395145[5] && - !_theResult____h395145[4] && - !_theResult____h395145[3] && - !_theResult____h395145[2] && - !_theResult____h395145[1] && - !_theResult____h395145[0]) ? - _theResult____h395145 : - _theResult___snd__h403294 ; - assign _theResult___snd__h403294 = + assign _theResult___snd__h403264 = { _theResult____h395144[55:0], 1'd0 } ; + assign _theResult___snd__h403275 = + (!_theResult____h395144[56] && _theResult____h395144[55]) ? + _theResult___snd__h403277 : + _theResult___snd__h403287 ; + assign _theResult___snd__h403277 = { _theResult____h395144[54:0], 2'd0 } ; + assign _theResult___snd__h403287 = + (!_theResult____h395144[56] && !_theResult____h395144[55] && + !_theResult____h395144[54] && + !_theResult____h395144[53] && + !_theResult____h395144[52] && + !_theResult____h395144[51] && + !_theResult____h395144[50] && + !_theResult____h395144[49] && + !_theResult____h395144[48] && + !_theResult____h395144[47] && + !_theResult____h395144[46] && + !_theResult____h395144[45] && + !_theResult____h395144[44] && + !_theResult____h395144[43] && + !_theResult____h395144[42] && + !_theResult____h395144[41] && + !_theResult____h395144[40] && + !_theResult____h395144[39] && + !_theResult____h395144[38] && + !_theResult____h395144[37] && + !_theResult____h395144[36] && + !_theResult____h395144[35] && + !_theResult____h395144[34] && + !_theResult____h395144[33] && + !_theResult____h395144[32] && + !_theResult____h395144[31] && + !_theResult____h395144[30] && + !_theResult____h395144[29] && + !_theResult____h395144[28] && + !_theResult____h395144[27] && + !_theResult____h395144[26] && + !_theResult____h395144[25] && + !_theResult____h395144[24] && + !_theResult____h395144[23] && + !_theResult____h395144[22] && + !_theResult____h395144[21] && + !_theResult____h395144[20] && + !_theResult____h395144[19] && + !_theResult____h395144[18] && + !_theResult____h395144[17] && + !_theResult____h395144[16] && + !_theResult____h395144[15] && + !_theResult____h395144[14] && + !_theResult____h395144[13] && + !_theResult____h395144[12] && + !_theResult____h395144[11] && + !_theResult____h395144[10] && + !_theResult____h395144[9] && + !_theResult____h395144[8] && + !_theResult____h395144[7] && + !_theResult____h395144[6] && + !_theResult____h395144[5] && + !_theResult____h395144[4] && + !_theResult____h395144[3] && + !_theResult____h395144[2] && + !_theResult____h395144[1] && + !_theResult____h395144[0]) ? + _theResult____h395144 : + _theResult___snd__h403293 ; + assign _theResult___snd__h403293 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56[54:0], 2'd0 } ; - assign _theResult___snd__h403317 = - _theResult____h395145 << + assign _theResult___snd__h403316 = + _theResult____h395144 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 ; - assign _theResult___snd__h411861 = + assign _theResult___snd__h411860 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h411870 : - _theResult___snd__h411863 ; - assign _theResult___snd__h411863 = + _theResult___snd__h411869 : + _theResult___snd__h411862 ; + assign _theResult___snd__h411862 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h411870 = + assign _theResult___snd__h411869 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h387543 : - _theResult___snd__h411876 ; - assign _theResult___snd__h411876 = + sfd__h387542 : + _theResult___snd__h411875 ; + assign _theResult___snd__h411875 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58[54:0], 2'd0 } ; - assign _theResult___snd__h411899 = - sfd__h387543 << + assign _theResult___snd__h411898 = + sfd__h387542 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 ; - assign _theResult___snd__h421031 = { _theResult____h412782[55:0], 1'd0 } ; - assign _theResult___snd__h421042 = - (!_theResult____h412782[56] && _theResult____h412782[55]) ? - _theResult___snd__h421044 : - _theResult___snd__h421054 ; - assign _theResult___snd__h421044 = { _theResult____h412782[54:0], 2'd0 } ; - assign _theResult___snd__h421054 = - (!_theResult____h412782[56] && !_theResult____h412782[55] && - !_theResult____h412782[54] && - !_theResult____h412782[53] && - !_theResult____h412782[52] && - !_theResult____h412782[51] && - !_theResult____h412782[50] && - !_theResult____h412782[49] && - !_theResult____h412782[48] && - !_theResult____h412782[47] && - !_theResult____h412782[46] && - !_theResult____h412782[45] && - !_theResult____h412782[44] && - !_theResult____h412782[43] && - !_theResult____h412782[42] && - !_theResult____h412782[41] && - !_theResult____h412782[40] && - !_theResult____h412782[39] && - !_theResult____h412782[38] && - !_theResult____h412782[37] && - !_theResult____h412782[36] && - !_theResult____h412782[35] && - !_theResult____h412782[34] && - !_theResult____h412782[33] && - !_theResult____h412782[32] && - !_theResult____h412782[31] && - !_theResult____h412782[30] && - !_theResult____h412782[29] && - !_theResult____h412782[28] && - !_theResult____h412782[27] && - !_theResult____h412782[26] && - !_theResult____h412782[25] && - !_theResult____h412782[24] && - !_theResult____h412782[23] && - !_theResult____h412782[22] && - !_theResult____h412782[21] && - !_theResult____h412782[20] && - !_theResult____h412782[19] && - !_theResult____h412782[18] && - !_theResult____h412782[17] && - !_theResult____h412782[16] && - !_theResult____h412782[15] && - !_theResult____h412782[14] && - !_theResult____h412782[13] && - !_theResult____h412782[12] && - !_theResult____h412782[11] && - !_theResult____h412782[10] && - !_theResult____h412782[9] && - !_theResult____h412782[8] && - !_theResult____h412782[7] && - !_theResult____h412782[6] && - !_theResult____h412782[5] && - !_theResult____h412782[4] && - !_theResult____h412782[3] && - !_theResult____h412782[2] && - !_theResult____h412782[1] && - !_theResult____h412782[0]) ? - _theResult____h412782 : - _theResult___snd__h421060 ; - assign _theResult___snd__h421060 = + assign _theResult___snd__h421030 = { _theResult____h412781[55:0], 1'd0 } ; + assign _theResult___snd__h421041 = + (!_theResult____h412781[56] && _theResult____h412781[55]) ? + _theResult___snd__h421043 : + _theResult___snd__h421053 ; + assign _theResult___snd__h421043 = { _theResult____h412781[54:0], 2'd0 } ; + assign _theResult___snd__h421053 = + (!_theResult____h412781[56] && !_theResult____h412781[55] && + !_theResult____h412781[54] && + !_theResult____h412781[53] && + !_theResult____h412781[52] && + !_theResult____h412781[51] && + !_theResult____h412781[50] && + !_theResult____h412781[49] && + !_theResult____h412781[48] && + !_theResult____h412781[47] && + !_theResult____h412781[46] && + !_theResult____h412781[45] && + !_theResult____h412781[44] && + !_theResult____h412781[43] && + !_theResult____h412781[42] && + !_theResult____h412781[41] && + !_theResult____h412781[40] && + !_theResult____h412781[39] && + !_theResult____h412781[38] && + !_theResult____h412781[37] && + !_theResult____h412781[36] && + !_theResult____h412781[35] && + !_theResult____h412781[34] && + !_theResult____h412781[33] && + !_theResult____h412781[32] && + !_theResult____h412781[31] && + !_theResult____h412781[30] && + !_theResult____h412781[29] && + !_theResult____h412781[28] && + !_theResult____h412781[27] && + !_theResult____h412781[26] && + !_theResult____h412781[25] && + !_theResult____h412781[24] && + !_theResult____h412781[23] && + !_theResult____h412781[22] && + !_theResult____h412781[21] && + !_theResult____h412781[20] && + !_theResult____h412781[19] && + !_theResult____h412781[18] && + !_theResult____h412781[17] && + !_theResult____h412781[16] && + !_theResult____h412781[15] && + !_theResult____h412781[14] && + !_theResult____h412781[13] && + !_theResult____h412781[12] && + !_theResult____h412781[11] && + !_theResult____h412781[10] && + !_theResult____h412781[9] && + !_theResult____h412781[8] && + !_theResult____h412781[7] && + !_theResult____h412781[6] && + !_theResult____h412781[5] && + !_theResult____h412781[4] && + !_theResult____h412781[3] && + !_theResult____h412781[2] && + !_theResult____h412781[1] && + !_theResult____h412781[0]) ? + _theResult____h412781 : + _theResult___snd__h421059 ; + assign _theResult___snd__h421059 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66[54:0], 2'd0 } ; - assign _theResult___snd__h421083 = - _theResult____h412782 << + assign _theResult___snd__h421082 = + _theResult____h412781 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 ; - assign _theResult___snd__h429651 = + assign _theResult___snd__h429650 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h429665 : - _theResult___snd__h411863 ; - assign _theResult___snd__h429665 = + _theResult___snd__h429664 : + _theResult___snd__h411862 ; + assign _theResult___snd__h429664 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h387543 : - _theResult___snd__h429671 ; - assign _theResult___snd__h429671 = + sfd__h387542 : + _theResult___snd__h429670 ; + assign _theResult___snd__h429670 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71[54:0], 2'd0 } ; - assign _theResult___snd__h429689 = - sfd__h387543 << + assign _theResult___snd__h429688 = + sfd__h387542 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360) ; - assign _theResult___snd__h448953 = { _theResult____h440833[55:0], 1'd0 } ; - assign _theResult___snd__h448964 = - (!_theResult____h440833[56] && _theResult____h440833[55]) ? - _theResult___snd__h448966 : - _theResult___snd__h448976 ; - assign _theResult___snd__h448966 = { _theResult____h440833[54:0], 2'd0 } ; - assign _theResult___snd__h448976 = - (!_theResult____h440833[56] && !_theResult____h440833[55] && - !_theResult____h440833[54] && - !_theResult____h440833[53] && - !_theResult____h440833[52] && - !_theResult____h440833[51] && - !_theResult____h440833[50] && - !_theResult____h440833[49] && - !_theResult____h440833[48] && - !_theResult____h440833[47] && - !_theResult____h440833[46] && - !_theResult____h440833[45] && - !_theResult____h440833[44] && - !_theResult____h440833[43] && - !_theResult____h440833[42] && - !_theResult____h440833[41] && - !_theResult____h440833[40] && - !_theResult____h440833[39] && - !_theResult____h440833[38] && - !_theResult____h440833[37] && - !_theResult____h440833[36] && - !_theResult____h440833[35] && - !_theResult____h440833[34] && - !_theResult____h440833[33] && - !_theResult____h440833[32] && - !_theResult____h440833[31] && - !_theResult____h440833[30] && - !_theResult____h440833[29] && - !_theResult____h440833[28] && - !_theResult____h440833[27] && - !_theResult____h440833[26] && - !_theResult____h440833[25] && - !_theResult____h440833[24] && - !_theResult____h440833[23] && - !_theResult____h440833[22] && - !_theResult____h440833[21] && - !_theResult____h440833[20] && - !_theResult____h440833[19] && - !_theResult____h440833[18] && - !_theResult____h440833[17] && - !_theResult____h440833[16] && - !_theResult____h440833[15] && - !_theResult____h440833[14] && - !_theResult____h440833[13] && - !_theResult____h440833[12] && - !_theResult____h440833[11] && - !_theResult____h440833[10] && - !_theResult____h440833[9] && - !_theResult____h440833[8] && - !_theResult____h440833[7] && - !_theResult____h440833[6] && - !_theResult____h440833[5] && - !_theResult____h440833[4] && - !_theResult____h440833[3] && - !_theResult____h440833[2] && - !_theResult____h440833[1] && - !_theResult____h440833[0]) ? - _theResult____h440833 : - _theResult___snd__h448982 ; - assign _theResult___snd__h448982 = + assign _theResult___snd__h448952 = { _theResult____h440832[55:0], 1'd0 } ; + assign _theResult___snd__h448963 = + (!_theResult____h440832[56] && _theResult____h440832[55]) ? + _theResult___snd__h448965 : + _theResult___snd__h448975 ; + assign _theResult___snd__h448965 = { _theResult____h440832[54:0], 2'd0 } ; + assign _theResult___snd__h448975 = + (!_theResult____h440832[56] && !_theResult____h440832[55] && + !_theResult____h440832[54] && + !_theResult____h440832[53] && + !_theResult____h440832[52] && + !_theResult____h440832[51] && + !_theResult____h440832[50] && + !_theResult____h440832[49] && + !_theResult____h440832[48] && + !_theResult____h440832[47] && + !_theResult____h440832[46] && + !_theResult____h440832[45] && + !_theResult____h440832[44] && + !_theResult____h440832[43] && + !_theResult____h440832[42] && + !_theResult____h440832[41] && + !_theResult____h440832[40] && + !_theResult____h440832[39] && + !_theResult____h440832[38] && + !_theResult____h440832[37] && + !_theResult____h440832[36] && + !_theResult____h440832[35] && + !_theResult____h440832[34] && + !_theResult____h440832[33] && + !_theResult____h440832[32] && + !_theResult____h440832[31] && + !_theResult____h440832[30] && + !_theResult____h440832[29] && + !_theResult____h440832[28] && + !_theResult____h440832[27] && + !_theResult____h440832[26] && + !_theResult____h440832[25] && + !_theResult____h440832[24] && + !_theResult____h440832[23] && + !_theResult____h440832[22] && + !_theResult____h440832[21] && + !_theResult____h440832[20] && + !_theResult____h440832[19] && + !_theResult____h440832[18] && + !_theResult____h440832[17] && + !_theResult____h440832[16] && + !_theResult____h440832[15] && + !_theResult____h440832[14] && + !_theResult____h440832[13] && + !_theResult____h440832[12] && + !_theResult____h440832[11] && + !_theResult____h440832[10] && + !_theResult____h440832[9] && + !_theResult____h440832[8] && + !_theResult____h440832[7] && + !_theResult____h440832[6] && + !_theResult____h440832[5] && + !_theResult____h440832[4] && + !_theResult____h440832[3] && + !_theResult____h440832[2] && + !_theResult____h440832[1] && + !_theResult____h440832[0]) ? + _theResult____h440832 : + _theResult___snd__h448981 ; + assign _theResult___snd__h448981 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91[54:0], 2'd0 } ; - assign _theResult___snd__h449005 = - _theResult____h440833 << + assign _theResult___snd__h449004 = + _theResult____h440832 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 ; - assign _theResult___snd__h457549 = + assign _theResult___snd__h457548 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h457558 : - _theResult___snd__h457551 ; - assign _theResult___snd__h457551 = + _theResult___snd__h457557 : + _theResult___snd__h457550 ; + assign _theResult___snd__h457550 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h457558 = + assign _theResult___snd__h457557 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h433231 : - _theResult___snd__h457564 ; - assign _theResult___snd__h457564 = + sfd__h433230 : + _theResult___snd__h457563 ; + assign _theResult___snd__h457563 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93[54:0], 2'd0 } ; - assign _theResult___snd__h457587 = - sfd__h433231 << + assign _theResult___snd__h457586 = + sfd__h433230 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 ; - assign _theResult___snd__h466719 = { _theResult____h458470[55:0], 1'd0 } ; - assign _theResult___snd__h466730 = - (!_theResult____h458470[56] && _theResult____h458470[55]) ? - _theResult___snd__h466732 : - _theResult___snd__h466742 ; - assign _theResult___snd__h466732 = { _theResult____h458470[54:0], 2'd0 } ; - assign _theResult___snd__h466742 = - (!_theResult____h458470[56] && !_theResult____h458470[55] && - !_theResult____h458470[54] && - !_theResult____h458470[53] && - !_theResult____h458470[52] && - !_theResult____h458470[51] && - !_theResult____h458470[50] && - !_theResult____h458470[49] && - !_theResult____h458470[48] && - !_theResult____h458470[47] && - !_theResult____h458470[46] && - !_theResult____h458470[45] && - !_theResult____h458470[44] && - !_theResult____h458470[43] && - !_theResult____h458470[42] && - !_theResult____h458470[41] && - !_theResult____h458470[40] && - !_theResult____h458470[39] && - !_theResult____h458470[38] && - !_theResult____h458470[37] && - !_theResult____h458470[36] && - !_theResult____h458470[35] && - !_theResult____h458470[34] && - !_theResult____h458470[33] && - !_theResult____h458470[32] && - !_theResult____h458470[31] && - !_theResult____h458470[30] && - !_theResult____h458470[29] && - !_theResult____h458470[28] && - !_theResult____h458470[27] && - !_theResult____h458470[26] && - !_theResult____h458470[25] && - !_theResult____h458470[24] && - !_theResult____h458470[23] && - !_theResult____h458470[22] && - !_theResult____h458470[21] && - !_theResult____h458470[20] && - !_theResult____h458470[19] && - !_theResult____h458470[18] && - !_theResult____h458470[17] && - !_theResult____h458470[16] && - !_theResult____h458470[15] && - !_theResult____h458470[14] && - !_theResult____h458470[13] && - !_theResult____h458470[12] && - !_theResult____h458470[11] && - !_theResult____h458470[10] && - !_theResult____h458470[9] && - !_theResult____h458470[8] && - !_theResult____h458470[7] && - !_theResult____h458470[6] && - !_theResult____h458470[5] && - !_theResult____h458470[4] && - !_theResult____h458470[3] && - !_theResult____h458470[2] && - !_theResult____h458470[1] && - !_theResult____h458470[0]) ? - _theResult____h458470 : - _theResult___snd__h466748 ; - assign _theResult___snd__h466748 = + assign _theResult___snd__h466718 = { _theResult____h458469[55:0], 1'd0 } ; + assign _theResult___snd__h466729 = + (!_theResult____h458469[56] && _theResult____h458469[55]) ? + _theResult___snd__h466731 : + _theResult___snd__h466741 ; + assign _theResult___snd__h466731 = { _theResult____h458469[54:0], 2'd0 } ; + assign _theResult___snd__h466741 = + (!_theResult____h458469[56] && !_theResult____h458469[55] && + !_theResult____h458469[54] && + !_theResult____h458469[53] && + !_theResult____h458469[52] && + !_theResult____h458469[51] && + !_theResult____h458469[50] && + !_theResult____h458469[49] && + !_theResult____h458469[48] && + !_theResult____h458469[47] && + !_theResult____h458469[46] && + !_theResult____h458469[45] && + !_theResult____h458469[44] && + !_theResult____h458469[43] && + !_theResult____h458469[42] && + !_theResult____h458469[41] && + !_theResult____h458469[40] && + !_theResult____h458469[39] && + !_theResult____h458469[38] && + !_theResult____h458469[37] && + !_theResult____h458469[36] && + !_theResult____h458469[35] && + !_theResult____h458469[34] && + !_theResult____h458469[33] && + !_theResult____h458469[32] && + !_theResult____h458469[31] && + !_theResult____h458469[30] && + !_theResult____h458469[29] && + !_theResult____h458469[28] && + !_theResult____h458469[27] && + !_theResult____h458469[26] && + !_theResult____h458469[25] && + !_theResult____h458469[24] && + !_theResult____h458469[23] && + !_theResult____h458469[22] && + !_theResult____h458469[21] && + !_theResult____h458469[20] && + !_theResult____h458469[19] && + !_theResult____h458469[18] && + !_theResult____h458469[17] && + !_theResult____h458469[16] && + !_theResult____h458469[15] && + !_theResult____h458469[14] && + !_theResult____h458469[13] && + !_theResult____h458469[12] && + !_theResult____h458469[11] && + !_theResult____h458469[10] && + !_theResult____h458469[9] && + !_theResult____h458469[8] && + !_theResult____h458469[7] && + !_theResult____h458469[6] && + !_theResult____h458469[5] && + !_theResult____h458469[4] && + !_theResult____h458469[3] && + !_theResult____h458469[2] && + !_theResult____h458469[1] && + !_theResult____h458469[0]) ? + _theResult____h458469 : + _theResult___snd__h466747 ; + assign _theResult___snd__h466747 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101[54:0], 2'd0 } ; - assign _theResult___snd__h466771 = - _theResult____h458470 << + assign _theResult___snd__h466770 = + _theResult____h458469 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 ; - assign _theResult___snd__h475339 = + assign _theResult___snd__h475338 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h475353 : - _theResult___snd__h457551 ; - assign _theResult___snd__h475353 = + _theResult___snd__h475352 : + _theResult___snd__h457550 ; + assign _theResult___snd__h475352 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h433231 : - _theResult___snd__h475359 ; - assign _theResult___snd__h475359 = + sfd__h433230 : + _theResult___snd__h475358 ; + assign _theResult___snd__h475358 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106[54:0], 2'd0 } ; - assign _theResult___snd__h475377 = - sfd__h433231 << + assign _theResult___snd__h475376 = + sfd__h433230 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752) ; - assign _theResult___snd__h505511 = + assign _theResult___snd__h505510 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h505520 : - _theResult___snd__h505513 ; - assign _theResult___snd__h505513 = + _theResult___snd__h505519 : + _theResult___snd__h505512 ; + assign _theResult___snd__h505512 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ; - assign _theResult___snd__h505520 = + assign _theResult___snd__h505519 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8662) ? - sfd__h486559 : - _theResult___snd__h505526 ; - assign _theResult___snd__h505526 = + sfd__h486558 : + _theResult___snd__h505525 ; + assign _theResult___snd__h505525 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h505549 = - sfd__h486559 << + assign _theResult___snd__h505548 = + sfd__h486558 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8689 ; - assign _theResult___snd__h515148 = { _theResult____h506901[55:0], 1'd0 } ; - assign _theResult___snd__h515159 = - (!_theResult____h506901[56] && _theResult____h506901[55]) ? - _theResult___snd__h515161 : - _theResult___snd__h515171 ; - assign _theResult___snd__h515161 = { _theResult____h506901[54:0], 2'd0 } ; - assign _theResult___snd__h515171 = - (!_theResult____h506901[56] && !_theResult____h506901[55] && - !_theResult____h506901[54] && - !_theResult____h506901[53] && - !_theResult____h506901[52] && - !_theResult____h506901[51] && - !_theResult____h506901[50] && - !_theResult____h506901[49] && - !_theResult____h506901[48] && - !_theResult____h506901[47] && - !_theResult____h506901[46] && - !_theResult____h506901[45] && - !_theResult____h506901[44] && - !_theResult____h506901[43] && - !_theResult____h506901[42] && - !_theResult____h506901[41] && - !_theResult____h506901[40] && - !_theResult____h506901[39] && - !_theResult____h506901[38] && - !_theResult____h506901[37] && - !_theResult____h506901[36] && - !_theResult____h506901[35] && - !_theResult____h506901[34] && - !_theResult____h506901[33] && - !_theResult____h506901[32] && - !_theResult____h506901[31] && - !_theResult____h506901[30] && - !_theResult____h506901[29] && - !_theResult____h506901[28] && - !_theResult____h506901[27] && - !_theResult____h506901[26] && - !_theResult____h506901[25] && - !_theResult____h506901[24] && - !_theResult____h506901[23] && - !_theResult____h506901[22] && - !_theResult____h506901[21] && - !_theResult____h506901[20] && - !_theResult____h506901[19] && - !_theResult____h506901[18] && - !_theResult____h506901[17] && - !_theResult____h506901[16] && - !_theResult____h506901[15] && - !_theResult____h506901[14] && - !_theResult____h506901[13] && - !_theResult____h506901[12] && - !_theResult____h506901[11] && - !_theResult____h506901[10] && - !_theResult____h506901[9] && - !_theResult____h506901[8] && - !_theResult____h506901[7] && - !_theResult____h506901[6] && - !_theResult____h506901[5] && - !_theResult____h506901[4] && - !_theResult____h506901[3] && - !_theResult____h506901[2] && - !_theResult____h506901[1] && - !_theResult____h506901[0]) ? - _theResult____h506901 : - _theResult___snd__h515177 ; - assign _theResult___snd__h515177 = + assign _theResult___snd__h515147 = { _theResult____h506900[55:0], 1'd0 } ; + assign _theResult___snd__h515158 = + (!_theResult____h506900[56] && _theResult____h506900[55]) ? + _theResult___snd__h515160 : + _theResult___snd__h515170 ; + assign _theResult___snd__h515160 = { _theResult____h506900[54:0], 2'd0 } ; + assign _theResult___snd__h515170 = + (!_theResult____h506900[56] && !_theResult____h506900[55] && + !_theResult____h506900[54] && + !_theResult____h506900[53] && + !_theResult____h506900[52] && + !_theResult____h506900[51] && + !_theResult____h506900[50] && + !_theResult____h506900[49] && + !_theResult____h506900[48] && + !_theResult____h506900[47] && + !_theResult____h506900[46] && + !_theResult____h506900[45] && + !_theResult____h506900[44] && + !_theResult____h506900[43] && + !_theResult____h506900[42] && + !_theResult____h506900[41] && + !_theResult____h506900[40] && + !_theResult____h506900[39] && + !_theResult____h506900[38] && + !_theResult____h506900[37] && + !_theResult____h506900[36] && + !_theResult____h506900[35] && + !_theResult____h506900[34] && + !_theResult____h506900[33] && + !_theResult____h506900[32] && + !_theResult____h506900[31] && + !_theResult____h506900[30] && + !_theResult____h506900[29] && + !_theResult____h506900[28] && + !_theResult____h506900[27] && + !_theResult____h506900[26] && + !_theResult____h506900[25] && + !_theResult____h506900[24] && + !_theResult____h506900[23] && + !_theResult____h506900[22] && + !_theResult____h506900[21] && + !_theResult____h506900[20] && + !_theResult____h506900[19] && + !_theResult____h506900[18] && + !_theResult____h506900[17] && + !_theResult____h506900[16] && + !_theResult____h506900[15] && + !_theResult____h506900[14] && + !_theResult____h506900[13] && + !_theResult____h506900[12] && + !_theResult____h506900[11] && + !_theResult____h506900[10] && + !_theResult____h506900[9] && + !_theResult____h506900[8] && + !_theResult____h506900[7] && + !_theResult____h506900[6] && + !_theResult____h506900[5] && + !_theResult____h506900[4] && + !_theResult____h506900[3] && + !_theResult____h506900[2] && + !_theResult____h506900[1] && + !_theResult____h506900[0]) ? + _theResult____h506900 : + _theResult___snd__h515176 ; + assign _theResult___snd__h515176 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h515200 = - _theResult____h506901 << + assign _theResult___snd__h515199 = + _theResult____h506900 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9001 ; - assign _theResult___snd__h523916 = + assign _theResult___snd__h523915 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h523930 : - _theResult___snd__h505513 ; - assign _theResult___snd__h523930 = + _theResult___snd__h523929 : + _theResult___snd__h505512 ; + assign _theResult___snd__h523929 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8662) ? - sfd__h486559 : - _theResult___snd__h523936 ; - assign _theResult___snd__h523936 = + sfd__h486558 : + _theResult___snd__h523935 ; + assign _theResult___snd__h523935 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h523954 = - sfd__h486559 << + assign _theResult___snd__h523953 = + sfd__h486558 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9052 ; - assign _theResult___snd__h544312 = + assign _theResult___snd__h544311 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h544321 : - _theResult___snd__h544314 ; - assign _theResult___snd__h544314 = + _theResult___snd__h544320 : + _theResult___snd__h544313 ; + assign _theResult___snd__h544313 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ; - assign _theResult___snd__h544321 = + assign _theResult___snd__h544320 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d10150) ? - sfd__h525501 : - _theResult___snd__h544327 ; - assign _theResult___snd__h544327 = + sfd__h525500 : + _theResult___snd__h544326 ; + assign _theResult___snd__h544326 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h544350 = - sfd__h525501 << + assign _theResult___snd__h544349 = + sfd__h525500 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10177 ; - assign _theResult___snd__h553949 = { _theResult____h545702[55:0], 1'd0 } ; - assign _theResult___snd__h553960 = - (!_theResult____h545702[56] && _theResult____h545702[55]) ? - _theResult___snd__h553962 : - _theResult___snd__h553972 ; - assign _theResult___snd__h553962 = { _theResult____h545702[54:0], 2'd0 } ; - assign _theResult___snd__h553972 = - (!_theResult____h545702[56] && !_theResult____h545702[55] && - !_theResult____h545702[54] && - !_theResult____h545702[53] && - !_theResult____h545702[52] && - !_theResult____h545702[51] && - !_theResult____h545702[50] && - !_theResult____h545702[49] && - !_theResult____h545702[48] && - !_theResult____h545702[47] && - !_theResult____h545702[46] && - !_theResult____h545702[45] && - !_theResult____h545702[44] && - !_theResult____h545702[43] && - !_theResult____h545702[42] && - !_theResult____h545702[41] && - !_theResult____h545702[40] && - !_theResult____h545702[39] && - !_theResult____h545702[38] && - !_theResult____h545702[37] && - !_theResult____h545702[36] && - !_theResult____h545702[35] && - !_theResult____h545702[34] && - !_theResult____h545702[33] && - !_theResult____h545702[32] && - !_theResult____h545702[31] && - !_theResult____h545702[30] && - !_theResult____h545702[29] && - !_theResult____h545702[28] && - !_theResult____h545702[27] && - !_theResult____h545702[26] && - !_theResult____h545702[25] && - !_theResult____h545702[24] && - !_theResult____h545702[23] && - !_theResult____h545702[22] && - !_theResult____h545702[21] && - !_theResult____h545702[20] && - !_theResult____h545702[19] && - !_theResult____h545702[18] && - !_theResult____h545702[17] && - !_theResult____h545702[16] && - !_theResult____h545702[15] && - !_theResult____h545702[14] && - !_theResult____h545702[13] && - !_theResult____h545702[12] && - !_theResult____h545702[11] && - !_theResult____h545702[10] && - !_theResult____h545702[9] && - !_theResult____h545702[8] && - !_theResult____h545702[7] && - !_theResult____h545702[6] && - !_theResult____h545702[5] && - !_theResult____h545702[4] && - !_theResult____h545702[3] && - !_theResult____h545702[2] && - !_theResult____h545702[1] && - !_theResult____h545702[0]) ? - _theResult____h545702 : - _theResult___snd__h553978 ; - assign _theResult___snd__h553978 = + assign _theResult___snd__h553948 = { _theResult____h545701[55:0], 1'd0 } ; + assign _theResult___snd__h553959 = + (!_theResult____h545701[56] && _theResult____h545701[55]) ? + _theResult___snd__h553961 : + _theResult___snd__h553971 ; + assign _theResult___snd__h553961 = { _theResult____h545701[54:0], 2'd0 } ; + assign _theResult___snd__h553971 = + (!_theResult____h545701[56] && !_theResult____h545701[55] && + !_theResult____h545701[54] && + !_theResult____h545701[53] && + !_theResult____h545701[52] && + !_theResult____h545701[51] && + !_theResult____h545701[50] && + !_theResult____h545701[49] && + !_theResult____h545701[48] && + !_theResult____h545701[47] && + !_theResult____h545701[46] && + !_theResult____h545701[45] && + !_theResult____h545701[44] && + !_theResult____h545701[43] && + !_theResult____h545701[42] && + !_theResult____h545701[41] && + !_theResult____h545701[40] && + !_theResult____h545701[39] && + !_theResult____h545701[38] && + !_theResult____h545701[37] && + !_theResult____h545701[36] && + !_theResult____h545701[35] && + !_theResult____h545701[34] && + !_theResult____h545701[33] && + !_theResult____h545701[32] && + !_theResult____h545701[31] && + !_theResult____h545701[30] && + !_theResult____h545701[29] && + !_theResult____h545701[28] && + !_theResult____h545701[27] && + !_theResult____h545701[26] && + !_theResult____h545701[25] && + !_theResult____h545701[24] && + !_theResult____h545701[23] && + !_theResult____h545701[22] && + !_theResult____h545701[21] && + !_theResult____h545701[20] && + !_theResult____h545701[19] && + !_theResult____h545701[18] && + !_theResult____h545701[17] && + !_theResult____h545701[16] && + !_theResult____h545701[15] && + !_theResult____h545701[14] && + !_theResult____h545701[13] && + !_theResult____h545701[12] && + !_theResult____h545701[11] && + !_theResult____h545701[10] && + !_theResult____h545701[9] && + !_theResult____h545701[8] && + !_theResult____h545701[7] && + !_theResult____h545701[6] && + !_theResult____h545701[5] && + !_theResult____h545701[4] && + !_theResult____h545701[3] && + !_theResult____h545701[2] && + !_theResult____h545701[1] && + !_theResult____h545701[0]) ? + _theResult____h545701 : + _theResult___snd__h553977 ; + assign _theResult___snd__h553977 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h554001 = - _theResult____h545702 << + assign _theResult___snd__h554000 = + _theResult____h545701 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10474 ; - assign _theResult___snd__h562717 = + assign _theResult___snd__h562716 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h562731 : - _theResult___snd__h544314 ; - assign _theResult___snd__h562731 = + _theResult___snd__h562730 : + _theResult___snd__h544313 ; + assign _theResult___snd__h562730 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d10150) ? - sfd__h525501 : - _theResult___snd__h562737 ; - assign _theResult___snd__h562737 = + sfd__h525500 : + _theResult___snd__h562736 ; + assign _theResult___snd__h562736 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h562755 = - sfd__h525501 << + assign _theResult___snd__h562754 = + sfd__h525500 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10525 ; - assign _theResult___snd__h583513 = + assign _theResult___snd__h583512 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h583522 : - _theResult___snd__h583515 ; - assign _theResult___snd__h583515 = + _theResult___snd__h583521 : + _theResult___snd__h583514 ; + assign _theResult___snd__h583514 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ; - assign _theResult___snd__h583522 = + assign _theResult___snd__h583521 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d9387) ? - sfd__h564702 : - _theResult___snd__h583528 ; - assign _theResult___snd__h583528 = + sfd__h564701 : + _theResult___snd__h583527 ; + assign _theResult___snd__h583527 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h583551 = - sfd__h564702 << + assign _theResult___snd__h583550 = + sfd__h564701 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9414 ; - assign _theResult___snd__h593150 = { _theResult____h584903[55:0], 1'd0 } ; - assign _theResult___snd__h593161 = - (!_theResult____h584903[56] && _theResult____h584903[55]) ? - _theResult___snd__h593163 : - _theResult___snd__h593173 ; - assign _theResult___snd__h593163 = { _theResult____h584903[54:0], 2'd0 } ; - assign _theResult___snd__h593173 = - (!_theResult____h584903[56] && !_theResult____h584903[55] && - !_theResult____h584903[54] && - !_theResult____h584903[53] && - !_theResult____h584903[52] && - !_theResult____h584903[51] && - !_theResult____h584903[50] && - !_theResult____h584903[49] && - !_theResult____h584903[48] && - !_theResult____h584903[47] && - !_theResult____h584903[46] && - !_theResult____h584903[45] && - !_theResult____h584903[44] && - !_theResult____h584903[43] && - !_theResult____h584903[42] && - !_theResult____h584903[41] && - !_theResult____h584903[40] && - !_theResult____h584903[39] && - !_theResult____h584903[38] && - !_theResult____h584903[37] && - !_theResult____h584903[36] && - !_theResult____h584903[35] && - !_theResult____h584903[34] && - !_theResult____h584903[33] && - !_theResult____h584903[32] && - !_theResult____h584903[31] && - !_theResult____h584903[30] && - !_theResult____h584903[29] && - !_theResult____h584903[28] && - !_theResult____h584903[27] && - !_theResult____h584903[26] && - !_theResult____h584903[25] && - !_theResult____h584903[24] && - !_theResult____h584903[23] && - !_theResult____h584903[22] && - !_theResult____h584903[21] && - !_theResult____h584903[20] && - !_theResult____h584903[19] && - !_theResult____h584903[18] && - !_theResult____h584903[17] && - !_theResult____h584903[16] && - !_theResult____h584903[15] && - !_theResult____h584903[14] && - !_theResult____h584903[13] && - !_theResult____h584903[12] && - !_theResult____h584903[11] && - !_theResult____h584903[10] && - !_theResult____h584903[9] && - !_theResult____h584903[8] && - !_theResult____h584903[7] && - !_theResult____h584903[6] && - !_theResult____h584903[5] && - !_theResult____h584903[4] && - !_theResult____h584903[3] && - !_theResult____h584903[2] && - !_theResult____h584903[1] && - !_theResult____h584903[0]) ? - _theResult____h584903 : - _theResult___snd__h593179 ; - assign _theResult___snd__h593179 = + assign _theResult___snd__h593149 = { _theResult____h584902[55:0], 1'd0 } ; + assign _theResult___snd__h593160 = + (!_theResult____h584902[56] && _theResult____h584902[55]) ? + _theResult___snd__h593162 : + _theResult___snd__h593172 ; + assign _theResult___snd__h593162 = { _theResult____h584902[54:0], 2'd0 } ; + assign _theResult___snd__h593172 = + (!_theResult____h584902[56] && !_theResult____h584902[55] && + !_theResult____h584902[54] && + !_theResult____h584902[53] && + !_theResult____h584902[52] && + !_theResult____h584902[51] && + !_theResult____h584902[50] && + !_theResult____h584902[49] && + !_theResult____h584902[48] && + !_theResult____h584902[47] && + !_theResult____h584902[46] && + !_theResult____h584902[45] && + !_theResult____h584902[44] && + !_theResult____h584902[43] && + !_theResult____h584902[42] && + !_theResult____h584902[41] && + !_theResult____h584902[40] && + !_theResult____h584902[39] && + !_theResult____h584902[38] && + !_theResult____h584902[37] && + !_theResult____h584902[36] && + !_theResult____h584902[35] && + !_theResult____h584902[34] && + !_theResult____h584902[33] && + !_theResult____h584902[32] && + !_theResult____h584902[31] && + !_theResult____h584902[30] && + !_theResult____h584902[29] && + !_theResult____h584902[28] && + !_theResult____h584902[27] && + !_theResult____h584902[26] && + !_theResult____h584902[25] && + !_theResult____h584902[24] && + !_theResult____h584902[23] && + !_theResult____h584902[22] && + !_theResult____h584902[21] && + !_theResult____h584902[20] && + !_theResult____h584902[19] && + !_theResult____h584902[18] && + !_theResult____h584902[17] && + !_theResult____h584902[16] && + !_theResult____h584902[15] && + !_theResult____h584902[14] && + !_theResult____h584902[13] && + !_theResult____h584902[12] && + !_theResult____h584902[11] && + !_theResult____h584902[10] && + !_theResult____h584902[9] && + !_theResult____h584902[8] && + !_theResult____h584902[7] && + !_theResult____h584902[6] && + !_theResult____h584902[5] && + !_theResult____h584902[4] && + !_theResult____h584902[3] && + !_theResult____h584902[2] && + !_theResult____h584902[1] && + !_theResult____h584902[0]) ? + _theResult____h584902 : + _theResult___snd__h593178 ; + assign _theResult___snd__h593178 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h593202 = - _theResult____h584903 << + assign _theResult___snd__h593201 = + _theResult____h584902 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9711 ; - assign _theResult___snd__h601918 = + assign _theResult___snd__h601917 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h601932 : - _theResult___snd__h583515 ; - assign _theResult___snd__h601932 = + _theResult___snd__h601931 : + _theResult___snd__h583514 ; + assign _theResult___snd__h601931 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d9387) ? - sfd__h564702 : - _theResult___snd__h601938 ; - assign _theResult___snd__h601938 = + sfd__h564701 : + _theResult___snd__h601937 ; + assign _theResult___snd__h601937 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h601956 = - sfd__h564702 << + assign _theResult___snd__h601955 = + sfd__h564701 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9762 ; - assign _theResult___snd__h607310 = - b__h606762[63] ? b___1__h607375 : b__h606762 ; - assign _theResult___snd_fst_exp__h366746 = + assign _theResult___snd__h607309 = + b__h606761[63] ? b___1__h607374 : b__h606761 ; + assign _theResult___snd_fst_exp__h366745 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_exp__h358161 : - _theResult___fst_exp__h366743 ; - assign _theResult___snd_fst_exp__h384566 = + _theResult___fst_exp__h358160 : + _theResult___fst_exp__h366742 ; + assign _theResult___snd_fst_exp__h384565 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_exp__h375927 : - _theResult___fst_exp__h384563 ; - assign _theResult___snd_fst_exp__h412436 = + _theResult___fst_exp__h375926 : + _theResult___fst_exp__h384562 ; + assign _theResult___snd_fst_exp__h412435 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_exp__h403851 : - _theResult___fst_exp__h412433 ; - assign _theResult___snd_fst_exp__h430256 = + _theResult___fst_exp__h403850 : + _theResult___fst_exp__h412432 ; + assign _theResult___snd_fst_exp__h430255 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_exp__h421617 : - _theResult___fst_exp__h430253 ; - assign _theResult___snd_fst_exp__h458124 = + _theResult___fst_exp__h421616 : + _theResult___fst_exp__h430252 ; + assign _theResult___snd_fst_exp__h458123 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_exp__h449539 : - _theResult___fst_exp__h458121 ; - assign _theResult___snd_fst_exp__h475944 = + _theResult___fst_exp__h449538 : + _theResult___fst_exp__h458120 ; + assign _theResult___snd_fst_exp__h475943 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_exp__h467305 : - _theResult___fst_exp__h475941 ; - assign _theResult___snd_fst_exp__h506321 = + _theResult___fst_exp__h467304 : + _theResult___fst_exp__h475940 ; + assign _theResult___snd_fst_exp__h506320 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8618 ? 11'd0 : - _theResult___fst_exp__h506318 ; - assign _theResult___snd_fst_exp__h524756 = + _theResult___fst_exp__h506317 ; + assign _theResult___snd_fst_exp__h524755 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d8754 ? - _theResult___fst_exp__h515969 : - _theResult___fst_exp__h524753 ; - assign _theResult___snd_fst_exp__h545122 = + _theResult___fst_exp__h515968 : + _theResult___fst_exp__h524752 ; + assign _theResult___snd_fst_exp__h545121 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10106 ? 11'd0 : - _theResult___fst_exp__h545119 ; - assign _theResult___snd_fst_exp__h563557 = + _theResult___fst_exp__h545118 ; + assign _theResult___snd_fst_exp__h563556 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d10227 ? - _theResult___fst_exp__h554770 : - _theResult___fst_exp__h563554 ; - assign _theResult___snd_fst_exp__h584323 = + _theResult___fst_exp__h554769 : + _theResult___fst_exp__h563553 ; + assign _theResult___snd_fst_exp__h584322 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9343 ? 11'd0 : - _theResult___fst_exp__h584320 ; - assign _theResult___snd_fst_exp__h602758 = + _theResult___fst_exp__h584319 ; + assign _theResult___snd_fst_exp__h602757 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9464 ? - _theResult___fst_exp__h593971 : - _theResult___fst_exp__h602755 ; - assign _theResult___snd_fst_sfd__h341798 = + _theResult___fst_exp__h593970 : + _theResult___fst_exp__h602754 ; + assign _theResult___snd_fst_sfd__h341797 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h366747 = + assign _theResult___snd_fst_sfd__h366746 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_sfd__h358162 : - _theResult___fst_sfd__h366744 ; - assign _theResult___snd_fst_sfd__h384567 = + _theResult___fst_sfd__h358161 : + _theResult___fst_sfd__h366743 ; + assign _theResult___snd_fst_sfd__h384566 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_sfd__h375928 : - _theResult___fst_sfd__h384564 ; - assign _theResult___snd_fst_sfd__h387493 = + _theResult___fst_sfd__h375927 : + _theResult___fst_sfd__h384563 ; + assign _theResult___snd_fst_sfd__h387492 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h412437 = + assign _theResult___snd_fst_sfd__h412436 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_sfd__h403852 : - _theResult___fst_sfd__h412434 ; - assign _theResult___snd_fst_sfd__h430257 = + _theResult___fst_sfd__h403851 : + _theResult___fst_sfd__h412433 ; + assign _theResult___snd_fst_sfd__h430256 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_sfd__h421618 : - _theResult___fst_sfd__h430254 ; - assign _theResult___snd_fst_sfd__h433181 = + _theResult___fst_sfd__h421617 : + _theResult___fst_sfd__h430253 ; + assign _theResult___snd_fst_sfd__h433180 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h458125 = + assign _theResult___snd_fst_sfd__h458124 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_sfd__h449540 : - _theResult___fst_sfd__h458122 ; - assign _theResult___snd_fst_sfd__h475945 = + _theResult___fst_sfd__h449539 : + _theResult___fst_sfd__h458121 ; + assign _theResult___snd_fst_sfd__h475944 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_sfd__h467306 : - _theResult___fst_sfd__h475942 ; - assign _theResult___snd_fst_sfd__h486513 = + _theResult___fst_sfd__h467305 : + _theResult___fst_sfd__h475941 ; + assign _theResult___snd_fst_sfd__h486512 = (coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h486262 ; - assign _theResult___snd_fst_sfd__h506322 = + out___1_sfd__h486261 ; + assign _theResult___snd_fst_sfd__h506321 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8618 ? 52'd0 : - _theResult___fst_sfd__h506319 ; - assign _theResult___snd_fst_sfd__h524757 = + _theResult___fst_sfd__h506318 ; + assign _theResult___snd_fst_sfd__h524756 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d8754 ? - _theResult___fst_sfd__h515970 : - _theResult___fst_sfd__h524754 ; - assign _theResult___snd_fst_sfd__h525455 = + _theResult___fst_sfd__h515969 : + _theResult___fst_sfd__h524753 ; + assign _theResult___snd_fst_sfd__h525454 = (coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h525204 ; - assign _theResult___snd_fst_sfd__h545123 = + out___1_sfd__h525203 ; + assign _theResult___snd_fst_sfd__h545122 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10106 ? 52'd0 : - _theResult___fst_sfd__h545120 ; - assign _theResult___snd_fst_sfd__h563558 = + _theResult___fst_sfd__h545119 ; + assign _theResult___snd_fst_sfd__h563557 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d10227 ? - _theResult___fst_sfd__h554771 : - _theResult___fst_sfd__h563555 ; - assign _theResult___snd_fst_sfd__h564656 = + _theResult___fst_sfd__h554770 : + _theResult___fst_sfd__h563554 ; + assign _theResult___snd_fst_sfd__h564655 = (coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h564405 ; - assign _theResult___snd_fst_sfd__h584324 = + out___1_sfd__h564404 ; + assign _theResult___snd_fst_sfd__h584323 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9343 ? 52'd0 : - _theResult___fst_sfd__h584321 ; - assign _theResult___snd_fst_sfd__h602759 = + _theResult___fst_sfd__h584320 ; + assign _theResult___snd_fst_sfd__h602758 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__4_ETC___d9464 ? - _theResult___fst_sfd__h593972 : - _theResult___fst_sfd__h602756 ; - assign a___1__h606923 = + _theResult___fst_sfd__h593971 : + _theResult___fst_sfd__h602755 ; + assign a___1__h606922 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 } ; - assign a___1__h607314 = 64'd0 - a__h606761 ; - assign a__h606761 = + assign a___1__h607313 = 64'd0 - a__h606760 ; + assign a__h606760 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h606923 : + a___1__h606922 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h606924 = + assign b___1__h606923 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h607375 = 64'd0 - b__h606762 ; - assign b__h606762 = + assign b___1__h607374 = 64'd0 - b__h606761 ; + assign b__h606761 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h606924 : + b___1__h606923 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h606909 = { {64{a__h606761[63]}}, a__h606761 } ; - assign b__h606985 = { {64{b__h606762[63]}}, b__h606762 } ; - assign b__h607086 = { 64'd0, a__h606761 } ; - assign b__h607098 = { 64'd0, b__h606762 } ; - assign base__h704873 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h705076 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h702271 = - commitStage_commitTrap[4] ? i__h702446 : i__h702286 ; + assign b__h606908 = { {64{a__h606760[63]}}, a__h606760 } ; + assign b__h606984 = { {64{b__h606761[63]}}, b__h606761 } ; + assign b__h607085 = { 64'd0, a__h606760 } ; + assign b__h607097 = { 64'd0, b__h606761 } ; + assign base__h707033 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h707236 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h704431 = + commitStage_commitTrap[4] ? i__h704606 : i__h704446 ; + assign checkForException_3069_BIT_4_3070_OR_csrf_fs_r_ETC___d13509 = + checkForException___d13069[4] || + csrf_fs_reg == 2'd0 && + (fetchStage$pipelines_0_first[95] && + fetchStage$pipelines_0_first[94] || + fetchStage$pipelines_0_first[88] && + fetchStage$pipelines_0_first[87] || + fetchStage$pipelines_0_first[81] || + fetchStage$pipelines_0_first[75] && + fetchStage$pipelines_0_first[74]) ; + assign checkForException_3686_BIT_4_3687_OR_csrf_fs_r_ETC___d13767 = + checkForException___d13686[4] || + csrf_fs_reg == 2'd0 && + (fetchStage$pipelines_1_first[95] && + fetchStage$pipelines_1_first[94] || + fetchStage$pipelines_1_first[88] && + fetchStage$pipelines_1_first[87] || + fetchStage$pipelines_1_first[81] || + fetchStage$pipelines_1_first[75] && + fetchStage$pipelines_1_first[74]) ; assign coreFix_aluExe_0_bypassWire_0_wget__2302_BITS__ETC___d12304 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27313,7 +27447,7 @@ module mkCore(CLK, (coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1479_BITS__ETC___d11481 = @@ -27521,11 +27655,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] - 8'd127 ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13895 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13986 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13875) ; + NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d13966) ; assign coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -27561,7 +27695,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h257156 ; + y__h257157 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 || @@ -27912,14 +28046,14 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14559 = + assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14652 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14554 ; + NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14647 ; assign csrf_debug_int_pend_read__1844_CONCAT_0b0_2867_ETC___d12872 = { csrf_debug_int_pend, 2'b0, @@ -27933,211 +28067,252 @@ module mkCore(CLK, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ; - assign csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 = - csrf_prv_reg_read__2863_ULE_1___d14382 && + assign csrf_fs_reg_read__1686_EQ_0_3058_AND_fetchStag_ETC___d13104 = + csrf_fs_reg == 2'd0 && + (fetchStage$pipelines_0_first[95] && + fetchStage$pipelines_0_first[94] || + fetchStage$pipelines_0_first[88] && + fetchStage$pipelines_0_first[87] || + fetchStage$pipelines_0_first[81] || + fetchStage$pipelines_0_first[75] && + fetchStage$pipelines_0_first[74]) || + fetchStage$pipelines_0_first[199:195] == 5'd13 && + (fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13099 || + csrf_prv_reg_read__2863_ULT_IF_fetchStage_pipe_ETC___d13101) ; + assign csrf_prv_reg_read__2863_ULE_1_4475_AND_IF_comm_ETC___d14515 = + csrf_prv_reg_read__2863_ULE_1___d14475 && (commitStage_commitTrap[4] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14402 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14420) ; - assign csrf_prv_reg_read__2863_ULE_1___d14382 = csrf_prv_reg <= 2'd1 ; - assign data77961_BITS_31_TO_0__q2 = data__h477961[31:0] ; - assign data78891_BITS_31_TO_0__q6 = data__h478891[31:0] ; - assign data___1__h478473 = - { {32{data77961_BITS_31_TO_0__q2[31]}}, - data77961_BITS_31_TO_0__q2 } ; - assign data___1__h479403 = - { {32{data78891_BITS_31_TO_0__q6[31]}}, - data78891_BITS_31_TO_0__q6 } ; - assign data__h477961 = + _0b0_CONCAT_csrf_mideleg_11_reg_read__1801_1802_ETC___d14495 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1793_1794_ETC___d14513) ; + assign csrf_prv_reg_read__2863_ULE_1___d14475 = csrf_prv_reg <= 2'd1 ; + assign csrf_prv_reg_read__2863_ULT_IF_fetchStage_pipe_ETC___d13101 = + csrf_prv_reg < + IF_fetchStage_pipelines_0_first__2835_BIT_173__ETC___d13096[9:8] ; + assign data77960_BITS_31_TO_0__q2 = data__h477960[31:0] ; + assign data78890_BITS_31_TO_0__q6 = data__h478890[31:0] ; + assign data___1__h478472 = + { {32{data77960_BITS_31_TO_0__q2[31]}}, + data77960_BITS_31_TO_0__q2 } ; + assign data___1__h479402 = + { {32{data78890_BITS_31_TO_0__q6[31]}}, + data78890_BITS_31_TO_0__q6 } ; + assign data__h477960 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h478891 = + assign data__h478890 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h478657 : - x_remainder__h478658 ; - assign din_inc___2_exp__h384597 = _theResult___fst_exp__h357564 + 8'd1 ; - assign din_inc___2_exp__h384621 = _theResult___fst_exp__h366220 + 8'd1 ; - assign din_inc___2_exp__h384651 = _theResult___fst_exp__h375330 + 8'd1 ; - assign din_inc___2_exp__h384675 = _theResult___fst_exp__h384015 + 8'd1 ; - assign din_inc___2_exp__h430287 = _theResult___fst_exp__h403254 + 8'd1 ; - assign din_inc___2_exp__h430311 = _theResult___fst_exp__h411910 + 8'd1 ; - assign din_inc___2_exp__h430341 = _theResult___fst_exp__h421020 + 8'd1 ; - assign din_inc___2_exp__h430365 = _theResult___fst_exp__h429705 + 8'd1 ; - assign din_inc___2_exp__h475975 = _theResult___fst_exp__h448942 + 8'd1 ; - assign din_inc___2_exp__h475999 = _theResult___fst_exp__h457598 + 8'd1 ; - assign din_inc___2_exp__h476029 = _theResult___fst_exp__h466708 + 8'd1 ; - assign din_inc___2_exp__h476053 = _theResult___fst_exp__h475393 + 8'd1 ; - assign din_inc___2_exp__h524810 = _theResult___fst_exp__h505560 + 11'd1 ; - assign din_inc___2_exp__h524845 = _theResult___fst_exp__h515137 + 11'd1 ; - assign din_inc___2_exp__h524871 = _theResult___fst_exp__h523970 + 11'd1 ; - assign din_inc___2_exp__h563611 = _theResult___fst_exp__h544361 + 11'd1 ; - assign din_inc___2_exp__h563646 = _theResult___fst_exp__h553938 + 11'd1 ; - assign din_inc___2_exp__h563672 = _theResult___fst_exp__h562771 + 11'd1 ; - assign din_inc___2_exp__h602812 = _theResult___fst_exp__h583562 + 11'd1 ; - assign din_inc___2_exp__h602847 = _theResult___fst_exp__h593139 + 11'd1 ; - assign din_inc___2_exp__h602873 = _theResult___fst_exp__h601972 + 11'd1 ; - assign enabled_ints___1__h655692 = pend_ints__h655193 & y__h655704 ; - assign enabled_ints__h655739 = - pend_ints__h655193 & - { r1__read_BITS_12_TO_0___h655715, csrf_mideleg_1_0_reg } ; - assign fallthrough_pc__h666996 = + x_quotient__h478656 : + x_remainder__h478657 ; + assign din_inc___2_exp__h384596 = _theResult___fst_exp__h357563 + 8'd1 ; + assign din_inc___2_exp__h384620 = _theResult___fst_exp__h366219 + 8'd1 ; + assign din_inc___2_exp__h384650 = _theResult___fst_exp__h375329 + 8'd1 ; + assign din_inc___2_exp__h384674 = _theResult___fst_exp__h384014 + 8'd1 ; + assign din_inc___2_exp__h430286 = _theResult___fst_exp__h403253 + 8'd1 ; + assign din_inc___2_exp__h430310 = _theResult___fst_exp__h411909 + 8'd1 ; + assign din_inc___2_exp__h430340 = _theResult___fst_exp__h421019 + 8'd1 ; + assign din_inc___2_exp__h430364 = _theResult___fst_exp__h429704 + 8'd1 ; + assign din_inc___2_exp__h475974 = _theResult___fst_exp__h448941 + 8'd1 ; + assign din_inc___2_exp__h475998 = _theResult___fst_exp__h457597 + 8'd1 ; + assign din_inc___2_exp__h476028 = _theResult___fst_exp__h466707 + 8'd1 ; + assign din_inc___2_exp__h476052 = _theResult___fst_exp__h475392 + 8'd1 ; + assign din_inc___2_exp__h524809 = _theResult___fst_exp__h505559 + 11'd1 ; + assign din_inc___2_exp__h524844 = _theResult___fst_exp__h515136 + 11'd1 ; + assign din_inc___2_exp__h524870 = _theResult___fst_exp__h523969 + 11'd1 ; + assign din_inc___2_exp__h563610 = _theResult___fst_exp__h544360 + 11'd1 ; + assign din_inc___2_exp__h563645 = _theResult___fst_exp__h553937 + 11'd1 ; + assign din_inc___2_exp__h563671 = _theResult___fst_exp__h562770 + 11'd1 ; + assign din_inc___2_exp__h602811 = _theResult___fst_exp__h583561 + 11'd1 ; + assign din_inc___2_exp__h602846 = _theResult___fst_exp__h593138 + 11'd1 ; + assign din_inc___2_exp__h602872 = _theResult___fst_exp__h601971 + 11'd1 ; + assign enabled_ints___1__h655697 = pend_ints__h655198 & y__h655709 ; + assign enabled_ints__h655744 = + pend_ints__h655198 & + { r1__read_BITS_12_TO_0___h655720, csrf_mideleg_1_0_reg } ; + assign fallthrough_pc__h667687 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h681798 = + assign fallthrough_pc__h683150 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; - assign fcsr_csr__read__h614542 = { 56'd0, x__h617216 } ; - assign fetchStage_RDY_pipelines_0_first__2832_AND_NOT_ETC___d13381 = + assign fcsr_csr__read__h614541 = { 56'd0, x__h617215 } ; + assign fetchStage_RDY_pipelines_0_first__2832_AND_NOT_ETC___d13440 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 ; - assign fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13285 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 ; + assign fetchStage_RDY_pipelines_0_first__2832_AND_epo_ETC___d13320 = fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13447 = + assign fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13506 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13442 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13501 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13385 ; - assign fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964 = + IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13444 ; + assign fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14056 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 ; - assign fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14069 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 ; + assign fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14174 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13961 && - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13646 || - !coreFix_aluExe_0_rsAlu$canEnq ; - assign fetchStage_pipelines_0_canDeq__2833_AND_fetchS_ETC___d13954 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d14053 && + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724 || + !coreFix_aluExe_0_rsAlu$canEnq || + (!fetchStage$pipelines_0_canDeq || + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14169 || + fetchStage$pipelines_0_first[194:192] != 3'd0 && + fetchStage$pipelines_0_first[194:192] != 3'd1 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457) && + coreFix_aluExe_1_rsAlu$canEnq && + !coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453 ; + assign fetchStage_pipelines_0_canDeq__2833_AND_fetchS_ETC___d14045 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13837 || + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13928 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2844_BITS_194_TO_ETC___d13848 || + (fetchStage_pipelines_1_first__2844_BITS_194_TO_ETC___d13939 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13853 || - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13950) && - IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13782 ; - assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13892 = + fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13944 || + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14041) && + IF_fetchStage_RDY_pipelines_1_first__2843_AND__ETC___d13872 ; + assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13983 = fetchStage$pipelines_0_canDeq && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13898 = + assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13989 = fetchStage$pipelines_0_canDeq && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 ; - assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13899 = - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13898 || + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 ; + assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13990 = + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13989 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13920 = - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13892 || + assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14011 = + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13983 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13913 ; - assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14217 = + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14004 ; + assign fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14310 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14215 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14308 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign fetchStage_pipelines_0_canDeq__2833_AND_specTa_ETC___d14047 = + assign fetchStage_pipelines_0_canDeq__2833_AND_specTa_ETC___d14139 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13646 = + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13099 = + (fetchStage$pipelines_0_first[194:192] == 3'd0 && + fetchStage$pipelines_0_first[178:174] == 5'd15 || + rs1__h659255 != 5'd0 || + imm__h659256 != 32'd0) && + IF_fetchStage_pipelines_0_first__2835_BIT_173__ETC___d13096[11:10] == + 2'b11 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394) ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13665 = + coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453) ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13745 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13658 || + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13738 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13814 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13831 = + fetchStage$pipelines_0_first[68] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[2] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[3] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[4] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[5] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[6] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[7] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[8] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[9] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[10] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[11] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13922 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13829 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13837 = + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13911 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13920 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13928 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3362__ETC___d13796 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13836 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13859 = + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13887 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13927 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13950 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13658 || + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13738 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13866 = + !coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13957 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13658 || + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13738 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13913 = + coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14004 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13454 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13912 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13924 = + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13514 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14003 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14015 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13454 || - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13923 ; - assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14075 = + fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13514 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14014 ; + assign fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14169 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || checkForException___d13069[4] || - !rob$enqPort_0_canEnq || - fetchStage$pipelines_0_first[194:192] != 3'd0 && - fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 ; - assign fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13454 = + !rob$enqPort_0_canEnq ; + assign fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13514 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -28148,10 +28323,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || fetchStage$pipelines_0_first[68] || - checkForException___d13069[4] || + checkForException_3069_BIT_4_3070_OR_csrf_fs_r_ETC___d13509 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13658 = + assign fetchStage_pipelines_0_first__2835_BITS_199_TO_ETC___d13738 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -28161,13 +28336,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072 || + fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13736 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037 = - { fetchStage$pipelines_0_first[173], - CASE_fetchStagepipelines_0_first_BITS_172_TO__ETC__q225 } ; - assign fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072 = + assign fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13736 = fetchStage$pipelines_0_first[68] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] || @@ -28184,13 +28356,13 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] || - checkForException___d13069[4] ; - assign fetchStage_pipelines_1_first__2844_BITS_194_TO_ETC___d13848 = + checkForException_3069_BIT_4_3070_OR_csrf_fs_r_ETC___d13509 ; + assign fetchStage_pipelines_1_first__2844_BITS_194_TO_ETC___d13939 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13845 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13936 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13686 = + assign fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13774 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -28200,13 +28372,13 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - fetchStage_pipelines_1_first__2844_BIT_68_3503_ETC___d13681 || + fetchStage_pipelines_1_first__2844_BIT_68_3563_ETC___d13769 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13385 ; - assign fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13853 = + IF_fetchStage_RDY_pipelines_0_first__2832_AND__ETC___d13444 ; + assign fetchStage_pipelines_1_first__2844_BITS_199_TO_ETC___d13944 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -28217,15 +28389,15 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || fetchStage$pipelines_1_first[68] || - checkForException___d13626[4] || + checkForException_3686_BIT_4_3687_OR_csrf_fs_r_ETC___d13767 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13837 ; - assign fetchStage_pipelines_1_first__2844_BIT_173_353_ETC___d13605 = + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13928 ; + assign fetchStage_pipelines_1_first__2844_BIT_173_359_ETC___d13665 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 } ; - assign fetchStage_pipelines_1_first__2844_BIT_68_3503_ETC___d13681 = + assign fetchStage_pipelines_1_first__2844_BIT_68_3563_ETC___d13769 = fetchStage$pipelines_1_first[68] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] || @@ -28242,106 +28414,110 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14] || - checkForException___d13626[4] ; - assign fflags__h716900 = - NOT_rob_deqPort_0_canDeq__4759_4760_OR_rob_deq_ETC___d14951 ? - y_avValue_snd_fst__h716960 : - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14957 ; - assign fflags_csr__read__h614517 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h614528 = { 61'd0, csrf_frm_reg } ; - assign guard__h349463 = - { IF_sfdin57558_BIT_33_THEN_2_ELSE_0__q22[1], - { sfdin__h357558[32:0], 23'd0 } != 56'd0 } ; - assign guard__h358172 = - { IF_theResult___snd66171_BIT_33_THEN_2_ELSE_0__q24[1], - { _theResult___snd__h366171[32:0], 23'd0 } != 56'd0 } ; - assign guard__h367102 = - { IF_sfdin75324_BIT_33_THEN_2_ELSE_0__q32[1], - { sfdin__h375324[32:0], 23'd0 } != 56'd0 } ; - assign guard__h367700 = x__h367802 != 57'd0 ; - assign guard__h375938 = - { IF_theResult___snd83961_BIT_33_THEN_2_ELSE_0__q37[1], - { _theResult___snd__h383961[32:0], 23'd0 } != 56'd0 } ; - assign guard__h395155 = - { IF_sfdin03248_BIT_33_THEN_2_ELSE_0__q57[1], - { sfdin__h403248[32:0], 23'd0 } != 56'd0 } ; - assign guard__h403862 = - { IF_theResult___snd11861_BIT_33_THEN_2_ELSE_0__q59[1], - { _theResult___snd__h411861[32:0], 23'd0 } != 56'd0 } ; - assign guard__h412792 = - { IF_sfdin21014_BIT_33_THEN_2_ELSE_0__q67[1], - { sfdin__h421014[32:0], 23'd0 } != 56'd0 } ; - assign guard__h413390 = x__h413492 != 57'd0 ; - assign guard__h421628 = - { IF_theResult___snd29651_BIT_33_THEN_2_ELSE_0__q72[1], - { _theResult___snd__h429651[32:0], 23'd0 } != 56'd0 } ; - assign guard__h440843 = - { IF_sfdin48936_BIT_33_THEN_2_ELSE_0__q92[1], - { sfdin__h448936[32:0], 23'd0 } != 56'd0 } ; - assign guard__h449550 = - { IF_theResult___snd57549_BIT_33_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h457549[32:0], 23'd0 } != 56'd0 } ; - assign guard__h458480 = - { IF_sfdin66702_BIT_33_THEN_2_ELSE_0__q102[1], - { sfdin__h466702[32:0], 23'd0 } != 56'd0 } ; - assign guard__h459078 = x__h459180 != 57'd0 ; - assign guard__h467316 = - { IF_theResult___snd75339_BIT_33_THEN_2_ELSE_0__q107[1], - { _theResult___snd__h475339[32:0], 23'd0 } != 56'd0 } ; - assign guard__h497599 = - { IF_theResult___snd05511_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h505511[3:0], 52'd0 } != 56'd0 } ; - assign guard__h506911 = - { IF_sfdin15131_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h515131[3:0], 52'd0 } != 56'd0 } ; - assign guard__h507509 = x__h507609 != 57'd0 ; - assign guard__h515980 = - { IF_theResult___snd23916_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h523916[3:0], 52'd0 } != 56'd0 } ; - assign guard__h536400 = - { IF_theResult___snd44312_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h544312[3:0], 52'd0 } != 56'd0 } ; - assign guard__h545712 = - { IF_sfdin53932_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h553932[3:0], 52'd0 } != 56'd0 } ; - assign guard__h546310 = x__h546410 != 57'd0 ; - assign guard__h554781 = - { IF_theResult___snd62717_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h562717[3:0], 52'd0 } != 56'd0 } ; - assign guard__h575601 = - { IF_theResult___snd83513_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h583513[3:0], 52'd0 } != 56'd0 } ; - assign guard__h584913 = - { IF_sfdin93133_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h593133[3:0], 52'd0 } != 56'd0 } ; - assign guard__h585511 = x__h585611 != 57'd0 ; - assign guard__h593982 = - { IF_theResult___snd01918_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h601918[3:0], 52'd0 } != 56'd0 } ; - assign idx__h684592 = + checkForException_3686_BIT_4_3687_OR_csrf_fs_r_ETC___d13767 ; + assign fflags__h719060 = + NOT_rob_deqPort_0_canDeq__4852_4853_OR_rob_deq_ETC___d15044 ? + y_avValue_snd_fst__h719120 : + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15050 ; + assign fflags_csr__read__h614516 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h614527 = { 61'd0, csrf_frm_reg } ; + assign guard__h349462 = + { IF_sfdin57557_BIT_33_THEN_2_ELSE_0__q22[1], + { sfdin__h357557[32:0], 23'd0 } != 56'd0 } ; + assign guard__h358171 = + { IF_theResult___snd66170_BIT_33_THEN_2_ELSE_0__q24[1], + { _theResult___snd__h366170[32:0], 23'd0 } != 56'd0 } ; + assign guard__h367101 = + { IF_sfdin75323_BIT_33_THEN_2_ELSE_0__q32[1], + { sfdin__h375323[32:0], 23'd0 } != 56'd0 } ; + assign guard__h367699 = x__h367801 != 57'd0 ; + assign guard__h375937 = + { IF_theResult___snd83960_BIT_33_THEN_2_ELSE_0__q37[1], + { _theResult___snd__h383960[32:0], 23'd0 } != 56'd0 } ; + assign guard__h395154 = + { IF_sfdin03247_BIT_33_THEN_2_ELSE_0__q57[1], + { sfdin__h403247[32:0], 23'd0 } != 56'd0 } ; + assign guard__h403861 = + { IF_theResult___snd11860_BIT_33_THEN_2_ELSE_0__q59[1], + { _theResult___snd__h411860[32:0], 23'd0 } != 56'd0 } ; + assign guard__h412791 = + { IF_sfdin21013_BIT_33_THEN_2_ELSE_0__q67[1], + { sfdin__h421013[32:0], 23'd0 } != 56'd0 } ; + assign guard__h413389 = x__h413491 != 57'd0 ; + assign guard__h421627 = + { IF_theResult___snd29650_BIT_33_THEN_2_ELSE_0__q72[1], + { _theResult___snd__h429650[32:0], 23'd0 } != 56'd0 } ; + assign guard__h440842 = + { IF_sfdin48935_BIT_33_THEN_2_ELSE_0__q92[1], + { sfdin__h448935[32:0], 23'd0 } != 56'd0 } ; + assign guard__h449549 = + { IF_theResult___snd57548_BIT_33_THEN_2_ELSE_0__q94[1], + { _theResult___snd__h457548[32:0], 23'd0 } != 56'd0 } ; + assign guard__h458479 = + { IF_sfdin66701_BIT_33_THEN_2_ELSE_0__q102[1], + { sfdin__h466701[32:0], 23'd0 } != 56'd0 } ; + assign guard__h459077 = x__h459179 != 57'd0 ; + assign guard__h467315 = + { IF_theResult___snd75338_BIT_33_THEN_2_ELSE_0__q107[1], + { _theResult___snd__h475338[32:0], 23'd0 } != 56'd0 } ; + assign guard__h497598 = + { IF_theResult___snd05510_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h505510[3:0], 52'd0 } != 56'd0 } ; + assign guard__h506910 = + { IF_sfdin15130_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h515130[3:0], 52'd0 } != 56'd0 } ; + assign guard__h507508 = x__h507608 != 57'd0 ; + assign guard__h515979 = + { IF_theResult___snd23915_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h523915[3:0], 52'd0 } != 56'd0 } ; + assign guard__h536399 = + { IF_theResult___snd44311_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h544311[3:0], 52'd0 } != 56'd0 } ; + assign guard__h545711 = + { IF_sfdin53931_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h553931[3:0], 52'd0 } != 56'd0 } ; + assign guard__h546309 = x__h546409 != 57'd0 ; + assign guard__h554780 = + { IF_theResult___snd62716_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h562716[3:0], 52'd0 } != 56'd0 } ; + assign guard__h575600 = + { IF_theResult___snd83512_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h583512[3:0], 52'd0 } != 56'd0 } ; + assign guard__h584912 = + { IF_sfdin93132_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h593132[3:0], 52'd0 } != 56'd0 } ; + assign guard__h585510 = x__h585610 != 57'd0 ; + assign guard__h593981 = + { IF_theResult___snd01917_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h601917[3:0], 52'd0 } != 56'd0 } ; + assign idx__h686610 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13647 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13725 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13665) && + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13745) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394 ; - assign k__h669941 = + !coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453 ; + assign imm__h659256 = + fetchStage$pipelines_0_first[160] ? + fetchStage$pipelines_0_first[159:128] : + 32'd0 ; + assign k__h671298 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3392__ETC___d13394 ; - assign mcause_csr__read__h616189 = - { r1__read__h618754, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h615934 = - { r1__read__h618741, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h615534 = - { r1__read__h618577, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h615629 = - { r1__read__h618594, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h615760 = - { r1__read__h618618, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h616429 = - { r1__read__h618760, csrf_software_int_pend_vec_0 } ; + !coreFix_aluExe_0_rsAlu_approximateCount__3451__ETC___d13453 ; + assign mcause_csr__read__h616188 = + { r1__read__h618755, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h615933 = + { r1__read__h618742, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h615533 = + { r1__read__h618578, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h615628 = + { r1__read__h618595, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h615759 = + { r1__read__h618619, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h616428 = + { r1__read__h618761, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28374,9 +28550,15 @@ module mkCore(CLK, !mmio_dataRespQ_deqReq_lat_0$whas && !mmio_dataRespQ_deqReq_rl) && mmio_dataRespQ_full ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13308 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13110 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && - NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13289 && + (fetchStage$pipelines_0_first[68] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d13106) && + rob$isEmpty ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13367 = + mmio_pRqQ_empty && epochManager$checkEpoch_0_check && + !fetchStage$pipelines_0_first[68] && + NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_286_ETC___d13348 && (fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -28386,9 +28568,9 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13958 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14050 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && - NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13289 && + NOT_fetchStage_pipelines_0_first__2835_BIT_68__ETC___d13433 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -28411,297 +28593,297 @@ module mkCore(CLK, !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; assign msip__h75409 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h615386 = { r1__read__h618442, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h615842 = - { r1__read__h618736, csrf_mtvec_mode_low_reg } ; - assign n___1__h200471 = + assign mstatus_csr__read__h615385 = { r1__read__h618441, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h615841 = + { r1__read__h618737, csrf_mtvec_mode_low_reg } ; + assign n___1__h200472 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h199068[63:56], + x__h199069[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h199068[55:48], + x__h199069[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h199068[47:40], + x__h199069[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h199068[39:32], + x__h199069[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h199068[31:24], + x__h199069[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h199068[23:16], + x__h199069[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h199068[15:8], + x__h199069[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h199068[7:0] } ; + x__h199069[7:0] } ; assign n__read__h6134 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h616533 = + assign n__read__h616532 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h616724 = + assign n__read__h616723 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h713751 = + assign n__read__h715911 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h300172 = + assign next_deqP___1__h300173 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h308168 = + assign next_deqP___1__h308169 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h314449 = + assign next_deqP___1__h314450 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h322303 = + assign next_deqP___1__h322304 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h332360 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h335585 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h712992 = + assign next_deqP___1__h332361 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h335586 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h715152 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : - rob_deqPort_0_deq_data__4241_BITS_282_TO_219_4_ETC___d14727 ; - assign out___1_sfd__h486262 = + rob_deqPort_0_deq_data__4334_BITS_282_TO_219_4_ETC___d14820 ; + assign out___1_sfd__h486261 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ; - assign out___1_sfd__h525204 = + assign out___1_sfd__h525203 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ; - assign out___1_sfd__h564405 = + assign out___1_sfd__h564404 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ; - assign out_exp__h358083 = - sfdin__h357558[34] ? - _theResult___exp__h358080 : - _theResult___fst_exp__h357564 ; - assign out_exp__h366665 = - _theResult___snd__h366171[34] ? - _theResult___exp__h366662 : - _theResult___fst_exp__h366220 ; - assign out_exp__h375849 = - sfdin__h375324[34] ? - _theResult___exp__h375846 : - _theResult___fst_exp__h375330 ; - assign out_exp__h384485 = - _theResult___snd__h383961[34] ? - _theResult___exp__h384482 : - _theResult___fst_exp__h384015 ; - assign out_exp__h403773 = - sfdin__h403248[34] ? - _theResult___exp__h403770 : - _theResult___fst_exp__h403254 ; - assign out_exp__h412355 = - _theResult___snd__h411861[34] ? - _theResult___exp__h412352 : - _theResult___fst_exp__h411910 ; - assign out_exp__h421539 = - sfdin__h421014[34] ? - _theResult___exp__h421536 : - _theResult___fst_exp__h421020 ; - assign out_exp__h430175 = - _theResult___snd__h429651[34] ? - _theResult___exp__h430172 : - _theResult___fst_exp__h429705 ; - assign out_exp__h449461 = - sfdin__h448936[34] ? - _theResult___exp__h449458 : - _theResult___fst_exp__h448942 ; - assign out_exp__h458043 = - _theResult___snd__h457549[34] ? - _theResult___exp__h458040 : - _theResult___fst_exp__h457598 ; - assign out_exp__h467227 = - sfdin__h466702[34] ? - _theResult___exp__h467224 : - _theResult___fst_exp__h466708 ; - assign out_exp__h475863 = - _theResult___snd__h475339[34] ? - _theResult___exp__h475860 : - _theResult___fst_exp__h475393 ; - assign out_exp__h506218 = - _theResult___snd__h505511[5] ? - _theResult___exp__h506215 : - _theResult___fst_exp__h505560 ; - assign out_exp__h515869 = - sfdin__h515131[5] ? - _theResult___exp__h515866 : - _theResult___fst_exp__h515137 ; - assign out_exp__h524653 = - _theResult___snd__h523916[5] ? - _theResult___exp__h524650 : - _theResult___fst_exp__h523970 ; - assign out_exp__h545019 = - _theResult___snd__h544312[5] ? - _theResult___exp__h545016 : - _theResult___fst_exp__h544361 ; - assign out_exp__h554670 = - sfdin__h553932[5] ? - _theResult___exp__h554667 : - _theResult___fst_exp__h553938 ; - assign out_exp__h563454 = - _theResult___snd__h562717[5] ? - _theResult___exp__h563451 : - _theResult___fst_exp__h562771 ; - assign out_exp__h584220 = - _theResult___snd__h583513[5] ? - _theResult___exp__h584217 : - _theResult___fst_exp__h583562 ; - assign out_exp__h593871 = - sfdin__h593133[5] ? - _theResult___exp__h593868 : - _theResult___fst_exp__h593139 ; - assign out_exp__h602655 = - _theResult___snd__h601918[5] ? - _theResult___exp__h602652 : - _theResult___fst_exp__h601972 ; - assign out_f_exp__h384861 = - (_theResult___exp__h384584 == 8'd255 && - _theResult___sfd__h384585 != 23'd0 || + assign out_exp__h358082 = + sfdin__h357557[34] ? + _theResult___exp__h358079 : + _theResult___fst_exp__h357563 ; + assign out_exp__h366664 = + _theResult___snd__h366170[34] ? + _theResult___exp__h366661 : + _theResult___fst_exp__h366219 ; + assign out_exp__h375848 = + sfdin__h375323[34] ? + _theResult___exp__h375845 : + _theResult___fst_exp__h375329 ; + assign out_exp__h384484 = + _theResult___snd__h383960[34] ? + _theResult___exp__h384481 : + _theResult___fst_exp__h384014 ; + assign out_exp__h403772 = + sfdin__h403247[34] ? + _theResult___exp__h403769 : + _theResult___fst_exp__h403253 ; + assign out_exp__h412354 = + _theResult___snd__h411860[34] ? + _theResult___exp__h412351 : + _theResult___fst_exp__h411909 ; + assign out_exp__h421538 = + sfdin__h421013[34] ? + _theResult___exp__h421535 : + _theResult___fst_exp__h421019 ; + assign out_exp__h430174 = + _theResult___snd__h429650[34] ? + _theResult___exp__h430171 : + _theResult___fst_exp__h429704 ; + assign out_exp__h449460 = + sfdin__h448935[34] ? + _theResult___exp__h449457 : + _theResult___fst_exp__h448941 ; + assign out_exp__h458042 = + _theResult___snd__h457548[34] ? + _theResult___exp__h458039 : + _theResult___fst_exp__h457597 ; + assign out_exp__h467226 = + sfdin__h466701[34] ? + _theResult___exp__h467223 : + _theResult___fst_exp__h466707 ; + assign out_exp__h475862 = + _theResult___snd__h475338[34] ? + _theResult___exp__h475859 : + _theResult___fst_exp__h475392 ; + assign out_exp__h506217 = + _theResult___snd__h505510[5] ? + _theResult___exp__h506214 : + _theResult___fst_exp__h505559 ; + assign out_exp__h515868 = + sfdin__h515130[5] ? + _theResult___exp__h515865 : + _theResult___fst_exp__h515136 ; + assign out_exp__h524652 = + _theResult___snd__h523915[5] ? + _theResult___exp__h524649 : + _theResult___fst_exp__h523969 ; + assign out_exp__h545018 = + _theResult___snd__h544311[5] ? + _theResult___exp__h545015 : + _theResult___fst_exp__h544360 ; + assign out_exp__h554669 = + sfdin__h553931[5] ? + _theResult___exp__h554666 : + _theResult___fst_exp__h553937 ; + assign out_exp__h563453 = + _theResult___snd__h562716[5] ? + _theResult___exp__h563450 : + _theResult___fst_exp__h562770 ; + assign out_exp__h584219 = + _theResult___snd__h583512[5] ? + _theResult___exp__h584216 : + _theResult___fst_exp__h583561 ; + assign out_exp__h593870 = + sfdin__h593132[5] ? + _theResult___exp__h593867 : + _theResult___fst_exp__h593138 ; + assign out_exp__h602654 = + _theResult___snd__h601917[5] ? + _theResult___exp__h602651 : + _theResult___fst_exp__h601971 ; + assign out_f_exp__h384860 = + (_theResult___exp__h384583 == 8'd255 && + _theResult___sfd__h384584 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h384575 ; - assign out_f_exp__h430551 = - (_theResult___exp__h430274 == 8'd255 && - _theResult___sfd__h430275 != 23'd0 || + _theResult___fst_exp__h384574 ; + assign out_f_exp__h430550 = + (_theResult___exp__h430273 == 8'd255 && + _theResult___sfd__h430274 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h430265 ; - assign out_f_exp__h476239 = - (_theResult___exp__h475962 == 8'd255 && - _theResult___sfd__h475963 != 23'd0 || + _theResult___fst_exp__h430264 ; + assign out_f_exp__h476238 = + (_theResult___exp__h475961 == 8'd255 && + _theResult___sfd__h475962 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h475953 ; - assign out_f_sfd__h384862 = - (_theResult___exp__h384584 == 8'd255 && - _theResult___sfd__h384585 != 23'd0) ? + _theResult___fst_exp__h475952 ; + assign out_f_sfd__h384861 = + (_theResult___exp__h384583 == 8'd255 && + _theResult___sfd__h384584 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h384585 ; - assign out_f_sfd__h430552 = - (_theResult___exp__h430274 == 8'd255 && - _theResult___sfd__h430275 != 23'd0) ? + _theResult___sfd__h384584 ; + assign out_f_sfd__h430551 = + (_theResult___exp__h430273 == 8'd255 && + _theResult___sfd__h430274 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h430275 ; - assign out_f_sfd__h476240 = - (_theResult___exp__h475962 == 8'd255 && - _theResult___sfd__h475963 != 23'd0) ? + _theResult___sfd__h430274 ; + assign out_f_sfd__h476239 = + (_theResult___exp__h475961 == 8'd255 && + _theResult___sfd__h475962 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h475963 ; - assign out_sfd__h358084 = - sfdin__h357558[34] ? - _theResult___sfd__h358081 : - sfdin__h357558[56:34] ; - assign out_sfd__h366666 = - _theResult___snd__h366171[34] ? - _theResult___sfd__h366663 : - _theResult___snd__h366171[56:34] ; - assign out_sfd__h375850 = - sfdin__h375324[34] ? - _theResult___sfd__h375847 : - sfdin__h375324[56:34] ; - assign out_sfd__h384486 = - _theResult___snd__h383961[34] ? - _theResult___sfd__h384483 : - _theResult___snd__h383961[56:34] ; - assign out_sfd__h403774 = - sfdin__h403248[34] ? - _theResult___sfd__h403771 : - sfdin__h403248[56:34] ; - assign out_sfd__h412356 = - _theResult___snd__h411861[34] ? - _theResult___sfd__h412353 : - _theResult___snd__h411861[56:34] ; - assign out_sfd__h421540 = - sfdin__h421014[34] ? - _theResult___sfd__h421537 : - sfdin__h421014[56:34] ; - assign out_sfd__h430176 = - _theResult___snd__h429651[34] ? - _theResult___sfd__h430173 : - _theResult___snd__h429651[56:34] ; - assign out_sfd__h449462 = - sfdin__h448936[34] ? - _theResult___sfd__h449459 : - sfdin__h448936[56:34] ; - assign out_sfd__h458044 = - _theResult___snd__h457549[34] ? - _theResult___sfd__h458041 : - _theResult___snd__h457549[56:34] ; - assign out_sfd__h467228 = - sfdin__h466702[34] ? - _theResult___sfd__h467225 : - sfdin__h466702[56:34] ; - assign out_sfd__h475864 = - _theResult___snd__h475339[34] ? - _theResult___sfd__h475861 : - _theResult___snd__h475339[56:34] ; - assign out_sfd__h506219 = - _theResult___snd__h505511[5] ? - _theResult___sfd__h506216 : - _theResult___snd__h505511[56:5] ; - assign out_sfd__h515870 = - sfdin__h515131[5] ? - _theResult___sfd__h515867 : - sfdin__h515131[56:5] ; - assign out_sfd__h524654 = - _theResult___snd__h523916[5] ? - _theResult___sfd__h524651 : - _theResult___snd__h523916[56:5] ; - assign out_sfd__h545020 = - _theResult___snd__h544312[5] ? - _theResult___sfd__h545017 : - _theResult___snd__h544312[56:5] ; - assign out_sfd__h554671 = - sfdin__h553932[5] ? - _theResult___sfd__h554668 : - sfdin__h553932[56:5] ; - assign out_sfd__h563455 = - _theResult___snd__h562717[5] ? - _theResult___sfd__h563452 : - _theResult___snd__h562717[56:5] ; - assign out_sfd__h584221 = - _theResult___snd__h583513[5] ? - _theResult___sfd__h584218 : - _theResult___snd__h583513[56:5] ; - assign out_sfd__h593872 = - sfdin__h593133[5] ? - _theResult___sfd__h593869 : - sfdin__h593133[56:5] ; - assign out_sfd__h602656 = - _theResult___snd__h601918[5] ? - _theResult___sfd__h602653 : - _theResult___snd__h601918[56:5] ; - assign pend_ints__h655193 = + _theResult___sfd__h475962 ; + assign out_sfd__h358083 = + sfdin__h357557[34] ? + _theResult___sfd__h358080 : + sfdin__h357557[56:34] ; + assign out_sfd__h366665 = + _theResult___snd__h366170[34] ? + _theResult___sfd__h366662 : + _theResult___snd__h366170[56:34] ; + assign out_sfd__h375849 = + sfdin__h375323[34] ? + _theResult___sfd__h375846 : + sfdin__h375323[56:34] ; + assign out_sfd__h384485 = + _theResult___snd__h383960[34] ? + _theResult___sfd__h384482 : + _theResult___snd__h383960[56:34] ; + assign out_sfd__h403773 = + sfdin__h403247[34] ? + _theResult___sfd__h403770 : + sfdin__h403247[56:34] ; + assign out_sfd__h412355 = + _theResult___snd__h411860[34] ? + _theResult___sfd__h412352 : + _theResult___snd__h411860[56:34] ; + assign out_sfd__h421539 = + sfdin__h421013[34] ? + _theResult___sfd__h421536 : + sfdin__h421013[56:34] ; + assign out_sfd__h430175 = + _theResult___snd__h429650[34] ? + _theResult___sfd__h430172 : + _theResult___snd__h429650[56:34] ; + assign out_sfd__h449461 = + sfdin__h448935[34] ? + _theResult___sfd__h449458 : + sfdin__h448935[56:34] ; + assign out_sfd__h458043 = + _theResult___snd__h457548[34] ? + _theResult___sfd__h458040 : + _theResult___snd__h457548[56:34] ; + assign out_sfd__h467227 = + sfdin__h466701[34] ? + _theResult___sfd__h467224 : + sfdin__h466701[56:34] ; + assign out_sfd__h475863 = + _theResult___snd__h475338[34] ? + _theResult___sfd__h475860 : + _theResult___snd__h475338[56:34] ; + assign out_sfd__h506218 = + _theResult___snd__h505510[5] ? + _theResult___sfd__h506215 : + _theResult___snd__h505510[56:5] ; + assign out_sfd__h515869 = + sfdin__h515130[5] ? + _theResult___sfd__h515866 : + sfdin__h515130[56:5] ; + assign out_sfd__h524653 = + _theResult___snd__h523915[5] ? + _theResult___sfd__h524650 : + _theResult___snd__h523915[56:5] ; + assign out_sfd__h545019 = + _theResult___snd__h544311[5] ? + _theResult___sfd__h545016 : + _theResult___snd__h544311[56:5] ; + assign out_sfd__h554670 = + sfdin__h553931[5] ? + _theResult___sfd__h554667 : + sfdin__h553931[56:5] ; + assign out_sfd__h563454 = + _theResult___snd__h562716[5] ? + _theResult___sfd__h563451 : + _theResult___snd__h562716[56:5] ; + assign out_sfd__h584220 = + _theResult___snd__h583512[5] ? + _theResult___sfd__h584217 : + _theResult___snd__h583512[56:5] ; + assign out_sfd__h593871 = + sfdin__h593132[5] ? + _theResult___sfd__h593868 : + sfdin__h593132[56:5] ; + assign out_sfd__h602655 = + _theResult___snd__h601917[5] ? + _theResult___sfd__h602652 : + _theResult___snd__h601917[56:5] ; + assign pend_ints__h655198 = { csrf_debug_int_pend_read__1844_CONCAT_0b0_2867_ETC___d12877, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h718414 = csrf_prv_reg ; - assign prv__h718458 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h479478 = + assign prv__h720574 = csrf_prv_reg ; + assign prv__h720618 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h479477 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign q__h607919 = + assign q__h607918 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] / coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ; - assign r1__read_BITS_12_TO_0___h655715 = + assign r1__read_BITS_12_TO_0___h655720 = { 3'd0, csrf_mideleg_11_reg, 1'b0, @@ -28709,178 +28891,179 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read__h617231 = { r1__read__h617233, csrf_ie_vec_1 } ; - assign r1__read__h617233 = { r1__read__h617235, 2'b0 } ; - assign r1__read__h617235 = { r1__read__h617237, csrf_prev_ie_vec_0 } ; - assign r1__read__h617237 = { r1__read__h617239, csrf_prev_ie_vec_1 } ; - assign r1__read__h617239 = { r1__read__h617241, 2'b0 } ; - assign r1__read__h617241 = { r1__read__h617243, csrf_spp_reg } ; - assign r1__read__h617243 = { r1__read__h617245, 4'b0 } ; - assign r1__read__h617245 = { r1__read__h617247, csrf_fs_reg } ; - assign r1__read__h617247 = { r1__read__h617249, 2'd0 } ; - assign r1__read__h617249 = { r1__read__h617251, 1'b0 } ; - assign r1__read__h617251 = { r1__read__h617253, csrf_sum_reg } ; - assign r1__read__h617253 = { r1__read__h617255, csrf_mxr_reg } ; - assign r1__read__h617255 = { r1__read__h617257, 12'b0 } ; - assign r1__read__h617257 = { r1__read__h617259, 2'b10 } ; - assign r1__read__h617259 = { r__h617263, 29'b0 } ; - assign r1__read__h617635 = - { r1__read__h617637, csrf_software_int_en_vec_1 } ; - assign r1__read__h617637 = { r1__read__h617639, 2'b0 } ; - assign r1__read__h617639 = { r1__read__h617641, csrf_timer_int_en_vec_0 } ; - assign r1__read__h617641 = { r1__read__h617643, csrf_timer_int_en_vec_1 } ; - assign r1__read__h617643 = { r1__read__h617645, 2'b0 } ; - assign r1__read__h617645 = - { r1__read__h617647, csrf_external_int_en_vec_0 } ; - assign r1__read__h617647 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h618165 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h618170 = { r1__read__h618172, csrf_scounteren_tm_reg } ; - assign r1__read__h618172 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h618183 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h618189 = - { r1__read__h618191, csrf_software_int_pend_vec_1 } ; - assign r1__read__h618191 = { r1__read__h618193, 2'b0 } ; - assign r1__read__h618193 = - { r1__read__h618195, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h618195 = - { r1__read__h618197, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h618197 = { r1__read__h618199, 2'b0 } ; - assign r1__read__h618199 = - { r1__read__h618201, csrf_external_int_pend_vec_0 } ; - assign r1__read__h618201 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h618419 = { vm_mode_reg__read__h618425, 16'd0 } ; - assign r1__read__h618442 = { r1__read__h618444, csrf_ie_vec_1 } ; - assign r1__read__h618444 = { r1__read__h618446, 1'b0 } ; - assign r1__read__h618446 = { r1__read__h618448, csrf_ie_vec_3 } ; - assign r1__read__h618448 = { r1__read__h618450, csrf_prev_ie_vec_0 } ; - assign r1__read__h618450 = { r1__read__h618452, csrf_prev_ie_vec_1 } ; - assign r1__read__h618452 = { r1__read__h618454, 1'b0 } ; - assign r1__read__h618454 = { r1__read__h618456, csrf_prev_ie_vec_3 } ; - assign r1__read__h618456 = { r1__read__h618458, csrf_spp_reg } ; - assign r1__read__h618458 = { r1__read__h618460, 2'b0 } ; - assign r1__read__h618460 = { r1__read__h618462, csrf_mpp_reg } ; - assign r1__read__h618462 = { r1__read__h618464, csrf_fs_reg } ; - assign r1__read__h618464 = { r1__read__h618466, 2'd0 } ; - assign r1__read__h618466 = { r1__read__h618468, csrf_mprv_reg } ; - assign r1__read__h618468 = { r1__read__h618470, csrf_sum_reg } ; - assign r1__read__h618470 = { r1__read__h618472, csrf_mxr_reg } ; - assign r1__read__h618472 = { r1__read__h618474, csrf_tvm_reg } ; - assign r1__read__h618474 = { r1__read__h618476, csrf_tw_reg } ; - assign r1__read__h618476 = { r1__read__h618478, csrf_tsr_reg } ; - assign r1__read__h618478 = { r1__read__h618480, 9'b0 } ; - assign r1__read__h618480 = { r1__read__h618482, 2'b10 } ; - assign r1__read__h618482 = { r1__read__h618484, 2'b10 } ; - assign r1__read__h618484 = { r__h617263, 27'b0 } ; - assign r1__read__h618577 = { r1__read__h618579, 1'b0 } ; - assign r1__read__h618579 = { r1__read__h618581, csrf_medeleg_13_11_reg } ; - assign r1__read__h618581 = { r1__read__h618583, 1'b0 } ; - assign r1__read__h618583 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h618594 = { r1__read__h618596, 1'b0 } ; - assign r1__read__h618596 = { r1__read__h618598, csrf_mideleg_5_3_reg } ; - assign r1__read__h618598 = { r1__read__h618600, 1'b0 } ; - assign r1__read__h618600 = { r1__read__h618602, csrf_mideleg_9_7_reg } ; - assign r1__read__h618602 = { r1__read__h618604, 1'b0 } ; - assign r1__read__h618604 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h618618 = - { r1__read__h618620, csrf_software_int_en_vec_1 } ; - assign r1__read__h618620 = { r1__read__h618622, 1'b0 } ; - assign r1__read__h618622 = - { r1__read__h618624, csrf_software_int_en_vec_3 } ; - assign r1__read__h618624 = { r1__read__h618626, csrf_timer_int_en_vec_0 } ; - assign r1__read__h618626 = { r1__read__h618628, csrf_timer_int_en_vec_1 } ; - assign r1__read__h618628 = { r1__read__h618630, 1'b0 } ; - assign r1__read__h618630 = { r1__read__h618632, csrf_timer_int_en_vec_3 } ; - assign r1__read__h618632 = - { r1__read__h618634, csrf_external_int_en_vec_0 } ; - assign r1__read__h618634 = - { r1__read__h618636, csrf_external_int_en_vec_1 } ; - assign r1__read__h618636 = { r1__read__h618638, 1'b0 } ; - assign r1__read__h618638 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h618736 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h618741 = { r1__read__h618743, csrf_mcounteren_tm_reg } ; - assign r1__read__h618743 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h618754 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h618760 = - { r1__read__h618762, csrf_software_int_pend_vec_1 } ; - assign r1__read__h618762 = { r1__read__h618764, 1'b0 } ; - assign r1__read__h618764 = - { r1__read__h618766, csrf_software_int_pend_vec_3 } ; - assign r1__read__h618766 = - { r1__read__h618768, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h618768 = - { r1__read__h618770, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h618770 = { r1__read__h618772, 1'b0 } ; - assign r1__read__h618772 = - { r1__read__h618774, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h618774 = - { r1__read__h618776, csrf_external_int_pend_vec_0 } ; - assign r1__read__h618776 = - { r1__read__h618778, csrf_external_int_pend_vec_1 } ; - assign r1__read__h618778 = { r1__read__h618780, 1'b0 } ; - assign r1__read__h618780 = - { r1__read__h618782, csrf_external_int_pend_vec_3 } ; - assign r1__read__h618782 = { r1__read__h618784, 2'b0 } ; - assign r1__read__h618784 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h485840 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h485841 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h479505 = + assign r1__read_BITS_13_TO_12___h659124 = csrf_fs_reg ; + assign r1__read__h617230 = { r1__read__h617232, csrf_ie_vec_1 } ; + assign r1__read__h617232 = { r1__read__h617234, 2'b0 } ; + assign r1__read__h617234 = { r1__read__h617236, csrf_prev_ie_vec_0 } ; + assign r1__read__h617236 = { r1__read__h617238, csrf_prev_ie_vec_1 } ; + assign r1__read__h617238 = { r1__read__h617240, 2'b0 } ; + assign r1__read__h617240 = { r1__read__h617242, csrf_spp_reg } ; + assign r1__read__h617242 = { r1__read__h617244, 4'b0 } ; + assign r1__read__h617244 = { r1__read__h617246, csrf_fs_reg } ; + assign r1__read__h617246 = { r1__read__h617248, 2'd0 } ; + assign r1__read__h617248 = { r1__read__h617250, 1'b0 } ; + assign r1__read__h617250 = { r1__read__h617252, csrf_sum_reg } ; + assign r1__read__h617252 = { r1__read__h617254, csrf_mxr_reg } ; + assign r1__read__h617254 = { r1__read__h617256, 12'b0 } ; + assign r1__read__h617256 = { r1__read__h617258, 2'b10 } ; + assign r1__read__h617258 = { r__h617262, 29'b0 } ; + assign r1__read__h617634 = + { r1__read__h617636, csrf_software_int_en_vec_1 } ; + assign r1__read__h617636 = { r1__read__h617638, 2'b0 } ; + assign r1__read__h617638 = { r1__read__h617640, csrf_timer_int_en_vec_0 } ; + assign r1__read__h617640 = { r1__read__h617642, csrf_timer_int_en_vec_1 } ; + assign r1__read__h617642 = { r1__read__h617644, 2'b0 } ; + assign r1__read__h617644 = + { r1__read__h617646, csrf_external_int_en_vec_0 } ; + assign r1__read__h617646 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h618164 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h618169 = { r1__read__h618171, csrf_scounteren_tm_reg } ; + assign r1__read__h618171 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h618182 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h618188 = + { r1__read__h618190, csrf_software_int_pend_vec_1 } ; + assign r1__read__h618190 = { r1__read__h618192, 2'b0 } ; + assign r1__read__h618192 = + { r1__read__h618194, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h618194 = + { r1__read__h618196, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h618196 = { r1__read__h618198, 2'b0 } ; + assign r1__read__h618198 = + { r1__read__h618200, csrf_external_int_pend_vec_0 } ; + assign r1__read__h618200 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h618418 = { vm_mode_reg__read__h618424, 16'd0 } ; + assign r1__read__h618441 = { r1__read__h618443, csrf_ie_vec_1 } ; + assign r1__read__h618443 = { r1__read__h618445, 1'b0 } ; + assign r1__read__h618445 = { r1__read__h618447, csrf_ie_vec_3 } ; + assign r1__read__h618447 = { r1__read__h618449, csrf_prev_ie_vec_0 } ; + assign r1__read__h618449 = { r1__read__h618451, csrf_prev_ie_vec_1 } ; + assign r1__read__h618451 = { r1__read__h618453, 1'b0 } ; + assign r1__read__h618453 = { r1__read__h618455, csrf_prev_ie_vec_3 } ; + assign r1__read__h618455 = { r1__read__h618457, csrf_spp_reg } ; + assign r1__read__h618457 = { r1__read__h618459, 2'b0 } ; + assign r1__read__h618459 = { r1__read__h618461, csrf_mpp_reg } ; + assign r1__read__h618461 = { r1__read__h618463, csrf_fs_reg } ; + assign r1__read__h618463 = { r1__read__h618465, 2'd0 } ; + assign r1__read__h618465 = { r1__read__h618467, csrf_mprv_reg } ; + assign r1__read__h618467 = { r1__read__h618469, csrf_sum_reg } ; + assign r1__read__h618469 = { r1__read__h618471, csrf_mxr_reg } ; + assign r1__read__h618471 = { r1__read__h618473, csrf_tvm_reg } ; + assign r1__read__h618473 = { r1__read__h618475, csrf_tw_reg } ; + assign r1__read__h618475 = { r1__read__h618477, csrf_tsr_reg } ; + assign r1__read__h618477 = { r1__read__h618479, 9'b0 } ; + assign r1__read__h618479 = { r1__read__h618481, 2'b10 } ; + assign r1__read__h618481 = { r1__read__h618483, 2'b10 } ; + assign r1__read__h618483 = { r__h617262, 27'b0 } ; + assign r1__read__h618578 = { r1__read__h618580, 1'b0 } ; + assign r1__read__h618580 = { r1__read__h618582, csrf_medeleg_13_11_reg } ; + assign r1__read__h618582 = { r1__read__h618584, 1'b0 } ; + assign r1__read__h618584 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h618595 = { r1__read__h618597, 1'b0 } ; + assign r1__read__h618597 = { r1__read__h618599, csrf_mideleg_5_3_reg } ; + assign r1__read__h618599 = { r1__read__h618601, 1'b0 } ; + assign r1__read__h618601 = { r1__read__h618603, csrf_mideleg_9_7_reg } ; + assign r1__read__h618603 = { r1__read__h618605, 1'b0 } ; + assign r1__read__h618605 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h618619 = + { r1__read__h618621, csrf_software_int_en_vec_1 } ; + assign r1__read__h618621 = { r1__read__h618623, 1'b0 } ; + assign r1__read__h618623 = + { r1__read__h618625, csrf_software_int_en_vec_3 } ; + assign r1__read__h618625 = { r1__read__h618627, csrf_timer_int_en_vec_0 } ; + assign r1__read__h618627 = { r1__read__h618629, csrf_timer_int_en_vec_1 } ; + assign r1__read__h618629 = { r1__read__h618631, 1'b0 } ; + assign r1__read__h618631 = { r1__read__h618633, csrf_timer_int_en_vec_3 } ; + assign r1__read__h618633 = + { r1__read__h618635, csrf_external_int_en_vec_0 } ; + assign r1__read__h618635 = + { r1__read__h618637, csrf_external_int_en_vec_1 } ; + assign r1__read__h618637 = { r1__read__h618639, 1'b0 } ; + assign r1__read__h618639 = { 52'd4, csrf_external_int_en_vec_3 } ; + assign r1__read__h618737 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h618742 = { r1__read__h618744, csrf_mcounteren_tm_reg } ; + assign r1__read__h618744 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h618755 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h618761 = + { r1__read__h618763, csrf_software_int_pend_vec_1 } ; + assign r1__read__h618763 = { r1__read__h618765, 1'b0 } ; + assign r1__read__h618765 = + { r1__read__h618767, csrf_software_int_pend_vec_3 } ; + assign r1__read__h618767 = + { r1__read__h618769, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h618769 = + { r1__read__h618771, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h618771 = { r1__read__h618773, 1'b0 } ; + assign r1__read__h618773 = + { r1__read__h618775, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h618775 = + { r1__read__h618777, csrf_external_int_pend_vec_0 } ; + assign r1__read__h618777 = + { r1__read__h618779, csrf_external_int_pend_vec_1 } ; + assign r1__read__h618779 = { r1__read__h618781, 1'b0 } ; + assign r1__read__h618781 = + { r1__read__h618783, csrf_external_int_pend_vec_3 } ; + assign r1__read__h618783 = { r1__read__h618785, 2'b0 } ; + assign r1__read__h618785 = { 49'b0, csrf_debug_int_pend } ; + assign rVal1__h485839 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h485840 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h479504 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h607920 = + assign r__h607919 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] % coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ; - assign r__h617263 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3276__ETC___d13816 = + assign r__h617262 = csrf_fs_reg == 2'b11 ; + assign regRenamingTable_RDY_rename_0_getRename__3311__ETC___d13907 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__3872__ETC___d13890 = + assign regRenamingTable_RDY_rename_1_getRename__3963__ETC___d13981 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13875) && - _0_OR_NOT_fetchStage_pipelines_1_first__2844_BI_ETC___d13888 ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13442 = + NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d13966) && + _0_OR_NOT_fetchStage_pipelines_1_first__2844_BI_ETC___d13979 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13501 = regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13697 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13785 = regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13709 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13797 = regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13427 && + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13486 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 || + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13845 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13936 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13843 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13934 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13976 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14068 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13989 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14081 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d13985 ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13994 = + NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d14077 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14086 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && @@ -28888,103 +29071,103 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d13999 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14091 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d14019 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14111 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && - NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d13985 ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d14023 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && + NOT_fetchStage_pipelines_0_first__2835_BITS_32_ETC___d14077 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14115 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d14029 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14121 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && (fetchStage$pipelines_0_first[199:195] != 5'd14) != fetchStage$pipelines_0_first[160] ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d14033 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14125 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d14041 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3362_AND__ETC___d14215 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14308 = regRenamingTable$rename_0_canRename && !checkForException___d13069[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 ; - assign regRenamingTable_rename_1_canRename__3475_AND__ETC___d14136 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 ; + assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14231 = regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14132 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14227 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_1_canRename__3475_AND__ETC___d14151 = + assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14246 = regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14132 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14227 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14147 ; - assign regRenamingTable_rename_1_canRename__3475_AND__ETC___d14176 = + NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14242 ; + assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14271 = regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 && - NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14147 ; - assign regRenamingTable_rename_1_canRename__3475_AND__ETC___d14180 = + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 && + NOT_fetchStage_pipelines_1_first__2844_BITS_32_ETC___d14242 ; + assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14275 = regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 && fetchStage$pipelines_1_first[173] ; - assign regRenamingTable_rename_1_canRename__3475_AND__ETC___d14186 = + assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14281 = regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14091 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d14186 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14160 && + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14255 && (fetchStage$pipelines_1_first[199:195] != 5'd14) != fetchStage$pipelines_1_first[160] ; - assign renaming_spec_bits__h684461 = + assign renaming_spec_bits__h686479 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h681922 : + y_avValue_snd_fst__h683274 : specTagManager$currentSpecBits ; - assign res_data__h341240 = { 32'd0, x__h341252 } ; - assign res_data__h341245 = + assign res_data__h341239 = { 32'd0, x__h341251 } ; + assign res_data__h341244 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28997,8 +29180,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h386935 = { 32'd0, x__h386947 } ; - assign res_data__h386940 = + assign res_data__h386934 = { 32'd0, x__h386946 } ; + assign res_data__h386939 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -29011,8 +29194,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h432623 = { 32'd0, x__h432635 } ; - assign res_data__h432628 = + assign res_data__h432622 = { 32'd0, x__h432634 } ; + assign res_data__h432627 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -29025,7 +29208,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h341241 = + assign res_fflags__h341240 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -29093,7 +29276,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351 } ; - assign res_fflags__h386936 = + assign res_fflags__h386935 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -29161,7 +29344,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743 } ; - assign res_fflags__h432624 = + assign res_fflags__h432623 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -29229,338 +29412,343 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135 } ; - assign resp_addr__h295349 = + assign resp_addr__h295350 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h367705 = + assign result__h367704 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[0] | - guard__h367700 } ; - assign result__h413395 = + guard__h367699 } ; + assign result__h413394 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[0] | - guard__h413390 } ; - assign result__h459083 = + guard__h413389 } ; + assign result__h459082 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[0] | - guard__h459078 } ; - assign result__h507514 = + guard__h459077 } ; + assign result__h507513 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8759[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8759[0] | - guard__h507509 } ; - assign result__h546315 = + guard__h507508 } ; + assign result__h546314 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10232[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10232[0] | - guard__h546310 } ; - assign result__h585516 = + guard__h546309 } ; + assign result__h585515 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9469[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9469[0] | - guard__h585511 } ; + guard__h585510 } ; assign result__h650909 = w__h650904 & y__h650938 ; assign result__h650960 = ~x__h650959 ; - assign rob_RDY_enqPort_1_enq__3936_AND_NOT_fetchStage_ETC___d13944 = + assign rob_RDY_enqPort_1_enq__4027_AND_NOT_fetchStage_ETC___d14035 = rob$RDY_enqPort_1_enq && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3360_3441_OR_NOT__ETC___d13940) && + NOT_specTagManager_canClaim__3416_3500_OR_NOT__ETC___d14031) && (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign rob_deqPort_0_deq_data__4241_BITS_282_TO_219_4_ETC___d14727 = + assign rob_deqPort_0_deq_data__4334_BITS_282_TO_219_4_ETC___d14820 = rob$deqPort_0_deq_data[282:219] + 64'd4 ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q262 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h615243 = { r1__read__h618419, csrf_ppn_reg } ; - assign sbIdx__h158171 = + assign rs1__h659255 = + (fetchStage$pipelines_0_first[88] && + !fetchStage$pipelines_0_first[87]) ? + fetchStage$pipelines_0_first[86:82] : + 5'd0 ; + assign satp_csr__read__h615242 = { r1__read__h618418, csrf_ppn_reg } ; + assign sbIdx__h158170 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h615041 = - { r1__read__h618183, csrf_scause_code_reg } ; - assign scounteren_csr__read__h614903 = - { r1__read__h618170, csrf_scounteren_cy_reg } ; - assign sfd__h341848 = { value__h350075, 3'd0 } ; - assign sfd__h357656 = + assign scause_csr__read__h615040 = + { r1__read__h618182, csrf_scause_code_reg } ; + assign scounteren_csr__read__h614902 = + { r1__read__h618169, csrf_scounteren_cy_reg } ; + assign sfd__h341847 = { value__h350074, 3'd0 } ; + assign sfd__h357655 = { 1'b0, - _theResult___fst_exp__h357564 != 8'd0, - sfdin__h357558[56:34] } + + _theResult___fst_exp__h357563 != 8'd0, + sfdin__h357557[56:34] } + 25'd1 ; - assign sfd__h366238 = + assign sfd__h366237 = { 1'b0, - _theResult___fst_exp__h366220 != 8'd0, - _theResult___snd__h366171[56:34] } + + _theResult___fst_exp__h366219 != 8'd0, + _theResult___snd__h366170[56:34] } + 25'd1 ; - assign sfd__h375422 = + assign sfd__h375421 = { 1'b0, - _theResult___fst_exp__h375330 != 8'd0, - sfdin__h375324[56:34] } + + _theResult___fst_exp__h375329 != 8'd0, + sfdin__h375323[56:34] } + 25'd1 ; - assign sfd__h384034 = + assign sfd__h384033 = { 1'b0, - _theResult___fst_exp__h384015 != 8'd0, - _theResult___snd__h383961[56:34] } + + _theResult___fst_exp__h384014 != 8'd0, + _theResult___snd__h383960[56:34] } + 25'd1 ; - assign sfd__h387543 = { value__h395765, 3'd0 } ; - assign sfd__h403346 = + assign sfd__h387542 = { value__h395764, 3'd0 } ; + assign sfd__h403345 = { 1'b0, - _theResult___fst_exp__h403254 != 8'd0, - sfdin__h403248[56:34] } + + _theResult___fst_exp__h403253 != 8'd0, + sfdin__h403247[56:34] } + 25'd1 ; - assign sfd__h411928 = + assign sfd__h411927 = { 1'b0, - _theResult___fst_exp__h411910 != 8'd0, - _theResult___snd__h411861[56:34] } + + _theResult___fst_exp__h411909 != 8'd0, + _theResult___snd__h411860[56:34] } + 25'd1 ; - assign sfd__h421112 = + assign sfd__h421111 = { 1'b0, - _theResult___fst_exp__h421020 != 8'd0, - sfdin__h421014[56:34] } + + _theResult___fst_exp__h421019 != 8'd0, + sfdin__h421013[56:34] } + 25'd1 ; - assign sfd__h429724 = + assign sfd__h429723 = { 1'b0, - _theResult___fst_exp__h429705 != 8'd0, - _theResult___snd__h429651[56:34] } + + _theResult___fst_exp__h429704 != 8'd0, + _theResult___snd__h429650[56:34] } + 25'd1 ; - assign sfd__h433231 = { value__h441453, 3'd0 } ; - assign sfd__h449034 = + assign sfd__h433230 = { value__h441452, 3'd0 } ; + assign sfd__h449033 = { 1'b0, - _theResult___fst_exp__h448942 != 8'd0, - sfdin__h448936[56:34] } + + _theResult___fst_exp__h448941 != 8'd0, + sfdin__h448935[56:34] } + 25'd1 ; - assign sfd__h457616 = + assign sfd__h457615 = { 1'b0, - _theResult___fst_exp__h457598 != 8'd0, - _theResult___snd__h457549[56:34] } + + _theResult___fst_exp__h457597 != 8'd0, + _theResult___snd__h457548[56:34] } + 25'd1 ; - assign sfd__h466800 = + assign sfd__h466799 = { 1'b0, - _theResult___fst_exp__h466708 != 8'd0, - sfdin__h466702[56:34] } + + _theResult___fst_exp__h466707 != 8'd0, + sfdin__h466701[56:34] } + 25'd1 ; - assign sfd__h475412 = + assign sfd__h475411 = { 1'b0, - _theResult___fst_exp__h475393 != 8'd0, - _theResult___snd__h475339[56:34] } + + _theResult___fst_exp__h475392 != 8'd0, + _theResult___snd__h475338[56:34] } + 25'd1 ; - assign sfd__h486559 = { value__h491117, 32'd0 } ; - assign sfd__h505578 = + assign sfd__h486558 = { value__h491116, 32'd0 } ; + assign sfd__h505577 = { 1'b0, - _theResult___fst_exp__h505560 != 11'd0, - _theResult___snd__h505511[56:5] } + + _theResult___fst_exp__h505559 != 11'd0, + _theResult___snd__h505510[56:5] } + 54'd1 ; - assign sfd__h515229 = + assign sfd__h515228 = { 1'b0, - _theResult___fst_exp__h515137 != 11'd0, - sfdin__h515131[56:5] } + + _theResult___fst_exp__h515136 != 11'd0, + sfdin__h515130[56:5] } + 54'd1 ; - assign sfd__h523989 = + assign sfd__h523988 = { 1'b0, - _theResult___fst_exp__h523970 != 11'd0, - _theResult___snd__h523916[56:5] } + + _theResult___fst_exp__h523969 != 11'd0, + _theResult___snd__h523915[56:5] } + 54'd1 ; - assign sfd__h525501 = { value__h529918, 32'd0 } ; - assign sfd__h544379 = + assign sfd__h525500 = { value__h529917, 32'd0 } ; + assign sfd__h544378 = { 1'b0, - _theResult___fst_exp__h544361 != 11'd0, - _theResult___snd__h544312[56:5] } + + _theResult___fst_exp__h544360 != 11'd0, + _theResult___snd__h544311[56:5] } + 54'd1 ; - assign sfd__h554030 = + assign sfd__h554029 = { 1'b0, - _theResult___fst_exp__h553938 != 11'd0, - sfdin__h553932[56:5] } + + _theResult___fst_exp__h553937 != 11'd0, + sfdin__h553931[56:5] } + 54'd1 ; - assign sfd__h562790 = + assign sfd__h562789 = { 1'b0, - _theResult___fst_exp__h562771 != 11'd0, - _theResult___snd__h562717[56:5] } + + _theResult___fst_exp__h562770 != 11'd0, + _theResult___snd__h562716[56:5] } + 54'd1 ; - assign sfd__h564702 = { value__h569119, 32'd0 } ; - assign sfd__h583580 = + assign sfd__h564701 = { value__h569118, 32'd0 } ; + assign sfd__h583579 = { 1'b0, - _theResult___fst_exp__h583562 != 11'd0, - _theResult___snd__h583513[56:5] } + + _theResult___fst_exp__h583561 != 11'd0, + _theResult___snd__h583512[56:5] } + 54'd1 ; - assign sfd__h593231 = + assign sfd__h593230 = { 1'b0, - _theResult___fst_exp__h593139 != 11'd0, - sfdin__h593133[56:5] } + + _theResult___fst_exp__h593138 != 11'd0, + sfdin__h593132[56:5] } + 54'd1 ; - assign sfd__h601991 = + assign sfd__h601990 = { 1'b0, - _theResult___fst_exp__h601972 != 11'd0, - _theResult___snd__h601918[56:5] } + + _theResult___fst_exp__h601971 != 11'd0, + _theResult___snd__h601917[56:5] } + 54'd1 ; - assign sfdin__h357558 = - _theResult____h349453[56] ? - _theResult___snd__h357575 : - _theResult___snd__h357586 ; - assign sfdin__h375324 = - _theResult____h367092[56] ? - _theResult___snd__h375341 : - _theResult___snd__h375352 ; - assign sfdin__h403248 = - _theResult____h395145[56] ? - _theResult___snd__h403265 : - _theResult___snd__h403276 ; - assign sfdin__h421014 = - _theResult____h412782[56] ? - _theResult___snd__h421031 : - _theResult___snd__h421042 ; - assign sfdin__h448936 = - _theResult____h440833[56] ? - _theResult___snd__h448953 : - _theResult___snd__h448964 ; - assign sfdin__h466702 = - _theResult____h458470[56] ? - _theResult___snd__h466719 : - _theResult___snd__h466730 ; - assign sfdin__h515131 = - _theResult____h506901[56] ? - _theResult___snd__h515148 : - _theResult___snd__h515159 ; - assign sfdin__h553932 = - _theResult____h545702[56] ? - _theResult___snd__h553949 : - _theResult___snd__h553960 ; - assign sfdin__h593133 = - _theResult____h584903[56] ? - _theResult___snd__h593150 : - _theResult___snd__h593161 ; - assign shiftData__h184331 = - coreFix_memExe_regToExeQ$first[75:12] << x__h184460 ; - assign sie_csr__read__h614807 = - { r1__read__h617635, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h615180 = - { r1__read__h618189, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h687556 = specTagManager$currentSpecBits | y__h687569 ; - assign sstatus_csr__read__h614738 = { r1__read__h617231, csrf_ie_vec_0 } ; - assign stvec_csr__read__h614850 = - { r1__read__h618165, csrf_stvec_mode_low_reg } ; + assign sfdin__h357557 = + _theResult____h349452[56] ? + _theResult___snd__h357574 : + _theResult___snd__h357585 ; + assign sfdin__h375323 = + _theResult____h367091[56] ? + _theResult___snd__h375340 : + _theResult___snd__h375351 ; + assign sfdin__h403247 = + _theResult____h395144[56] ? + _theResult___snd__h403264 : + _theResult___snd__h403275 ; + assign sfdin__h421013 = + _theResult____h412781[56] ? + _theResult___snd__h421030 : + _theResult___snd__h421041 ; + assign sfdin__h448935 = + _theResult____h440832[56] ? + _theResult___snd__h448952 : + _theResult___snd__h448963 ; + assign sfdin__h466701 = + _theResult____h458469[56] ? + _theResult___snd__h466718 : + _theResult___snd__h466729 ; + assign sfdin__h515130 = + _theResult____h506900[56] ? + _theResult___snd__h515147 : + _theResult___snd__h515158 ; + assign sfdin__h553931 = + _theResult____h545701[56] ? + _theResult___snd__h553948 : + _theResult___snd__h553959 ; + assign sfdin__h593132 = + _theResult____h584902[56] ? + _theResult___snd__h593149 : + _theResult___snd__h593160 ; + assign shiftData__h184332 = + coreFix_memExe_regToExeQ$first[75:12] << x__h184461 ; + assign sie_csr__read__h614806 = + { r1__read__h617634, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h615179 = + { r1__read__h618188, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h689574 = specTagManager$currentSpecBits | y__h689587 ; + assign sstatus_csr__read__h614737 = { r1__read__h617230, csrf_ie_vec_0 } ; + assign stvec_csr__read__h614849 = + { r1__read__h618164, csrf_stvec_mode_low_reg } ; assign upd__h3639 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; assign upd__h4956 = n__read__h6134 + 64'd1 ; - assign v__h299313 = + assign v__h299314 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127) ? - v__h299544 : + v__h299545 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h299544 = + assign v__h299545 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h302658 = + assign v__h302659 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234) ? - v__h303176 : + v__h303177 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h303176 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h313172 = + assign v__h303177 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h313173 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405) ? - v__h313403 : + v__h313404 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h313403 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h317048 = + assign v__h313404 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h317049 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501) ? - v__h317279 : + v__h317280 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h317279 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h331649 = + assign v__h317280 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h331650 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730) ? - v__h331880 : + v__h331881 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h331880 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h334874 = + assign v__h331881 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h334875 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824) ? - v__h335105 : + v__h335106 : coreFix_memExe_forwardQ_enqP ; - assign v__h335105 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h607990 = + assign v__h335106 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h607989 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h608000 : + v__h607999 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h608000 = + assign v__h607999 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h609058 = v__h607990 - 2'd1 ; - assign v__h613035 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h614207 ; + assign v__h609057 = v__h607989 - 2'd1 ; + assign v__h613034 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h614206 ; assign v__h637485 = sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h638504 ; - assign vaddr__h184326 = + assign vaddr__h184327 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 } ; - assign value__h350075 = + assign value__h350074 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h395765 = + assign value__h395764 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h441453 = + assign value__h441452 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h491117 = + assign value__h491116 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ; - assign value__h529918 = + assign value__h529917 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ; - assign value__h569119 = + assign value__h569118 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ; - assign vm_mode_reg__read__h618425 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign vm_mode_reg__read__h618424 = { csrf_vm_mode_sv39_reg, 3'b0 } ; assign w__h650904 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? result__h650960 : 12'd4095 ; - assign x__h154745 = + assign x__h154744 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h154751 = + assign x__h154750 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h158292 = { 3'd0, sbIdx__h158171 } ; - assign x__h158298 = + assign x__h158291 = { 3'd0, sbIdx__h158170 } ; + assign x__h158297 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h161108 = + assign x__h161107 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h161112 = + assign x__h161111 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h162960 = + assign x__h162959 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : @@ -29570,114 +29758,113 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h184238 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183366 ; assign x__h184239 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184085 ; - assign x__h184460 = { vaddr__h184326[2:0], 3'b0 } ; - assign x__h194788 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183367 ; + assign x__h184240 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184086 ; + assign x__h184461 = { vaddr__h184327[2:0], 3'b0 } ; + assign x__h194789 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h194025[63:32] : - curData__h194025[31:0] ; + curData__h194026[63:32] : + curData__h194026[31:0] ; assign x__h20210 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h290546 = + assign x__h290547 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h290558 = + assign x__h290559 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h292412 = + assign x__h292413 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h305523 = + assign x__h305524 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h341252 = - { (_theResult___exp__h384584 != 8'd255 || - _theResult___sfd__h384585 == 23'd0) && + assign x__h341251 = + { (_theResult___exp__h384583 != 8'd255 || + _theResult___sfd__h384584 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236, - out_f_exp__h384861, - out_f_sfd__h384862 } ; - assign x__h367802 = - sfd__h341848 << (x__h367835[11] ? 12'hAAA : x__h367835) ; - assign x__h367835 = + out_f_exp__h384860, + out_f_sfd__h384861 } ; + assign x__h367801 = + sfd__h341847 << (x__h367834[11] ? 12'hAAA : x__h367834) ; + assign x__h367834 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ; - assign x__h386947 = - { (_theResult___exp__h430274 != 8'd255 || - _theResult___sfd__h430275 == 23'd0) && + assign x__h386946 = + { (_theResult___exp__h430273 != 8'd255 || + _theResult___sfd__h430274 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628, - out_f_exp__h430551, - out_f_sfd__h430552 } ; - assign x__h413492 = - sfd__h387543 << (x__h413525[11] ? 12'hAAA : x__h413525) ; - assign x__h413525 = + out_f_exp__h430550, + out_f_sfd__h430551 } ; + assign x__h413491 = + sfd__h387542 << (x__h413524[11] ? 12'hAAA : x__h413524) ; + assign x__h413524 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ; - assign x__h432635 = - { (_theResult___exp__h475962 != 8'd255 || - _theResult___sfd__h475963 == 23'd0) && + assign x__h432634 = + { (_theResult___exp__h475961 != 8'd255 || + _theResult___sfd__h475962 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020, - out_f_exp__h476239, - out_f_sfd__h476240 } ; + out_f_exp__h476238, + out_f_sfd__h476239 } ; assign x__h45579 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h459180 = - sfd__h433231 << (x__h459213[11] ? 12'hAAA : x__h459213) ; - assign x__h459213 = + assign x__h459179 = + sfd__h433230 << (x__h459212[11] ? 12'hAAA : x__h459212) ; + assign x__h459212 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ; assign x__h48115 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; + assign x__h485745 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h482808 ; assign x__h485746 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h482809 ; + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h483529 ; assign x__h485747 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h483530 ; - assign x__h485748 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h484245 ; - assign x__h507609 = sfd__h486559 << x__h507642 ; - assign x__h507642 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h484244 ; + assign x__h507608 = sfd__h486558 << x__h507641 ; + assign x__h507641 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8755 ; - assign x__h546410 = sfd__h525501 << x__h546443 ; - assign x__h546443 = + assign x__h546409 = sfd__h525500 << x__h546442 ; + assign x__h546442 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10228 ; - assign x__h585611 = sfd__h564702 << x__h585644 ; - assign x__h585644 = + assign x__h585610 = sfd__h564701 << x__h585643 ; + assign x__h585643 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9465 ; - assign x__h607298 = + assign x__h607297 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h607309 : - a__h606761 ; - assign x__h607324 = a__h606761[63] ^ b__h606762[63] ; - assign x__h607928 = { q__h607919, r__h607920 } ; - assign x__h617216 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h617271 = csrf_fs_reg ; - assign x__h621537 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h614264 : - v__h613035 ; + _theResult___fst__h607308 : + a__h606760 ; + assign x__h607323 = a__h606760[63] ^ b__h606761[63] ; + assign x__h607927 = { q__h607918, r__h607919 } ; + assign x__h617215 = { csrf_frm_reg, csrf_fflags_reg } ; assign x__h621538 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h619579 ; + coreFix_aluExe_1_dispToRegQ$first[131] ? + rVal1__h614263 : + v__h613034 ; + assign x__h621539 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h619580 ; assign x__h643521 = coreFix_aluExe_0_dispToRegQ$first[131] ? rVal1__h638559 : @@ -29686,20 +29873,20 @@ module mkCore(CLK, sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h641573 ; assign x__h650908 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; assign x__h650959 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h698600 = + assign x__h700760 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h704888 = { cause_code__h702271, 2'b0 } ; - assign x__h713161 = { 1'b0, csrf_spp_reg } ; - assign x__h717147 = - NOT_rob_deqPort_0_canDeq__4759_4760_OR_rob_deq_ETC___d14951 ? - y_avValue_snd_snd_snd_fst__h716970 : - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14978 ; + assign x__h707048 = { cause_code__h704431, 2'b0 } ; + assign x__h715321 = { 1'b0, csrf_spp_reg } ; + assign x__h719307 = + NOT_rob_deqPort_0_canDeq__4852_4853_OR_rob_deq_ETC___d15044 ? + y_avValue_snd_snd_snd_fst__h719130 : + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15071 ; assign x__h75524 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h317446 = + assign x_addr__h317447 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; @@ -29707,31 +29894,31 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h677222 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h692182 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h658934 = csrf_frm_reg ; - assign x_quotient__h478657 = + assign x_data_imm__h678579 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h694200 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h658939 = csrf_frm_reg ; + assign x_quotient__h478656 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h479478 : + q___1__h479477 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h614647 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h478658 = + assign x_reg_ifc__read__h614646 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h478657 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h479505 : + r___1__h479504 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h257156 = + assign y__h257157 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h624307 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; + assign y__h624308 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; assign y__h645998 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; assign y__h650938 = ~x__h650908 ; - assign y__h655704 = + assign y__h655709 = { 3'd7, ~csrf_mideleg_11_reg, 1'd1, @@ -29740,36 +29927,36 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h687569 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h716923 = - NOT_rob_deqPort_0_canDeq__4759_4760_OR_rob_deq_ETC___d14951 ? - y_avValue_snd_snd_snd_snd_snd__h716976 : - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14868 ; - assign y_avValue__h183366 = + assign y__h689587 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h719083 = + NOT_rob_deqPort_0_canDeq__4852_4853_OR_rob_deq_ETC___d15044 ? + y_avValue_snd_snd_snd_snd_snd__h719136 : + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d14961 ; + assign y_avValue__h183367 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679 ; - assign y_avValue__h184085 = + assign y_avValue__h184086 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687 ; - assign y_avValue__h482809 = + assign y_avValue__h482808 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 ; - assign y_avValue__h483530 = + assign y_avValue__h483529 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 ; - assign y_avValue__h484245 = + assign y_avValue__h484244 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 ; - assign y_avValue__h614207 = + assign y_avValue__h614206 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1478_1_ETC___d11505 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__147_ETC___d11899 ; - assign y_avValue__h619579 = + assign y_avValue__h619580 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1478_1_ETC___d11535 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__147_ETC___d11908 ; @@ -29781,30 +29968,30 @@ module mkCore(CLK, NOT_coreFix_aluExe_0_bypassWire_0_whas__2301_2_ETC___d12358 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__230_ETC___d12545 ; - assign y_avValue__h703149 = + assign y_avValue__h705309 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h704873 + { 58'd0, x__h704888 } : - base__h704873 ; - assign y_avValue__h704910 = + base__h707033 + { 58'd0, x__h707048 } : + base__h707033 ; + assign y_avValue__h707070 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h705076 + { 58'd0, x__h704888 } : - base__h705076 ; - assign y_avValue_fst__h681648 = + base__h707236 + { 58'd0, x__h707048 } : + base__h707236 ; + assign y_avValue_fst__h683000 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h687556 : + spec_bits__h689574 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h681922 = + assign y_avValue_snd_fst__h683274 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378) ? - y_avValue_snd_fst__h681957 : + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437) ? + y_avValue_snd_fst__h683309 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h681957 = - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 ? - y_avValue_fst__h681648 : + assign y_avValue_snd_fst__h683309 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 ? + y_avValue_fst__h683000 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h716307 = + assign y_avValue_snd_fst__h718467 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29818,7 +30005,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h716960 = + assign y_avValue_snd_fst__h719120 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29830,12 +30017,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14957 : - y_avValue_snd_fst__h716989 ; - assign y_avValue_snd_fst__h716989 = - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14957 | + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15050 : + y_avValue_snd_fst__h719149 ; + assign y_avValue_snd_fst__h719149 = + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15050 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_snd_snd_fst__h716317 = + assign y_avValue_snd_snd_snd_fst__h718477 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29849,7 +30036,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h716970 = + assign y_avValue_snd_snd_snd_fst__h719130 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29861,12 +30048,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14978 : - y_avValue_snd_snd_snd_fst__h716999 ; - assign y_avValue_snd_snd_snd_fst__h716999 = - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14978 + + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15071 : + y_avValue_snd_snd_snd_fst__h719159 ; + assign y_avValue_snd_snd_snd_fst__h719159 = + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d15071 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h716323 = + assign y_avValue_snd_snd_snd_snd_snd__h718483 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29880,7 +30067,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h716976 = + assign y_avValue_snd_snd_snd_snd_snd__h719136 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29892,10 +30079,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14868 : - y_avValue_snd_snd_snd_snd_snd__h717005 ; - assign y_avValue_snd_snd_snd_snd_snd__h717005 = - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14868 + + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d14961 : + y_avValue_snd_snd_snd_snd_snd__h719165 ; + assign y_avValue_snd_snd_snd_snd_snd__h719165 = + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d14961 + 64'd1 ; always@(mmio_cRqQ_data_0) begin @@ -29913,28 +30100,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h199068 = + x__h199069 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -29950,28 +30137,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h289113 = + x__h289114 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -29981,10 +30168,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h293334 = + addr__h293335 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h293334 = + addr__h293335 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -29993,36 +30180,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h194025 = + curData__h194026 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h703302 = commitStage_commitTrap[132:69]; - default: trap_val__h703302 = + 4'd0, 4'd3: trap_val__h705462 = commitStage_commitTrap[132:69]; + default: trap_val__h705462 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -30037,247 +30224,247 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h294883 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h294884 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h294883 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h294884 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h614517 or - frm_csr__read__h614528 or - fcsr_csr__read__h614542 or - sstatus_csr__read__h614738 or - sie_csr__read__h614807 or - stvec_csr__read__h614850 or - scounteren_csr__read__h614903 or + fflags_csr__read__h614516 or + frm_csr__read__h614527 or + fcsr_csr__read__h614541 or + sstatus_csr__read__h614737 or + sie_csr__read__h614806 or + stvec_csr__read__h614849 or + scounteren_csr__read__h614902 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h615041 or + scause_csr__read__h615040 or csrf_stval_csr or - sip_csr__read__h615180 or - satp_csr__read__h615243 or - mstatus_csr__read__h615386 or - medeleg_csr__read__h615534 or - mideleg_csr__read__h615629 or - mie_csr__read__h615760 or - mtvec_csr__read__h615842 or - mcounteren_csr__read__h615934 or + sip_csr__read__h615179 or + satp_csr__read__h615242 or + mstatus_csr__read__h615385 or + medeleg_csr__read__h615533 or + mideleg_csr__read__h615628 or + mie_csr__read__h615759 or + mtvec_csr__read__h615841 or + mcounteren_csr__read__h615933 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h616189 or + mcause_csr__read__h616188 or csrf_mtval_csr or - mip_csr__read__h616429 or - x_reg_ifc__read__h614647 or - n__read__h616533 or n__read__h616724 or csrf_time_reg) + mip_csr__read__h616428 or + x_reg_ifc__read__h614646 or + n__read__h616532 or n__read__h616723 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h614264 = fflags_csr__read__h614517; - 12'd2: rVal1__h614264 = frm_csr__read__h614528; - 12'd3: rVal1__h614264 = fcsr_csr__read__h614542; - 12'd256: rVal1__h614264 = sstatus_csr__read__h614738; - 12'd260: rVal1__h614264 = sie_csr__read__h614807; - 12'd261: rVal1__h614264 = stvec_csr__read__h614850; - 12'd262: rVal1__h614264 = scounteren_csr__read__h614903; - 12'd320: rVal1__h614264 = csrf_sscratch_csr; - 12'd321: rVal1__h614264 = csrf_sepc_csr; - 12'd322: rVal1__h614264 = scause_csr__read__h615041; - 12'd323: rVal1__h614264 = csrf_stval_csr; - 12'd324: rVal1__h614264 = sip_csr__read__h615180; - 12'd384: rVal1__h614264 = satp_csr__read__h615243; - 12'd768: rVal1__h614264 = mstatus_csr__read__h615386; - 12'd769: rVal1__h614264 = 64'h8000000000041129; - 12'd770: rVal1__h614264 = medeleg_csr__read__h615534; - 12'd771: rVal1__h614264 = mideleg_csr__read__h615629; - 12'd772: rVal1__h614264 = mie_csr__read__h615760; - 12'd773: rVal1__h614264 = mtvec_csr__read__h615842; - 12'd774: rVal1__h614264 = mcounteren_csr__read__h615934; - 12'd832: rVal1__h614264 = csrf_mscratch_csr; - 12'd833: rVal1__h614264 = csrf_mepc_csr; - 12'd834: rVal1__h614264 = mcause_csr__read__h616189; - 12'd835: rVal1__h614264 = csrf_mtval_csr; - 12'd836: rVal1__h614264 = mip_csr__read__h616429; - 12'd2048: rVal1__h614264 = 64'd0; - 12'd2049: rVal1__h614264 = x_reg_ifc__read__h614647; - 12'd2816, 12'd3072: rVal1__h614264 = n__read__h616533; - 12'd2818, 12'd3074: rVal1__h614264 = n__read__h616724; - 12'd3073: rVal1__h614264 = csrf_time_reg; - default: rVal1__h614264 = 64'd0; + 12'd1: rVal1__h614263 = fflags_csr__read__h614516; + 12'd2: rVal1__h614263 = frm_csr__read__h614527; + 12'd3: rVal1__h614263 = fcsr_csr__read__h614541; + 12'd256: rVal1__h614263 = sstatus_csr__read__h614737; + 12'd260: rVal1__h614263 = sie_csr__read__h614806; + 12'd261: rVal1__h614263 = stvec_csr__read__h614849; + 12'd262: rVal1__h614263 = scounteren_csr__read__h614902; + 12'd320: rVal1__h614263 = csrf_sscratch_csr; + 12'd321: rVal1__h614263 = csrf_sepc_csr; + 12'd322: rVal1__h614263 = scause_csr__read__h615040; + 12'd323: rVal1__h614263 = csrf_stval_csr; + 12'd324: rVal1__h614263 = sip_csr__read__h615179; + 12'd384: rVal1__h614263 = satp_csr__read__h615242; + 12'd768: rVal1__h614263 = mstatus_csr__read__h615385; + 12'd769: rVal1__h614263 = 64'h8000000000141129; + 12'd770: rVal1__h614263 = medeleg_csr__read__h615533; + 12'd771: rVal1__h614263 = mideleg_csr__read__h615628; + 12'd772: rVal1__h614263 = mie_csr__read__h615759; + 12'd773: rVal1__h614263 = mtvec_csr__read__h615841; + 12'd774: rVal1__h614263 = mcounteren_csr__read__h615933; + 12'd832: rVal1__h614263 = csrf_mscratch_csr; + 12'd833: rVal1__h614263 = csrf_mepc_csr; + 12'd834: rVal1__h614263 = mcause_csr__read__h616188; + 12'd835: rVal1__h614263 = csrf_mtval_csr; + 12'd836: rVal1__h614263 = mip_csr__read__h616428; + 12'd2048: rVal1__h614263 = 64'd0; + 12'd2049: rVal1__h614263 = x_reg_ifc__read__h614646; + 12'd2816, 12'd3072: rVal1__h614263 = n__read__h616532; + 12'd2818, 12'd3074: rVal1__h614263 = n__read__h616723; + 12'd3073: rVal1__h614263 = csrf_time_reg; + default: rVal1__h614263 = 64'd0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h614517 or - frm_csr__read__h614528 or - fcsr_csr__read__h614542 or - sstatus_csr__read__h614738 or - sie_csr__read__h614807 or - stvec_csr__read__h614850 or - scounteren_csr__read__h614903 or + fflags_csr__read__h614516 or + frm_csr__read__h614527 or + fcsr_csr__read__h614541 or + sstatus_csr__read__h614737 or + sie_csr__read__h614806 or + stvec_csr__read__h614849 or + scounteren_csr__read__h614902 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h615041 or + scause_csr__read__h615040 or csrf_stval_csr or - sip_csr__read__h615180 or - satp_csr__read__h615243 or - mstatus_csr__read__h615386 or - medeleg_csr__read__h615534 or - mideleg_csr__read__h615629 or - mie_csr__read__h615760 or - mtvec_csr__read__h615842 or - mcounteren_csr__read__h615934 or + sip_csr__read__h615179 or + satp_csr__read__h615242 or + mstatus_csr__read__h615385 or + medeleg_csr__read__h615533 or + mideleg_csr__read__h615628 or + mie_csr__read__h615759 or + mtvec_csr__read__h615841 or + mcounteren_csr__read__h615933 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h616189 or + mcause_csr__read__h616188 or csrf_mtval_csr or - mip_csr__read__h616429 or - x_reg_ifc__read__h614647 or - n__read__h616533 or n__read__h616724 or csrf_time_reg) + mip_csr__read__h616428 or + x_reg_ifc__read__h614646 or + n__read__h616532 or n__read__h616723 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h638559 = fflags_csr__read__h614517; - 12'd2: rVal1__h638559 = frm_csr__read__h614528; - 12'd3: rVal1__h638559 = fcsr_csr__read__h614542; - 12'd256: rVal1__h638559 = sstatus_csr__read__h614738; - 12'd260: rVal1__h638559 = sie_csr__read__h614807; - 12'd261: rVal1__h638559 = stvec_csr__read__h614850; - 12'd262: rVal1__h638559 = scounteren_csr__read__h614903; + 12'd1: rVal1__h638559 = fflags_csr__read__h614516; + 12'd2: rVal1__h638559 = frm_csr__read__h614527; + 12'd3: rVal1__h638559 = fcsr_csr__read__h614541; + 12'd256: rVal1__h638559 = sstatus_csr__read__h614737; + 12'd260: rVal1__h638559 = sie_csr__read__h614806; + 12'd261: rVal1__h638559 = stvec_csr__read__h614849; + 12'd262: rVal1__h638559 = scounteren_csr__read__h614902; 12'd320: rVal1__h638559 = csrf_sscratch_csr; 12'd321: rVal1__h638559 = csrf_sepc_csr; - 12'd322: rVal1__h638559 = scause_csr__read__h615041; + 12'd322: rVal1__h638559 = scause_csr__read__h615040; 12'd323: rVal1__h638559 = csrf_stval_csr; - 12'd324: rVal1__h638559 = sip_csr__read__h615180; - 12'd384: rVal1__h638559 = satp_csr__read__h615243; - 12'd768: rVal1__h638559 = mstatus_csr__read__h615386; - 12'd769: rVal1__h638559 = 64'h8000000000041129; - 12'd770: rVal1__h638559 = medeleg_csr__read__h615534; - 12'd771: rVal1__h638559 = mideleg_csr__read__h615629; - 12'd772: rVal1__h638559 = mie_csr__read__h615760; - 12'd773: rVal1__h638559 = mtvec_csr__read__h615842; - 12'd774: rVal1__h638559 = mcounteren_csr__read__h615934; + 12'd324: rVal1__h638559 = sip_csr__read__h615179; + 12'd384: rVal1__h638559 = satp_csr__read__h615242; + 12'd768: rVal1__h638559 = mstatus_csr__read__h615385; + 12'd769: rVal1__h638559 = 64'h8000000000141129; + 12'd770: rVal1__h638559 = medeleg_csr__read__h615533; + 12'd771: rVal1__h638559 = mideleg_csr__read__h615628; + 12'd772: rVal1__h638559 = mie_csr__read__h615759; + 12'd773: rVal1__h638559 = mtvec_csr__read__h615841; + 12'd774: rVal1__h638559 = mcounteren_csr__read__h615933; 12'd832: rVal1__h638559 = csrf_mscratch_csr; 12'd833: rVal1__h638559 = csrf_mepc_csr; - 12'd834: rVal1__h638559 = mcause_csr__read__h616189; + 12'd834: rVal1__h638559 = mcause_csr__read__h616188; 12'd835: rVal1__h638559 = csrf_mtval_csr; - 12'd836: rVal1__h638559 = mip_csr__read__h616429; + 12'd836: rVal1__h638559 = mip_csr__read__h616428; 12'd2048: rVal1__h638559 = 64'd0; - 12'd2049: rVal1__h638559 = x_reg_ifc__read__h614647; - 12'd2816, 12'd3072: rVal1__h638559 = n__read__h616533; - 12'd2818, 12'd3074: rVal1__h638559 = n__read__h616724; + 12'd2049: rVal1__h638559 = x_reg_ifc__read__h614646; + 12'd2816, 12'd3072: rVal1__h638559 = n__read__h616532; + 12'd2818, 12'd3074: rVal1__h638559 = n__read__h616723; 12'd3073: rVal1__h638559 = csrf_time_reg; default: rVal1__h638559 = 64'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h395127 = 8'd255; + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h440814 = 8'd255; 3'd2: - _theResult___fst_exp__h395127 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h440814 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h395127 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h440814 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h395127 = 8'd254; - default: _theResult___fst_exp__h395127 = 8'd0; + 3'd4: _theResult___fst_exp__h440814 = 8'd254; + default: _theResult___fst_exp__h440814 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h349435 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h349434 = 8'd255; 3'd2: - _theResult___fst_exp__h349435 = + _theResult___fst_exp__h349434 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h349435 = + _theResult___fst_exp__h349434 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h349435 = 8'd254; - default: _theResult___fst_exp__h349435 = 8'd0; + 3'd4: _theResult___fst_exp__h349434 = 8'd254; + default: _theResult___fst_exp__h349434 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h349436 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h349435 = 23'd0; 3'd2: - _theResult___fst_sfd__h349436 = + _theResult___fst_sfd__h349435 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h349436 = + _theResult___fst_sfd__h349435 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h349436 = 23'd8388607; - default: _theResult___fst_sfd__h349436 = 23'd0; + 3'd4: _theResult___fst_sfd__h349435 = 23'd8388607; + default: _theResult___fst_sfd__h349435 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h395128 = 23'd0; + 3'd0, 3'd1: _theResult___fst_exp__h395126 = 8'd255; 3'd2: - _theResult___fst_sfd__h395128 = + _theResult___fst_exp__h395126 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h395128 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h395128 = 23'd8388607; - default: _theResult___fst_sfd__h395128 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h440815 = 8'd255; - 3'd2: - _theResult___fst_exp__h440815 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h440815 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___fst_exp__h395126 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h440815 = 8'd254; - default: _theResult___fst_exp__h440815 = 8'd0; + 3'd4: _theResult___fst_exp__h395126 = 8'd254; + default: _theResult___fst_exp__h395126 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h395127 = 23'd0; + 3'd2: + _theResult___fst_sfd__h395127 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h395127 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h395127 = 23'd8388607; + default: _theResult___fst_sfd__h395127 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h440816 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h440815 = 23'd0; 3'd2: - _theResult___fst_sfd__h440816 = + _theResult___fst_sfd__h440815 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h440816 = + _theResult___fst_sfd__h440815 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h440816 = 23'd8388607; - default: _theResult___fst_sfd__h440816 = 23'd0; + 3'd4: _theResult___fst_sfd__h440815 = 23'd8388607; + default: _theResult___fst_sfd__h440815 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -30404,16 +30591,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h702286 = commitStage_commitTrap[3:0]; - default: i__h702286 = 4'd15; + i__h704446 = commitStage_commitTrap[3:0]; + default: i__h704446 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11: - i__h702446 = commitStage_commitTrap[3:0]; - default: i__h702446 = 4'd14; + i__h704606 = commitStage_commitTrap[3:0]; + default: i__h704606 = 4'd14; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -30485,6 +30672,23 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[15:0]; + 2'd1: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[31:16]; + 2'd2: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[47:32]; + 2'd3: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[63:48]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -30513,23 +30717,6 @@ module mkCore(CLK, mmio_dataRespQ_data_0[63:56]; endcase end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[15:0]; - 2'd1: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[31:16]; - 2'd2: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[47:32]; - 2'd3: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[63:48]; - endcase - end always@(coreFix_memExe_dTlb$procResp) begin case (coreFix_memExe_dTlb$procResp[105:103]) @@ -30641,446 +30828,459 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h358172 or - _theResult___fst_exp__h366220 or - out_exp__h366665 or _theResult___exp__h366662) - begin - case (guard__h358172) - 2'b0, 2'b01: - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q25 = - _theResult___fst_exp__h366220; - 2'b10: - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q25 = - out_exp__h366665; - 2'b11: - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q25 = - _theResult___exp__h366662; - endcase - end - always@(guard__h358172 or - _theResult___fst_exp__h366220 or _theResult___exp__h366662) - begin - case (guard__h358172) - 2'b0: - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q26 = - _theResult___fst_exp__h366220; - 2'b01, 2'b10, 2'b11: - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q26 = - _theResult___exp__h366662; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q25 or - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q26 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or - _theResult___fst_exp__h366220) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h366740 = - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q25; - 3'd1: - _theResult___fst_exp__h366740 = - CASE_guard58172_0b0_theResult___fst_exp66220_0_ETC__q26; - 3'd2: - _theResult___fst_exp__h366740 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; - 3'd3: - _theResult___fst_exp__h366740 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; - 3'd4: _theResult___fst_exp__h366740 = _theResult___fst_exp__h366220; - default: _theResult___fst_exp__h366740 = 8'd0; - endcase - end - always@(guard__h349463 or - _theResult___fst_exp__h357564 or - out_exp__h358083 or _theResult___exp__h358080) - begin - case (guard__h349463) - 2'b0, 2'b01: - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q27 = - _theResult___fst_exp__h357564; - 2'b10: - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q27 = - out_exp__h358083; - 2'b11: - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q27 = - _theResult___exp__h358080; - endcase - end - always@(guard__h349463 or - _theResult___fst_exp__h357564 or _theResult___exp__h358080) - begin - case (guard__h349463) - 2'b0: - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q28 = - _theResult___fst_exp__h357564; - 2'b01, 2'b10, 2'b11: - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q28 = - _theResult___exp__h358080; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q27 or - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q28 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 or - _theResult___fst_exp__h357564) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h358158 = - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q27; - 3'd1: - _theResult___fst_exp__h358158 = - CASE_guard49463_0b0_theResult___fst_exp57564_0_ETC__q28; - 3'd2: - _theResult___fst_exp__h358158 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406; - 3'd3: - _theResult___fst_exp__h358158 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409; - 3'd4: _theResult___fst_exp__h358158 = _theResult___fst_exp__h357564; - default: _theResult___fst_exp__h358158 = 8'd0; - endcase - end - always@(guard__h367102 or - _theResult___fst_exp__h375330 or - out_exp__h375849 or _theResult___exp__h375846) - begin - case (guard__h367102) - 2'b0, 2'b01: - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q33 = - _theResult___fst_exp__h375330; - 2'b10: - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q33 = - out_exp__h375849; - 2'b11: - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q33 = - _theResult___exp__h375846; - endcase - end - always@(guard__h367102 or - _theResult___fst_exp__h375330 or _theResult___exp__h375846) - begin - case (guard__h367102) - 2'b0: - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q34 = - _theResult___fst_exp__h375330; - 2'b01, 2'b10, 2'b11: - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q34 = - _theResult___exp__h375846; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q33 or - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q34 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 or - _theResult___fst_exp__h375330) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h375924 = - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q33; - 3'd1: - _theResult___fst_exp__h375924 = - CASE_guard67102_0b0_theResult___fst_exp75330_0_ETC__q34; - 3'd2: - _theResult___fst_exp__h375924 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953; - 3'd3: - _theResult___fst_exp__h375924 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955; - 3'd4: _theResult___fst_exp__h375924 = _theResult___fst_exp__h375330; - default: _theResult___fst_exp__h375924 = 8'd0; - endcase - end - always@(guard__h375938 or - _theResult___fst_exp__h384015 or - out_exp__h384485 or _theResult___exp__h384482) - begin - case (guard__h375938) - 2'b0, 2'b01: - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q38 = - _theResult___fst_exp__h384015; - 2'b10: - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q38 = - out_exp__h384485; - 2'b11: - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q38 = - _theResult___exp__h384482; - endcase - end - always@(guard__h375938 or - _theResult___fst_exp__h384015 or _theResult___exp__h384482) - begin - case (guard__h375938) - 2'b0: - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q39 = - _theResult___fst_exp__h384015; - 2'b01, 2'b10, 2'b11: - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q39 = - _theResult___exp__h384482; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q38 or - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q39 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___fst_exp__h384015) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h384560 = - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q38; - 3'd1: - _theResult___fst_exp__h384560 = - CASE_guard75938_0b0_theResult___fst_exp84015_0_ETC__q39; - 3'd2: - _theResult___fst_exp__h384560 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; - 3'd3: - _theResult___fst_exp__h384560 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_exp__h384560 = _theResult___fst_exp__h384015; - default: _theResult___fst_exp__h384560 = 8'd0; - endcase - end - always@(guard__h358172 or - _theResult___snd__h366171 or - out_sfd__h366666 or _theResult___sfd__h366663) - begin - case (guard__h358172) - 2'b0, 2'b01: - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q40 = - _theResult___snd__h366171[56:34]; - 2'b10: - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q40 = - out_sfd__h366666; - 2'b11: - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q40 = - _theResult___sfd__h366663; - endcase - end - always@(guard__h358172 or - _theResult___snd__h366171 or _theResult___sfd__h366663) - begin - case (guard__h358172) - 2'b0: - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q41 = - _theResult___snd__h366171[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q41 = - _theResult___sfd__h366663; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q40 or - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q41 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or - _theResult___snd__h366171) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h366741 = - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q40; - 3'd1: - _theResult___fst_sfd__h366741 = - CASE_guard58172_0b0_theResult___snd66171_BITS__ETC__q41; - 3'd2: - _theResult___fst_sfd__h366741 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; - 3'd3: - _theResult___fst_sfd__h366741 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074; - 3'd4: _theResult___fst_sfd__h366741 = _theResult___snd__h366171[56:34]; - default: _theResult___fst_sfd__h366741 = 23'd0; - endcase - end - always@(guard__h349463 or - sfdin__h357558 or out_sfd__h358084 or _theResult___sfd__h358081) - begin - case (guard__h349463) - 2'b0, 2'b01: - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q42 = - sfdin__h357558[56:34]; - 2'b10: - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q42 = - out_sfd__h358084; - 2'b11: - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h358081; - endcase - end - always@(guard__h349463 or sfdin__h357558 or _theResult___sfd__h358081) - begin - case (guard__h349463) - 2'b0: - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q43 = - sfdin__h357558[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h358081; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q42 or - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q43 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or - sfdin__h357558) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h358159 = - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q42; - 3'd1: - _theResult___fst_sfd__h358159 = - CASE_guard49463_0b0_sfdin57558_BITS_56_TO_34_0_ETC__q43; - 3'd2: - _theResult___fst_sfd__h358159 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; - 3'd3: - _theResult___fst_sfd__h358159 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; - 3'd4: _theResult___fst_sfd__h358159 = sfdin__h357558[56:34]; - default: _theResult___fst_sfd__h358159 = 23'd0; - endcase - end - always@(guard__h367102 or - sfdin__h375324 or out_sfd__h375850 or _theResult___sfd__h375847) - begin - case (guard__h367102) - 2'b0, 2'b01: - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q44 = - sfdin__h375324[56:34]; - 2'b10: - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q44 = - out_sfd__h375850; - 2'b11: - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h375847; - endcase - end - always@(guard__h367102 or sfdin__h375324 or _theResult___sfd__h375847) - begin - case (guard__h367102) - 2'b0: - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q45 = - sfdin__h375324[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q45 = - _theResult___sfd__h375847; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q44 or - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q45 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 or - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 or - sfdin__h375324) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h375925 = - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q44; - 3'd1: - _theResult___fst_sfd__h375925 = - CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q45; - 3'd2: - _theResult___fst_sfd__h375925 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099; - 3'd3: - _theResult___fst_sfd__h375925 = - IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101; - 3'd4: _theResult___fst_sfd__h375925 = sfdin__h375324[56:34]; - default: _theResult___fst_sfd__h375925 = 23'd0; - endcase - end - always@(guard__h375938 or - _theResult___snd__h383961 or - out_sfd__h384486 or _theResult___sfd__h384483) - begin - case (guard__h375938) - 2'b0, 2'b01: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 = - _theResult___snd__h383961[56:34]; - 2'b10: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 = - out_sfd__h384486; - 2'b11: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 = - _theResult___sfd__h384483; - endcase - end - always@(guard__h375938 or - _theResult___snd__h383961 or _theResult___sfd__h384483) - begin - case (guard__h375938) - 2'b0: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 = - _theResult___snd__h383961[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 = - _theResult___sfd__h384483; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 or - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or - _theResult___snd__h383961) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h384561 = - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46; - 3'd1: - _theResult___fst_sfd__h384561 = - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47; - 3'd2: - _theResult___fst_sfd__h384561 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; - 3'd3: - _theResult___fst_sfd__h384561 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; - 3'd4: _theResult___fst_sfd__h384561 = _theResult___snd__h383961[56:34]; - default: _theResult___fst_sfd__h384561 = 23'd0; - endcase - end - always@(guard__h349463 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h349463) + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(guard__h358171 or + _theResult___fst_exp__h366219 or + out_exp__h366664 or _theResult___exp__h366661) + begin + case (guard__h358171) + 2'b0, 2'b01: + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q25 = + _theResult___fst_exp__h366219; + 2'b10: + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q25 = + out_exp__h366664; + 2'b11: + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q25 = + _theResult___exp__h366661; + endcase + end + always@(guard__h358171 or + _theResult___fst_exp__h366219 or _theResult___exp__h366661) + begin + case (guard__h358171) + 2'b0: + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q26 = + _theResult___fst_exp__h366219; + 2'b01, 2'b10, 2'b11: + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q26 = + _theResult___exp__h366661; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q25 or + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q26 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or + _theResult___fst_exp__h366219) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h366739 = + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q25; + 3'd1: + _theResult___fst_exp__h366739 = + CASE_guard58171_0b0_theResult___fst_exp66219_0_ETC__q26; + 3'd2: + _theResult___fst_exp__h366739 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; + 3'd3: + _theResult___fst_exp__h366739 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; + 3'd4: _theResult___fst_exp__h366739 = _theResult___fst_exp__h366219; + default: _theResult___fst_exp__h366739 = 8'd0; + endcase + end + always@(guard__h349462 or + _theResult___fst_exp__h357563 or + out_exp__h358082 or _theResult___exp__h358079) + begin + case (guard__h349462) + 2'b0, 2'b01: + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q27 = + _theResult___fst_exp__h357563; + 2'b10: + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q27 = + out_exp__h358082; + 2'b11: + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q27 = + _theResult___exp__h358079; + endcase + end + always@(guard__h349462 or + _theResult___fst_exp__h357563 or _theResult___exp__h358079) + begin + case (guard__h349462) + 2'b0: + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q28 = + _theResult___fst_exp__h357563; + 2'b01, 2'b10, 2'b11: + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q28 = + _theResult___exp__h358079; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q27 or + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q28 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 or + _theResult___fst_exp__h357563) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h358157 = + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q27; + 3'd1: + _theResult___fst_exp__h358157 = + CASE_guard49462_0b0_theResult___fst_exp57563_0_ETC__q28; + 3'd2: + _theResult___fst_exp__h358157 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406; + 3'd3: + _theResult___fst_exp__h358157 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409; + 3'd4: _theResult___fst_exp__h358157 = _theResult___fst_exp__h357563; + default: _theResult___fst_exp__h358157 = 8'd0; + endcase + end + always@(guard__h367101 or + _theResult___fst_exp__h375329 or + out_exp__h375848 or _theResult___exp__h375845) + begin + case (guard__h367101) + 2'b0, 2'b01: + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q33 = + _theResult___fst_exp__h375329; + 2'b10: + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q33 = + out_exp__h375848; + 2'b11: + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q33 = + _theResult___exp__h375845; + endcase + end + always@(guard__h367101 or + _theResult___fst_exp__h375329 or _theResult___exp__h375845) + begin + case (guard__h367101) + 2'b0: + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q34 = + _theResult___fst_exp__h375329; + 2'b01, 2'b10, 2'b11: + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q34 = + _theResult___exp__h375845; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q33 or + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q34 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 or + _theResult___fst_exp__h375329) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h375923 = + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q33; + 3'd1: + _theResult___fst_exp__h375923 = + CASE_guard67101_0b0_theResult___fst_exp75329_0_ETC__q34; + 3'd2: + _theResult___fst_exp__h375923 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953; + 3'd3: + _theResult___fst_exp__h375923 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955; + 3'd4: _theResult___fst_exp__h375923 = _theResult___fst_exp__h375329; + default: _theResult___fst_exp__h375923 = 8'd0; + endcase + end + always@(guard__h375937 or + _theResult___fst_exp__h384014 or + out_exp__h384484 or _theResult___exp__h384481) + begin + case (guard__h375937) + 2'b0, 2'b01: + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q38 = + _theResult___fst_exp__h384014; + 2'b10: + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q38 = + out_exp__h384484; + 2'b11: + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q38 = + _theResult___exp__h384481; + endcase + end + always@(guard__h375937 or + _theResult___fst_exp__h384014 or _theResult___exp__h384481) + begin + case (guard__h375937) + 2'b0: + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q39 = + _theResult___fst_exp__h384014; + 2'b01, 2'b10, 2'b11: + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q39 = + _theResult___exp__h384481; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q38 or + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q39 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or + _theResult___fst_exp__h384014) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h384559 = + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q38; + 3'd1: + _theResult___fst_exp__h384559 = + CASE_guard75937_0b0_theResult___fst_exp84014_0_ETC__q39; + 3'd2: + _theResult___fst_exp__h384559 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; + 3'd3: + _theResult___fst_exp__h384559 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; + 3'd4: _theResult___fst_exp__h384559 = _theResult___fst_exp__h384014; + default: _theResult___fst_exp__h384559 = 8'd0; + endcase + end + always@(guard__h358171 or + _theResult___snd__h366170 or + out_sfd__h366665 or _theResult___sfd__h366662) + begin + case (guard__h358171) + 2'b0, 2'b01: + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q40 = + _theResult___snd__h366170[56:34]; + 2'b10: + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q40 = + out_sfd__h366665; + 2'b11: + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q40 = + _theResult___sfd__h366662; + endcase + end + always@(guard__h358171 or + _theResult___snd__h366170 or _theResult___sfd__h366662) + begin + case (guard__h358171) + 2'b0: + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q41 = + _theResult___snd__h366170[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q41 = + _theResult___sfd__h366662; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q40 or + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q41 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or + _theResult___snd__h366170) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h366740 = + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q40; + 3'd1: + _theResult___fst_sfd__h366740 = + CASE_guard58171_0b0_theResult___snd66170_BITS__ETC__q41; + 3'd2: + _theResult___fst_sfd__h366740 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; + 3'd3: + _theResult___fst_sfd__h366740 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074; + 3'd4: _theResult___fst_sfd__h366740 = _theResult___snd__h366170[56:34]; + default: _theResult___fst_sfd__h366740 = 23'd0; + endcase + end + always@(guard__h349462 or + sfdin__h357557 or out_sfd__h358083 or _theResult___sfd__h358080) + begin + case (guard__h349462) + 2'b0, 2'b01: + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q42 = + sfdin__h357557[56:34]; + 2'b10: + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q42 = + out_sfd__h358083; + 2'b11: + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h358080; + endcase + end + always@(guard__h349462 or sfdin__h357557 or _theResult___sfd__h358080) + begin + case (guard__h349462) + 2'b0: + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q43 = + sfdin__h357557[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h358080; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q42 or + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q43 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or + sfdin__h357557) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h358158 = + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q42; + 3'd1: + _theResult___fst_sfd__h358158 = + CASE_guard49462_0b0_sfdin57557_BITS_56_TO_34_0_ETC__q43; + 3'd2: + _theResult___fst_sfd__h358158 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; + 3'd3: + _theResult___fst_sfd__h358158 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; + 3'd4: _theResult___fst_sfd__h358158 = sfdin__h357557[56:34]; + default: _theResult___fst_sfd__h358158 = 23'd0; + endcase + end + always@(guard__h367101 or + sfdin__h375323 or out_sfd__h375849 or _theResult___sfd__h375846) + begin + case (guard__h367101) + 2'b0, 2'b01: + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q44 = + sfdin__h375323[56:34]; + 2'b10: + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q44 = + out_sfd__h375849; + 2'b11: + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h375846; + endcase + end + always@(guard__h367101 or sfdin__h375323 or _theResult___sfd__h375846) + begin + case (guard__h367101) + 2'b0: + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q45 = + sfdin__h375323[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q45 = + _theResult___sfd__h375846; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q44 or + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q45 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 or + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 or + sfdin__h375323) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h375924 = + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q44; + 3'd1: + _theResult___fst_sfd__h375924 = + CASE_guard67101_0b0_sfdin75323_BITS_56_TO_34_0_ETC__q45; + 3'd2: + _theResult___fst_sfd__h375924 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099; + 3'd3: + _theResult___fst_sfd__h375924 = + IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101; + 3'd4: _theResult___fst_sfd__h375924 = sfdin__h375323[56:34]; + default: _theResult___fst_sfd__h375924 = 23'd0; + endcase + end + always@(guard__h375937 or + _theResult___snd__h383960 or + out_sfd__h384485 or _theResult___sfd__h384482) + begin + case (guard__h375937) + 2'b0, 2'b01: + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q46 = + _theResult___snd__h383960[56:34]; + 2'b10: + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q46 = + out_sfd__h384485; + 2'b11: + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q46 = + _theResult___sfd__h384482; + endcase + end + always@(guard__h375937 or + _theResult___snd__h383960 or _theResult___sfd__h384482) + begin + case (guard__h375937) + 2'b0: + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q47 = + _theResult___snd__h383960[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q47 = + _theResult___sfd__h384482; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q46 or + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q47 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or + _theResult___snd__h383960) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h384560 = + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q46; + 3'd1: + _theResult___fst_sfd__h384560 = + CASE_guard75937_0b0_theResult___snd83960_BITS__ETC__q47; + 3'd2: + _theResult___fst_sfd__h384560 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; + 3'd3: + _theResult___fst_sfd__h384560 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; + 3'd4: _theResult___fst_sfd__h384560 = _theResult___snd__h383960[56:34]; + default: _theResult___fst_sfd__h384560 = 23'd0; + endcase + end + always@(guard__h349462 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h349462) 2'b0, 2'b01, 2'b10: - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard49462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h349463 == 2'b11 && + CASE_guard49462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h349462 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h349463) + CASE_guard49462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h349462) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard49462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - (guard__h349463 == 2'b0) ? + (guard__h349462 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h349463 == 2'b01 || guard__h349463 == 2'b10 || - guard__h349463 == 2'b11) && + (guard__h349462 == 2'b01 || guard__h349462 == 2'b10 || + guard__h349462 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = @@ -31091,34 +31291,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h349463 or + always@(guard__h349462 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h349463) + case (guard__h349462) 2'b0, 2'b01, 2'b10: - CASE_guard49463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard49462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard49463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h349463 != 2'b11 || + CASE_guard49462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h349462 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard49463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h349463) + CASE_guard49462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h349462) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - CASE_guard49463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + CASE_guard49462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - (guard__h349463 == 2'b0) ? + (guard__h349462 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h349463 != 2'b01 && guard__h349463 != 2'b10 && - guard__h349463 != 2'b11 || + guard__h349462 != 2'b01 && guard__h349462 != 2'b10 && + guard__h349462 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = @@ -31129,34 +31329,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h358172 or + always@(guard__h358171 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h358172) + case (guard__h358171) 2'b0, 2'b01, 2'b10: - CASE_guard58172_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + CASE_guard58171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard58172_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = - guard__h358172 == 2'b11 && + CASE_guard58171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + guard__h358171 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard58172_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or - guard__h358172) + CASE_guard58171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or + guard__h358171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - CASE_guard58172_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; + CASE_guard58171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - (guard__h358172 == 2'b0) ? + (guard__h358171 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h358172 == 2'b01 || guard__h358172 == 2'b10 || - guard__h358172 == 2'b11) && + (guard__h358171 == 2'b01 || guard__h358171 == 2'b10 || + guard__h358171 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = @@ -31167,34 +31367,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h358172 or + always@(guard__h358171 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h358172) + case (guard__h358171) 2'b0, 2'b01, 2'b10: - CASE_guard58172_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + CASE_guard58171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard58172_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = - guard__h358172 != 2'b11 || + CASE_guard58171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + guard__h358171 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard58172_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or - guard__h358172) + CASE_guard58171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or + guard__h358171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - CASE_guard58172_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; + CASE_guard58171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - (guard__h358172 == 2'b0) ? + (guard__h358171 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h358172 != 2'b01 && guard__h358172 != 2'b10 && - guard__h358172 != 2'b11 || + guard__h358171 != 2'b01 && guard__h358171 != 2'b10 && + guard__h358171 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = @@ -31205,34 +31405,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h367102 or + always@(guard__h367101 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h367102) + case (guard__h367101) 2'b0, 2'b01, 2'b10: - CASE_guard67102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard67101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard67102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h367102 == 2'b11 && + CASE_guard67101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h367101 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard67102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h367102) + CASE_guard67101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h367101) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - CASE_guard67102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard67101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - (guard__h367102 == 2'b0) ? + (guard__h367101 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h367102 == 2'b01 || guard__h367102 == 2'b10 || - guard__h367102 == 2'b11) && + (guard__h367101 == 2'b01 || guard__h367101 == 2'b10 || + guard__h367101 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = @@ -31243,34 +31443,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h367102 or + always@(guard__h367101 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h367102) + case (guard__h367101) 2'b0, 2'b01, 2'b10: - CASE_guard67102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard67101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard67102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h367102 != 2'b11 || + CASE_guard67101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h367101 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard67102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h367102) + CASE_guard67101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h367101) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - CASE_guard67102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard67101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - (guard__h367102 == 2'b0) ? + (guard__h367101 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h367102 != 2'b01 && guard__h367102 != 2'b10 && - guard__h367102 != 2'b11 || + guard__h367101 != 2'b01 && guard__h367101 != 2'b10 && + guard__h367101 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = @@ -31281,34 +31481,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h375938 or + always@(guard__h375937 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h375938) + case (guard__h375937) 2'b0, 2'b01, 2'b10: - CASE_guard75938_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + CASE_guard75937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard75938_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = - guard__h375938 == 2'b11 && + CASE_guard75937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + guard__h375937 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard75938_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or - guard__h375938) + CASE_guard75937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or + guard__h375937) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - CASE_guard75938_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; + CASE_guard75937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - (guard__h375938 == 2'b0) ? + (guard__h375937 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h375938 == 2'b01 || guard__h375938 == 2'b10 || - guard__h375938 == 2'b11) && + (guard__h375937 == 2'b01 || guard__h375937 == 2'b10 || + guard__h375937 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = @@ -31319,34 +31519,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h375938 or + always@(guard__h375937 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h375938) + case (guard__h375937) 2'b0, 2'b01, 2'b10: - CASE_guard75938_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + CASE_guard75937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard75938_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = - guard__h375938 != 2'b11 || + CASE_guard75937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + guard__h375937 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard75938_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or - guard__h375938) + CASE_guard75937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or + guard__h375937) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - CASE_guard75938_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; + CASE_guard75937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - (guard__h375938 == 2'b0) ? + (guard__h375937 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h375938 != 2'b01 && guard__h375938 != 2'b10 && - guard__h375938 != 2'b11 || + guard__h375937 != 2'b01 && guard__h375937 != 2'b10 && + guard__h375937 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = @@ -31357,19 +31557,6 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -31383,446 +31570,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h403862 or - _theResult___fst_exp__h411910 or - out_exp__h412355 or _theResult___exp__h412352) + always@(guard__h403861 or + _theResult___fst_exp__h411909 or + out_exp__h412354 or _theResult___exp__h412351) begin - case (guard__h403862) + case (guard__h403861) 2'b0, 2'b01: - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q60 = - _theResult___fst_exp__h411910; + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q60 = + _theResult___fst_exp__h411909; 2'b10: - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q60 = - out_exp__h412355; + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q60 = + out_exp__h412354; 2'b11: - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q60 = - _theResult___exp__h412352; + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q60 = + _theResult___exp__h412351; endcase end - always@(guard__h403862 or - _theResult___fst_exp__h411910 or _theResult___exp__h412352) + always@(guard__h403861 or + _theResult___fst_exp__h411909 or _theResult___exp__h412351) begin - case (guard__h403862) + case (guard__h403861) 2'b0: - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q61 = - _theResult___fst_exp__h411910; + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q61 = + _theResult___fst_exp__h411909; 2'b01, 2'b10, 2'b11: - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q61 = - _theResult___exp__h412352; + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q61 = + _theResult___exp__h412351; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q60 or - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q61 or + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q60 or + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q61 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 or - _theResult___fst_exp__h411910) + _theResult___fst_exp__h411909) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h412430 = - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q60; + _theResult___fst_exp__h412429 = + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q60; 3'd1: - _theResult___fst_exp__h412430 = - CASE_guard03862_0b0_theResult___fst_exp11910_0_ETC__q61; + _theResult___fst_exp__h412429 = + CASE_guard03861_0b0_theResult___fst_exp11909_0_ETC__q61; 3'd2: - _theResult___fst_exp__h412430 = + _theResult___fst_exp__h412429 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020; 3'd3: - _theResult___fst_exp__h412430 = + _theResult___fst_exp__h412429 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022; - 3'd4: _theResult___fst_exp__h412430 = _theResult___fst_exp__h411910; - default: _theResult___fst_exp__h412430 = 8'd0; + 3'd4: _theResult___fst_exp__h412429 = _theResult___fst_exp__h411909; + default: _theResult___fst_exp__h412429 = 8'd0; endcase end - always@(guard__h395155 or - _theResult___fst_exp__h403254 or - out_exp__h403773 or _theResult___exp__h403770) + always@(guard__h395154 or + _theResult___fst_exp__h403253 or + out_exp__h403772 or _theResult___exp__h403769) begin - case (guard__h395155) + case (guard__h395154) 2'b0, 2'b01: - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q62 = - _theResult___fst_exp__h403254; + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q62 = + _theResult___fst_exp__h403253; 2'b10: - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q62 = - out_exp__h403773; + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q62 = + out_exp__h403772; 2'b11: - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q62 = - _theResult___exp__h403770; + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q62 = + _theResult___exp__h403769; endcase end - always@(guard__h395155 or - _theResult___fst_exp__h403254 or _theResult___exp__h403770) + always@(guard__h395154 or + _theResult___fst_exp__h403253 or _theResult___exp__h403769) begin - case (guard__h395155) + case (guard__h395154) 2'b0: - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q63 = - _theResult___fst_exp__h403254; + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q63 = + _theResult___fst_exp__h403253; 2'b01, 2'b10, 2'b11: - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q63 = - _theResult___exp__h403770; + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q63 = + _theResult___exp__h403769; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q62 or - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q63 or + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q62 or + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q63 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 or - _theResult___fst_exp__h403254) + _theResult___fst_exp__h403253) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h403848 = - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q62; + _theResult___fst_exp__h403847 = + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q62; 3'd1: - _theResult___fst_exp__h403848 = - CASE_guard95155_0b0_theResult___fst_exp03254_0_ETC__q63; + _theResult___fst_exp__h403847 = + CASE_guard95154_0b0_theResult___fst_exp03253_0_ETC__q63; 3'd2: - _theResult___fst_exp__h403848 = + _theResult___fst_exp__h403847 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798; 3'd3: - _theResult___fst_exp__h403848 = + _theResult___fst_exp__h403847 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801; - 3'd4: _theResult___fst_exp__h403848 = _theResult___fst_exp__h403254; - default: _theResult___fst_exp__h403848 = 8'd0; + 3'd4: _theResult___fst_exp__h403847 = _theResult___fst_exp__h403253; + default: _theResult___fst_exp__h403847 = 8'd0; endcase end - always@(guard__h412792 or - _theResult___fst_exp__h421020 or - out_exp__h421539 or _theResult___exp__h421536) + always@(guard__h412791 or + _theResult___fst_exp__h421019 or + out_exp__h421538 or _theResult___exp__h421535) begin - case (guard__h412792) + case (guard__h412791) 2'b0, 2'b01: - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q68 = - _theResult___fst_exp__h421020; + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q68 = + _theResult___fst_exp__h421019; 2'b10: - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q68 = - out_exp__h421539; + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q68 = + out_exp__h421538; 2'b11: - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q68 = - _theResult___exp__h421536; + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q68 = + _theResult___exp__h421535; endcase end - always@(guard__h412792 or - _theResult___fst_exp__h421020 or _theResult___exp__h421536) + always@(guard__h412791 or + _theResult___fst_exp__h421019 or _theResult___exp__h421535) begin - case (guard__h412792) + case (guard__h412791) 2'b0: - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q69 = - _theResult___fst_exp__h421020; + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q69 = + _theResult___fst_exp__h421019; 2'b01, 2'b10, 2'b11: - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q69 = - _theResult___exp__h421536; + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q69 = + _theResult___exp__h421535; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q68 or - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q69 or + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q68 or + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q69 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 or - _theResult___fst_exp__h421020) + _theResult___fst_exp__h421019) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h421614 = - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q68; + _theResult___fst_exp__h421613 = + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q68; 3'd1: - _theResult___fst_exp__h421614 = - CASE_guard12792_0b0_theResult___fst_exp21020_0_ETC__q69; + _theResult___fst_exp__h421613 = + CASE_guard12791_0b0_theResult___fst_exp21019_0_ETC__q69; 3'd2: - _theResult___fst_exp__h421614 = + _theResult___fst_exp__h421613 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345; 3'd3: - _theResult___fst_exp__h421614 = + _theResult___fst_exp__h421613 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347; - 3'd4: _theResult___fst_exp__h421614 = _theResult___fst_exp__h421020; - default: _theResult___fst_exp__h421614 = 8'd0; + 3'd4: _theResult___fst_exp__h421613 = _theResult___fst_exp__h421019; + default: _theResult___fst_exp__h421613 = 8'd0; endcase end - always@(guard__h421628 or - _theResult___fst_exp__h429705 or - out_exp__h430175 or _theResult___exp__h430172) + always@(guard__h421627 or + _theResult___fst_exp__h429704 or + out_exp__h430174 or _theResult___exp__h430171) begin - case (guard__h421628) + case (guard__h421627) 2'b0, 2'b01: - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q73 = - _theResult___fst_exp__h429705; + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q73 = + _theResult___fst_exp__h429704; 2'b10: - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q73 = - out_exp__h430175; + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q73 = + out_exp__h430174; 2'b11: - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q73 = - _theResult___exp__h430172; + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q73 = + _theResult___exp__h430171; endcase end - always@(guard__h421628 or - _theResult___fst_exp__h429705 or _theResult___exp__h430172) + always@(guard__h421627 or + _theResult___fst_exp__h429704 or _theResult___exp__h430171) begin - case (guard__h421628) + case (guard__h421627) 2'b0: - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q74 = - _theResult___fst_exp__h429705; + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q74 = + _theResult___fst_exp__h429704; 2'b01, 2'b10, 2'b11: - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q74 = - _theResult___exp__h430172; + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q74 = + _theResult___exp__h430171; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q73 or - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q74 or + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q73 or + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q74 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___fst_exp__h429705) + _theResult___fst_exp__h429704) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h430250 = - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q73; + _theResult___fst_exp__h430249 = + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q73; 3'd1: - _theResult___fst_exp__h430250 = - CASE_guard21628_0b0_theResult___fst_exp29705_0_ETC__q74; + _theResult___fst_exp__h430249 = + CASE_guard21627_0b0_theResult___fst_exp29704_0_ETC__q74; 3'd2: - _theResult___fst_exp__h430250 = + _theResult___fst_exp__h430249 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_exp__h430250 = + _theResult___fst_exp__h430249 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_exp__h430250 = _theResult___fst_exp__h429705; - default: _theResult___fst_exp__h430250 = 8'd0; + 3'd4: _theResult___fst_exp__h430249 = _theResult___fst_exp__h429704; + default: _theResult___fst_exp__h430249 = 8'd0; endcase end - always@(guard__h403862 or - _theResult___snd__h411861 or - out_sfd__h412356 or _theResult___sfd__h412353) + always@(guard__h403861 or + _theResult___snd__h411860 or + out_sfd__h412355 or _theResult___sfd__h412352) begin - case (guard__h403862) + case (guard__h403861) 2'b0, 2'b01: - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q75 = - _theResult___snd__h411861[56:34]; + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q75 = + _theResult___snd__h411860[56:34]; 2'b10: - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q75 = - out_sfd__h412356; + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q75 = + out_sfd__h412355; 2'b11: - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q75 = - _theResult___sfd__h412353; + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q75 = + _theResult___sfd__h412352; endcase end - always@(guard__h403862 or - _theResult___snd__h411861 or _theResult___sfd__h412353) + always@(guard__h403861 or + _theResult___snd__h411860 or _theResult___sfd__h412352) begin - case (guard__h403862) + case (guard__h403861) 2'b0: - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q76 = - _theResult___snd__h411861[56:34]; + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q76 = + _theResult___snd__h411860[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q76 = - _theResult___sfd__h412353; + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q76 = + _theResult___sfd__h412352; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q75 or - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q76 or + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q75 or + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q76 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or - _theResult___snd__h411861) + _theResult___snd__h411860) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h412431 = - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q75; + _theResult___fst_sfd__h412430 = + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q75; 3'd1: - _theResult___fst_sfd__h412431 = - CASE_guard03862_0b0_theResult___snd11861_BITS__ETC__q76; + _theResult___fst_sfd__h412430 = + CASE_guard03861_0b0_theResult___snd11860_BITS__ETC__q76; 3'd2: - _theResult___fst_sfd__h412431 = + _theResult___fst_sfd__h412430 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; 3'd3: - _theResult___fst_sfd__h412431 = + _theResult___fst_sfd__h412430 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466; - 3'd4: _theResult___fst_sfd__h412431 = _theResult___snd__h411861[56:34]; - default: _theResult___fst_sfd__h412431 = 23'd0; + 3'd4: _theResult___fst_sfd__h412430 = _theResult___snd__h411860[56:34]; + default: _theResult___fst_sfd__h412430 = 23'd0; endcase end - always@(guard__h395155 or - sfdin__h403248 or out_sfd__h403774 or _theResult___sfd__h403771) + always@(guard__h395154 or + sfdin__h403247 or out_sfd__h403773 or _theResult___sfd__h403770) begin - case (guard__h395155) + case (guard__h395154) 2'b0, 2'b01: - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q77 = - sfdin__h403248[56:34]; + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q77 = + sfdin__h403247[56:34]; 2'b10: - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q77 = - out_sfd__h403774; + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q77 = + out_sfd__h403773; 2'b11: - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h403771; + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h403770; endcase end - always@(guard__h395155 or sfdin__h403248 or _theResult___sfd__h403771) + always@(guard__h395154 or sfdin__h403247 or _theResult___sfd__h403770) begin - case (guard__h395155) + case (guard__h395154) 2'b0: - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q78 = - sfdin__h403248[56:34]; + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q78 = + sfdin__h403247[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h403771; + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h403770; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q77 or - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q78 or + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q77 or + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q78 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or - sfdin__h403248) + sfdin__h403247) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h403849 = - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h403848 = + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q77; 3'd1: - _theResult___fst_sfd__h403849 = - CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h403848 = + CASE_guard95154_0b0_sfdin03247_BITS_56_TO_34_0_ETC__q78; 3'd2: - _theResult___fst_sfd__h403849 = + _theResult___fst_sfd__h403848 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; 3'd3: - _theResult___fst_sfd__h403849 = + _theResult___fst_sfd__h403848 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; - 3'd4: _theResult___fst_sfd__h403849 = sfdin__h403248[56:34]; - default: _theResult___fst_sfd__h403849 = 23'd0; + 3'd4: _theResult___fst_sfd__h403848 = sfdin__h403247[56:34]; + default: _theResult___fst_sfd__h403848 = 23'd0; endcase end - always@(guard__h412792 or - sfdin__h421014 or out_sfd__h421540 or _theResult___sfd__h421537) + always@(guard__h412791 or + sfdin__h421013 or out_sfd__h421539 or _theResult___sfd__h421536) begin - case (guard__h412792) + case (guard__h412791) 2'b0, 2'b01: - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q79 = - sfdin__h421014[56:34]; + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q79 = + sfdin__h421013[56:34]; 2'b10: - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q79 = - out_sfd__h421540; + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q79 = + out_sfd__h421539; 2'b11: - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h421537; + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h421536; endcase end - always@(guard__h412792 or sfdin__h421014 or _theResult___sfd__h421537) + always@(guard__h412791 or sfdin__h421013 or _theResult___sfd__h421536) begin - case (guard__h412792) + case (guard__h412791) 2'b0: - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q80 = - sfdin__h421014[56:34]; + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q80 = + sfdin__h421013[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q80 = - _theResult___sfd__h421537; + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q80 = + _theResult___sfd__h421536; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q79 or - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q80 or + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q79 or + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q80 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 or - sfdin__h421014) + sfdin__h421013) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h421615 = - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h421614 = + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q79; 3'd1: - _theResult___fst_sfd__h421615 = - CASE_guard12792_0b0_sfdin21014_BITS_56_TO_34_0_ETC__q80; + _theResult___fst_sfd__h421614 = + CASE_guard12791_0b0_sfdin21013_BITS_56_TO_34_0_ETC__q80; 3'd2: - _theResult___fst_sfd__h421615 = + _theResult___fst_sfd__h421614 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491; 3'd3: - _theResult___fst_sfd__h421615 = + _theResult___fst_sfd__h421614 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493; - 3'd4: _theResult___fst_sfd__h421615 = sfdin__h421014[56:34]; - default: _theResult___fst_sfd__h421615 = 23'd0; + 3'd4: _theResult___fst_sfd__h421614 = sfdin__h421013[56:34]; + default: _theResult___fst_sfd__h421614 = 23'd0; endcase end - always@(guard__h421628 or - _theResult___snd__h429651 or - out_sfd__h430176 or _theResult___sfd__h430173) + always@(guard__h421627 or + _theResult___snd__h429650 or + out_sfd__h430175 or _theResult___sfd__h430172) begin - case (guard__h421628) + case (guard__h421627) 2'b0, 2'b01: - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q81 = - _theResult___snd__h429651[56:34]; + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q81 = + _theResult___snd__h429650[56:34]; 2'b10: - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q81 = - out_sfd__h430176; + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q81 = + out_sfd__h430175; 2'b11: - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q81 = - _theResult___sfd__h430173; + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q81 = + _theResult___sfd__h430172; endcase end - always@(guard__h421628 or - _theResult___snd__h429651 or _theResult___sfd__h430173) + always@(guard__h421627 or + _theResult___snd__h429650 or _theResult___sfd__h430172) begin - case (guard__h421628) + case (guard__h421627) 2'b0: - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q82 = - _theResult___snd__h429651[56:34]; + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q82 = + _theResult___snd__h429650[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q82 = - _theResult___sfd__h430173; + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q82 = + _theResult___sfd__h430172; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q81 or - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q82 or + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q81 or + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q82 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 or - _theResult___snd__h429651) + _theResult___snd__h429650) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h430251 = - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q81; + _theResult___fst_sfd__h430250 = + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q81; 3'd1: - _theResult___fst_sfd__h430251 = - CASE_guard21628_0b0_theResult___snd29651_BITS__ETC__q82; + _theResult___fst_sfd__h430250 = + CASE_guard21627_0b0_theResult___snd29650_BITS__ETC__q82; 3'd2: - _theResult___fst_sfd__h430251 = + _theResult___fst_sfd__h430250 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510; 3'd3: - _theResult___fst_sfd__h430251 = + _theResult___fst_sfd__h430250 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512; - 3'd4: _theResult___fst_sfd__h430251 = _theResult___snd__h429651[56:34]; - default: _theResult___fst_sfd__h430251 = 23'd0; + 3'd4: _theResult___fst_sfd__h430250 = _theResult___snd__h429650[56:34]; + default: _theResult___fst_sfd__h430250 = 23'd0; endcase end - always@(guard__h395155 or + always@(guard__h395154 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h395155) + case (guard__h395154) 2'b0, 2'b01, 2'b10: - CASE_guard95155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + CASE_guard95154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard95155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = - guard__h395155 == 2'b11 && + CASE_guard95154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + guard__h395154 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard95155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or - guard__h395155) + CASE_guard95154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or + guard__h395154) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - CASE_guard95155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; + CASE_guard95154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - (guard__h395155 == 2'b0) ? + (guard__h395154 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h395155 == 2'b01 || guard__h395155 == 2'b10 || - guard__h395155 == 2'b11) && + (guard__h395154 == 2'b01 || guard__h395154 == 2'b10 || + guard__h395154 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = @@ -31833,34 +32020,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h395155 or + always@(guard__h395154 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h395155) + case (guard__h395154) 2'b0, 2'b01, 2'b10: - CASE_guard95155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = + CASE_guard95154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard95155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = - guard__h395155 != 2'b11 || + CASE_guard95154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = + guard__h395154 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard95155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or - guard__h395155) + CASE_guard95154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or + guard__h395154) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - CASE_guard95155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84; + CASE_guard95154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - (guard__h395155 == 2'b0) ? + (guard__h395154 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h395155 != 2'b01 && guard__h395155 != 2'b10 && - guard__h395155 != 2'b11 || + guard__h395154 != 2'b01 && guard__h395154 != 2'b10 && + guard__h395154 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = @@ -31871,34 +32058,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h403862 or + always@(guard__h403861 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h403862) + case (guard__h403861) 2'b0, 2'b01, 2'b10: - CASE_guard03862_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + CASE_guard03861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard03862_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = - guard__h403862 == 2'b11 && + CASE_guard03861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + guard__h403861 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard03862_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or - guard__h403862) + CASE_guard03861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or + guard__h403861) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - CASE_guard03862_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85; + CASE_guard03861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - (guard__h403862 == 2'b0) ? + (guard__h403861 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h403862 == 2'b01 || guard__h403862 == 2'b10 || - guard__h403862 == 2'b11) && + (guard__h403861 == 2'b01 || guard__h403861 == 2'b10 || + guard__h403861 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = @@ -31909,34 +32096,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h403862 or + always@(guard__h403861 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h403862) + case (guard__h403861) 2'b0, 2'b01, 2'b10: - CASE_guard03862_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + CASE_guard03861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard03862_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = - guard__h403862 != 2'b11 || + CASE_guard03861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + guard__h403861 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard03862_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or - guard__h403862) + CASE_guard03861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or + guard__h403861) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - CASE_guard03862_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; + CASE_guard03861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - (guard__h403862 == 2'b0) ? + (guard__h403861 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h403862 != 2'b01 && guard__h403862 != 2'b10 && - guard__h403862 != 2'b11 || + guard__h403861 != 2'b01 && guard__h403861 != 2'b10 && + guard__h403861 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = @@ -31947,34 +32134,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h412792 or + always@(guard__h412791 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h412792) + case (guard__h412791) 2'b0, 2'b01, 2'b10: - CASE_guard12792_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + CASE_guard12791_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard12792_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = - guard__h412792 == 2'b11 && + CASE_guard12791_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + guard__h412791 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard12792_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or - guard__h412792) + CASE_guard12791_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or + guard__h412791) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - CASE_guard12792_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; + CASE_guard12791_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - (guard__h412792 == 2'b0) ? + (guard__h412791 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h412792 == 2'b01 || guard__h412792 == 2'b10 || - guard__h412792 == 2'b11) && + (guard__h412791 == 2'b01 || guard__h412791 == 2'b10 || + guard__h412791 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = @@ -31985,34 +32172,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h412792 or + always@(guard__h412791 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h412792) + case (guard__h412791) 2'b0, 2'b01, 2'b10: - CASE_guard12792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = + CASE_guard12791_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard12792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = - guard__h412792 != 2'b11 || + CASE_guard12791_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = + guard__h412791 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard12792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or - guard__h412792) + CASE_guard12791_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or + guard__h412791) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - CASE_guard12792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; + CASE_guard12791_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - (guard__h412792 == 2'b0) ? + (guard__h412791 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h412792 != 2'b01 && guard__h412792 != 2'b10 && - guard__h412792 != 2'b11 || + guard__h412791 != 2'b01 && guard__h412791 != 2'b10 && + guard__h412791 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = @@ -32023,34 +32210,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h421628 or + always@(guard__h421627 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h421628) + case (guard__h421627) 2'b0, 2'b01, 2'b10: - CASE_guard21628_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + CASE_guard21627_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard21628_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = - guard__h421628 == 2'b11 && + CASE_guard21627_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + guard__h421627 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard21628_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or - guard__h421628) + CASE_guard21627_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or + guard__h421627) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - CASE_guard21628_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; + CASE_guard21627_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - (guard__h421628 == 2'b0) ? + (guard__h421627 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h421628 == 2'b01 || guard__h421628 == 2'b10 || - guard__h421628 == 2'b11) && + (guard__h421627 == 2'b01 || guard__h421627 == 2'b10 || + guard__h421627 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = @@ -32061,34 +32248,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h421628 or + always@(guard__h421627 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h421628) + case (guard__h421627) 2'b0, 2'b01, 2'b10: - CASE_guard21628_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + CASE_guard21627_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard21628_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = - guard__h421628 != 2'b11 || + CASE_guard21627_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + guard__h421627 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard21628_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or - guard__h421628) + CASE_guard21627_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or + guard__h421627) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - CASE_guard21628_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; + CASE_guard21627_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - (guard__h421628 == 2'b0) ? + (guard__h421627 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h421628 != 2'b01 && guard__h421628 != 2'b10 && - guard__h421628 != 2'b11 || + guard__h421627 != 2'b01 && guard__h421627 != 2'b10 && + guard__h421627 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = @@ -32125,484 +32312,491 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h449550 or - _theResult___fst_exp__h457598 or - out_exp__h458043 or _theResult___exp__h458040) + always@(fetchStage$pipelines_0_first) begin - case (guard__h449550) - 2'b0, 2'b01: - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q95 = - _theResult___fst_exp__h457598; - 2'b10: - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q95 = - out_exp__h458043; - 2'b11: - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q95 = - _theResult___exp__h458040; + case (fetchStage$pipelines_0_first[172:161]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd2048, + 12'd2049, + 12'd2816, + 12'd2818, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035 = + fetchStage$pipelines_0_first[172:161]; + default: IF_fetchStage_pipelines_0_first__2835_BITS_172_ETC___d13035 = + 12'd2303; endcase end - always@(guard__h449550 or - _theResult___fst_exp__h457598 or _theResult___exp__h458040) + always@(guard__h449549 or + _theResult___fst_exp__h457597 or + out_exp__h458042 or _theResult___exp__h458039) begin - case (guard__h449550) + case (guard__h449549) + 2'b0, 2'b01: + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q95 = + _theResult___fst_exp__h457597; + 2'b10: + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q95 = + out_exp__h458042; + 2'b11: + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q95 = + _theResult___exp__h458039; + endcase + end + always@(guard__h449549 or + _theResult___fst_exp__h457597 or _theResult___exp__h458039) + begin + case (guard__h449549) 2'b0: - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q96 = - _theResult___fst_exp__h457598; + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q96 = + _theResult___fst_exp__h457597; 2'b01, 2'b10, 2'b11: - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q96 = - _theResult___exp__h458040; + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q96 = + _theResult___exp__h458039; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q95 or - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q96 or + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q95 or + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q96 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 or - _theResult___fst_exp__h457598) + _theResult___fst_exp__h457597) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h458118 = - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q95; + _theResult___fst_exp__h458117 = + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q95; 3'd1: - _theResult___fst_exp__h458118 = - CASE_guard49550_0b0_theResult___fst_exp57598_0_ETC__q96; + _theResult___fst_exp__h458117 = + CASE_guard49549_0b0_theResult___fst_exp57597_0_ETC__q96; 3'd2: - _theResult___fst_exp__h458118 = + _theResult___fst_exp__h458117 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412; 3'd3: - _theResult___fst_exp__h458118 = + _theResult___fst_exp__h458117 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414; - 3'd4: _theResult___fst_exp__h458118 = _theResult___fst_exp__h457598; - default: _theResult___fst_exp__h458118 = 8'd0; + 3'd4: _theResult___fst_exp__h458117 = _theResult___fst_exp__h457597; + default: _theResult___fst_exp__h458117 = 8'd0; endcase end - always@(guard__h440843 or - _theResult___fst_exp__h448942 or - out_exp__h449461 or _theResult___exp__h449458) + always@(guard__h440842 or + _theResult___fst_exp__h448941 or + out_exp__h449460 or _theResult___exp__h449457) begin - case (guard__h440843) + case (guard__h440842) 2'b0, 2'b01: - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q97 = - _theResult___fst_exp__h448942; + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q97 = + _theResult___fst_exp__h448941; 2'b10: - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q97 = - out_exp__h449461; + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q97 = + out_exp__h449460; 2'b11: - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q97 = - _theResult___exp__h449458; + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q97 = + _theResult___exp__h449457; endcase end - always@(guard__h440843 or - _theResult___fst_exp__h448942 or _theResult___exp__h449458) + always@(guard__h440842 or + _theResult___fst_exp__h448941 or _theResult___exp__h449457) begin - case (guard__h440843) + case (guard__h440842) 2'b0: - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q98 = - _theResult___fst_exp__h448942; + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q98 = + _theResult___fst_exp__h448941; 2'b01, 2'b10, 2'b11: - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q98 = - _theResult___exp__h449458; + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q98 = + _theResult___exp__h449457; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q97 or - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q98 or + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q97 or + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q98 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 or - _theResult___fst_exp__h448942) + _theResult___fst_exp__h448941) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h449536 = - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q97; + _theResult___fst_exp__h449535 = + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q97; 3'd1: - _theResult___fst_exp__h449536 = - CASE_guard40843_0b0_theResult___fst_exp48942_0_ETC__q98; + _theResult___fst_exp__h449535 = + CASE_guard40842_0b0_theResult___fst_exp48941_0_ETC__q98; 3'd2: - _theResult___fst_exp__h449536 = + _theResult___fst_exp__h449535 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190; 3'd3: - _theResult___fst_exp__h449536 = + _theResult___fst_exp__h449535 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193; - 3'd4: _theResult___fst_exp__h449536 = _theResult___fst_exp__h448942; - default: _theResult___fst_exp__h449536 = 8'd0; + 3'd4: _theResult___fst_exp__h449535 = _theResult___fst_exp__h448941; + default: _theResult___fst_exp__h449535 = 8'd0; endcase end - always@(guard__h458480 or - _theResult___fst_exp__h466708 or - out_exp__h467227 or _theResult___exp__h467224) + always@(guard__h458479 or + _theResult___fst_exp__h466707 or + out_exp__h467226 or _theResult___exp__h467223) begin - case (guard__h458480) + case (guard__h458479) 2'b0, 2'b01: - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q103 = - _theResult___fst_exp__h466708; + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q103 = + _theResult___fst_exp__h466707; 2'b10: - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q103 = - out_exp__h467227; + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q103 = + out_exp__h467226; 2'b11: - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q103 = - _theResult___exp__h467224; + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q103 = + _theResult___exp__h467223; endcase end - always@(guard__h458480 or - _theResult___fst_exp__h466708 or _theResult___exp__h467224) + always@(guard__h458479 or + _theResult___fst_exp__h466707 or _theResult___exp__h467223) begin - case (guard__h458480) + case (guard__h458479) 2'b0: - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q104 = - _theResult___fst_exp__h466708; + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q104 = + _theResult___fst_exp__h466707; 2'b01, 2'b10, 2'b11: - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q104 = - _theResult___exp__h467224; + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q104 = + _theResult___exp__h467223; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q103 or - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q104 or + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q103 or + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q104 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 or - _theResult___fst_exp__h466708) + _theResult___fst_exp__h466707) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h467302 = - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q103; + _theResult___fst_exp__h467301 = + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q103; 3'd1: - _theResult___fst_exp__h467302 = - CASE_guard58480_0b0_theResult___fst_exp66708_0_ETC__q104; + _theResult___fst_exp__h467301 = + CASE_guard58479_0b0_theResult___fst_exp66707_0_ETC__q104; 3'd2: - _theResult___fst_exp__h467302 = + _theResult___fst_exp__h467301 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737; 3'd3: - _theResult___fst_exp__h467302 = + _theResult___fst_exp__h467301 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739; - 3'd4: _theResult___fst_exp__h467302 = _theResult___fst_exp__h466708; - default: _theResult___fst_exp__h467302 = 8'd0; + 3'd4: _theResult___fst_exp__h467301 = _theResult___fst_exp__h466707; + default: _theResult___fst_exp__h467301 = 8'd0; endcase end - always@(guard__h467316 or - _theResult___fst_exp__h475393 or - out_exp__h475863 or _theResult___exp__h475860) + always@(guard__h467315 or + _theResult___fst_exp__h475392 or + out_exp__h475862 or _theResult___exp__h475859) begin - case (guard__h467316) + case (guard__h467315) 2'b0, 2'b01: - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q108 = - _theResult___fst_exp__h475393; + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q108 = + _theResult___fst_exp__h475392; 2'b10: - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q108 = - out_exp__h475863; + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q108 = + out_exp__h475862; 2'b11: - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q108 = - _theResult___exp__h475860; + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q108 = + _theResult___exp__h475859; endcase end - always@(guard__h467316 or - _theResult___fst_exp__h475393 or _theResult___exp__h475860) + always@(guard__h467315 or + _theResult___fst_exp__h475392 or _theResult___exp__h475859) begin - case (guard__h467316) + case (guard__h467315) 2'b0: - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q109 = - _theResult___fst_exp__h475393; + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q109 = + _theResult___fst_exp__h475392; 2'b01, 2'b10, 2'b11: - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q109 = - _theResult___exp__h475860; + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q109 = + _theResult___exp__h475859; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q108 or - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q109 or + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q108 or + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q109 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___fst_exp__h475393) + _theResult___fst_exp__h475392) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h475938 = - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q108; + _theResult___fst_exp__h475937 = + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q108; 3'd1: - _theResult___fst_exp__h475938 = - CASE_guard67316_0b0_theResult___fst_exp75393_0_ETC__q109; + _theResult___fst_exp__h475937 = + CASE_guard67315_0b0_theResult___fst_exp75392_0_ETC__q109; 3'd2: - _theResult___fst_exp__h475938 = + _theResult___fst_exp__h475937 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; 3'd3: - _theResult___fst_exp__h475938 = + _theResult___fst_exp__h475937 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_exp__h475938 = _theResult___fst_exp__h475393; - default: _theResult___fst_exp__h475938 = 8'd0; + 3'd4: _theResult___fst_exp__h475937 = _theResult___fst_exp__h475392; + default: _theResult___fst_exp__h475937 = 8'd0; endcase end - always@(guard__h449550 or - _theResult___snd__h457549 or - out_sfd__h458044 or _theResult___sfd__h458041) + always@(guard__h449549 or + _theResult___snd__h457548 or + out_sfd__h458043 or _theResult___sfd__h458040) begin - case (guard__h449550) + case (guard__h449549) 2'b0, 2'b01: - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q110 = - _theResult___snd__h457549[56:34]; + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q110 = + _theResult___snd__h457548[56:34]; 2'b10: - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q110 = - out_sfd__h458044; + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q110 = + out_sfd__h458043; 2'b11: - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q110 = - _theResult___sfd__h458041; + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q110 = + _theResult___sfd__h458040; endcase end - always@(guard__h449550 or - _theResult___snd__h457549 or _theResult___sfd__h458041) + always@(guard__h449549 or + _theResult___snd__h457548 or _theResult___sfd__h458040) begin - case (guard__h449550) + case (guard__h449549) 2'b0: - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q111 = - _theResult___snd__h457549[56:34]; + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q111 = + _theResult___snd__h457548[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q111 = - _theResult___sfd__h458041; + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q111 = + _theResult___sfd__h458040; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q110 or - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q111 or + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q110 or + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q111 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 or - _theResult___snd__h457549) + _theResult___snd__h457548) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h458119 = - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q110; + _theResult___fst_sfd__h458118 = + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q110; 3'd1: - _theResult___fst_sfd__h458119 = - CASE_guard49550_0b0_theResult___snd57549_BITS__ETC__q111; + _theResult___fst_sfd__h458118 = + CASE_guard49549_0b0_theResult___snd57548_BITS__ETC__q111; 3'd2: - _theResult___fst_sfd__h458119 = + _theResult___fst_sfd__h458118 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856; 3'd3: - _theResult___fst_sfd__h458119 = + _theResult___fst_sfd__h458118 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858; - 3'd4: _theResult___fst_sfd__h458119 = _theResult___snd__h457549[56:34]; - default: _theResult___fst_sfd__h458119 = 23'd0; + 3'd4: _theResult___fst_sfd__h458118 = _theResult___snd__h457548[56:34]; + default: _theResult___fst_sfd__h458118 = 23'd0; endcase end - always@(guard__h440843 or - sfdin__h448936 or out_sfd__h449462 or _theResult___sfd__h449459) + always@(guard__h440842 or + sfdin__h448935 or out_sfd__h449461 or _theResult___sfd__h449458) begin - case (guard__h440843) + case (guard__h440842) 2'b0, 2'b01: - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q112 = - sfdin__h448936[56:34]; + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q112 = + sfdin__h448935[56:34]; 2'b10: - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q112 = - out_sfd__h449462; + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q112 = + out_sfd__h449461; 2'b11: - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h449459; + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h449458; endcase end - always@(guard__h440843 or sfdin__h448936 or _theResult___sfd__h449459) + always@(guard__h440842 or sfdin__h448935 or _theResult___sfd__h449458) begin - case (guard__h440843) + case (guard__h440842) 2'b0: - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q113 = - sfdin__h448936[56:34]; + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q113 = + sfdin__h448935[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h449459; + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h449458; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q112 or - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q113 or + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q112 or + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q113 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 or - sfdin__h448936) + sfdin__h448935) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h449537 = - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h449536 = + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q112; 3'd1: - _theResult___fst_sfd__h449537 = - CASE_guard40843_0b0_sfdin48936_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h449536 = + CASE_guard40842_0b0_sfdin48935_BITS_56_TO_34_0_ETC__q113; 3'd2: - _theResult___fst_sfd__h449537 = + _theResult___fst_sfd__h449536 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837; 3'd3: - _theResult___fst_sfd__h449537 = + _theResult___fst_sfd__h449536 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839; - 3'd4: _theResult___fst_sfd__h449537 = sfdin__h448936[56:34]; - default: _theResult___fst_sfd__h449537 = 23'd0; + 3'd4: _theResult___fst_sfd__h449536 = sfdin__h448935[56:34]; + default: _theResult___fst_sfd__h449536 = 23'd0; endcase end - always@(guard__h458480 or - sfdin__h466702 or out_sfd__h467228 or _theResult___sfd__h467225) + always@(guard__h458479 or + sfdin__h466701 or out_sfd__h467227 or _theResult___sfd__h467224) begin - case (guard__h458480) + case (guard__h458479) 2'b0, 2'b01: - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q114 = - sfdin__h466702[56:34]; + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q114 = + sfdin__h466701[56:34]; 2'b10: - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q114 = - out_sfd__h467228; + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q114 = + out_sfd__h467227; 2'b11: - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h467225; + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h467224; endcase end - always@(guard__h458480 or sfdin__h466702 or _theResult___sfd__h467225) + always@(guard__h458479 or sfdin__h466701 or _theResult___sfd__h467224) begin - case (guard__h458480) + case (guard__h458479) 2'b0: - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q115 = - sfdin__h466702[56:34]; + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q115 = + sfdin__h466701[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q115 = - _theResult___sfd__h467225; + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q115 = + _theResult___sfd__h467224; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q114 or - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q115 or + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q114 or + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q115 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 or - sfdin__h466702) + sfdin__h466701) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h467303 = - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h467302 = + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q114; 3'd1: - _theResult___fst_sfd__h467303 = - CASE_guard58480_0b0_sfdin66702_BITS_56_TO_34_0_ETC__q115; + _theResult___fst_sfd__h467302 = + CASE_guard58479_0b0_sfdin66701_BITS_56_TO_34_0_ETC__q115; 3'd2: - _theResult___fst_sfd__h467303 = + _theResult___fst_sfd__h467302 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883; 3'd3: - _theResult___fst_sfd__h467303 = + _theResult___fst_sfd__h467302 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885; - 3'd4: _theResult___fst_sfd__h467303 = sfdin__h466702[56:34]; - default: _theResult___fst_sfd__h467303 = 23'd0; + 3'd4: _theResult___fst_sfd__h467302 = sfdin__h466701[56:34]; + default: _theResult___fst_sfd__h467302 = 23'd0; endcase end - always@(guard__h440843 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + always@(guard__h467315 or + _theResult___snd__h475338 or + out_sfd__h475863 or _theResult___sfd__h475860) begin - case (guard__h440843) - 2'b0, 2'b01, 2'b10: - CASE_guard40843_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q116 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard40843_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q116 = - guard__h440843 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard40843_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q116 or - guard__h440843) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - CASE_guard40843_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q116; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - (guard__h440843 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h440843 == 2'b01 || guard__h440843 == 2'b10 || - guard__h440843 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h467316 or - _theResult___snd__h475339 or - out_sfd__h475864 or _theResult___sfd__h475861) - begin - case (guard__h467316) + case (guard__h467315) 2'b0, 2'b01: - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q117 = - _theResult___snd__h475339[56:34]; + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q116 = + _theResult___snd__h475338[56:34]; 2'b10: - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q117 = - out_sfd__h475864; + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q116 = + out_sfd__h475863; 2'b11: - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q117 = - _theResult___sfd__h475861; + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q116 = + _theResult___sfd__h475860; endcase end - always@(guard__h467316 or - _theResult___snd__h475339 or _theResult___sfd__h475861) + always@(guard__h467315 or + _theResult___snd__h475338 or _theResult___sfd__h475860) begin - case (guard__h467316) + case (guard__h467315) 2'b0: - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q118 = - _theResult___snd__h475339[56:34]; + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q117 = + _theResult___snd__h475338[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q118 = - _theResult___sfd__h475861; + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q117 = + _theResult___sfd__h475860; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q117 or - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q118 or + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q116 or + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q117 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 or - _theResult___snd__h475339) + _theResult___snd__h475338) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h475939 = - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q117; + _theResult___fst_sfd__h475938 = + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q116; 3'd1: - _theResult___fst_sfd__h475939 = - CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q118; + _theResult___fst_sfd__h475938 = + CASE_guard67315_0b0_theResult___snd75338_BITS__ETC__q117; 3'd2: - _theResult___fst_sfd__h475939 = + _theResult___fst_sfd__h475938 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902; 3'd3: - _theResult___fst_sfd__h475939 = + _theResult___fst_sfd__h475938 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904; - 3'd4: _theResult___fst_sfd__h475939 = _theResult___snd__h475339[56:34]; - default: _theResult___fst_sfd__h475939 = 23'd0; + 3'd4: _theResult___fst_sfd__h475938 = _theResult___snd__h475338[56:34]; + default: _theResult___fst_sfd__h475938 = 23'd0; endcase end - always@(guard__h440843 or + always@(guard__h440842 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h440843) + case (guard__h440842) 2'b0, 2'b01, 2'b10: - CASE_guard40843_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = + CASE_guard40842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard40843_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = - guard__h440843 != 2'b11 || + CASE_guard40842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + guard__h440842 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard40843_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 or - guard__h440843) + CASE_guard40842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or + guard__h440842) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard40843_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119; + CASE_guard40842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h440843 == 2'b0) ? + (guard__h440842 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h440843 != 2'b01 && guard__h440843 != 2'b10 && - guard__h440843 != 2'b11 || + guard__h440842 != 2'b01 && guard__h440842 != 2'b10 && + guard__h440842 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = @@ -32613,34 +32807,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h449550 or + always@(guard__h440842 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h449550) + case (guard__h440842) 2'b0, 2'b01, 2'b10: - CASE_guard49550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + CASE_guard40842_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard49550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = - guard__h449550 == 2'b11 && + CASE_guard40842_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h440842 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard49550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or - guard__h449550) + CASE_guard40842_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h440842) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = + CASE_guard40842_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = + (guard__h440842 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + (guard__h440842 == 2'b01 || guard__h440842 == 2'b10 || + guard__h440842 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h449549 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h449549) + 2'b0, 2'b01, 2'b10: + CASE_guard49549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard49549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + guard__h449549 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard49549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or + guard__h449549) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard49550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; + CASE_guard49549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - (guard__h449550 == 2'b0) ? + (guard__h449549 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h449550 == 2'b01 || guard__h449550 == 2'b10 || - guard__h449550 == 2'b11) && + (guard__h449549 == 2'b01 || guard__h449549 == 2'b10 || + guard__h449549 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = @@ -32651,34 +32883,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h449550 or + always@(guard__h449549 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h449550) + case (guard__h449549) 2'b0, 2'b01, 2'b10: - CASE_guard49550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + CASE_guard49549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard49550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = - guard__h449550 != 2'b11 || + CASE_guard49549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + guard__h449549 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard49550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or - guard__h449550) + CASE_guard49549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or + guard__h449549) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - CASE_guard49550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; + CASE_guard49549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - (guard__h449550 == 2'b0) ? + (guard__h449549 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h449550 != 2'b01 && guard__h449550 != 2'b10 && - guard__h449550 != 2'b11 || + guard__h449549 != 2'b01 && guard__h449549 != 2'b10 && + guard__h449549 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = @@ -32689,34 +32921,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h458480 or + always@(guard__h458479 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h458480) + case (guard__h458479) 2'b0, 2'b01, 2'b10: - CASE_guard58480_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + CASE_guard58479_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard58480_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = - guard__h458480 == 2'b11 && + CASE_guard58479_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + guard__h458479 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard58480_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or - guard__h458480) + CASE_guard58479_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or + guard__h458479) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - CASE_guard58480_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; + CASE_guard58479_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - (guard__h458480 == 2'b0) ? + (guard__h458479 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h458480 == 2'b01 || guard__h458480 == 2'b10 || - guard__h458480 == 2'b11) && + (guard__h458479 == 2'b01 || guard__h458479 == 2'b10 || + guard__h458479 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = @@ -32727,34 +32959,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h458480 or + always@(guard__h458479 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h458480) + case (guard__h458479) 2'b0, 2'b01, 2'b10: - CASE_guard58480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + CASE_guard58479_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard58480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = - guard__h458480 != 2'b11 || + CASE_guard58479_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + guard__h458479 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard58480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or - guard__h458480) + CASE_guard58479_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or + guard__h458479) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - CASE_guard58480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; + CASE_guard58479_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - (guard__h458480 == 2'b0) ? + (guard__h458479 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h458480 != 2'b01 && guard__h458480 != 2'b10 && - guard__h458480 != 2'b11 || + guard__h458479 != 2'b01 && guard__h458479 != 2'b10 && + guard__h458479 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = @@ -32765,34 +32997,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h467316 or + always@(guard__h467315 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h467316) + case (guard__h467315) 2'b0, 2'b01, 2'b10: - CASE_guard67316_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + CASE_guard67315_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67316_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = - guard__h467316 == 2'b11 && + CASE_guard67315_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + guard__h467315 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67316_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or - guard__h467316) + CASE_guard67315_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or + guard__h467315) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - CASE_guard67316_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; + CASE_guard67315_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - (guard__h467316 == 2'b0) ? + (guard__h467315 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h467316 == 2'b01 || guard__h467316 == 2'b10 || - guard__h467316 == 2'b11) && + (guard__h467315 == 2'b01 || guard__h467315 == 2'b10 || + guard__h467315 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = @@ -32803,34 +33035,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h467316 or + always@(guard__h467315 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h467316) + case (guard__h467315) 2'b0, 2'b01, 2'b10: - CASE_guard67316_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + CASE_guard67315_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67316_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = - guard__h467316 != 2'b11 || + CASE_guard67315_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + guard__h467315 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67316_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or - guard__h467316) + CASE_guard67315_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or + guard__h467315) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - CASE_guard67316_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; + CASE_guard67315_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - (guard__h467316 == 2'b0) ? + (guard__h467315 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h467316 != 2'b01 && guard__h467316 != 2'b10 && - guard__h467316 != 2'b11 || + guard__h467315 != 2'b01 && guard__h467315 != 2'b10 && + guard__h467315 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = @@ -32887,28 +33119,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h497599 or - _theResult___fst_exp__h505560 or _theResult___exp__h506215) + always@(guard__h497598 or + _theResult___fst_exp__h505559 or _theResult___exp__h506214) begin - case (guard__h497599) + case (guard__h497598) 2'b0: - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q135 = - _theResult___fst_exp__h505560; + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q135 = + _theResult___fst_exp__h505559; 2'b01, 2'b10, 2'b11: - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q135 = - _theResult___exp__h506215; + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q135 = + _theResult___exp__h506214; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h505560 or + _theResult___fst_exp__h505559 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9121 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9119 or - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q135) + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9125 = - _theResult___fst_exp__h505560; + _theResult___fst_exp__h505559; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9125 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9121; @@ -32917,40 +33149,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9119; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9125 = - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q135; + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9125 = 11'd0; endcase end - always@(guard__h497599 or - _theResult___fst_exp__h505560 or - out_exp__h506218 or _theResult___exp__h506215) + always@(guard__h497598 or + _theResult___fst_exp__h505559 or + out_exp__h506217 or _theResult___exp__h506214) begin - case (guard__h497599) + case (guard__h497598) 2'b0, 2'b01: - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q136 = - _theResult___fst_exp__h505560; + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q136 = + _theResult___fst_exp__h505559; 2'b10: - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q136 = - out_exp__h506218; + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q136 = + out_exp__h506217; 2'b11: - CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q136 = - _theResult___exp__h506215; + CASE_guard97598_0b0_theResult___fst_exp05559_0_ETC__q136 = + _theResult___exp__h506214; endcase end - always@(guard__h497599 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h497598 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h497599) + case (guard__h497598) 2'b0, 2'b01, 2'b10: - CASE_guard97599_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard97598_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard97599_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h497599 == 2'b11 && + CASE_guard97598_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h497598 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h497599) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h497598) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32958,29 +33190,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h497599 == 2'b0) ? + (guard__h497598 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h497599 == 2'b01 || guard__h497599 == 2'b10 || - guard__h497599 == 2'b11) && + (guard__h497598 == 2'b01 || guard__h497598 == 2'b10 || + guard__h497598 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h506911 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h506910 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h506911) + case (guard__h506910) 2'b0, 2'b01, 2'b10: - CASE_guard06911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard06910_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard06911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h506911 == 2'b11 && + CASE_guard06910_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h506910 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h506911) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h506910) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32988,29 +33220,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h506911 == 2'b0) ? + (guard__h506910 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h506911 == 2'b01 || guard__h506911 == 2'b10 || - guard__h506911 == 2'b11) && + (guard__h506910 == 2'b01 || guard__h506910 == 2'b10 || + guard__h506910 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h515980 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h515979 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h515980) + case (guard__h515979) 2'b0, 2'b01, 2'b10: - CASE_guard15980_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard15979_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard15980_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h515980 == 2'b11 && + CASE_guard15979_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h515979 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h515980) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h515979) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33018,38 +33250,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h515980 == 2'b0) ? + (guard__h515979 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h515980 == 2'b01 || guard__h515980 == 2'b10 || - guard__h515980 == 2'b11) && + (guard__h515979 == 2'b01 || guard__h515979 == 2'b10 || + guard__h515979 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h575601 or - _theResult___fst_exp__h583562 or _theResult___exp__h584217) + always@(guard__h575600 or + _theResult___fst_exp__h583561 or _theResult___exp__h584216) begin - case (guard__h575601) + case (guard__h575600) 2'b0: - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q152 = - _theResult___fst_exp__h583562; + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q152 = + _theResult___fst_exp__h583561; 2'b01, 2'b10, 2'b11: - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q152 = - _theResult___exp__h584217; + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q152 = + _theResult___exp__h584216; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h583562 or + _theResult___fst_exp__h583561 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9831 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9829 or - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q152) + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9835 = - _theResult___fst_exp__h583562; + _theResult___fst_exp__h583561; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9835 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9831; @@ -33058,40 +33290,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9829; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9835 = - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q152; + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9835 = 11'd0; endcase end - always@(guard__h575601 or - _theResult___fst_exp__h583562 or - out_exp__h584220 or _theResult___exp__h584217) + always@(guard__h575600 or + _theResult___fst_exp__h583561 or + out_exp__h584219 or _theResult___exp__h584216) begin - case (guard__h575601) + case (guard__h575600) 2'b0, 2'b01: - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q153 = - _theResult___fst_exp__h583562; + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q153 = + _theResult___fst_exp__h583561; 2'b10: - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q153 = - out_exp__h584220; + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q153 = + out_exp__h584219; 2'b11: - CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q153 = - _theResult___exp__h584217; + CASE_guard75600_0b0_theResult___fst_exp83561_0_ETC__q153 = + _theResult___exp__h584216; endcase end - always@(guard__h575601 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h575600 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h575601) + case (guard__h575600) 2'b0, 2'b01, 2'b10: - CASE_guard75601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard75600_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard75601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h575601 == 2'b11 && + CASE_guard75600_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h575600 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h575601) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h575600) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33099,29 +33331,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h575601 == 2'b0) ? + (guard__h575600 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h575601 == 2'b01 || guard__h575601 == 2'b10 || - guard__h575601 == 2'b11) && + (guard__h575600 == 2'b01 || guard__h575600 == 2'b10 || + guard__h575600 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h584913 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h584912 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h584913) + case (guard__h584912) 2'b0, 2'b01, 2'b10: - CASE_guard84913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard84912_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard84913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h584913 == 2'b11 && + CASE_guard84912_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h584912 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h584913) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h584912) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33129,29 +33361,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h584913 == 2'b0) ? + (guard__h584912 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h584913 == 2'b01 || guard__h584913 == 2'b10 || - guard__h584913 == 2'b11) && + (guard__h584912 == 2'b01 || guard__h584912 == 2'b10 || + guard__h584912 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h593982 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h593981 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h593982) + case (guard__h593981) 2'b0, 2'b01, 2'b10: - CASE_guard93982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard93981_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard93982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h593982 == 2'b11 && + CASE_guard93981_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h593981 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h593982) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h593981) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33159,29 +33391,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h593982 == 2'b0) ? + (guard__h593981 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h593982 == 2'b01 || guard__h593982 == 2'b10 || - guard__h593982 == 2'b11) && + (guard__h593981 == 2'b01 || guard__h593981 == 2'b10 || + guard__h593981 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h584913 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h584912 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h584913) + case (guard__h584912) 2'b0, 2'b01, 2'b10: - CASE_guard84913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard84912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard84913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h584913 != 2'b11 || + CASE_guard84912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h584912 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h584913) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h584912) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33189,29 +33421,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h584913 == 2'b0) ? + (guard__h584912 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h584913 != 2'b01 && guard__h584913 != 2'b10 && - guard__h584913 != 2'b11 || + guard__h584912 != 2'b01 && guard__h584912 != 2'b10 && + guard__h584912 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h593982 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h593981 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h593982) + case (guard__h593981) 2'b0, 2'b01, 2'b10: - CASE_guard93982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard93981_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard93982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h593982 != 2'b11 || + CASE_guard93981_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h593981 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h593982) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h593981) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33219,29 +33451,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h593982 == 2'b0) ? + (guard__h593981 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h593982 != 2'b01 && guard__h593982 != 2'b10 && - guard__h593982 != 2'b11 || + guard__h593981 != 2'b01 && guard__h593981 != 2'b10 && + guard__h593981 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h575601 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h575600 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h575601) + case (guard__h575600) 2'b0, 2'b01, 2'b10: - CASE_guard75601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard75600_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard75601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h575601 != 2'b11 || + CASE_guard75600_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h575600 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h575601) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h575600) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33249,38 +33481,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h575601 == 2'b0) ? + (guard__h575600 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h575601 != 2'b01 && guard__h575601 != 2'b10 && - guard__h575601 != 2'b11 || + guard__h575600 != 2'b01 && guard__h575600 != 2'b10 && + guard__h575600 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h536400 or - _theResult___fst_exp__h544361 or _theResult___exp__h545016) + always@(guard__h536399 or + _theResult___fst_exp__h544360 or _theResult___exp__h545015) begin - case (guard__h536400) + case (guard__h536399) 2'b0: - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q175 = - _theResult___fst_exp__h544361; + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q175 = + _theResult___fst_exp__h544360; 2'b01, 2'b10, 2'b11: - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q175 = - _theResult___exp__h545016; + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q175 = + _theResult___exp__h545015; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h544361 or + _theResult___fst_exp__h544360 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10594 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10592 or - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q175) + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10598 = - _theResult___fst_exp__h544361; + _theResult___fst_exp__h544360; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10598 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10594; @@ -33289,49 +33521,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10592; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10598 = - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q175; + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10598 = 11'd0; endcase end - always@(guard__h536400 or - _theResult___fst_exp__h544361 or - out_exp__h545019 or _theResult___exp__h545016) + always@(guard__h536399 or + _theResult___fst_exp__h544360 or + out_exp__h545018 or _theResult___exp__h545015) begin - case (guard__h536400) + case (guard__h536399) 2'b0, 2'b01: - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q176 = - _theResult___fst_exp__h544361; + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q176 = + _theResult___fst_exp__h544360; 2'b10: - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q176 = - out_exp__h545019; + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q176 = + out_exp__h545018; 2'b11: - CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q176 = - _theResult___exp__h545016; + CASE_guard36399_0b0_theResult___fst_exp44360_0_ETC__q176 = + _theResult___exp__h545015; endcase end - always@(guard__h545712 or - _theResult___fst_exp__h553938 or _theResult___exp__h554667) + always@(guard__h545711 or + _theResult___fst_exp__h553937 or _theResult___exp__h554666) begin - case (guard__h545712) + case (guard__h545711) 2'b0: - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q177 = - _theResult___fst_exp__h553938; + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q177 = + _theResult___fst_exp__h553937; 2'b01, 2'b10, 2'b11: - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q177 = - _theResult___exp__h554667; + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q177 = + _theResult___exp__h554666; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h553938 or + _theResult___fst_exp__h553937 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10632 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10630 or - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q177) + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10636 = - _theResult___fst_exp__h553938; + _theResult___fst_exp__h553937; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10636 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10632; @@ -33340,49 +33572,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10630; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10636 = - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q177; + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10636 = 11'd0; endcase end - always@(guard__h545712 or - _theResult___fst_exp__h553938 or - out_exp__h554670 or _theResult___exp__h554667) + always@(guard__h545711 or + _theResult___fst_exp__h553937 or + out_exp__h554669 or _theResult___exp__h554666) begin - case (guard__h545712) + case (guard__h545711) 2'b0, 2'b01: - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q178 = - _theResult___fst_exp__h553938; + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q178 = + _theResult___fst_exp__h553937; 2'b10: - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q178 = - out_exp__h554670; + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q178 = + out_exp__h554669; 2'b11: - CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q178 = - _theResult___exp__h554667; + CASE_guard45711_0b0_theResult___fst_exp53937_0_ETC__q178 = + _theResult___exp__h554666; endcase end - always@(guard__h554781 or - _theResult___fst_exp__h562771 or _theResult___exp__h563451) + always@(guard__h554780 or + _theResult___fst_exp__h562770 or _theResult___exp__h563450) begin - case (guard__h554781) + case (guard__h554780) 2'b0: - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q179 = - _theResult___fst_exp__h562771; + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q179 = + _theResult___fst_exp__h562770; 2'b01, 2'b10, 2'b11: - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q179 = - _theResult___exp__h563451; + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q179 = + _theResult___exp__h563450; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h562771 or + _theResult___fst_exp__h562770 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10663 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10661 or - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q179) + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10667 = - _theResult___fst_exp__h562771; + _theResult___fst_exp__h562770; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10667 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10663; @@ -33391,49 +33623,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10661; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10667 = - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q179; + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10667 = 11'd0; endcase end - always@(guard__h554781 or - _theResult___fst_exp__h562771 or - out_exp__h563454 or _theResult___exp__h563451) + always@(guard__h554780 or + _theResult___fst_exp__h562770 or + out_exp__h563453 or _theResult___exp__h563450) begin - case (guard__h554781) + case (guard__h554780) 2'b0, 2'b01: - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q180 = - _theResult___fst_exp__h562771; + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q180 = + _theResult___fst_exp__h562770; 2'b10: - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q180 = - out_exp__h563454; + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q180 = + out_exp__h563453; 2'b11: - CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q180 = - _theResult___exp__h563451; + CASE_guard54780_0b0_theResult___fst_exp62770_0_ETC__q180 = + _theResult___exp__h563450; endcase end - always@(guard__h584913 or - _theResult___fst_exp__h593139 or _theResult___exp__h593868) + always@(guard__h584912 or + _theResult___fst_exp__h593138 or _theResult___exp__h593867) begin - case (guard__h584913) + case (guard__h584912) 2'b0: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181 = - _theResult___fst_exp__h593139; + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q181 = + _theResult___fst_exp__h593138; 2'b01, 2'b10, 2'b11: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181 = - _theResult___exp__h593868; + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q181 = + _theResult___exp__h593867; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h593139 or + _theResult___fst_exp__h593138 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9869 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9867 or - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181) + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 = - _theResult___fst_exp__h593139; + _theResult___fst_exp__h593138; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9869; @@ -33442,49 +33674,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9867; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 = - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181; + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 = 11'd0; endcase end - always@(guard__h584913 or - _theResult___fst_exp__h593139 or - out_exp__h593871 or _theResult___exp__h593868) + always@(guard__h584912 or + _theResult___fst_exp__h593138 or + out_exp__h593870 or _theResult___exp__h593867) begin - case (guard__h584913) + case (guard__h584912) 2'b0, 2'b01: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 = - _theResult___fst_exp__h593139; + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q182 = + _theResult___fst_exp__h593138; 2'b10: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 = - out_exp__h593871; + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q182 = + out_exp__h593870; 2'b11: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 = - _theResult___exp__h593868; + CASE_guard84912_0b0_theResult___fst_exp93138_0_ETC__q182 = + _theResult___exp__h593867; endcase end - always@(guard__h593982 or - _theResult___fst_exp__h601972 or _theResult___exp__h602652) + always@(guard__h593981 or + _theResult___fst_exp__h601971 or _theResult___exp__h602651) begin - case (guard__h593982) + case (guard__h593981) 2'b0: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183 = - _theResult___fst_exp__h601972; + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q183 = + _theResult___fst_exp__h601971; 2'b01, 2'b10, 2'b11: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183 = - _theResult___exp__h602652; + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q183 = + _theResult___exp__h602651; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h601972 or + _theResult___fst_exp__h601971 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9900 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9898 or - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183) + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = - _theResult___fst_exp__h601972; + _theResult___fst_exp__h601971; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9900; @@ -33493,40 +33725,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9898; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183; + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = 11'd0; endcase end - always@(guard__h593982 or - _theResult___fst_exp__h601972 or - out_exp__h602655 or _theResult___exp__h602652) + always@(guard__h593981 or + _theResult___fst_exp__h601971 or + out_exp__h602654 or _theResult___exp__h602651) begin - case (guard__h593982) + case (guard__h593981) 2'b0, 2'b01: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 = - _theResult___fst_exp__h601972; + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q184 = + _theResult___fst_exp__h601971; 2'b10: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 = - out_exp__h602655; + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q184 = + out_exp__h602654; 2'b11: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 = - _theResult___exp__h602652; + CASE_guard93981_0b0_theResult___fst_exp01971_0_ETC__q184 = + _theResult___exp__h602651; endcase end - always@(guard__h536400 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h545711 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h536400) + case (guard__h545711) 2'b0, 2'b01, 2'b10: - CASE_guard36400_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard45711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard36400_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h536400 == 2'b11 && + CASE_guard45711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h545711 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536400) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h545711) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33534,29 +33766,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h536400 == 2'b0) ? + (guard__h545711 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h536400 == 2'b01 || guard__h536400 == 2'b10 || - guard__h536400 == 2'b11) && + (guard__h545711 == 2'b01 || guard__h545711 == 2'b10 || + guard__h545711 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h545712 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h536399 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h545712) + case (guard__h536399) 2'b0, 2'b01, 2'b10: - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard36399_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h545712 == 2'b11 && + CASE_guard36399_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h536399 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h545712) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536399) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33564,29 +33796,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h545712 == 2'b0) ? + (guard__h536399 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h545712 == 2'b01 || guard__h545712 == 2'b10 || - guard__h545712 == 2'b11) && + (guard__h536399 == 2'b01 || guard__h536399 == 2'b10 || + guard__h536399 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h554781 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h554780 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h554781) + case (guard__h554780) 2'b0, 2'b01, 2'b10: - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard54780_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h554781 == 2'b11 && + CASE_guard54780_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h554780 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h554781) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h554780) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33594,29 +33826,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h554781 == 2'b0) ? + (guard__h554780 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h554781 == 2'b01 || guard__h554781 == 2'b10 || - guard__h554781 == 2'b11) && + (guard__h554780 == 2'b01 || guard__h554780 == 2'b10 || + guard__h554780 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h545712 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h545711 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h545712) + case (guard__h545711) 2'b0, 2'b01, 2'b10: - CASE_guard45712_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard45711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard45712_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h545712 != 2'b11 || + CASE_guard45711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h545711 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h545712) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h545711) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33624,29 +33856,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h545712 == 2'b0) ? + (guard__h545711 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h545712 != 2'b01 && guard__h545712 != 2'b10 && - guard__h545712 != 2'b11 || + guard__h545711 != 2'b01 && guard__h545711 != 2'b10 && + guard__h545711 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h554781 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h536399 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h554781) + case (guard__h536399) 2'b0, 2'b01, 2'b10: - CASE_guard54781_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard36399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard54781_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h554781 != 2'b11 || + CASE_guard36399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h536399 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h554781) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536399) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33654,29 +33886,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h554781 == 2'b0) ? + (guard__h536399 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h554781 != 2'b01 && guard__h554781 != 2'b10 && - guard__h554781 != 2'b11 || + guard__h536399 != 2'b01 && guard__h536399 != 2'b10 && + guard__h536399 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h536400 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h554780 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h536400) + case (guard__h554780) 2'b0, 2'b01, 2'b10: - CASE_guard36400_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard54780_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard36400_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h536400 != 2'b11 || + CASE_guard54780_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h554780 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536400) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h554780) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33684,38 +33916,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h536400 == 2'b0) ? + (guard__h554780 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h536400 != 2'b01 && guard__h536400 != 2'b10 && - guard__h536400 != 2'b11 || + guard__h554780 != 2'b01 && guard__h554780 != 2'b10 && + guard__h554780 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h536400 or - _theResult___snd__h544312 or _theResult___sfd__h545017) + always@(guard__h536399 or + _theResult___snd__h544311 or _theResult___sfd__h545016) begin - case (guard__h536400) + case (guard__h536399) 2'b0: - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q197 = - _theResult___snd__h544312[56:5]; + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q197 = + _theResult___snd__h544311[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q197 = - _theResult___sfd__h545017; + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q197 = + _theResult___sfd__h545016; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h544312 or + _theResult___snd__h544311 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10689 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10687 or - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q197) + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10693 = - _theResult___snd__h544312[56:5]; + _theResult___snd__h544311[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10693 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10689; @@ -33724,98 +33956,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10687; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10693 = - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q197; + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10693 = 52'd0; endcase end - always@(guard__h536400 or - _theResult___snd__h544312 or - out_sfd__h545020 or _theResult___sfd__h545017) + always@(guard__h536399 or + _theResult___snd__h544311 or + out_sfd__h545019 or _theResult___sfd__h545016) begin - case (guard__h536400) + case (guard__h536399) 2'b0, 2'b01: - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q198 = - _theResult___snd__h544312[56:5]; + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q198 = + _theResult___snd__h544311[56:5]; 2'b10: - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q198 = - out_sfd__h545020; + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q198 = + out_sfd__h545019; 2'b11: - CASE_guard36400_0b0_theResult___snd44312_BITS__ETC__q198 = - _theResult___sfd__h545017; + CASE_guard36399_0b0_theResult___snd44311_BITS__ETC__q198 = + _theResult___sfd__h545016; endcase end - always@(guard__h545712 or sfdin__h553932 or _theResult___sfd__h554668) + always@(guard__h554780 or + _theResult___snd__h562716 or _theResult___sfd__h563451) begin - case (guard__h545712) + case (guard__h554780) 2'b0: - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h553932[56:5]; + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q199 = + _theResult___snd__h562716[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h554668; + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q199 = + _theResult___sfd__h563451; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h553932 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10715 or - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10713 or - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q199) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = - sfdin__h553932[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10715; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = - IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10713; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q199; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = - 52'd0; - endcase - end - always@(guard__h545712 or - sfdin__h553932 or out_sfd__h554671 or _theResult___sfd__h554668) - begin - case (guard__h545712) - 2'b0, 2'b01: - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h553932[56:5]; - 2'b10: - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h554671; - 2'b11: - CASE_guard45712_0b0_sfdin53932_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h554668; - endcase - end - always@(guard__h554781 or - _theResult___snd__h562717 or _theResult___sfd__h563452) - begin - case (guard__h554781) - 2'b0: - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q201 = - _theResult___snd__h562717[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q201 = - _theResult___sfd__h563452; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h562717 or + _theResult___snd__h562716 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10734 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10732 or - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q201) + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10738 = - _theResult___snd__h562717[56:5]; + _theResult___snd__h562716[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10738 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10734; @@ -33824,49 +34007,98 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10732; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10738 = - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q201; + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10738 = 52'd0; endcase end - always@(guard__h554781 or - _theResult___snd__h562717 or - out_sfd__h563455 or _theResult___sfd__h563452) + always@(guard__h554780 or + _theResult___snd__h562716 or + out_sfd__h563454 or _theResult___sfd__h563451) begin - case (guard__h554781) + case (guard__h554780) 2'b0, 2'b01: - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q202 = - _theResult___snd__h562717[56:5]; + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q200 = + _theResult___snd__h562716[56:5]; 2'b10: - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q202 = - out_sfd__h563455; + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q200 = + out_sfd__h563454; 2'b11: - CASE_guard54781_0b0_theResult___snd62717_BITS__ETC__q202 = - _theResult___sfd__h563452; + CASE_guard54780_0b0_theResult___snd62716_BITS__ETC__q200 = + _theResult___sfd__h563451; endcase end - always@(guard__h506911 or - _theResult___fst_exp__h515137 or _theResult___exp__h515866) + always@(guard__h545711 or sfdin__h553931 or _theResult___sfd__h554667) begin - case (guard__h506911) + case (guard__h545711) 2'b0: - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q203 = - _theResult___fst_exp__h515137; + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q201 = + sfdin__h553931[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q203 = - _theResult___exp__h515866; + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q201 = + _theResult___sfd__h554667; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h515137 or + sfdin__h553931 or + IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10715 or + IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10713 or + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q201) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = + sfdin__h553931[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = + IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10715; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = + IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10713; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q201; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719 = + 52'd0; + endcase + end + always@(guard__h545711 or + sfdin__h553931 or out_sfd__h554670 or _theResult___sfd__h554667) + begin + case (guard__h545711) + 2'b0, 2'b01: + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q202 = + sfdin__h553931[56:5]; + 2'b10: + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q202 = + out_sfd__h554670; + 2'b11: + CASE_guard45711_0b0_sfdin53931_BITS_56_TO_5_0b_ETC__q202 = + _theResult___sfd__h554667; + endcase + end + always@(guard__h506910 or + _theResult___fst_exp__h515136 or _theResult___exp__h515865) + begin + case (guard__h506910) + 2'b0: + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q203 = + _theResult___fst_exp__h515136; + 2'b01, 2'b10, 2'b11: + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q203 = + _theResult___exp__h515865; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h515136 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9164 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9162 or - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q203) + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9168 = - _theResult___fst_exp__h515137; + _theResult___fst_exp__h515136; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9168 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9164; @@ -33875,49 +34107,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9162; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9168 = - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q203; + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9168 = 11'd0; endcase end - always@(guard__h506911 or - _theResult___fst_exp__h515137 or - out_exp__h515869 or _theResult___exp__h515866) + always@(guard__h506910 or + _theResult___fst_exp__h515136 or + out_exp__h515868 or _theResult___exp__h515865) begin - case (guard__h506911) + case (guard__h506910) 2'b0, 2'b01: - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q204 = - _theResult___fst_exp__h515137; + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q204 = + _theResult___fst_exp__h515136; 2'b10: - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q204 = - out_exp__h515869; + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q204 = + out_exp__h515868; 2'b11: - CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q204 = - _theResult___exp__h515866; + CASE_guard06910_0b0_theResult___fst_exp15136_0_ETC__q204 = + _theResult___exp__h515865; endcase end - always@(guard__h515980 or - _theResult___fst_exp__h523970 or _theResult___exp__h524650) + always@(guard__h515979 or + _theResult___fst_exp__h523969 or _theResult___exp__h524649) begin - case (guard__h515980) + case (guard__h515979) 2'b0: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205 = - _theResult___fst_exp__h523970; + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q205 = + _theResult___fst_exp__h523969; 2'b01, 2'b10, 2'b11: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205 = - _theResult___exp__h524650; + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q205 = + _theResult___exp__h524649; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h523970 or + _theResult___fst_exp__h523969 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9195 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9193 or - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205) + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 = - _theResult___fst_exp__h523970; + _theResult___fst_exp__h523969; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9195; @@ -33926,49 +34158,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9193; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 = - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205; + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 = 11'd0; endcase end - always@(guard__h515980 or - _theResult___fst_exp__h523970 or - out_exp__h524653 or _theResult___exp__h524650) + always@(guard__h515979 or + _theResult___fst_exp__h523969 or + out_exp__h524652 or _theResult___exp__h524649) begin - case (guard__h515980) + case (guard__h515979) 2'b0, 2'b01: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 = - _theResult___fst_exp__h523970; + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q206 = + _theResult___fst_exp__h523969; 2'b10: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 = - out_exp__h524653; + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q206 = + out_exp__h524652; 2'b11: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 = - _theResult___exp__h524650; + CASE_guard15979_0b0_theResult___fst_exp23969_0_ETC__q206 = + _theResult___exp__h524649; endcase end - always@(guard__h497599 or - _theResult___snd__h505511 or _theResult___sfd__h506216) + always@(guard__h497598 or + _theResult___snd__h505510 or _theResult___sfd__h506215) begin - case (guard__h497599) + case (guard__h497598) 2'b0: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207 = - _theResult___snd__h505511[56:5]; + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q207 = + _theResult___snd__h505510[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207 = - _theResult___sfd__h506216; + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q207 = + _theResult___sfd__h506215; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h505511 or + _theResult___snd__h505510 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9221 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9219 or - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207) + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = - _theResult___snd__h505511[56:5]; + _theResult___snd__h505510[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9221; @@ -33977,48 +34209,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9219; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207; + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = 52'd0; endcase end - always@(guard__h497599 or - _theResult___snd__h505511 or - out_sfd__h506219 or _theResult___sfd__h506216) + always@(guard__h497598 or + _theResult___snd__h505510 or + out_sfd__h506218 or _theResult___sfd__h506215) begin - case (guard__h497599) + case (guard__h497598) 2'b0, 2'b01: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 = - _theResult___snd__h505511[56:5]; + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q208 = + _theResult___snd__h505510[56:5]; 2'b10: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 = - out_sfd__h506219; + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q208 = + out_sfd__h506218; 2'b11: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 = - _theResult___sfd__h506216; + CASE_guard97598_0b0_theResult___snd05510_BITS__ETC__q208 = + _theResult___sfd__h506215; endcase end - always@(guard__h506911 or sfdin__h515131 or _theResult___sfd__h515867) + always@(guard__h506910 or sfdin__h515130 or _theResult___sfd__h515866) begin - case (guard__h506911) + case (guard__h506910) 2'b0: - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q209 = - sfdin__h515131[56:5]; + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q209 = + sfdin__h515130[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q209 = - _theResult___sfd__h515867; + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q209 = + _theResult___sfd__h515866; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h515131 or + sfdin__h515130 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9248 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9246 or - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q209) + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9252 = - sfdin__h515131[56:5]; + sfdin__h515130[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9252 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9248; @@ -34027,48 +34259,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9246; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9252 = - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q209; + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9252 = 52'd0; endcase end - always@(guard__h506911 or - sfdin__h515131 or out_sfd__h515870 or _theResult___sfd__h515867) + always@(guard__h506910 or + sfdin__h515130 or out_sfd__h515869 or _theResult___sfd__h515866) begin - case (guard__h506911) + case (guard__h506910) 2'b0, 2'b01: - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q210 = - sfdin__h515131[56:5]; + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q210 = + sfdin__h515130[56:5]; 2'b10: - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q210 = - out_sfd__h515870; + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q210 = + out_sfd__h515869; 2'b11: - CASE_guard06911_0b0_sfdin15131_BITS_56_TO_5_0b_ETC__q210 = - _theResult___sfd__h515867; + CASE_guard06910_0b0_sfdin15130_BITS_56_TO_5_0b_ETC__q210 = + _theResult___sfd__h515866; endcase end - always@(guard__h515980 or - _theResult___snd__h523916 or _theResult___sfd__h524651) + always@(guard__h515979 or + _theResult___snd__h523915 or _theResult___sfd__h524650) begin - case (guard__h515980) + case (guard__h515979) 2'b0: - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q211 = - _theResult___snd__h523916[56:5]; + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q211 = + _theResult___snd__h523915[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q211 = - _theResult___sfd__h524651; + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q211 = + _theResult___sfd__h524650; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h523916 or + _theResult___snd__h523915 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9267 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9265 or - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q211) + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9271 = - _theResult___snd__h523916[56:5]; + _theResult___snd__h523915[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9271 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9267; @@ -34077,49 +34309,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9265; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9271 = - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q211; + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9271 = 52'd0; endcase end - always@(guard__h515980 or - _theResult___snd__h523916 or - out_sfd__h524654 or _theResult___sfd__h524651) + always@(guard__h515979 or + _theResult___snd__h523915 or + out_sfd__h524653 or _theResult___sfd__h524650) begin - case (guard__h515980) + case (guard__h515979) 2'b0, 2'b01: - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q212 = - _theResult___snd__h523916[56:5]; + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q212 = + _theResult___snd__h523915[56:5]; 2'b10: - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q212 = - out_sfd__h524654; + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q212 = + out_sfd__h524653; 2'b11: - CASE_guard15980_0b0_theResult___snd23916_BITS__ETC__q212 = - _theResult___sfd__h524651; + CASE_guard15979_0b0_theResult___snd23915_BITS__ETC__q212 = + _theResult___sfd__h524650; endcase end - always@(guard__h575601 or - _theResult___snd__h583513 or _theResult___sfd__h584218) + always@(guard__h575600 or + _theResult___snd__h583512 or _theResult___sfd__h584217) begin - case (guard__h575601) + case (guard__h575600) 2'b0: - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q213 = - _theResult___snd__h583513[56:5]; + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q213 = + _theResult___snd__h583512[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q213 = - _theResult___sfd__h584218; + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q213 = + _theResult___sfd__h584217; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h583513 or + _theResult___snd__h583512 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9926 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9924 or - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q213) + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9930 = - _theResult___snd__h583513[56:5]; + _theResult___snd__h583512[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9930 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9926; @@ -34128,48 +34360,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9924; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9930 = - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q213; + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9930 = 52'd0; endcase end - always@(guard__h575601 or - _theResult___snd__h583513 or - out_sfd__h584221 or _theResult___sfd__h584218) + always@(guard__h575600 or + _theResult___snd__h583512 or + out_sfd__h584220 or _theResult___sfd__h584217) begin - case (guard__h575601) + case (guard__h575600) 2'b0, 2'b01: - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q214 = - _theResult___snd__h583513[56:5]; + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q214 = + _theResult___snd__h583512[56:5]; 2'b10: - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q214 = - out_sfd__h584221; + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q214 = + out_sfd__h584220; 2'b11: - CASE_guard75601_0b0_theResult___snd83513_BITS__ETC__q214 = - _theResult___sfd__h584218; + CASE_guard75600_0b0_theResult___snd83512_BITS__ETC__q214 = + _theResult___sfd__h584217; endcase end - always@(guard__h584913 or sfdin__h593133 or _theResult___sfd__h593869) + always@(guard__h584912 or sfdin__h593132 or _theResult___sfd__h593868) begin - case (guard__h584913) + case (guard__h584912) 2'b0: - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h593133[56:5]; + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h593132[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h593869; + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h593868; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h593133 or + sfdin__h593132 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9952 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9950 or - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q215) + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9956 = - sfdin__h593133[56:5]; + sfdin__h593132[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9956 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9952; @@ -34178,24 +34410,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9950; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9956 = - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q215; + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9956 = 52'd0; endcase end - always@(guard__h584913 or - sfdin__h593133 or out_sfd__h593872 or _theResult___sfd__h593869) + always@(guard__h584912 or + sfdin__h593132 or out_sfd__h593871 or _theResult___sfd__h593868) begin - case (guard__h584913) + case (guard__h584912) 2'b0, 2'b01: - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h593133[56:5]; + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h593132[56:5]; 2'b10: - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h593872; + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h593871; 2'b11: - CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h593869; + CASE_guard84912_0b0_sfdin93132_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h593868; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34230,28 +34462,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10944; endcase end - always@(guard__h593982 or - _theResult___snd__h601918 or _theResult___sfd__h602653) + always@(guard__h593981 or + _theResult___snd__h601917 or _theResult___sfd__h602652) begin - case (guard__h593982) + case (guard__h593981) 2'b0: - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q217 = - _theResult___snd__h601918[56:5]; + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q217 = + _theResult___snd__h601917[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q217 = - _theResult___sfd__h602653; + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q217 = + _theResult___sfd__h602652; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h601918 or + _theResult___snd__h601917 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9971 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9969 or - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q217) + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9975 = - _theResult___snd__h601918[56:5]; + _theResult___snd__h601917[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9975 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9971; @@ -34260,25 +34492,25 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9969; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9975 = - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q217; + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9975 = 52'd0; endcase end - always@(guard__h593982 or - _theResult___snd__h601918 or - out_sfd__h602656 or _theResult___sfd__h602653) + always@(guard__h593981 or + _theResult___snd__h601917 or + out_sfd__h602655 or _theResult___sfd__h602652) begin - case (guard__h593982) + case (guard__h593981) 2'b0, 2'b01: - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q218 = - _theResult___snd__h601918[56:5]; + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q218 = + _theResult___snd__h601917[56:5]; 2'b10: - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q218 = - out_sfd__h602656; + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q218 = + out_sfd__h602655; 2'b11: - CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q218 = - _theResult___sfd__h602653; + CASE_guard93981_0b0_theResult___snd01917_BITS__ETC__q218 = + _theResult___sfd__h602652; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34477,74 +34709,29 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[67:64]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 = fetchStage$pipelines_0_first[67:64]; 4'd11: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd10; + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 = 4'd10; 4'd12: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd11; + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 = 4'd11; 4'd13: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd12; - default: IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 = 4'd12; + default: IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13174 = 4'd13; endcase end always@(fetchStage$pipelines_0_first) - begin - case (fetchStage$pipelines_0_first[172:161]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_fetchStagepipelines_0_first_BITS_172_TO__ETC__q225 = - fetchStage$pipelines_0_first[172:161]; - default: CASE_fetchStagepipelines_0_first_BITS_172_TO__ETC__q225 = - 12'd2303; - endcase - end - always@(fetchStage$pipelines_0_first) begin case (fetchStage$pipelines_0_first[177:175]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q226 = + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = fetchStage$pipelines_0_first[177:175]; - default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q226 = 3'd7; + default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = 3'd7; endcase end always@(fetchStage$pipelines_0_first or - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q226) + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: @@ -34555,7 +34742,7 @@ module mkCore(CLK, { fetchStage$pipelines_0_first[194:192], 9'h0AA, fetchStage$pipelines_0_first[182:178], - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q226, + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, fetchStage$pipelines_0_first[174] }; default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961 = 21'd1485482; @@ -34565,24 +34752,21 @@ module mkCore(CLK, begin case (checkForException___d13069[3:0]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 = + CASE_checkForException_3069_BITS_3_TO_0_0_chec_ETC__q226 = checkForException___d13069[3:0]; - 4'd11: - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 = 4'd10; - 4'd12: - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 = 4'd11; - 4'd13: - IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 = 4'd12; - default: IF_checkForException_3069_BIT_4_3070_THEN_IF_c_ETC___d13168 = + 4'd11: CASE_checkForException_3069_BITS_3_TO_0_0_chec_ETC__q226 = 4'd10; + 4'd12: CASE_checkForException_3069_BITS_3_TO_0_0_chec_ETC__q226 = 4'd11; + 4'd13: CASE_checkForException_3069_BITS_3_TO_0_0_chec_ETC__q226 = 4'd12; + default: CASE_checkForException_3069_BITS_3_TO_0_0_chec_ETC__q226 = 4'd13; endcase end - always@(IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13245) + always@(IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13280) begin - case (IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13245) + case (IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13280) 4'd0, 4'd1: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863__ETC__q227 = - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13245; + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3__ETC___d13280; 4'd2: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863__ETC__q227 = 4'd3; 4'd3: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863__ETC__q227 = 4'd4; 4'd4: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2863__ETC__q227 = 4'd5; @@ -34594,15 +34778,15 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h669941 or + always@(k__h671298 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669941) + case (k__h671298) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -34611,69 +34795,69 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13414 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13473 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13414 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13473 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13414 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13473 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410; + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469; endcase end - always@(k__h669941 or + always@(k__h671298 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669941) + case (k__h671298) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or regRenamingTable$rename_0_canRename or - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13433 or + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13492 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13433; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13492; 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 && + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378; + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13438 = + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437; + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13497 = regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378; + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13437; endcase end always@(fetchStage$pipelines_0_first or @@ -34681,32 +34865,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13469 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13529 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13469 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13529 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13469 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13529 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464); + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524); endcase end always@(fetchStage$pipelines_1_first) @@ -34768,36 +34952,36 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529 = + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589 = fetchStage$pipelines_1_first[194:174]; 3'd4: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529 = + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589 = { fetchStage$pipelines_1_first[194:192], 9'h0AA, fetchStage$pipelines_1_first[182:178], CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13529 = + default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13589 = 21'd1485482; endcase end - always@(idx__h684592 or + always@(idx__h686610 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13647 or + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13725 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13653 or + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13731 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h684592) + case (idx__h686610) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13647 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13725 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13653 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13731 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -34813,61 +34997,72 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 or - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724 or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 or + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13814 or + NOT_coreFix_memExe_rsMem_canEnq__3460_3521_OR__ETC___d13817 or + NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13816) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13730 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 || - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13724; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 || + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13814; 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13730 = - !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 || - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 = + NOT_coreFix_memExe_rsMem_canEnq__3460_3521_OR__ETC___d13817; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13730 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13730 = - fetchStage_pipelines_0_first__2835_BIT_68_2862_ETC___d13072; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 = + NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13816; + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 = + fetchStage$pipelines_0_first[68] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[0] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[1] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[2] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[3] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[4] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[5] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[6] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[7] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[8] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[9] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[10] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[11] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[12] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[13] || + IF_IF_NOT_csrf_prv_reg_read__2863_EQ_3_2864_28_ETC___d12904[14]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398) + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13751 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13751 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13841 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457; + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13841 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410; + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13768 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13858 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13768 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13858 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13768 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13858 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410; + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469; endcase end always@(fetchStage$pipelines_1_first or @@ -34883,46 +35078,34 @@ module mkCore(CLK, end always@(fetchStage$pipelines_1_first or regRenamingTable$rename_1_canRename or - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13638 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670 or - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13736 or - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13765 or - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13774 or - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13748 or + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13716 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750 or + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13826 or + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13855 or + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13864 or + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13838 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13757) + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13847) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670 && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13736; + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750 && + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13826; 3'd2: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 = - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13765 && + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 = + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13855 && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13774; + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13864; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 = - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13748 && + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 = + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13838 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13757; - default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13779 = + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13847; + default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13869 = regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13638; - endcase - end - always@(k__h669941 or - coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) - begin - case (k__h669941) - 1'd0: - CASE_k69941_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = - coreFix_aluExe_0_rsAlu$RDY_enq; - 1'd1: - CASE_k69941_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = - coreFix_aluExe_1_rsAlu$RDY_enq; + NOT_fetchStage_pipelines_1_first__2844_BITS_19_ETC___d13716; endcase end always@(fetchStage$pipelines_0_first or @@ -34930,130 +35113,142 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = coreFix_memExe_lsq$RDY_enqSt; endcase end + always@(k__h671298 or + coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) + begin + case (k__h671298) + 1'd0: + CASE_k71298_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + coreFix_aluExe_0_rsAlu$RDY_enq; + 1'd1: + CASE_k71298_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + coreFix_aluExe_1_rsAlu$RDY_enq; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13822 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13913 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13822 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13913 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13822 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13913 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464); + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 or - regRenamingTable_RDY_rename_0_getRename__3276__ETC___d13816 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 or + regRenamingTable_RDY_rename_0_getRename__3311__ETC___d13907 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13803 or + _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13894 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 || + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13911 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13803; + _0_OR_NOT_fetchStage_pipelines_0_first__2835_BI_ETC___d13894; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13911 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13820 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13911 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 || - regRenamingTable_RDY_rename_0_getRename__3276__ETC___d13816; + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 || + regRenamingTable_RDY_rename_0_getRename__3311__ETC___d13907; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13836 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13927 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13836 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13927 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13836 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13927 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464); + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13843 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__338_ETC___d13431 && + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13934 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13490 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13843 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13934 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13843 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13934 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13410; + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13469; endcase end - always@(idx__h684592 or + always@(idx__h686610 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13859 or + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13950 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13866 or + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13957 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h684592) + case (idx__h686610) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13870 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13961 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13859) && + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13950) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13870 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13961 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13866) && + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13957) && coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13878 or + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13969 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13885 or + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13976 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin case (fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13878 || + NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13969 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13885) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13976) 1'd0: CASE_fetchStagepipelines_0_canDeq_AND_NOT_fet_ETC__q234 = coreFix_aluExe_0_rsAlu$RDY_enq; @@ -35075,82 +35270,82 @@ module mkCore(CLK, end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398) + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13912 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13912 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14003 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457; + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14003 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464); + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524); endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398 or + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13923 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3388_co_ETC___d13398; + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14014 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3447_co_ETC___d13457; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13923 = + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14014 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d13923 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d14014 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13464; + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d13524; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13899 or + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13990 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13924 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670 or - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13920) + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14015 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750 or + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14011) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13934 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13670; + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14025 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2833_AN_ETC___d13750; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13934 = - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13920; - default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13934 = + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14025 = + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d14011; + default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14025 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - (fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13899 || + (fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13990 || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d13924); + fetchStage_pipelines_0_first__2835_BITS_194_TO_ETC___d14015); endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13899 or + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13990 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13904 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13870 or - regRenamingTable_RDY_rename_1_getRename__3872__ETC___d13890 or - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13892 or + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13995 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13961 or + regRenamingTable_RDY_rename_1_getRename__3963__ETC___d13981 or + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13983 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13895) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13986) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13909 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13870 || - regRenamingTable_RDY_rename_1_getRename__3872__ETC___d13890; + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14000 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__283_ETC___d13961 || + regRenamingTable_RDY_rename_1_getRename__3963__ETC___d13981; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13909 = - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13892 || + IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14000 = + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13983 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13895; - default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d13909 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13986; + default: IF_fetchStage_pipelines_1_first__2844_BITS_194_ETC___d14000 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13899 || + fetchStage_pipelines_0_canDeq__2833_AND_regRen_ETC___d13990 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13904; + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d13995; endcase end always@(fetchStage$pipelines_0_first or @@ -35158,9 +35353,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14006 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14098 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14006 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14098 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -35169,20 +35364,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14003 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14003 = - coreFix_memExe_lsq$enqStTag[5]; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14012 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14104 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14012 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14104 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -35191,9 +35375,20 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14009 = + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14095 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14095 = + coreFix_memExe_lsq$enqStTag[5]; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14101 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14009 = + default: IF_fetchStage_pipelines_0_first__2835_BITS_191_ETC___d14101 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -35202,9 +35397,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14169 = + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14264 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14169 = + default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14264 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -35213,9 +35408,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14167 = + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14262 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14167 = + default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14262 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -35224,9 +35419,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14166 = + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14261 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14166 = + default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14261 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -35235,9 +35430,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14168 = + IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14263 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14168 = + default: IF_fetchStage_pipelines_1_first__2844_BITS_191_ETC___d14263 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -35245,78 +35440,78 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd0; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd1; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd2; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd8; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd9; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd10; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd11; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd12; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd13; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd14; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd15; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd16; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd17; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd18; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd19; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd20; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd21; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd22; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd23; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd24; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd25; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd26; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd27; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd28; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd29; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd29; 12'd2048: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd6; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd7; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd30; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd31; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd3; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd4; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd5; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd32; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd33; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd34; + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 = + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 = 6'd36; endcase end @@ -37972,21 +38167,21 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == 6'd6) + IF_rob_deqPort_0_deq_data__4334_BIT_181_4563_T_ETC___d14637 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_IF_rob_deqPort_0_deq_data__4241_BITS_97_TO_ETC___d14730) + NOT_IF_rob_deqPort_0_deq_data__4334_BITS_97_TO_ETC___d14823) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_IF_rob_deqPort_0_deq_data__4241_BITS_97_TO_ETC___d14730) + NOT_IF_rob_deqPort_0_deq_data__4334_BITS_97_TO_ETC___d14823) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 506, column 39\nppc must be pc + 4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_IF_rob_deqPort_0_deq_data__4241_BITS_97_TO_ETC___d14730) + NOT_IF_rob_deqPort_0_deq_data__4334_BITS_97_TO_ETC___d14823) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -38002,15 +38197,15 @@ module mkCore(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14740) + NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14833) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14740) + NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14833) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 550, column 54\nonly CSR has valid csr idx"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14740) + NOT_rob_deqPort_0_deq_data__4334_BITS_186_TO_1_ETC___d14833) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -38175,7 +38370,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", commitStage_rg_instret + - IF_rob_deqPort_0_canDeq__4759_THEN_IF_NOT_rob__ETC___d14868, + IF_rob_deqPort_0_canDeq__4852_THEN_IF_NOT_rob__ETC___d14961, rob$deqPort_1_deq_data[282:219], rob$deqPort_1_deq_data[218:187], " iType:"); @@ -38468,21 +38663,21 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12049[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624307)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624308)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12049[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624307)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624308)) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 279, column 84\nCsr inst ppc = pc+4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12049[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624307)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624308)) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -39329,15 +39524,15 @@ module mkCore(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h607990 == 2'd0) + v__h607989 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h607990 == 2'd0) + v__h607989 == 2'd0) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv\", line 172, column 38\ncredit underflow"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h607990 == 2'd0) + v__h607989 == 2'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -39346,7 +39541,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && specTagManager$currentSpecBits != 12'd0) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 352, column 34\ncannot have spec bits"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 394, column 34\ncannot have spec bits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && specTagManager$currentSpecBits != 12'd0) @@ -39360,7 +39555,7 @@ module mkCore(CLK, if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[199:195] != 5'd13) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 377, column 42\nonly CSR inst send to exe"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 419, column 42\nonly CSR inst send to exe"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[194:192] == 3'd0 && @@ -39381,7 +39576,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd16 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 384, column 22\nnon-CSR inst not send to exe"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 426, column 22\nnon-CSR inst not send to exe"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[194:192] != 3'd0 && @@ -39405,7 +39600,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd2 || fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4)) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 386, column 22\nnon-exe inst exec func is other"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 428, column 22\nnon-exe inst exec func is other"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[194:192] != 3'd0 && @@ -39423,7 +39618,7 @@ module mkCore(CLK, if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[75] && fetchStage$pipelines_0_first[74]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 405, column 29\nsystem inst never touches FP regs"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 447, column 29\nsystem inst never touches FP regs"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[75] && @@ -39432,149 +39627,149 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13989) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14081) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13989) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 814, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14081) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 857, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13989) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14081) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13994) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14086) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13994) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 815, column 59\nFpuMulDiv never explicitly read/write CSR"); + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14086) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 858, column 59\nFpuMulDiv never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d13994) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14086) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14019) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14111) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14019) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 846, column 65\nMem next PC is not PC+4/PC+2"); + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14111) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 889, column 65\nMem next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14019) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14111) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14023) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14115) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14023) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 847, column 63\nMem never explicitly read/write CSR"); + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14115) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 890, column 63\nMem never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14023) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14115) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14029) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14121) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14029) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 849, column 42\nMem (non-Fence) needs imm for virtual addr"); + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14121) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 892, column 42\nMem (non-Fence) needs imm for virtual addr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3362_AND__ETC___d14029) + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14121) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14151) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14246) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14151) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 814, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14246) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 857, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14151) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14246) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14157) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14252) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14157) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 815, column 59\nFpuMulDiv never explicitly read/write CSR"); + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14252) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 858, column 59\nFpuMulDiv never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14157) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14252) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14176) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14271) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14176) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 846, column 65\nMem next PC is not PC+4/PC+2"); + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14271) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 889, column 65\nMem next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14176) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14271) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14180) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14275) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14180) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 847, column 63\nMem never explicitly read/write CSR"); + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14275) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 890, column 63\nMem never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14180) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14275) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14186) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14281) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14186) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 849, column 42\nMem (non-Fence) needs imm for virtual addr"); + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14281) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 892, column 42\nMem (non-Fence) needs imm for virtual addr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14083 && - regRenamingTable_rename_1_canRename__3475_AND__ETC___d14186) + NOT_fetchStage_pipelines_0_canDeq__2833_2834_O_ETC___d14178 && + regRenamingTable_rename_1_canRename__3535_AND__ETC___d14281) $finish(32'd0); end // synopsys translate_on diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v index 1727e7e..23b4916 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v @@ -2009,16 +2009,17 @@ module mkCoreW(CLK, // rule RL_rl_cpu_hart0_reset_from_soc_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && proc$RDY_hart0_server_reset_request_put && + plic$RDY_server_reset_request_put && + fabric_2x3$RDY_reset && f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; // rule RL_rl_cpu_hart0_reset_complete assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - plic$RDY_server_reset_response_get && proc$RDY_start && - proc$RDY_hart0_server_reset_response_get && + proc$RDY_start && proc$RDY_hart0_server_reset_response_get && + plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; @@ -2038,15 +2039,16 @@ module mkCoreW(CLK, // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; assign f_reset_reqs$DEQ = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && proc$RDY_hart0_server_reset_request_put && + plic$RDY_server_reset_request_put && + fabric_2x3$RDY_reset && f_reset_reqs$EMPTY_N ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps assign f_reset_rsps$ENQ = - plic$RDY_server_reset_response_get && proc$RDY_start && - proc$RDY_hart0_server_reset_response_get && + proc$RDY_start && proc$RDY_hart0_server_reset_response_get && + plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N ; assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; assign f_reset_rsps$CLR = 1'b0 ; diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDTlbSynth.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDTlbSynth.v index deca5f7..315e915 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDTlbSynth.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDTlbSynth.v @@ -1346,10 +1346,10 @@ module mkDTlbSynth(CLK, wire [31 : 0] MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1; wire [5 : 0] MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1, MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2; - wire [3 : 0] MUX_m_pendWait_0$write_1__VAL_2, - MUX_m_pendWait_1$write_1__VAL_2, - MUX_m_pendWait_2$write_1__VAL_2, - MUX_m_pendWait_3$write_1__VAL_2; + wire [3 : 0] MUX_m_pendWait_0$write_1__VAL_1, + MUX_m_pendWait_1$write_1__VAL_1, + MUX_m_pendWait_2$write_1__VAL_1, + MUX_m_pendWait_3$write_1__VAL_1; wire [2 : 0] MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1, MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2, MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3; @@ -1422,7 +1422,7 @@ module mkDTlbSynth(CLK, SEL_ARR_m_ldTransRsFromPQ_data_0_00_BITS_54_TO_ETC___d791, ppn__h121971; reg [26 : 0] CASE_level9044_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q2, - CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3, + CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4, CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q13, CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q14, CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q15, @@ -1433,7 +1433,7 @@ module mkDTlbSynth(CLK, CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q20, CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q21, CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22, - CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q4, + CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3, CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23, CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q24, CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q25, @@ -2771,14 +2771,10 @@ module mkDTlbSynth(CLK, WILL_FIRE_RL_m_doPoisonedProcResp && idx__h105839 == 2'd3 ; assign MUX_m_pendValid_3_dummy2_0$write_1__SEL_2 = EN_deqProcResp && idx__h124884 == 2'd3 ; - assign MUX_m_pendWait_0$write_1__SEL_1 = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd0 ; - assign MUX_m_pendWait_1$write_1__SEL_1 = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd1 ; - assign MUX_m_pendWait_2$write_1__SEL_1 = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd2 ; - assign MUX_m_pendWait_3$write_1__SEL_1 = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd3 ; + assign MUX_m_pendWait_0$write_1__SEL_1 = EN_procReq && _dfoo63 ; + assign MUX_m_pendWait_1$write_1__SEL_1 = EN_procReq && _dfoo61 ; + assign MUX_m_pendWait_2$write_1__SEL_1 = EN_procReq && _dfoo59 ; + assign MUX_m_pendWait_3$write_1__SEL_1 = EN_procReq && _dfoo57 ; assign MUX_m_tlb_m_updRepIdx_dummy2_1$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && !SEL_ARR_m_pendPoisoned_0_12_m_pendPoisoned_1_1_ETC___d717 && @@ -2925,25 +2921,25 @@ module mkDTlbSynth(CLK, (SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2949 ? DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2951 : { procReq_req[76:13], 5'd10 }) ; - assign MUX_m_pendWait_0$write_1__VAL_2 = + assign MUX_m_pendWait_0$write_1__VAL_1 = SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2898 ? 4'd2 : (SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2946 ? 4'd2 : _dfoo32) ; - assign MUX_m_pendWait_1$write_1__VAL_2 = + assign MUX_m_pendWait_1$write_1__VAL_1 = SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2899 ? 4'd2 : (SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2947 ? 4'd2 : _dfoo30) ; - assign MUX_m_pendWait_2$write_1__VAL_2 = + assign MUX_m_pendWait_2$write_1__VAL_1 = SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2900 ? 4'd2 : (SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2948 ? 4'd2 : _dfoo28) ; - assign MUX_m_pendWait_3$write_1__VAL_2 = + assign MUX_m_pendWait_3$write_1__VAL_1 = SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2901 ? 4'd2 : (SEL_ARR_m_freeQ_data_0_079_m_freeQ_data_1_080__ETC___d2949 ? @@ -3349,38 +3345,38 @@ module mkDTlbSynth(CLK, // register m_pendWait_0 assign m_pendWait_0$D_IN = MUX_m_pendWait_0$write_1__SEL_1 ? - 4'd2 : - MUX_m_pendWait_0$write_1__VAL_2 ; + MUX_m_pendWait_0$write_1__VAL_1 : + 4'd2 ; assign m_pendWait_0$EN = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd0 || - EN_procReq && _dfoo63 ; + EN_procReq && _dfoo63 || + WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd0 ; // register m_pendWait_1 assign m_pendWait_1$D_IN = MUX_m_pendWait_1$write_1__SEL_1 ? - 4'd2 : - MUX_m_pendWait_1$write_1__VAL_2 ; + MUX_m_pendWait_1$write_1__VAL_1 : + 4'd2 ; assign m_pendWait_1$EN = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd1 || - EN_procReq && _dfoo61 ; + EN_procReq && _dfoo61 || + WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd1 ; // register m_pendWait_2 assign m_pendWait_2$D_IN = MUX_m_pendWait_2$write_1__SEL_1 ? - 4'd2 : - MUX_m_pendWait_2$write_1__VAL_2 ; + MUX_m_pendWait_2$write_1__VAL_1 : + 4'd2 ; assign m_pendWait_2$EN = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd2 || - EN_procReq && _dfoo59 ; + EN_procReq && _dfoo59 || + WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd2 ; // register m_pendWait_3 assign m_pendWait_3$D_IN = MUX_m_pendWait_3$write_1__SEL_1 ? - 4'd2 : - MUX_m_pendWait_3$write_1__VAL_2 ; + MUX_m_pendWait_3$write_1__VAL_1 : + 4'd2 ; assign m_pendWait_3$EN = - WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd3 || - EN_procReq && _dfoo57 ; + EN_procReq && _dfoo57 || + WILL_FIRE_RL_m_doPRs && idx__h68669 == 2'd3 ; // register m_perfReqQ_clearReq_rl assign m_perfReqQ_clearReq_rl$D_IN = 1'd0 ; @@ -5166,7 +5162,7 @@ module mkDTlbSynth(CLK, CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22 == m_tlb_m_entryVec_19[79:53] ; assign IF_m_tlb_m_entryVec_1_62_BITS_1_TO_0_66_EQ_0_1_ETC___d2119 = - CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q4 == + CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 == m_tlb_m_entryVec_1[79:53] ; assign IF_m_tlb_m_entryVec_20_166_BITS_1_TO_0_170_EQ__ETC___d2309 = CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23 == @@ -5760,7 +5756,7 @@ module mkDTlbSynth(CLK, !m_tlb_m_updRepIdx_rl[5] ; assign NOT_m_tlb_m_validVec_0_34_35_OR_NOT_IF_m_tlb_m_ETC___d2112 = !m_tlb_m_validVec_0 || - CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 != + CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 != m_tlb_m_entryVec_0[79:53] ; assign NOT_m_tlb_m_validVec_0_34_35_OR_NOT_IF_m_tlb_m_ETC___d2132 = NOT_m_tlb_m_validVec_0_34_35_OR_NOT_IF_m_tlb_m_ETC___d2112 && @@ -6726,18 +6722,6 @@ module mkDTlbSynth(CLK, 2'd3: idx__h106632 = m_freeQ_data_3; endcase end - always@(m_ldTransRsFromPQ_deqP or - m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) - begin - case (m_ldTransRsFromPQ_deqP) - 1'd0: - SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 = - m_ldTransRsFromPQ_data_0[6]; - 1'd1: - SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 = - m_ldTransRsFromPQ_data_1[6]; - endcase - end always@(m_ldTransRsFromPQ_deqP or m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) begin @@ -6820,6 +6804,18 @@ module mkDTlbSynth(CLK, !m_ldTransRsFromPQ_data_1[4]; endcase end + always@(m_ldTransRsFromPQ_deqP or + m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) + begin + case (m_ldTransRsFromPQ_deqP) + 1'd0: + SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 = + m_ldTransRsFromPQ_data_0[6]; + 1'd1: + SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 = + m_ldTransRsFromPQ_data_1[6]; + endcase + end always@(m_ldTransRsFromPQ_deqP or m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) begin @@ -6888,6 +6884,18 @@ module mkDTlbSynth(CLK, m_ldTransRsFromPQ_data_1[4]; endcase end + always@(m_ldTransRsFromPQ_deqP or + m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) + begin + case (m_ldTransRsFromPQ_deqP) + 1'd0: + SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 = + !m_ldTransRsFromPQ_data_0[10]; + 1'd1: + SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 = + !m_ldTransRsFromPQ_data_1[10]; + endcase + end always@(m_ldTransRsFromPQ_deqP or m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) begin @@ -6912,18 +6920,6 @@ module mkDTlbSynth(CLK, m_ldTransRsFromPQ_data_1[81:55]; endcase end - always@(m_ldTransRsFromPQ_deqP or - m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) - begin - case (m_ldTransRsFromPQ_deqP) - 1'd0: - SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 = - !m_ldTransRsFromPQ_data_0[10]; - 1'd1: - SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 = - !m_ldTransRsFromPQ_data_1[10]; - endcase - end always@(m_ldTransRsFromPQ_deqP or m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1) begin @@ -7063,34 +7059,34 @@ module mkDTlbSynth(CLK, m_pendWait_3[3:2] == 2'd0; endcase end - always@(m_tlb_m_entryVec_0 or procReq_req) - begin - case (m_tlb_m_entryVec_0[1:0]) - 2'd0: - CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 = - procReq_req[51:25]; - 2'd1: - CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 = - { procReq_req[51:34], 9'd0 }; - 2'd2: - CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 = - { procReq_req[51:43], 18'd0 }; - 2'd3: CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 = 27'd0; - endcase - end always@(m_tlb_m_entryVec_1 or procReq_req) begin case (m_tlb_m_entryVec_1[1:0]) 2'd0: - CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q4 = + CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 = procReq_req[51:25]; 2'd1: - CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q4 = + CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 = { procReq_req[51:34], 9'd0 }; 2'd2: - CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q4 = + CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 = { procReq_req[51:43], 18'd0 }; - 2'd3: CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q4 = 27'd0; + 2'd3: CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 = 27'd0; + endcase + end + always@(m_tlb_m_entryVec_0 or procReq_req) + begin + case (m_tlb_m_entryVec_0[1:0]) + 2'd0: + CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 = + procReq_req[51:25]; + 2'd1: + CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 = + { procReq_req[51:34], 9'd0 }; + 2'd2: + CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 = + { procReq_req[51:43], 18'd0 }; + 2'd3: CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 = 27'd0; endcase end always@(m_tlb_m_entryVec_2 or procReq_req) @@ -8795,31 +8791,6 @@ module mkDTlbSynth(CLK, 4'd9; endcase end - always@(idx__h124884 or - IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or - IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or - IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 or - IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160) - begin - case (idx__h124884) - 2'd0: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = - IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 == - 4'd7; - 2'd1: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = - IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 == - 4'd7; - 2'd2: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = - IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 == - 4'd7; - 2'd3: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = - IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160 == - 4'd7; - endcase - end always@(idx__h124884 or IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or @@ -8845,6 +8816,31 @@ module mkDTlbSynth(CLK, 4'd8; endcase end + always@(idx__h124884 or + IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or + IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or + IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 or + IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160) + begin + case (idx__h124884) + 2'd0: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = + IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 == + 4'd7; + 2'd1: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = + IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 == + 4'd7; + 2'd2: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = + IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 == + 4'd7; + 2'd3: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3205 = + IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160 == + 4'd7; + endcase + end always@(idx__h124884 or IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or @@ -8870,6 +8866,31 @@ module mkDTlbSynth(CLK, 4'd6; endcase end + always@(idx__h124884 or + IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or + IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or + IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 or + IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160) + begin + case (idx__h124884) + 2'd0: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = + IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 == + 4'd1; + 2'd1: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = + IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 == + 4'd1; + 2'd2: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = + IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 == + 4'd1; + 2'd3: + SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = + IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160 == + 4'd1; + endcase + end always@(idx__h124884 or IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or @@ -8970,31 +8991,6 @@ module mkDTlbSynth(CLK, 4'd2; endcase end - always@(idx__h124884 or - IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or - IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or - IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 or - IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160) - begin - case (idx__h124884) - 2'd0: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = - IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 == - 4'd1; - 2'd1: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = - IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 == - 4'd1; - 2'd2: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = - IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 == - 4'd1; - 2'd3: - SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 = - IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160 == - 4'd1; - endcase - end always@(idx__h124884 or IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or @@ -9224,24 +9220,6 @@ module mkDTlbSynth(CLK, m_pendInst_3[65]; endcase end - always@(idx__h124884 or - m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) - begin - case (idx__h124884) - 2'd0: - SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = - m_pendInst_0[89:85]; - 2'd1: - SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = - m_pendInst_1[89:85]; - 2'd2: - SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = - m_pendInst_2[89:85]; - 2'd3: - SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = - m_pendInst_3[89:85]; - endcase - end always@(idx__h124884 or m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) begin @@ -9260,6 +9238,24 @@ module mkDTlbSynth(CLK, m_pendInst_3[90]; endcase end + always@(idx__h124884 or + m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) + begin + case (idx__h124884) + 2'd0: + SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = + m_pendInst_0[89:85]; + 2'd1: + SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = + m_pendInst_1[89:85]; + 2'd2: + SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = + m_pendInst_2[89:85]; + 2'd3: + SEL_ARR_m_pendInst_0_23_BITS_89_TO_85_258_m_pe_ETC___d3263 = + m_pendInst_3[89:85]; + endcase + end always@(idx__h124884 or m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) begin @@ -9296,24 +9292,6 @@ module mkDTlbSynth(CLK, m_pendInst_3[64:1]; endcase end - always@(idx__h124884 or - m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) - begin - case (idx__h124884) - 2'd0: - SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = - m_pendInst_0[0]; - 2'd1: - SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = - m_pendInst_1[0]; - 2'd2: - SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = - m_pendInst_2[0]; - 2'd3: - SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = - m_pendInst_3[0]; - endcase - end always@(idx__h124884 or m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) begin @@ -9332,6 +9310,24 @@ module mkDTlbSynth(CLK, m_pendInst_3[77:73]; endcase end + always@(idx__h124884 or + m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) + begin + case (idx__h124884) + 2'd0: + SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = + m_pendInst_0[0]; + 2'd1: + SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = + m_pendInst_1[0]; + 2'd2: + SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = + m_pendInst_2[0]; + 2'd3: + SEL_ARR_m_pendInst_0_23_BIT_0_349_m_pendInst_1_ETC___d3354 = + m_pendInst_3[0]; + endcase + end always@(idx__h124884 or m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3) begin diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v index 687d7b3..a056b58 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v @@ -2711,21 +2711,21 @@ module mkFetchStage(CLK, SEL_ARR_IF_rg_pending_straddle_555_THEN_IF_SEL_ETC___d4385; reg [11 : 0] CASE_decode_217_BITS_72_TO_61_1_decode_217_BIT_ETC__q4, CASE_decode_805_BITS_72_TO_61_1_decode_805_BIT_ETC__q7, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q208; - reg [9 : 0] CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, + reg [9 : 0] CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q209; reg [4 : 0] CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q189, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q192, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202, + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q58, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q61, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199, - CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207, + CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q37, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q66; @@ -2765,7 +2765,7 @@ module mkFetchStage(CLK, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q29, SEL_ARR_instdata_data_0_727_BITS_195_TO_194_74_ETC___d4750, SEL_ARR_instdata_data_0_727_BITS_65_TO_64_728__ETC___d4735; - reg CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q201, + reg CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q202, CASE_f32d_deqP_0_IF_f32d_data_0_719_BITS_73_TO_ETC__q38, CASE_f32d_deqP_0_IF_f32d_data_0_719_BITS_73_TO_ETC__q39, CASE_f32d_deqP_0_IF_f32d_data_0_719_BITS_73_TO_ETC__q40, @@ -2817,8 +2817,8 @@ module mkFetchStage(CLK, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q169, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206, + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26, @@ -11336,7 +11336,7 @@ module mkFetchStage(CLK, assign IF_iTlb_to_proc_response_get_410_BIT_4_411_THE_ETC___d3506 = { x__h117460, !iTlb$to_proc_response_get[4] && mmio$getFetchTarget == 2'd1, - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q201, + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q202, out_main_epoch__h117169 } ; assign IF_instdata_deqP_lat_0_whas__77_THEN_instdata__ETC___d780 = CAN_FIRE_RL_doDecode ? upd__h140802 : instdata_deqP_rl ; @@ -12071,10 +12071,10 @@ module mkFetchStage(CLK, CAN_FIRE_RL_setTrainNAPByDec || !napTrainByDecQ_full_rl) ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d5583 = - { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, + { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 } ; + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206, + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d5640 = { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q8, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q9, @@ -12105,7 +12105,7 @@ module mkFetchStage(CLK, IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d5742, SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d5670 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d5953 = - { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202, + { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, IF_SEL_ARR_out_fifo_internalFifos_0_first__552_ETC___d5749, NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d5952 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d6167 = @@ -12151,7 +12151,7 @@ module mkFetchStage(CLK, IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6221, SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d6201 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d6309 = - { CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207, + { CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, IF_SEL_ARR_out_fifo_internalFifos_0_first__552_ETC___d6228, NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6308 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d6372 = @@ -13276,20 +13276,20 @@ module mkFetchStage(CLK, f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin case (f22f3_deqP) - 2'd0: value__h118386 = f22f3_data_0[267]; - 2'd1: value__h118386 = f22f3_data_1[267]; - 2'd2: value__h118386 = f22f3_data_2[267]; - 2'd3: value__h118386 = f22f3_data_3[267]; + 2'd0: value__h118398 = f22f3_data_0[202:139]; + 2'd1: value__h118398 = f22f3_data_1[202:139]; + 2'd2: value__h118398 = f22f3_data_2[202:139]; + 2'd3: value__h118398 = f22f3_data_3[202:139]; endcase end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin case (f22f3_deqP) - 2'd0: value__h118398 = f22f3_data_0[202:139]; - 2'd1: value__h118398 = f22f3_data_1[202:139]; - 2'd2: value__h118398 = f22f3_data_2[202:139]; - 2'd3: value__h118398 = f22f3_data_3[202:139]; + 2'd0: value__h118386 = f22f3_data_0[267]; + 2'd1: value__h118386 = f22f3_data_1[267]; + 2'd2: value__h118386 = f22f3_data_2[267]; + 2'd3: value__h118386 = f22f3_data_3[267]; endcase end always@(f22f3_deqP or @@ -16119,17 +16119,6 @@ module mkFetchStage(CLK, f32d_data_1[267]; endcase end - always@(f32d_deqP or f32d_data_0 or f32d_data_1) - begin - case (f32d_deqP) - 1'd0: - SEL_ARR_NOT_f32d_data_0_719_BIT_74_795_796_NOT_ETC___d4800 = - !f32d_data_0[74]; - 1'd1: - SEL_ARR_NOT_f32d_data_0_719_BIT_74_795_796_NOT_ETC___d4800 = - !f32d_data_1[74]; - endcase - end always@(n__read__h143420 or instdata_data_0 or instdata_data_1) begin case (n__read__h143420) @@ -16141,6 +16130,17 @@ module mkFetchStage(CLK, instdata_data_1[63:32]; endcase end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + SEL_ARR_NOT_f32d_data_0_719_BIT_74_795_796_NOT_ETC___d4800 = + !f32d_data_0[74]; + 1'd1: + SEL_ARR_NOT_f32d_data_0_719_BIT_74_795_796_NOT_ETC___d4800 = + !f32d_data_1[74]; + endcase + end always@(n__read__h143420 or instdata_data_0 or instdata_data_1) begin case (n__read__h143420) @@ -18982,26 +18982,38 @@ module mkFetchStage(CLK, !out_fifo_internalFifos_1$D_OUT[68]; endcase end - always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) - begin - case (f12f2_deqP) - 1'd0: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q201 = - f12f2_data_0[4]; - 1'd1: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q201 = - f12f2_data_1[4]; - endcase - end always@(x__h63248 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201 = out_fifo_internalFifos_0$D_OUT[199:195]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201 = + out_fifo_internalFifos_1$D_OUT[199:195]; + endcase + end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q202 = + f12f2_data_0[4]; + 1'd1: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q202 = + f12f2_data_1[4]; + endcase + end + always@(x__h73310 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h73310) + 1'd0: + CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = + out_fifo_internalFifos_0$D_OUT[199:195]; + 1'd1: + CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = out_fifo_internalFifos_1$D_OUT[199:195]; endcase end @@ -19010,10 +19022,10 @@ module mkFetchStage(CLK, begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = out_fifo_internalFifos_0$D_OUT[255:244]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = out_fifo_internalFifos_1$D_OUT[255:244]; endcase end @@ -19022,10 +19034,10 @@ module mkFetchStage(CLK, begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = out_fifo_internalFifos_0$D_OUT[243:234]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = out_fifo_internalFifos_1$D_OUT[243:234]; endcase end @@ -19034,10 +19046,10 @@ module mkFetchStage(CLK, begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = out_fifo_internalFifos_0$D_OUT[233]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = out_fifo_internalFifos_1$D_OUT[233]; endcase end @@ -19046,25 +19058,13 @@ module mkFetchStage(CLK, begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = out_fifo_internalFifos_0$D_OUT[232]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = out_fifo_internalFifos_1$D_OUT[232]; endcase end - always@(x__h73310 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h73310) - 1'd0: - CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = - out_fifo_internalFifos_0$D_OUT[199:195]; - 1'd1: - CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = - out_fifo_internalFifos_1$D_OUT[199:195]; - endcase - end always@(x__h73310 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivDispToRegFifo.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivDispToRegFifo.v index f1f59af..ba878bd 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivDispToRegFifo.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivDispToRegFifo.v @@ -101,6 +101,7 @@ module mkFpuMulDivDispToRegFifo(CLK, RDY_specUpdate_incorrectSpeculation; // inlined wires + wire [11 : 0] m_m_specBits_0_lat_1$wget; wire m_m_valid_0_lat_0$whas; // register m_m_row_0 @@ -259,6 +260,8 @@ module mkFpuMulDivDispToRegFifo(CLK, // inlined wires assign m_m_valid_0_lat_0$whas = MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ; + assign m_m_specBits_0_lat_1$wget = + sb__h9495 & specUpdate_correctSpeculation_mask ; // register m_m_row_0 assign m_m_row_0$D_IN = @@ -318,7 +321,7 @@ module mkFpuMulDivDispToRegFifo(CLK, m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 : 12'd0 ; - assign upd__h2327 = sb__h9495 & specUpdate_correctSpeculation_mask ; + assign upd__h2327 = m_m_specBits_0_lat_1$wget ; always@(enq_x) begin case (enq_x[60:58]) diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivRegToExeFifo.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivRegToExeFifo.v index 9841b8e..4217c3e 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivRegToExeFifo.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivRegToExeFifo.v @@ -101,6 +101,7 @@ module mkFpuMulDivRegToExeFifo(CLK, RDY_specUpdate_incorrectSpeculation; // inlined wires + wire [11 : 0] m_m_specBits_0_lat_1$wget; wire m_m_valid_0_lat_0$whas; // register m_m_row_0 @@ -259,6 +260,8 @@ module mkFpuMulDivRegToExeFifo(CLK, // inlined wires assign m_m_valid_0_lat_0$whas = MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ; + assign m_m_specBits_0_lat_1$wget = + sb__h9109 & specUpdate_correctSpeculation_mask ; // register m_m_row_0 assign m_m_row_0$D_IN = @@ -318,7 +321,7 @@ module mkFpuMulDivRegToExeFifo(CLK, m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 : 12'd0 ; - assign upd__h2327 = sb__h9109 & specUpdate_correctSpeculation_mask ; + assign upd__h2327 = m_m_specBits_0_lat_1$wget ; always@(enq_x) begin case (enq_x[228:226]) diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v index 274f0af..27fb37b 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v @@ -1622,12 +1622,12 @@ module mkLLCache(CLK, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q78, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q79, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q82, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q83, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q84, @@ -1738,6 +1738,7 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62, @@ -1748,10 +1749,9 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q112, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q113, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q116, @@ -3810,7 +3810,7 @@ module mkLLCache(CLK, SEL_ARR_cache_rqFromDmaQ_data_0_367_BIT_580_81_ETC___d2044, _1_CONCAT_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_ETC___d2062 } ; assign MUX_cache_cRqMshr$transfer_getEmptyEntryInit_2__VAL_2 = - { !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 || + { !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882, SEL_ARR_cache_rqFromDmaQ_data_0_367_BITS_516_T_ETC___d2164 } ; assign MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_1 = @@ -5807,7 +5807,7 @@ module mkLLCache(CLK, cache_cRqMshr$pipelineResp_getAddrSucc, 1'd0 } ; assign IF_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_ETC___d1884 = - (!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 || + (!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882) ? 2'd3 : 2'd1 ; @@ -6790,128 +6790,128 @@ module mkLLCache(CLK, perfReqQ_enqReq_lat_0$wget[4] : perfReqQ_enqReq_rl[4] ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 ; + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 ; assign NOT_SEL_ARR_NOT_cache_rsFromCQ_data_0_171_BIT__ETC___d2229 = { !CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249, @@ -7446,10 +7446,10 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q232, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q233 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2205 = - { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 } ; + { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2214 = { SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2205, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q78, @@ -8187,14 +8187,6 @@ module mkLLCache(CLK, cache_rsStToDmaQ_data_1[2:0]; endcase end - always@(cache_rqFromCQ_deqP or - cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) - begin - case (cache_rqFromCQ_deqP) - 1'd0: x__h237718 = cache_rqFromCQ_data_0[3:1]; - 1'd1: x__h237718 = cache_rqFromCQ_data_1[3:1]; - endcase - end always@(cache_cRqRetryIndexQ_deqP or cache_cRqRetryIndexQ_data_0 or cache_cRqRetryIndexQ_data_1 or @@ -8231,6 +8223,14 @@ module mkLLCache(CLK, 4'd15: x__h230768 = cache_cRqRetryIndexQ_data_15; endcase end + always@(cache_rqFromCQ_deqP or + cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) + begin + case (cache_rqFromCQ_deqP) + 1'd0: x__h237718 = cache_rqFromCQ_data_0[3:1]; + 1'd1: x__h237718 = cache_rqFromCQ_data_1[3:1]; + endcase + end always@(cache_rqFromCQ_deqP or cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) begin @@ -8291,63 +8291,15 @@ module mkLLCache(CLK, 1'd1: x__h255367 = cache_rsFromCQ_data_1[0]; endcase end - always@(cache_rsFromCQ_deqP or - cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) - begin - case (cache_rsFromCQ_deqP) - 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6 = - cache_rsFromCQ_data_0[512:449]; - 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6 = - cache_rsFromCQ_data_1[512:449]; - endcase - end - always@(cache_rsFromCQ_deqP or - cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) - begin - case (cache_rsFromCQ_deqP) - 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7 = - cache_rsFromCQ_data_0[448:385]; - 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7 = - cache_rsFromCQ_data_1[448:385]; - endcase - end - always@(cache_rsFromCQ_deqP or - cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) - begin - case (cache_rsFromCQ_deqP) - 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8 = - cache_rsFromCQ_data_0[384:321]; - 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8 = - cache_rsFromCQ_data_1[384:321]; - endcase - end - always@(cache_rsFromCQ_deqP or - cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) - begin - case (cache_rsFromCQ_deqP) - 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 = - cache_rsFromCQ_data_0[320:257]; - 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 = - cache_rsFromCQ_data_1[320:257]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 = !cache_rqFromDmaQ_data_0[578]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 = !cache_rqFromDmaQ_data_1[578]; endcase end @@ -8356,10 +8308,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 = !cache_rqFromDmaQ_data_0[579]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 = !cache_rqFromDmaQ_data_1[579]; endcase end @@ -8368,10 +8320,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 = !cache_rqFromDmaQ_data_0[580]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 = !cache_rqFromDmaQ_data_1[580]; endcase end @@ -8380,10 +8332,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 = !cache_rqFromDmaQ_data_0[576]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 = !cache_rqFromDmaQ_data_1[576]; endcase end @@ -8392,10 +8344,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = !cache_rqFromDmaQ_data_0[577]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = !cache_rqFromDmaQ_data_1[577]; endcase end @@ -8404,10 +8356,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = !cache_rqFromDmaQ_data_0[574]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = !cache_rqFromDmaQ_data_1[574]; endcase end @@ -8416,10 +8368,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = !cache_rqFromDmaQ_data_0[575]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = !cache_rqFromDmaQ_data_1[575]; endcase end @@ -8428,10 +8380,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = !cache_rqFromDmaQ_data_0[572]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = !cache_rqFromDmaQ_data_1[572]; endcase end @@ -8440,10 +8392,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = !cache_rqFromDmaQ_data_0[573]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = !cache_rqFromDmaQ_data_1[573]; endcase end @@ -8452,10 +8404,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = !cache_rqFromDmaQ_data_0[570]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = !cache_rqFromDmaQ_data_1[570]; endcase end @@ -8464,10 +8416,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = !cache_rqFromDmaQ_data_0[571]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = !cache_rqFromDmaQ_data_1[571]; endcase end @@ -8476,10 +8428,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = !cache_rqFromDmaQ_data_0[568]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = !cache_rqFromDmaQ_data_1[568]; endcase end @@ -8488,10 +8440,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = !cache_rqFromDmaQ_data_0[569]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = !cache_rqFromDmaQ_data_1[569]; endcase end @@ -8500,10 +8452,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = !cache_rqFromDmaQ_data_0[566]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = !cache_rqFromDmaQ_data_1[566]; endcase end @@ -8512,10 +8464,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = !cache_rqFromDmaQ_data_0[567]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = !cache_rqFromDmaQ_data_1[567]; endcase end @@ -8524,10 +8476,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = !cache_rqFromDmaQ_data_0[564]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = !cache_rqFromDmaQ_data_1[564]; endcase end @@ -8536,10 +8488,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = !cache_rqFromDmaQ_data_0[565]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = !cache_rqFromDmaQ_data_1[565]; endcase end @@ -8548,10 +8500,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = !cache_rqFromDmaQ_data_0[562]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = !cache_rqFromDmaQ_data_1[562]; endcase end @@ -8560,10 +8512,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = !cache_rqFromDmaQ_data_0[563]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = !cache_rqFromDmaQ_data_1[563]; endcase end @@ -8572,10 +8524,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = !cache_rqFromDmaQ_data_0[560]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = !cache_rqFromDmaQ_data_1[560]; endcase end @@ -8584,10 +8536,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = !cache_rqFromDmaQ_data_0[561]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = !cache_rqFromDmaQ_data_1[561]; endcase end @@ -8596,10 +8548,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = !cache_rqFromDmaQ_data_0[558]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = !cache_rqFromDmaQ_data_1[558]; endcase end @@ -8608,10 +8560,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = !cache_rqFromDmaQ_data_0[559]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = !cache_rqFromDmaQ_data_1[559]; endcase end @@ -8620,10 +8572,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = !cache_rqFromDmaQ_data_0[556]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = !cache_rqFromDmaQ_data_1[556]; endcase end @@ -8632,10 +8584,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = !cache_rqFromDmaQ_data_0[557]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = !cache_rqFromDmaQ_data_1[557]; endcase end @@ -8644,10 +8596,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = !cache_rqFromDmaQ_data_0[554]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = !cache_rqFromDmaQ_data_1[554]; endcase end @@ -8656,10 +8608,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = !cache_rqFromDmaQ_data_0[555]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = !cache_rqFromDmaQ_data_1[555]; endcase end @@ -8668,10 +8620,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = !cache_rqFromDmaQ_data_0[552]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = !cache_rqFromDmaQ_data_1[552]; endcase end @@ -8680,10 +8632,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = !cache_rqFromDmaQ_data_0[553]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = !cache_rqFromDmaQ_data_1[553]; endcase end @@ -8692,10 +8644,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = !cache_rqFromDmaQ_data_0[550]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = !cache_rqFromDmaQ_data_1[550]; endcase end @@ -8704,10 +8656,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = !cache_rqFromDmaQ_data_0[551]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = !cache_rqFromDmaQ_data_1[551]; endcase end @@ -8716,10 +8668,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = !cache_rqFromDmaQ_data_0[548]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = !cache_rqFromDmaQ_data_1[548]; endcase end @@ -8728,10 +8680,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = !cache_rqFromDmaQ_data_0[549]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = !cache_rqFromDmaQ_data_1[549]; endcase end @@ -8740,10 +8692,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = !cache_rqFromDmaQ_data_0[546]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = !cache_rqFromDmaQ_data_1[546]; endcase end @@ -8752,10 +8704,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = !cache_rqFromDmaQ_data_0[547]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = !cache_rqFromDmaQ_data_1[547]; endcase end @@ -8764,10 +8716,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = !cache_rqFromDmaQ_data_0[544]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = !cache_rqFromDmaQ_data_1[544]; endcase end @@ -8776,10 +8728,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = !cache_rqFromDmaQ_data_0[545]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = !cache_rqFromDmaQ_data_1[545]; endcase end @@ -8788,10 +8740,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = !cache_rqFromDmaQ_data_0[542]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = !cache_rqFromDmaQ_data_1[542]; endcase end @@ -8800,10 +8752,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = !cache_rqFromDmaQ_data_0[543]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = !cache_rqFromDmaQ_data_1[543]; endcase end @@ -8812,10 +8764,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = !cache_rqFromDmaQ_data_0[540]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = !cache_rqFromDmaQ_data_1[540]; endcase end @@ -8824,10 +8776,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = !cache_rqFromDmaQ_data_0[541]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = !cache_rqFromDmaQ_data_1[541]; endcase end @@ -8836,10 +8788,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = !cache_rqFromDmaQ_data_0[538]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = !cache_rqFromDmaQ_data_1[538]; endcase end @@ -8848,10 +8800,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = !cache_rqFromDmaQ_data_0[539]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = !cache_rqFromDmaQ_data_1[539]; endcase end @@ -8860,10 +8812,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = !cache_rqFromDmaQ_data_0[536]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = !cache_rqFromDmaQ_data_1[536]; endcase end @@ -8872,10 +8824,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = !cache_rqFromDmaQ_data_0[537]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = !cache_rqFromDmaQ_data_1[537]; endcase end @@ -8884,10 +8836,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = !cache_rqFromDmaQ_data_0[534]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = !cache_rqFromDmaQ_data_1[534]; endcase end @@ -8896,10 +8848,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = !cache_rqFromDmaQ_data_0[535]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = !cache_rqFromDmaQ_data_1[535]; endcase end @@ -8908,10 +8860,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = !cache_rqFromDmaQ_data_0[532]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = !cache_rqFromDmaQ_data_1[532]; endcase end @@ -8920,10 +8872,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = !cache_rqFromDmaQ_data_0[533]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = !cache_rqFromDmaQ_data_1[533]; endcase end @@ -8932,10 +8884,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = !cache_rqFromDmaQ_data_0[530]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = !cache_rqFromDmaQ_data_1[530]; endcase end @@ -8944,10 +8896,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = !cache_rqFromDmaQ_data_0[531]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = !cache_rqFromDmaQ_data_1[531]; endcase end @@ -8956,10 +8908,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = !cache_rqFromDmaQ_data_0[528]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = !cache_rqFromDmaQ_data_1[528]; endcase end @@ -8968,10 +8920,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = !cache_rqFromDmaQ_data_0[529]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = !cache_rqFromDmaQ_data_1[529]; endcase end @@ -8980,10 +8932,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = !cache_rqFromDmaQ_data_0[526]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = !cache_rqFromDmaQ_data_1[526]; endcase end @@ -8992,10 +8944,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = !cache_rqFromDmaQ_data_0[527]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = !cache_rqFromDmaQ_data_1[527]; endcase end @@ -9004,10 +8956,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = !cache_rqFromDmaQ_data_0[524]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = !cache_rqFromDmaQ_data_1[524]; endcase end @@ -9016,10 +8968,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = !cache_rqFromDmaQ_data_0[525]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = !cache_rqFromDmaQ_data_1[525]; endcase end @@ -9028,10 +8980,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = !cache_rqFromDmaQ_data_0[522]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = !cache_rqFromDmaQ_data_1[522]; endcase end @@ -9040,10 +8992,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = !cache_rqFromDmaQ_data_0[523]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = !cache_rqFromDmaQ_data_1[523]; endcase end @@ -9052,10 +9004,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = !cache_rqFromDmaQ_data_0[520]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = !cache_rqFromDmaQ_data_1[520]; endcase end @@ -9064,10 +9016,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = !cache_rqFromDmaQ_data_0[521]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = !cache_rqFromDmaQ_data_1[521]; endcase end @@ -9076,10 +9028,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = !cache_rqFromDmaQ_data_0[518]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = !cache_rqFromDmaQ_data_1[518]; endcase end @@ -9088,10 +9040,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = !cache_rqFromDmaQ_data_0[519]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = !cache_rqFromDmaQ_data_1[519]; endcase end @@ -9100,13 +9052,61 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = !cache_rqFromDmaQ_data_0[517]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 = + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = !cache_rqFromDmaQ_data_1[517]; endcase end + always@(cache_rsFromCQ_deqP or + cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) + begin + case (cache_rsFromCQ_deqP) + 1'd0: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 = + cache_rsFromCQ_data_0[512:449]; + 1'd1: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 = + cache_rsFromCQ_data_1[512:449]; + endcase + end + always@(cache_rsFromCQ_deqP or + cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) + begin + case (cache_rsFromCQ_deqP) + 1'd0: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 = + cache_rsFromCQ_data_0[448:385]; + 1'd1: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 = + cache_rsFromCQ_data_1[448:385]; + endcase + end + always@(cache_rsFromCQ_deqP or + cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) + begin + case (cache_rsFromCQ_deqP) + 1'd0: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 = + cache_rsFromCQ_data_0[384:321]; + 1'd1: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 = + cache_rsFromCQ_data_1[384:321]; + endcase + end + always@(cache_rsFromCQ_deqP or + cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) + begin + case (cache_rsFromCQ_deqP) + 1'd0: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 = + cache_rsFromCQ_data_0[320:257]; + 1'd1: + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 = + cache_rsFromCQ_data_1[320:257]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v index 9d3eb78..3e16643 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v @@ -1376,12 +1376,12 @@ module mkLLPipeline(CLK, // remaining internal signals reg [975 : 0] IF_send_r_BITS_583_TO_582_645_EQ_0_646_THEN_m__ETC___d3902; - reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21; + reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3; reg [47 : 0] y_avValue_info_tag__h196519; reg [3 : 0] CASE_send_r_BITS_583_TO_582_0_send_r_BITS_583__ETC__q2, SEL_ARR_IF_IF_m_pipe_enq2Mat_lat_0_whas__77_TH_ETC___d3536; - reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, + reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12, @@ -1393,7 +1393,7 @@ module mkLLPipeline(CLK, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20, - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5, + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8, @@ -3984,11 +3984,11 @@ module mkLLPipeline(CLK, // inlined wires assign m_pipe_enq2Mat_lat_0$wget = { 1'd1, - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, IF_IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypa_ETC___d2113 } ; assign m_pipe_enq2Mat_lat_2$wget = { 1'd1, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3, IF_send_r_BITS_583_TO_582_645_EQ_0_646_THEN_m__ETC___d3923 } ; assign m_pipe_mat2Out_lat_0$wget = { deqWrite_swapRq[4], @@ -5957,7 +5957,7 @@ module mkLLPipeline(CLK, IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypass__ETC___d1611 || m_pipe_enq2Mat_rl[517], m_pipe_enq2Mat_rl[516:4], - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, m_pipe_enq2Mat_rl[1:0] } ; assign IF_IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m__ETC___d2634 = (IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 == @@ -10177,25 +10177,38 @@ module mkLLPipeline(CLK, { 2'd2, send_r[517:516] }; endcase end + always@(send_r) + begin + case (send_r[583:582]) + 2'd0: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = + { 2'd0, send_r[67:0] }; + 2'd1: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = + { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; + default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = + { 2'd2, send_r[581:518], send_r[3:0] }; + endcase + end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[3:2]) 2'd0, 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = m_pipe_enq2Mat_rl[3:2]; - default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = 2'd2; + default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = 2'd2; endcase end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[1563:1562]) 2'd0: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = { 2'd0, m_pipe_enq2Mat_rl[1561:1494] }; 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = m_pipe_enq2Mat_rl[1563:1494]; - default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = + default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = { 2'd2, m_pipe_enq2Mat_rl[1561:1494] }; endcase end @@ -10578,10 +10591,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3189; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3195; endcase end @@ -10591,10 +10604,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3203; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3209; endcase end @@ -10604,10 +10617,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3217; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3223; endcase end @@ -10617,10 +10630,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3231; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3237; endcase end @@ -10630,10 +10643,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3245; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3251; endcase end @@ -10643,10 +10656,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3259; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3265; endcase end @@ -10656,10 +10669,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3273; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3279; endcase end @@ -10669,10 +10682,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3287; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3293; endcase end @@ -10682,10 +10695,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3301; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3307; endcase end @@ -10695,10 +10708,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3315; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3321; endcase end @@ -10708,10 +10721,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3329; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3335; endcase end @@ -10721,10 +10734,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3343; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3349; endcase end @@ -10734,10 +10747,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3357; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3363; endcase end @@ -10747,10 +10760,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3371; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3377; endcase end @@ -10760,10 +10773,10 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3385; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3391; endcase end @@ -10773,15 +10786,14 @@ module mkLLPipeline(CLK, begin case (x__h187917) 1'd0: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3399; 1'd1: - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 = + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3405; endcase end always@(way__h182888 or - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5 or CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 or CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 or CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 or @@ -10796,57 +10808,58 @@ module mkLLPipeline(CLK, CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 or CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 or CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 or - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20) + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 or + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21) begin case (way__h182888) 4'd0: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6; 4'd1: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7; 4'd2: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8; 4'd3: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9; 4'd4: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10; 4'd5: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11; 4'd6: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12; 4'd7: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13; 4'd8: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14; 4'd9: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15; 4'd10: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16; 4'd11: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17; 4'd12: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18; 4'd13: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19; 4'd14: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20; 4'd15: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 = - CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20; + CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21; endcase end always@(way__h182888 or @@ -11194,19 +11207,6 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3616; endcase end - always@(send_r) - begin - case (send_r[583:582]) - 2'd0: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = - { 2'd0, send_r[67:0] }; - 2'd1: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = - { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; - default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = - { 2'd2, send_r[581:518], send_r[3:0] }; - endcase - end // handling of inlined registers diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v index 5b4b895..68735ad 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v @@ -25072,75 +25072,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or @@ -25210,6 +25141,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11075 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25376,75 +25376,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[66]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11077 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11078 or @@ -25597,6 +25528,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[65]; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25680,75 +25680,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[64]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11114 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11115 or @@ -25901,6 +25832,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[63]; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25984,75 +25984,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[62]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or @@ -26122,6 +26053,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11168 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26288,75 +26288,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[60]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or @@ -26426,6 +26357,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11205 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26592,75 +26592,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[58]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11227 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11228 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11229 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11230 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11231 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11232 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11233 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11234 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11235 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11236 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11237 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11238 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11239 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11240) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11227; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11228; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11229; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11230; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11231; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11232; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11233; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11234; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11235; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11236; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11237; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11238; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11239; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11240; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244 or @@ -26730,6 +26661,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11227 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11228 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11229 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11230 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11231 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11232 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11233 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11234 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11235 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11236 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11237 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11238 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11239 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11240) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11227; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11228; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11229; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11230; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11231; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11232; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11233; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11234; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11235; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11236; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11237; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11238; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11239; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11242 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11240; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26896,75 +26896,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[56]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11262 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11263 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11264 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11265 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11266 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11267 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11268 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11269 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11270 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11271 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11272 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11273 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11274 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11275 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11276 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11277) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11262; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11263; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11264; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11265; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11266; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11267; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11268; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11269; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11270; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11271; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11272; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11273; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11274; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11275; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11276; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11277; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281 or @@ -27034,6 +26965,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11262 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11263 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11264 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11265 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11266 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11267 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11268 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11269 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11270 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11271 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11272 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11273 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11274 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11275 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11276 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11277) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11262; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11263; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11264; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11265; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11266; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11267; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11268; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11269; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11270; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11271; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11272; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11273; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11274; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11275; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11276; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11279 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11277; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -27200,75 +27200,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[54]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11299 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11300 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11301 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11302 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11303 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11304 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11305 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11306 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11307 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11308 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11309 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11310 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11311 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11312 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11313 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11299; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11300; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11301; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11302; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11303; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11304; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11305; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11306; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11307; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11308; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11309; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11310; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11311; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11312; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11313; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or @@ -27338,6 +27269,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11299 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11300 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11301 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11302 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11303 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11304 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11305 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11306 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11307 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11308 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11309 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11310 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11311 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11312 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11313 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11299; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11300; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11301; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11302; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11303; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11304; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11305; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11306; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11307; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11308; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11309; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11310; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11311; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11312; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11313; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11316 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -27808,75 +27808,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[50]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11375 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11376 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11377 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11378 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11379 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11380 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11381 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11382 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11383 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11384 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11385 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11386 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11387 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11388) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11375; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11376; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11377; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11378; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11379; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11380; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11381; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11382; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11383; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11384; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11385; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11386; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11387; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11388; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392 or @@ -27946,6 +27877,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11375 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11376 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11377 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11378 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11379 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11380 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11381 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11382 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11383 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11384 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11385 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11386 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11387 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11388) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11375; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11376; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11377; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11378; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11379; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11380; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11381; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11382; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11383; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11384; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11385; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11386; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11387; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11390 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11388; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -28112,75 +28112,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[48]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11410 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11411 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11412 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11413 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11414 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11415 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11416 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11417 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11418 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11419 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11420 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11421 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11422 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11423 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11424 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11410; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11411; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11412; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11413; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11414; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11415; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11416; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11417; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11418; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11419; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11420; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11421; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11422; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11423; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11424; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or @@ -28250,6 +28181,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11410 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11411 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11412 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11413 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11414 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11415 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11416 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11417 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11418 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11419 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11420 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11421 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11422 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11423 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11424 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11410; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11411; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11412; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11413; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11414; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11415; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11416; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11417; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11418; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11419; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11420; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11421; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11422; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11423; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11424; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11427 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -29024,75 +29024,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[42]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11521 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11522 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11523 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11524 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11525 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11526 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11527 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11528 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11529 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11530 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11531 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11532 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11533 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11534 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11535 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11536) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11521; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11522; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11523; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11524; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11525; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11526; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11527; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11528; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11529; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11530; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11531; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11532; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11533; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11534; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11535; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11536; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540 or @@ -29162,6 +29093,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11521 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11522 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11523 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11524 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11525 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11526 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11527 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11528 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11529 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11530 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11531 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11532 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11533 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11534 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11535 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11536) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11521; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11522; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11523; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11524; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11525; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11526; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11527; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11528; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11529; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11530; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11531; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11532; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11533; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11534; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11535; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11538 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11536; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -34535,73 +34535,6 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end - always@(transfer_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_15_rl[3]; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -34738,6 +34671,73 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10964; endcase end + always@(transfer_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_15_rl[3]; + endcase + end always@(sendToM_getSlot_n or m_slotVec_0_dummy2_0_read__2303_AND_m_slotVec__ETC___d12503 or m_slotVec_1_dummy2_0_read__2308_AND_m_slotVec__ETC___d12504 or @@ -35083,75 +35083,6 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_dummy2_0_read__2378_AND_m_slotVec_ETC___d12418; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; - endcase - end always@(sendToM_getData_n or m_dataValidVec_0_dummy2_0_read__2568_AND_m_dat_ETC___d12573 or m_dataValidVec_1_dummy2_0_read__2574_AND_m_dat_ETC___d12579 or @@ -35290,6 +35221,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11018; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or @@ -35360,72 +35360,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; endcase end always@(sendRsToDmaC_getRq_n or @@ -35842,75 +35842,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or @@ -35980,6 +35911,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11190; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11191; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11192; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11193; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11194; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11195; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11196; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11197; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11198; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11199; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11200; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11201; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11202; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13043 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226 or @@ -36257,72 +36257,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369; endcase end always@(sendRsToDmaC_getRq_n or @@ -36394,6 +36394,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or @@ -36463,75 +36532,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374 or @@ -36739,75 +36739,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or @@ -36946,6 +36877,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11480; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or @@ -37222,75 +37222,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or @@ -37360,6 +37291,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13074 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11595 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11596 or @@ -37843,75 +37843,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11726 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11727 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11728 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11729 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11730 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11731 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11732 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11733 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11734 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11735 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11736 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11737 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11738 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11739) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11726; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11727; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11728; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11729; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11730; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11731; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11732; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11733; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11734; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11735; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11736; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11737; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11738; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11739; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744 or @@ -37981,6 +37912,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11726 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11727 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11728 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11729 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11730 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11731 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11732 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11733 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11734 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11735 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11736 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11737 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11738 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11739) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11726; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11727; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11728; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11729; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11730; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11731; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11732; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11733; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11734; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11735; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11736; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11737; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11738; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13086 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11739; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11761 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11762 or @@ -38257,75 +38257,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11832; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11835 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11836 or @@ -38395,75 +38326,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11850; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or @@ -38533,6 +38395,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11891 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11892 or @@ -38809,75 +38740,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11961; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11965 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11966 or @@ -39016,6 +38878,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12017; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or @@ -39292,75 +39223,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12091; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or @@ -39430,6 +39292,144 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; + endcase + end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13118 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; + endcase + end always@(sendRsToDmaC_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0849_2187_OR_NOT_ETC___d12191 or NOT_m_reqVec_1_dummy2_0_read__0854_2192_OR_NOT_ETC___d12196 or @@ -39702,75 +39702,6 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10964; endcase end - always@(sendToM_getData_n or - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686 or - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693 or - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700 or - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707 or - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714 or - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721 or - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728 or - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735 or - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742 or - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749 or - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756 or - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763 or - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770 or - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777) - begin - case (sendToM_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or @@ -39909,6 +39840,75 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12811; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686 or + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693 or + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700 or + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707 or + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714 or + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721 or + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728 or + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735 or + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742 or + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749 or + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756 or + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763 or + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770 or + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777; + endcase + end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12781 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12783 or @@ -40185,7 +40185,7 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12846; endcase end - always@(sendRsToDmaC_getData_n or + always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or @@ -40203,54 +40203,54 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) begin - case (sendRsToDmaC_getData_n) + case (sendToM_getData_n) 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; endcase end @@ -40323,6 +40323,75 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12880; endcase end + always@(sendRsToDmaC_getData_n or + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891 or + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893 or + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895 or + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897 or + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899 or + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901 or + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903 or + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905 or + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907 or + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909 or + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911 or + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) + begin + case (sendRsToDmaC_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; + endcase + end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12919 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12921 or @@ -40392,75 +40461,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12949; endcase end - always@(sendToM_getData_n or - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891 or - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893 or - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895 or - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897 or - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899 or - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901 or - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903 or - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905 or - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907 or - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909 or - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911 or - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) - begin - case (sendToM_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; - endcase - end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12919 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12921 or @@ -40668,75 +40668,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11018; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or @@ -40875,6 +40806,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11077 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11078 or @@ -41151,75 +41151,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or @@ -41289,6 +41220,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13188 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or @@ -41772,75 +41772,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or @@ -41910,6 +41841,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13200 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or @@ -42187,72 +42187,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499) begin case (sendRqToC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499; endcase end always@(sendRqToC_getRq_n or @@ -42324,6 +42324,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11465 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11466 or @@ -42393,75 +42462,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11480; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11502 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11503 or @@ -42669,75 +42669,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or @@ -42876,6 +42807,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11610; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11613 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11614 or @@ -43152,75 +43152,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11684; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11706 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11707 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11708 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11709 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11710 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11711 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11712 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11713 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11714 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11715 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11716 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11717 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11718 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11719 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11720 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11706; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11707; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11708; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11709; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11710; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11711; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11712; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11713; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11714; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11715; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11716; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11717; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11718; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11719; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11720; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688 or @@ -43290,6 +43221,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11706 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11707 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11708 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11709 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11710 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11711 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11712 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11713 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11714 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11715 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11716 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11717 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11718 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11719 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11720 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11706; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11707; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11708; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11709; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11710; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11711; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11712; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11713; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11714; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11715; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11716; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11717; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11718; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11719; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11720; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13232 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725 or @@ -43773,75 +43773,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11850; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or @@ -43911,6 +43842,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13244 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11891 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11892 or @@ -44188,72 +44188,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035) begin case (sendRqToC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035; endcase end always@(sendRqToC_getRq_n or @@ -44325,6 +44325,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11980; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12002 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12003 or @@ -44394,75 +44463,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12017; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12039 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12040 or @@ -44670,75 +44670,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12091; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or @@ -44877,6 +44808,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; + endcase + end always@(sendRqToC_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0849_2187_OR_NOT_ETC___d12191 or NOT_m_reqVec_1_dummy2_0_read__0854_2192_OR_NOT_ETC___d12196 or @@ -46328,122 +46328,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[64]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[63]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[63]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[63]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[63]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[63]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[63]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[63]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[63]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[63]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[63]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[63]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[63]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[63]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[63]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[63]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[63]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46560,6 +46444,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[62]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[63]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[63]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[63]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[63]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[63]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[63]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[63]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[63]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[63]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[63]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[63]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[63]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[63]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[63]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[63]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14070 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[63]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47024,122 +47024,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[58]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[56]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[56]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[56]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[56]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[56]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[56]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[56]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[56]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[56]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[56]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[56]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[56]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[56]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[56]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[56]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[56]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47372,6 +47256,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[55]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[56]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[56]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[56]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[56]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[56]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[56]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[56]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[56]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[56]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[56]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[56]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[56]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[56]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[56]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[56]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[56]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47836,122 +47836,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[51]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[49]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[49]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[49]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[49]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[49]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[49]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[49]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[49]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[49]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[49]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[49]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[49]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[49]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[49]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[49]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[49]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48184,6 +48068,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[48]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[49]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[49]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[49]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[49]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[49]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[49]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[49]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[49]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[49]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[49]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[49]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[49]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[49]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[49]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[49]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[49]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48648,122 +48648,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[44]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[42]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[42]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[42]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[42]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[42]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[42]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[42]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[42]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[42]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[42]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[42]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[42]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[42]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[42]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[42]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[42]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48880,6 +48764,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[43]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[42]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[42]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[42]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[42]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[42]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[42]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[42]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[42]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[42]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[42]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[42]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[42]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[42]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[42]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[42]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14458 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[42]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49692,122 +49692,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[35]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[34]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[34]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[34]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[34]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[34]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[34]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[34]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[34]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[34]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[34]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[34]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[34]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[34]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[34]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[34]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[34]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49924,6 +49808,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[33]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[34]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[34]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[34]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[34]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[34]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[34]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[34]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[34]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[34]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[34]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[34]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[34]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[34]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[34]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[34]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14606 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[34]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50388,122 +50388,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[29]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[27]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[27]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[27]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[27]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[27]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[27]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[27]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[27]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[27]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[27]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[27]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[27]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[27]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[27]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[27]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[27]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50736,6 +50620,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[26]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[27]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[27]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[27]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[27]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[27]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[27]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[27]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[27]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[27]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[27]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[27]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[27]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[27]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[27]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[27]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[27]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51200,122 +51200,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[22]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[20]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[20]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[20]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[20]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[20]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[20]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[20]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[20]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[20]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[20]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[20]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[20]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[20]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[20]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[20]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[20]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51548,6 +51432,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[19]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[20]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[20]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[20]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[20]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[20]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[20]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[20]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[20]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[20]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[20]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[20]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[20]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[20]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[20]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[20]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[20]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52012,122 +52012,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[15]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[13]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[13]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[13]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[13]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[13]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[13]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[13]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[13]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[13]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[13]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[13]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[13]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[13]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[13]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[13]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[13]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52244,6 +52128,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[14]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[13]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[13]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[13]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[13]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[13]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[13]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[13]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[13]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[13]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[13]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[13]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[13]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[13]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[13]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[13]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14995 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[13]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -53007,73 +53007,6 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_15_rl[3]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -53206,6 +53139,73 @@ module mkLastLvCRqMshr(CLK, 2'd0; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_15_rl[3]; + endcase + end always@(pipelineResp_getAddrSucc_n or m_addrSuccValidVec_0_dummy2_1$Q_OUT or m_addrSuccValidVec_0_dummy2_2$Q_OUT or @@ -53872,73 +53872,6 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_rl[5:4]; endcase end - always@(sendRqToC_getSlot_n or - m_slotVec_0_rl or - m_slotVec_1_rl or - m_slotVec_2_rl or - m_slotVec_3_rl or - m_slotVec_4_rl or - m_slotVec_5_rl or - m_slotVec_6_rl or - m_slotVec_7_rl or - m_slotVec_8_rl or - m_slotVec_9_rl or - m_slotVec_10_rl or - m_slotVec_11_rl or - m_slotVec_12_rl or - m_slotVec_13_rl or m_slotVec_14_rl or m_slotVec_15_rl) - begin - case (sendRqToC_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_0_rl[1:0]; - 4'd1: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_1_rl[1:0]; - 4'd2: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_2_rl[1:0]; - 4'd3: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_3_rl[1:0]; - 4'd4: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_4_rl[1:0]; - 4'd5: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_5_rl[1:0]; - 4'd6: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_6_rl[1:0]; - 4'd7: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_7_rl[1:0]; - 4'd8: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_8_rl[1:0]; - 4'd9: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_9_rl[1:0]; - 4'd10: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_10_rl[1:0]; - 4'd11: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_11_rl[1:0]; - 4'd12: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_12_rl[1:0]; - 4'd13: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_13_rl[1:0]; - 4'd14: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_14_rl[1:0]; - 4'd15: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_15_rl[1:0]; - endcase - end always@(sendToM_getSlot_n or m_slotVec_0_rl or m_slotVec_1_rl or @@ -54073,6 +54006,73 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_rl[5:4]; endcase end + always@(sendRqToC_getSlot_n or + m_slotVec_0_rl or + m_slotVec_1_rl or + m_slotVec_2_rl or + m_slotVec_3_rl or + m_slotVec_4_rl or + m_slotVec_5_rl or + m_slotVec_6_rl or + m_slotVec_7_rl or + m_slotVec_8_rl or + m_slotVec_9_rl or + m_slotVec_10_rl or + m_slotVec_11_rl or + m_slotVec_12_rl or + m_slotVec_13_rl or m_slotVec_14_rl or m_slotVec_15_rl) + begin + case (sendRqToC_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_0_rl[1:0]; + 4'd1: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_1_rl[1:0]; + 4'd2: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_2_rl[1:0]; + 4'd3: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_3_rl[1:0]; + 4'd4: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_4_rl[1:0]; + 4'd5: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_5_rl[1:0]; + 4'd6: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_6_rl[1:0]; + 4'd7: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_7_rl[1:0]; + 4'd8: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_8_rl[1:0]; + 4'd9: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_9_rl[1:0]; + 4'd10: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_10_rl[1:0]; + 4'd11: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_11_rl[1:0]; + 4'd12: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_12_rl[1:0]; + 4'd13: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_13_rl[1:0]; + 4'd14: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_14_rl[1:0]; + 4'd15: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_15_rl[1:0]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or @@ -54515,75 +54515,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12168 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12169 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12170 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12171 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12172 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12173 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12174 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12175 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12176 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12177 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12178 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12179 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12180 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12181 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12182 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12168; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12169; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12170; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12171; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12172; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12173; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12174; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12175; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12176; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12177; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12178; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12179; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12180; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12181; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12182; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or @@ -54653,6 +54584,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12168 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12169 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12170 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12171 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12172 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12173 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12174 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12175 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12176 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12177 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12178 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12179 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12180 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12181 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12182 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12168; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12169; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12170; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12171; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12172; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12173; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12174; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12175; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12176; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12177; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12178; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12179; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12180; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12181; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12182; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13269 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -55786,6 +55786,74 @@ module mkLastLvCRqMshr(CLK, n__read_addr__h899271; endcase end + always@(sendRsToDmaC_getRq_n or + n__read_addr__h897906 or + n__read_addr__h897997 or + n__read_addr__h898088 or + n__read_addr__h898179 or + n__read_addr__h898270 or + n__read_addr__h898361 or + n__read_addr__h898452 or + n__read_addr__h898543 or + n__read_addr__h898634 or + n__read_addr__h898725 or + n__read_addr__h898816 or + n__read_addr__h898907 or + n__read_addr__h898998 or + n__read_addr__h899089 or + n__read_addr__h899180 or n__read_addr__h899271) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h897906; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h897997; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898088; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898179; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898270; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898361; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898452; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898543; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898634; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898725; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898816; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898907; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898998; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899089; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899180; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899271; + endcase + end always@(sendToM_getRq_n or IF_m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_ETC___d10931 or IF_m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_ETC___d10932 or @@ -55855,74 +55923,6 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10946; endcase end - always@(sendRsToDmaC_getRq_n or - n__read_addr__h897906 or - n__read_addr__h897997 or - n__read_addr__h898088 or - n__read_addr__h898179 or - n__read_addr__h898270 or - n__read_addr__h898361 or - n__read_addr__h898452 or - n__read_addr__h898543 or - n__read_addr__h898634 or - n__read_addr__h898725 or - n__read_addr__h898816 or - n__read_addr__h898907 or - n__read_addr__h898998 or - n__read_addr__h899089 or - n__read_addr__h899180 or n__read_addr__h899271) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h897906; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h897997; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898088; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898179; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898270; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898361; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898452; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898543; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898634; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898725; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898816; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898907; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898998; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899089; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899180; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899271; - endcase - end always@(sendRsToDmaC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_ETC___d10931 or IF_m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_ETC___d10932 or @@ -56129,74 +56129,6 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10946; endcase end - always@(pipelineResp_getRq_n or - n__read_addr__h995883 or - n__read_addr__h995985 or - n__read_addr__h996087 or - n__read_addr__h996189 or - n__read_addr__h996291 or - n__read_addr__h996393 or - n__read_addr__h996495 or - n__read_addr__h996597 or - n__read_addr__h996699 or - n__read_addr__h996801 or - n__read_addr__h996903 or - n__read_addr__h997005 or - n__read_addr__h997107 or - n__read_addr__h997209 or - n__read_addr__h997311 or n__read_addr__h997413) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h995883; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h995985; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996087; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996189; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996291; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996393; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996495; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996597; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996699; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996801; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996903; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997005; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997107; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997209; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997311; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997413; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -56329,6 +56261,74 @@ module mkLastLvCRqMshr(CLK, 2'd0; endcase end + always@(pipelineResp_getRq_n or + n__read_addr__h995883 or + n__read_addr__h995985 or + n__read_addr__h996087 or + n__read_addr__h996189 or + n__read_addr__h996291 or + n__read_addr__h996393 or + n__read_addr__h996495 or + n__read_addr__h996597 or + n__read_addr__h996699 or + n__read_addr__h996801 or + n__read_addr__h996903 or + n__read_addr__h997005 or + n__read_addr__h997107 or + n__read_addr__h997209 or + n__read_addr__h997311 or n__read_addr__h997413) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h995883; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h995985; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996087; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996189; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996291; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996393; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996495; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996597; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996699; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996801; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996903; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997005; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997107; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997209; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997311; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997413; + endcase + end always@(sendRqToC_setSlot_s) begin case (sendRqToC_setSlot_s[7:6]) @@ -56770,123 +56770,6 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3267; endcase end - always@(pipelineResp_getSlot_n or - m_slotVec_0_dummy2_1$Q_OUT or - m_slotVec_0_dummy2_2$Q_OUT or - IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1970 or - m_slotVec_1_dummy2_1$Q_OUT or - m_slotVec_1_dummy2_2$Q_OUT or - IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2056 or - m_slotVec_2_dummy2_1$Q_OUT or - m_slotVec_2_dummy2_2$Q_OUT or - IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2142 or - m_slotVec_3_dummy2_1$Q_OUT or - m_slotVec_3_dummy2_2$Q_OUT or - IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2228 or - m_slotVec_4_dummy2_1$Q_OUT or - m_slotVec_4_dummy2_2$Q_OUT or - IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2314 or - m_slotVec_5_dummy2_1$Q_OUT or - m_slotVec_5_dummy2_2$Q_OUT or - IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2400 or - m_slotVec_6_dummy2_1$Q_OUT or - m_slotVec_6_dummy2_2$Q_OUT or - IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2486 or - m_slotVec_7_dummy2_1$Q_OUT or - m_slotVec_7_dummy2_2$Q_OUT or - IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2572 or - m_slotVec_8_dummy2_1$Q_OUT or - m_slotVec_8_dummy2_2$Q_OUT or - IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2658 or - m_slotVec_9_dummy2_1$Q_OUT or - m_slotVec_9_dummy2_2$Q_OUT or - IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2744 or - m_slotVec_10_dummy2_1$Q_OUT or - m_slotVec_10_dummy2_2$Q_OUT or - IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2830 or - m_slotVec_11_dummy2_1$Q_OUT or - m_slotVec_11_dummy2_2$Q_OUT or - IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2916 or - m_slotVec_12_dummy2_1$Q_OUT or - m_slotVec_12_dummy2_2$Q_OUT or - IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d3002 or - m_slotVec_13_dummy2_1$Q_OUT or - m_slotVec_13_dummy2_2$Q_OUT or - IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3088 or - m_slotVec_14_dummy2_1$Q_OUT or - m_slotVec_14_dummy2_2$Q_OUT or - IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3174 or - m_slotVec_15_dummy2_1$Q_OUT or - m_slotVec_15_dummy2_2$Q_OUT or - IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3260) - begin - case (pipelineResp_getSlot_n) - 4'd0: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_0_dummy2_1$Q_OUT || !m_slotVec_0_dummy2_2$Q_OUT || - IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1970; - 4'd1: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_1_dummy2_1$Q_OUT || !m_slotVec_1_dummy2_2$Q_OUT || - IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2056; - 4'd2: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_2_dummy2_1$Q_OUT || !m_slotVec_2_dummy2_2$Q_OUT || - IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2142; - 4'd3: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_3_dummy2_1$Q_OUT || !m_slotVec_3_dummy2_2$Q_OUT || - IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2228; - 4'd4: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_4_dummy2_1$Q_OUT || !m_slotVec_4_dummy2_2$Q_OUT || - IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2314; - 4'd5: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_5_dummy2_1$Q_OUT || !m_slotVec_5_dummy2_2$Q_OUT || - IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2400; - 4'd6: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_6_dummy2_1$Q_OUT || !m_slotVec_6_dummy2_2$Q_OUT || - IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2486; - 4'd7: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_7_dummy2_1$Q_OUT || !m_slotVec_7_dummy2_2$Q_OUT || - IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2572; - 4'd8: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_8_dummy2_1$Q_OUT || !m_slotVec_8_dummy2_2$Q_OUT || - IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2658; - 4'd9: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_9_dummy2_1$Q_OUT || !m_slotVec_9_dummy2_2$Q_OUT || - IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2744; - 4'd10: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_10_dummy2_1$Q_OUT || !m_slotVec_10_dummy2_2$Q_OUT || - IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2830; - 4'd11: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_11_dummy2_1$Q_OUT || !m_slotVec_11_dummy2_2$Q_OUT || - IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2916; - 4'd12: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_12_dummy2_1$Q_OUT || !m_slotVec_12_dummy2_2$Q_OUT || - IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d3002; - 4'd13: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_13_dummy2_1$Q_OUT || !m_slotVec_13_dummy2_2$Q_OUT || - IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3088; - 4'd14: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_14_dummy2_1$Q_OUT || !m_slotVec_14_dummy2_2$Q_OUT || - IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3174; - 4'd15: - SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = - !m_slotVec_15_dummy2_1$Q_OUT || !m_slotVec_15_dummy2_2$Q_OUT || - IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3260; - endcase - end always@(pipelineResp_getSlot_n or m_slotVec_0_dummy2_1$Q_OUT or m_slotVec_0_dummy2_2$Q_OUT or @@ -57004,6 +56887,123 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221; endcase end + always@(pipelineResp_getSlot_n or + m_slotVec_0_dummy2_1$Q_OUT or + m_slotVec_0_dummy2_2$Q_OUT or + IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1970 or + m_slotVec_1_dummy2_1$Q_OUT or + m_slotVec_1_dummy2_2$Q_OUT or + IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2056 or + m_slotVec_2_dummy2_1$Q_OUT or + m_slotVec_2_dummy2_2$Q_OUT or + IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2142 or + m_slotVec_3_dummy2_1$Q_OUT or + m_slotVec_3_dummy2_2$Q_OUT or + IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2228 or + m_slotVec_4_dummy2_1$Q_OUT or + m_slotVec_4_dummy2_2$Q_OUT or + IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2314 or + m_slotVec_5_dummy2_1$Q_OUT or + m_slotVec_5_dummy2_2$Q_OUT or + IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2400 or + m_slotVec_6_dummy2_1$Q_OUT or + m_slotVec_6_dummy2_2$Q_OUT or + IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2486 or + m_slotVec_7_dummy2_1$Q_OUT or + m_slotVec_7_dummy2_2$Q_OUT or + IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2572 or + m_slotVec_8_dummy2_1$Q_OUT or + m_slotVec_8_dummy2_2$Q_OUT or + IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2658 or + m_slotVec_9_dummy2_1$Q_OUT or + m_slotVec_9_dummy2_2$Q_OUT or + IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2744 or + m_slotVec_10_dummy2_1$Q_OUT or + m_slotVec_10_dummy2_2$Q_OUT or + IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2830 or + m_slotVec_11_dummy2_1$Q_OUT or + m_slotVec_11_dummy2_2$Q_OUT or + IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2916 or + m_slotVec_12_dummy2_1$Q_OUT or + m_slotVec_12_dummy2_2$Q_OUT or + IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d3002 or + m_slotVec_13_dummy2_1$Q_OUT or + m_slotVec_13_dummy2_2$Q_OUT or + IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3088 or + m_slotVec_14_dummy2_1$Q_OUT or + m_slotVec_14_dummy2_2$Q_OUT or + IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3174 or + m_slotVec_15_dummy2_1$Q_OUT or + m_slotVec_15_dummy2_2$Q_OUT or + IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3260) + begin + case (pipelineResp_getSlot_n) + 4'd0: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_0_dummy2_1$Q_OUT || !m_slotVec_0_dummy2_2$Q_OUT || + IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1970; + 4'd1: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_1_dummy2_1$Q_OUT || !m_slotVec_1_dummy2_2$Q_OUT || + IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2056; + 4'd2: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_2_dummy2_1$Q_OUT || !m_slotVec_2_dummy2_2$Q_OUT || + IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2142; + 4'd3: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_3_dummy2_1$Q_OUT || !m_slotVec_3_dummy2_2$Q_OUT || + IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2228; + 4'd4: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_4_dummy2_1$Q_OUT || !m_slotVec_4_dummy2_2$Q_OUT || + IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2314; + 4'd5: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_5_dummy2_1$Q_OUT || !m_slotVec_5_dummy2_2$Q_OUT || + IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2400; + 4'd6: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_6_dummy2_1$Q_OUT || !m_slotVec_6_dummy2_2$Q_OUT || + IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2486; + 4'd7: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_7_dummy2_1$Q_OUT || !m_slotVec_7_dummy2_2$Q_OUT || + IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2572; + 4'd8: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_8_dummy2_1$Q_OUT || !m_slotVec_8_dummy2_2$Q_OUT || + IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2658; + 4'd9: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_9_dummy2_1$Q_OUT || !m_slotVec_9_dummy2_2$Q_OUT || + IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2744; + 4'd10: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_10_dummy2_1$Q_OUT || !m_slotVec_10_dummy2_2$Q_OUT || + IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2830; + 4'd11: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_11_dummy2_1$Q_OUT || !m_slotVec_11_dummy2_2$Q_OUT || + IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2916; + 4'd12: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_12_dummy2_1$Q_OUT || !m_slotVec_12_dummy2_2$Q_OUT || + IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d3002; + 4'd13: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_13_dummy2_1$Q_OUT || !m_slotVec_13_dummy2_2$Q_OUT || + IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3088; + 4'd14: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_14_dummy2_1$Q_OUT || !m_slotVec_14_dummy2_2$Q_OUT || + IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3174; + 4'd15: + SEL_ARR_NOT_m_slotVec_0_dummy2_1_read__2304_24_ETC___d15371 = + !m_slotVec_15_dummy2_1$Q_OUT || !m_slotVec_15_dummy2_2$Q_OUT || + IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3260; + endcase + end always@(pipelineResp_getSlot_n or IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1957 or IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2043 or diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemDispToRegFifo.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemDispToRegFifo.v index 29da713..3ba3569 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemDispToRegFifo.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemDispToRegFifo.v @@ -101,6 +101,7 @@ module mkMemDispToRegFifo(CLK, RDY_specUpdate_incorrectSpeculation; // inlined wires + wire [11 : 0] m_m_specBits_0_lat_1$wget; wire m_m_valid_0_lat_0$whas; // register m_m_row_0 @@ -254,6 +255,8 @@ module mkMemDispToRegFifo(CLK, // inlined wires assign m_m_valid_0_lat_0$whas = MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ; + assign m_m_specBits_0_lat_1$wget = + sb__h6991 & specUpdate_correctSpeculation_mask ; // register m_m_row_0 assign m_m_row_0$D_IN = enq_x[97:12] ; @@ -311,7 +314,7 @@ module mkMemDispToRegFifo(CLK, m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 : 12'd0 ; - assign upd__h2327 = sb__h6991 & specUpdate_correctSpeculation_mask ; + assign upd__h2327 = m_m_specBits_0_lat_1$wget ; // handling of inlined registers diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v index 89c6984..7b44dad 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v @@ -177,6 +177,7 @@ module mkMemLoader(CLK_portalClk, // inlined wires wire [640 : 0] memReqQ_enqReq_lat_0$wget; + wire memReqQ_enqReq_lat_0$whas; // register busy reg busy; @@ -655,7 +656,6 @@ module mkMemLoader(CLK_portalClk, wire MUX_busy$write_1__SEL_1, MUX_busy$write_1__SEL_2, MUX_expectWrData$write_1__SEL_1, - MUX_pendStCnt$write_1__SEL_2, MUX_writing$write_1__SEL_2; // remaining internal signals @@ -672,11 +672,11 @@ module mkMemLoader(CLK_portalClk, wire [31 : 0] IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187, IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41, IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11, - IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114, + IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84, + IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260, IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230, IF_mmio_req_wrBE_BIT_7_38_THEN_mmio_req_wrData_ETC___d864, - x__h10090, - x__h3821, + x__h4676, x__h6528; wire [7 : 0] IF_reqSel_69_EQ_0_76_THEN_hostWrDataQ_q_wDataO_ETC___d480, IF_reqSel_69_EQ_1_97_THEN_hostWrDataQ_q_wDataO_ETC___d499, @@ -1312,9 +1312,6 @@ module mkMemLoader(CLK_portalClk, mmio_req_wrBE_BIT_0_31_OR_mmio_req_wrBE_BIT_1__ETC___d849 ; assign MUX_expectWrData$write_1__SEL_1 = WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ; - assign MUX_pendStCnt$write_1__SEL_2 = - WILL_FIRE_RL_doStReq && - reqSel_69_EQ_7_70_OR_hostWrDataQ_q_wDataOut_wg_ETC___d800 ; assign MUX_writing$write_1__SEL_2 = WILL_FIRE_RL_doStResp && pendStCnt == 8'd1 && !expectWrData ; assign MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1 = @@ -1334,15 +1331,15 @@ module mkMemLoader(CLK_portalClk, hostWrAddrQ_q_rWrPtr_rsCounter | x__h938 : hostWrAddrQ_q_rWrPtr_rsCounter & y__h1133 ; assign MUX_hostWrDataQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrDataQ_q_rRdPtr_rsCounter[IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114[0]]) ? + (~hostWrDataQ_q_rRdPtr_rsCounter[x__h4676[0]]) ? hostWrDataQ_q_rRdPtr_rsCounter | x__h4511 : hostWrDataQ_q_rRdPtr_rsCounter & y__h4698 ; assign MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 = - (~hostWrDataQ_q_rWrPtr_rsCounter[x__h3821[0]]) ? + (~hostWrDataQ_q_rWrPtr_rsCounter[IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84[0]]) ? hostWrDataQ_q_rWrPtr_rsCounter | x__h3656 : hostWrDataQ_q_rWrPtr_rsCounter & y__h3843 ; assign MUX_hostWrDoneQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrDoneQ_q_rRdPtr_rsCounter[x__h10090[0]]) ? + (~hostWrDoneQ_q_rRdPtr_rsCounter[IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260[0]]) ? hostWrDoneQ_q_rRdPtr_rsCounter | x__h9925 : hostWrDoneQ_q_rRdPtr_rsCounter & y__h10112 ; assign MUX_hostWrDoneQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1379,6 +1376,9 @@ module mkMemLoader(CLK_portalClk, IF_reqSel_69_EQ_1_97_THEN_hostWrDataQ_q_wDataO_ETC___d499, IF_reqSel_69_EQ_0_76_THEN_hostWrDataQ_q_wDataO_ETC___d480, IF_reqSel_69_EQ_7_70_THEN_hostWrDataQ_q_wDataO_ETC___d726 } ; + assign memReqQ_enqReq_lat_0$whas = + WILL_FIRE_RL_doStReq && + reqSel_69_EQ_7_70_OR_hostWrDataQ_q_wDataOut_wg_ETC___d800 ; // register busy assign busy$D_IN = !MUX_busy$write_1__SEL_1 ; @@ -1521,7 +1521,7 @@ module mkMemLoader(CLK_portalClk, // register memReqQ_data_0 assign memReqQ_data_0$D_IN = { x_addr__h43806, - MUX_pendStCnt$write_1__SEL_2 ? + memReqQ_enqReq_lat_0$whas ? memReqQ_enqReq_lat_0$wget[575:0] : memReqQ_enqReq_rl[575:0] } ; assign memReqQ_data_0$EN = @@ -1556,13 +1556,13 @@ module mkMemLoader(CLK_portalClk, // register pendStCnt always@(MUX_expectWrData$write_1__SEL_1 or - MUX_pendStCnt$write_1__SEL_2 or + memReqQ_enqReq_lat_0$whas or MUX_pendStCnt$write_1__VAL_2 or WILL_FIRE_RL_doStResp or MUX_pendStCnt$write_1__VAL_3) begin case (1'b1) // synopsys parallel_case MUX_expectWrData$write_1__SEL_1: pendStCnt$D_IN = 8'd0; - MUX_pendStCnt$write_1__SEL_2: + memReqQ_enqReq_lat_0$whas: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_2; WILL_FIRE_RL_doStResp: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_3; default: pendStCnt$D_IN = 8'b10101010 /* unspecified value */ ; @@ -1724,7 +1724,7 @@ module mkMemLoader(CLK_portalClk, // submodule memReqQ_enqReq_dummy2_0 assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign memReqQ_enqReq_dummy2_0$EN = MUX_pendStCnt$write_1__SEL_2 ; + assign memReqQ_enqReq_dummy2_0$EN = memReqQ_enqReq_lat_0$whas ; // submodule memReqQ_enqReq_dummy2_1 assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; @@ -1779,8 +1779,12 @@ module mkMemLoader(CLK_portalClk, hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10 ? 32'd1 : 32'd0 ; - assign IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 = - hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? + assign IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 = + hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? + 32'd1 : + 32'd0 ; + assign IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 = + hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 ? 32'd1 : 32'd0 ; assign IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230 = @@ -1788,7 +1792,7 @@ module mkMemLoader(CLK_portalClk, 32'd1 : 32'd0 ; assign IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 = - MUX_pendStCnt$write_1__SEL_2 ? + memReqQ_enqReq_lat_0$whas ? memReqQ_enqReq_lat_0$wget[640] : memReqQ_enqReq_rl[640] ; assign IF_mmio_req_wrBE_BIT_7_38_THEN_mmio_req_wrData_ETC___d864 = @@ -2019,7 +2023,7 @@ module mkMemLoader(CLK_portalClk, !memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ; assign NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366 = (!memReqQ_enqReq_dummy2_2$Q_OUT || - (MUX_pendStCnt$write_1__SEL_2 ? + (memReqQ_enqReq_lat_0$whas ? !memReqQ_enqReq_lat_0$wget[640] : !memReqQ_enqReq_rl[640])) && (memReqQ_deqReq_dummy2_2$Q_OUT && @@ -2119,23 +2123,19 @@ module mkMemLoader(CLK_portalClk, (!respStQ_deqReq_dummy2_2$Q_OUT || !CAN_FIRE_RL_doStResp && !respStQ_deqReq_rl) && respStQ_full ; - assign x__h10090 = - hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 ? - 32'd1 : - 32'd0 ; assign x__h10885 = x_sReadBin__h10334 + 2'd1 ; assign x__h1801 = 2'd1 << IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 ; assign x__h2762 = x_sReadBin__h2210 + 2'd1 ; - assign x__h3656 = 2'd1 << x__h3821 ; - assign x__h3821 = - hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? + assign x__h3656 = + 2'd1 << + IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 ; + assign x__h4511 = 2'd1 << x__h4676 ; + assign x__h4676 = + hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? 32'd1 : 32'd0 ; - assign x__h4511 = - 2'd1 << - IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 ; assign x__h5470 = x_sReadBin__h4920 + 2'd1 ; assign x__h6363 = 2'd1 << x__h6528 ; assign x__h6528 = @@ -2152,9 +2152,11 @@ module mkMemLoader(CLK_portalClk, assign x__h938 = 2'd1 << IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 ; - assign x__h9925 = 2'd1 << x__h10090 ; + assign x__h9925 = + 2'd1 << + IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 ; assign x_addr__h43806 = - MUX_pendStCnt$write_1__SEL_2 ? + memReqQ_enqReq_lat_0$whas ? memReqQ_enqReq_lat_0$wget[639:576] : memReqQ_enqReq_rl[639:576] ; assign x_dReadBin__h10337 = diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemRegToExeFifo.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemRegToExeFifo.v index f346838..e9325af 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemRegToExeFifo.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemRegToExeFifo.v @@ -101,6 +101,7 @@ module mkMemRegToExeFifo(CLK, RDY_specUpdate_incorrectSpeculation; // inlined wires + wire [11 : 0] m_m_specBits_0_lat_1$wget; wire m_m_valid_0_lat_0$whas; // register m_m_row_0 @@ -254,6 +255,8 @@ module mkMemRegToExeFifo(CLK, // inlined wires assign m_m_valid_0_lat_0$whas = MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ; + assign m_m_specBits_0_lat_1$wget = + sb__h6440 & specUpdate_correctSpeculation_mask ; // register m_m_row_0 assign m_m_row_0$D_IN = enq_x[192:12] ; @@ -311,7 +314,7 @@ module mkMemRegToExeFifo(CLK, m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 : 12'd0 ; - assign upd__h2327 = sb__h6440 & specUpdate_correctSpeculation_mask ; + assign upd__h2327 = m_m_specBits_0_lat_1$wget ; // handling of inlined registers diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index 360ffc3..a6479d6 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -1878,7 +1878,7 @@ module mkProc(CLK, IF_NOT_propDstIdx_1_0_dummy2_1_read__287_288_O_ETC___d1332, IF_SEL_ARR_propDstIdx_0_dummy2_1_read__023_AND_ETC___d1130, IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__287_A_ETC___d1432, - IF_enqDst_0_lat_0_1_whas__496_THEN_enqDst_0_la_ETC___d1501, + IF_enqDst_0_lat_0_1_whas__495_THEN_enqDst_0_la_ETC___d1500, IF_enqDst_0_lat_0_whas__99_THEN_enqDst_0_lat_0_ETC___d1004, IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1240, IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1260, @@ -1890,15 +1890,15 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d940, IF_propDstData_1_0_lat_0_whas__159_THEN_propDs_ETC___d1190, IF_propDstData_1_1_lat_0_whas__197_THEN_propDs_ETC___d1228, - IF_propDstIdx_0_lat_0_1_whas__481_THEN_propDst_ETC___d1484, + IF_propDstIdx_0_lat_0_1_whas__480_THEN_propDst_ETC___d1483, IF_propDstIdx_0_lat_0_whas__70_THEN_propDstIdx_ETC___d973, IF_propDstIdx_1_0_lat_0_whas__144_THEN_propDst_ETC___d1147, IF_propDstIdx_1_1_lat_0_whas__151_THEN_propDst_ETC___d1154, IF_propDstIdx_1_lat_0_whas__77_THEN_propDstIdx_ETC___d980, - NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534, + NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533, NOT_enqDst_0_dummy2_0_read__044_045_OR_NOT_enq_ETC___d1060, NOT_enqDst_1_0_dummy2_0_read__318_319_OR_NOT_e_ETC___d1334, - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633, + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631, NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715, NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d723, NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d729, @@ -2792,32 +2792,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -2838,7 +2842,7 @@ module mkProc(CLK, // rule RL_doEnq_2 assign CAN_FIRE_RL_doEnq_2 = tlbQ$FULL_N && enqDst_0_dummy2_1_1$Q_OUT && - IF_enqDst_0_lat_0_1_whas__496_THEN_enqDst_0_la_ETC___d1501 ; + IF_enqDst_0_lat_0_1_whas__495_THEN_enqDst_0_la_ETC___d1500 ; assign WILL_FIRE_RL_doEnq_2 = CAN_FIRE_RL_doEnq_2 ; // rule RL_sendTlbReqToLLC @@ -2848,28 +2852,28 @@ module mkProc(CLK, // rule RL_sendLdRespToMemLoader assign CAN_FIRE_RL_sendLdRespToMemLoader = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_sendLdRespToMemLoader = CAN_FIRE_RL_sendLdRespToMemLoader ; // rule RL_sendLdRespToTlb assign CAN_FIRE_RL_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_sendLdRespToTlb = CAN_FIRE_RL_sendLdRespToTlb ; // rule RL_sendStRespToMemLoader assign CAN_FIRE_RL_sendStRespToMemLoader = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_sendStRespToMemLoader = CAN_FIRE_RL_sendStRespToMemLoader ; // rule RL_sendStRespToTlb assign CAN_FIRE_RL_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_sendStRespToTlb = CAN_FIRE_RL_sendStRespToTlb ; @@ -3680,10 +3684,10 @@ module mkProc(CLK, // register enqDst_0_rl_1 assign enqDst_0_rl_1$D_IN = { !CAN_FIRE_RL_doEnq_2 && - IF_enqDst_0_lat_0_1_whas__496_THEN_enqDst_0_la_ETC___d1501, + IF_enqDst_0_lat_0_1_whas__495_THEN_enqDst_0_la_ETC___d1500, CAN_FIRE_RL_doEnq_2 ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 ? + (NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 ? enqDst_0_lat_0_1$wget[64:0] : enqDst_0_rl_1[64:0]) } ; assign enqDst_0_rl_1$EN = 1'd1 ; @@ -4196,8 +4200,8 @@ module mkProc(CLK, // register propDstIdx_0_rl_1 assign propDstIdx_0_rl_1$D_IN = - !NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 && - IF_propDstIdx_0_lat_0_1_whas__481_THEN_propDst_ETC___d1484 ; + !NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 && + IF_propDstIdx_0_lat_0_1_whas__480_THEN_propDst_ETC___d1483 ; assign propDstIdx_0_rl_1$EN = 1'd1 ; // register propDstIdx_1_0_rl @@ -4417,7 +4421,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0_1 assign enqDst_0_dummy2_0_1$D_IN = 1'd1 ; assign enqDst_0_dummy2_0_1$EN = - NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 ; + NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -4438,11 +4442,11 @@ module mkProc(CLK, // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -4689,7 +4693,7 @@ module mkProc(CLK, // submodule propDstIdx_0_dummy2_1_1 assign propDstIdx_0_dummy2_1_1$D_IN = 1'd1 ; assign propDstIdx_0_dummy2_1_1$EN = - NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 ; + NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 ; // submodule propDstIdx_1_0_dummy2_0 assign propDstIdx_1_0_dummy2_0$D_IN = 1'd1 ; @@ -4717,7 +4721,7 @@ module mkProc(CLK, // submodule tlbQ assign tlbQ$D_IN = - NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 ? + NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 ? enqDst_0_lat_0_1$wget[64:0] : enqDst_0_rl_1[64:0] ; assign tlbQ$ENQ = CAN_FIRE_RL_doEnq_2 ; @@ -4813,8 +4817,8 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_1_whas__496_THEN_enqDst_0_la_ETC___d1501 = - NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 ? + assign IF_enqDst_0_lat_0_1_whas__495_THEN_enqDst_0_la_ETC___d1500 = + NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 ? enqDst_0_lat_0_1$wget[65] : enqDst_0_rl_1[65] ; assign IF_enqDst_0_lat_0_whas__99_THEN_enqDst_0_lat_0_ETC___d1004 = @@ -5077,7 +5081,7 @@ module mkProc(CLK, propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_1_whas__481_THEN_propDst_ETC___d1484 = + assign IF_propDstIdx_0_lat_0_1_whas__480_THEN_propDst_ETC___d1483 = CAN_FIRE_RL_srcPropose_4 || propDstIdx_0_rl_1 ; assign IF_propDstIdx_0_lat_0_whas__70_THEN_propDstIdx_ETC___d973 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; @@ -5087,11 +5091,11 @@ module mkProc(CLK, CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; assign IF_propDstIdx_1_lat_0_whas__77_THEN_propDstIdx_ETC___d980 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 = + assign NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 = (!enqDst_0_dummy2_0_1$Q_OUT || !enqDst_0_dummy2_1_1$Q_OUT || !enqDst_0_rl_1[65]) && propDstIdx_0_dummy2_1_1$Q_OUT && - IF_propDstIdx_0_lat_0_1_whas__481_THEN_propDst_ETC___d1484 ; + IF_propDstIdx_0_lat_0_1_whas__480_THEN_propDst_ETC___d1483 ; assign NOT_enqDst_0_dummy2_0_read__044_045_OR_NOT_enq_ETC___d1060 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && @@ -5102,7 +5106,7 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__287_AND__ETC___d1328 || IF_NOT_propDstIdx_1_0_dummy2_1_read__287_288_O_ETC___d1332) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 = mmioPlatform_curReq[66:64] != 3'd0 && @@ -5624,6 +5628,27 @@ module mkProc(CLK, 3'd7: strb8__h125580 = llc$to_mem_toM_first[575:568]; endcase end + always@(mmioPlatform_curReq or + result__h46061 or + result__h46089 or result__h46117 or result__h46145) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = + result__h46061; + 3'h2: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = + result__h46089; + 3'h4: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = + result__h46117; + 3'h6: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = + result__h46145; + default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = + 64'd0; + endcase + end always@(mmioPlatform_curReq or result__h45820 or result__h45848 or @@ -5659,27 +5684,6 @@ module mkProc(CLK, result__h46016; endcase end - always@(mmioPlatform_curReq or - result__h46061 or - result__h46089 or result__h46117 or result__h46145) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46061; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46089; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46117; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46145; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - 64'd0; - endcase - end always@(mmioPlatform_curReq or result__h46186 or result__h46214) begin case (mmioPlatform_curReq[2:0]) @@ -6816,7 +6820,7 @@ module mkProc(CLK, NOT_propDstIdx_1_1_dummy2_1_read__305_306_OR_I_ETC___d1438) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_1_read__527_528_OR_NOT_e_ETC___d1534 && + if (NOT_enqDst_0_dummy2_0_1_read__526_527_OR_NOT_e_ETC___d1533 && !CAN_FIRE_RL_srcPropose_4 && !propDstIdx_0_rl_1) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8020,7 +8024,7 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) begin v__h112139 = $stime; #0; @@ -8028,63 +8032,63 @@ module mkProc(CLK, v__h112133 = v__h112139 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h112133, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633 && + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633 && + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -8160,119 +8164,119 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633 && + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633 && + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && @@ -9500,147 +9504,147 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", mem_req_wr_addr_awaddr__h125664); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("AXI4_Wr_Data { ", "wid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", data64__h125579); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", strb8__h125580); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -9727,103 +9731,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", mem_req_rd_addr_araddr__h111740); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) begin v__h138450 = $stime; #0; @@ -9831,41 +9835,41 @@ module mkProc(CLK, v__h138444 = v__h138450 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", v__h138444, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) + NOT_llc_axi4_adapter_cfg_verbosity_read__614_U_ETC___d1631) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v index 002e929..cafed2d 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v @@ -19770,137 +19770,6 @@ module mkReorderBufferSynth(CLK, !m_valid_1_31_rl; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_0$read_deq[282:219]; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_1$read_deq[282:219]; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_2$read_deq[282:219]; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_3$read_deq[282:219]; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_4$read_deq[282:219]; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_5$read_deq[282:219]; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_6$read_deq[282:219]; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_7$read_deq[282:219]; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_8$read_deq[282:219]; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_9$read_deq[282:219]; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_10$read_deq[282:219]; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_11$read_deq[282:219]; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_12$read_deq[282:219]; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_13$read_deq[282:219]; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_14$read_deq[282:219]; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_15$read_deq[282:219]; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_16$read_deq[282:219]; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_17$read_deq[282:219]; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_18$read_deq[282:219]; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_19$read_deq[282:219]; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_20$read_deq[282:219]; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_21$read_deq[282:219]; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_22$read_deq[282:219]; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_23$read_deq[282:219]; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_24$read_deq[282:219]; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_25$read_deq[282:219]; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_26$read_deq[282:219]; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_27$read_deq[282:219]; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_28$read_deq[282:219]; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_29$read_deq[282:219]; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_30$read_deq[282:219]; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = - m_row_1_31$read_deq[282:219]; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -20032,6 +19901,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[282:219]; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_0$read_deq[282:219]; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_1$read_deq[282:219]; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_2$read_deq[282:219]; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_3$read_deq[282:219]; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_4$read_deq[282:219]; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_5$read_deq[282:219]; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_6$read_deq[282:219]; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_7$read_deq[282:219]; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_8$read_deq[282:219]; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_9$read_deq[282:219]; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_10$read_deq[282:219]; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_11$read_deq[282:219]; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_12$read_deq[282:219]; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_13$read_deq[282:219]; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_14$read_deq[282:219]; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_15$read_deq[282:219]; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_16$read_deq[282:219]; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_17$read_deq[282:219]; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_18$read_deq[282:219]; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_19$read_deq[282:219]; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_20$read_deq[282:219]; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_21$read_deq[282:219]; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_22$read_deq[282:219]; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_23$read_deq[282:219]; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_24$read_deq[282:219]; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_25$read_deq[282:219]; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_26$read_deq[282:219]; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_27$read_deq[282:219]; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_28$read_deq[282:219]; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_29$read_deq[282:219]; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_30$read_deq[282:219]; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168 = + m_row_1_31$read_deq[282:219]; + endcase + end always@(x__h99963 or SEL_ARR_m_row_0_0_read_deq__037_BITS_282_TO_21_ETC___d4102 or SEL_ARR_m_row_1_0_read_deq__103_BITS_282_TO_21_ETC___d4168) @@ -20189,137 +20189,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[218:187]; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_0$read_deq[186:182]; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_1$read_deq[186:182]; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_2$read_deq[186:182]; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_3$read_deq[186:182]; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_4$read_deq[186:182]; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_5$read_deq[186:182]; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_6$read_deq[186:182]; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_7$read_deq[186:182]; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_8$read_deq[186:182]; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_9$read_deq[186:182]; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_10$read_deq[186:182]; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_11$read_deq[186:182]; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_12$read_deq[186:182]; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_13$read_deq[186:182]; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_14$read_deq[186:182]; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_15$read_deq[186:182]; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_16$read_deq[186:182]; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_17$read_deq[186:182]; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_18$read_deq[186:182]; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_19$read_deq[186:182]; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_20$read_deq[186:182]; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_21$read_deq[186:182]; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_22$read_deq[186:182]; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_23$read_deq[186:182]; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_24$read_deq[186:182]; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_25$read_deq[186:182]; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_26$read_deq[186:182]; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_27$read_deq[186:182]; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_28$read_deq[186:182]; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_29$read_deq[186:182]; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_30$read_deq[186:182]; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = - m_row_0_31$read_deq[186:182]; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -20451,6 +20320,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[218:187]; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_0$read_deq[186:182]; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_1$read_deq[186:182]; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_2$read_deq[186:182]; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_3$read_deq[186:182]; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_4$read_deq[186:182]; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_5$read_deq[186:182]; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_6$read_deq[186:182]; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_7$read_deq[186:182]; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_8$read_deq[186:182]; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_9$read_deq[186:182]; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_10$read_deq[186:182]; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_11$read_deq[186:182]; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_12$read_deq[186:182]; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_13$read_deq[186:182]; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_14$read_deq[186:182]; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_15$read_deq[186:182]; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_16$read_deq[186:182]; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_17$read_deq[186:182]; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_18$read_deq[186:182]; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_19$read_deq[186:182]; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_20$read_deq[186:182]; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_21$read_deq[186:182]; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_22$read_deq[186:182]; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_23$read_deq[186:182]; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_24$read_deq[186:182]; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_25$read_deq[186:182]; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_26$read_deq[186:182]; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_27$read_deq[186:182]; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_28$read_deq[186:182]; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_29$read_deq[186:182]; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_30$read_deq[186:182]; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_186_TO_18_ETC___d4274 = + m_row_0_31$read_deq[186:182]; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -20713,137 +20713,6 @@ module mkReorderBufferSynth(CLK, !m_row_0_31$read_deq[181]; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_0$read_deq[181]; - 5'd1: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_1$read_deq[181]; - 5'd2: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_2$read_deq[181]; - 5'd3: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_3$read_deq[181]; - 5'd4: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_4$read_deq[181]; - 5'd5: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_5$read_deq[181]; - 5'd6: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_6$read_deq[181]; - 5'd7: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_7$read_deq[181]; - 5'd8: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_8$read_deq[181]; - 5'd9: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_9$read_deq[181]; - 5'd10: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_10$read_deq[181]; - 5'd11: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_11$read_deq[181]; - 5'd12: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_12$read_deq[181]; - 5'd13: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_13$read_deq[181]; - 5'd14: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_14$read_deq[181]; - 5'd15: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_15$read_deq[181]; - 5'd16: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_16$read_deq[181]; - 5'd17: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_17$read_deq[181]; - 5'd18: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_18$read_deq[181]; - 5'd19: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_19$read_deq[181]; - 5'd20: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_20$read_deq[181]; - 5'd21: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_21$read_deq[181]; - 5'd22: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_22$read_deq[181]; - 5'd23: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_23$read_deq[181]; - 5'd24: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_24$read_deq[181]; - 5'd25: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_25$read_deq[181]; - 5'd26: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_26$read_deq[181]; - 5'd27: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_27$read_deq[181]; - 5'd28: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_28$read_deq[181]; - 5'd29: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_29$read_deq[181]; - 5'd30: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_30$read_deq[181]; - 5'd31: - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = - !m_row_1_31$read_deq[181]; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -20975,6 +20844,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd1; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_0$read_deq[181]; + 5'd1: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_1$read_deq[181]; + 5'd2: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_2$read_deq[181]; + 5'd3: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_3$read_deq[181]; + 5'd4: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_4$read_deq[181]; + 5'd5: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_5$read_deq[181]; + 5'd6: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_6$read_deq[181]; + 5'd7: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_7$read_deq[181]; + 5'd8: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_8$read_deq[181]; + 5'd9: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_9$read_deq[181]; + 5'd10: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_10$read_deq[181]; + 5'd11: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_11$read_deq[181]; + 5'd12: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_12$read_deq[181]; + 5'd13: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_13$read_deq[181]; + 5'd14: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_14$read_deq[181]; + 5'd15: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_15$read_deq[181]; + 5'd16: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_16$read_deq[181]; + 5'd17: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_17$read_deq[181]; + 5'd18: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_18$read_deq[181]; + 5'd19: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_19$read_deq[181]; + 5'd20: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_20$read_deq[181]; + 5'd21: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_21$read_deq[181]; + 5'd22: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_22$read_deq[181]; + 5'd23: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_23$read_deq[181]; + 5'd24: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_24$read_deq[181]; + 5'd25: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_25$read_deq[181]; + 5'd26: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_26$read_deq[181]; + 5'd27: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_27$read_deq[181]; + 5'd28: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_28$read_deq[181]; + 5'd29: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_29$read_deq[181]; + 5'd30: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_30$read_deq[181]; + 5'd31: + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_181_37_ETC___d4442 = + !m_row_1_31$read_deq[181]; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -21106,6 +21106,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd1; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_0$read_deq[180:169] == 12'd2; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_1$read_deq[180:169] == 12'd2; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_2$read_deq[180:169] == 12'd2; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_3$read_deq[180:169] == 12'd2; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_4$read_deq[180:169] == 12'd2; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_5$read_deq[180:169] == 12'd2; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_6$read_deq[180:169] == 12'd2; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_7$read_deq[180:169] == 12'd2; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_8$read_deq[180:169] == 12'd2; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_9$read_deq[180:169] == 12'd2; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_10$read_deq[180:169] == 12'd2; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_11$read_deq[180:169] == 12'd2; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_12$read_deq[180:169] == 12'd2; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_13$read_deq[180:169] == 12'd2; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_14$read_deq[180:169] == 12'd2; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_15$read_deq[180:169] == 12'd2; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_16$read_deq[180:169] == 12'd2; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_17$read_deq[180:169] == 12'd2; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_18$read_deq[180:169] == 12'd2; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_19$read_deq[180:169] == 12'd2; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_20$read_deq[180:169] == 12'd2; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_21$read_deq[180:169] == 12'd2; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_22$read_deq[180:169] == 12'd2; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_23$read_deq[180:169] == 12'd2; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_24$read_deq[180:169] == 12'd2; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_25$read_deq[180:169] == 12'd2; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_26$read_deq[180:169] == 12'd2; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_27$read_deq[180:169] == 12'd2; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_28$read_deq[180:169] == 12'd2; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_29$read_deq[180:169] == 12'd2; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_30$read_deq[180:169] == 12'd2; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = + m_row_1_31$read_deq[180:169] == 12'd2; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -21368,137 +21499,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd3; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_0$read_deq[180:169] == 12'd2; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_1$read_deq[180:169] == 12'd2; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_2$read_deq[180:169] == 12'd2; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_3$read_deq[180:169] == 12'd2; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_4$read_deq[180:169] == 12'd2; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_5$read_deq[180:169] == 12'd2; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_6$read_deq[180:169] == 12'd2; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_7$read_deq[180:169] == 12'd2; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_8$read_deq[180:169] == 12'd2; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_9$read_deq[180:169] == 12'd2; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_10$read_deq[180:169] == 12'd2; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_11$read_deq[180:169] == 12'd2; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_12$read_deq[180:169] == 12'd2; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_13$read_deq[180:169] == 12'd2; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_14$read_deq[180:169] == 12'd2; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_15$read_deq[180:169] == 12'd2; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_16$read_deq[180:169] == 12'd2; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_17$read_deq[180:169] == 12'd2; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_18$read_deq[180:169] == 12'd2; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_19$read_deq[180:169] == 12'd2; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_20$read_deq[180:169] == 12'd2; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_21$read_deq[180:169] == 12'd2; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_22$read_deq[180:169] == 12'd2; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_23$read_deq[180:169] == 12'd2; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_24$read_deq[180:169] == 12'd2; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_25$read_deq[180:169] == 12'd2; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_26$read_deq[180:169] == 12'd2; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_27$read_deq[180:169] == 12'd2; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_28$read_deq[180:169] == 12'd2; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_29$read_deq[180:169] == 12'd2; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_30$read_deq[180:169] == 12'd2; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4647 = - m_row_1_31$read_deq[180:169] == 12'd2; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -21630,137 +21630,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd3; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_0$read_deq[180:169] == 12'd3072; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_1$read_deq[180:169] == 12'd3072; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_2$read_deq[180:169] == 12'd3072; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_3$read_deq[180:169] == 12'd3072; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_4$read_deq[180:169] == 12'd3072; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_5$read_deq[180:169] == 12'd3072; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_6$read_deq[180:169] == 12'd3072; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_7$read_deq[180:169] == 12'd3072; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_8$read_deq[180:169] == 12'd3072; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_9$read_deq[180:169] == 12'd3072; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_10$read_deq[180:169] == 12'd3072; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_11$read_deq[180:169] == 12'd3072; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_12$read_deq[180:169] == 12'd3072; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_13$read_deq[180:169] == 12'd3072; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_14$read_deq[180:169] == 12'd3072; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_15$read_deq[180:169] == 12'd3072; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_16$read_deq[180:169] == 12'd3072; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_17$read_deq[180:169] == 12'd3072; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_18$read_deq[180:169] == 12'd3072; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_19$read_deq[180:169] == 12'd3072; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_20$read_deq[180:169] == 12'd3072; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_21$read_deq[180:169] == 12'd3072; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_22$read_deq[180:169] == 12'd3072; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_23$read_deq[180:169] == 12'd3072; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_24$read_deq[180:169] == 12'd3072; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_25$read_deq[180:169] == 12'd3072; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_26$read_deq[180:169] == 12'd3072; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_27$read_deq[180:169] == 12'd3072; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_28$read_deq[180:169] == 12'd3072; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_29$read_deq[180:169] == 12'd3072; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_30$read_deq[180:169] == 12'd3072; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = - m_row_1_31$read_deq[180:169] == 12'd3072; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -21892,6 +21761,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd3072; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_0$read_deq[180:169] == 12'd3072; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_1$read_deq[180:169] == 12'd3072; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_2$read_deq[180:169] == 12'd3072; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_3$read_deq[180:169] == 12'd3072; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_4$read_deq[180:169] == 12'd3072; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_5$read_deq[180:169] == 12'd3072; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_6$read_deq[180:169] == 12'd3072; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_7$read_deq[180:169] == 12'd3072; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_8$read_deq[180:169] == 12'd3072; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_9$read_deq[180:169] == 12'd3072; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_10$read_deq[180:169] == 12'd3072; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_11$read_deq[180:169] == 12'd3072; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_12$read_deq[180:169] == 12'd3072; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_13$read_deq[180:169] == 12'd3072; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_14$read_deq[180:169] == 12'd3072; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_15$read_deq[180:169] == 12'd3072; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_16$read_deq[180:169] == 12'd3072; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_17$read_deq[180:169] == 12'd3072; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_18$read_deq[180:169] == 12'd3072; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_19$read_deq[180:169] == 12'd3072; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_20$read_deq[180:169] == 12'd3072; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_21$read_deq[180:169] == 12'd3072; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_22$read_deq[180:169] == 12'd3072; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_23$read_deq[180:169] == 12'd3072; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_24$read_deq[180:169] == 12'd3072; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_25$read_deq[180:169] == 12'd3072; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_26$read_deq[180:169] == 12'd3072; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_27$read_deq[180:169] == 12'd3072; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_28$read_deq[180:169] == 12'd3072; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_29$read_deq[180:169] == 12'd3072; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_30$read_deq[180:169] == 12'd3072; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d4787 = + m_row_1_31$read_deq[180:169] == 12'd3072; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -22154,137 +22154,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd3073; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_0$read_deq[180:169] == 12'd3074; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_1$read_deq[180:169] == 12'd3074; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_2$read_deq[180:169] == 12'd3074; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_3$read_deq[180:169] == 12'd3074; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_4$read_deq[180:169] == 12'd3074; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_5$read_deq[180:169] == 12'd3074; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_6$read_deq[180:169] == 12'd3074; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_7$read_deq[180:169] == 12'd3074; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_8$read_deq[180:169] == 12'd3074; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_9$read_deq[180:169] == 12'd3074; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_10$read_deq[180:169] == 12'd3074; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_11$read_deq[180:169] == 12'd3074; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_12$read_deq[180:169] == 12'd3074; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_13$read_deq[180:169] == 12'd3074; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_14$read_deq[180:169] == 12'd3074; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_15$read_deq[180:169] == 12'd3074; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_16$read_deq[180:169] == 12'd3074; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_17$read_deq[180:169] == 12'd3074; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_18$read_deq[180:169] == 12'd3074; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_19$read_deq[180:169] == 12'd3074; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_20$read_deq[180:169] == 12'd3074; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_21$read_deq[180:169] == 12'd3074; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_22$read_deq[180:169] == 12'd3074; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_23$read_deq[180:169] == 12'd3074; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_24$read_deq[180:169] == 12'd3074; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_25$read_deq[180:169] == 12'd3074; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_26$read_deq[180:169] == 12'd3074; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_27$read_deq[180:169] == 12'd3074; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_28$read_deq[180:169] == 12'd3074; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_29$read_deq[180:169] == 12'd3074; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_30$read_deq[180:169] == 12'd3074; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = - m_row_0_31$read_deq[180:169] == 12'd3074; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -22416,6 +22285,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd3074; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_0$read_deq[180:169] == 12'd3074; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_1$read_deq[180:169] == 12'd3074; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_2$read_deq[180:169] == 12'd3074; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_3$read_deq[180:169] == 12'd3074; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_4$read_deq[180:169] == 12'd3074; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_5$read_deq[180:169] == 12'd3074; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_6$read_deq[180:169] == 12'd3074; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_7$read_deq[180:169] == 12'd3074; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_8$read_deq[180:169] == 12'd3074; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_9$read_deq[180:169] == 12'd3074; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_10$read_deq[180:169] == 12'd3074; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_11$read_deq[180:169] == 12'd3074; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_12$read_deq[180:169] == 12'd3074; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_13$read_deq[180:169] == 12'd3074; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_14$read_deq[180:169] == 12'd3074; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_15$read_deq[180:169] == 12'd3074; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_16$read_deq[180:169] == 12'd3074; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_17$read_deq[180:169] == 12'd3074; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_18$read_deq[180:169] == 12'd3074; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_19$read_deq[180:169] == 12'd3074; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_20$read_deq[180:169] == 12'd3074; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_21$read_deq[180:169] == 12'd3074; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_22$read_deq[180:169] == 12'd3074; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_23$read_deq[180:169] == 12'd3074; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_24$read_deq[180:169] == 12'd3074; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_25$read_deq[180:169] == 12'd3074; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_26$read_deq[180:169] == 12'd3074; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_27$read_deq[180:169] == 12'd3074; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_28$read_deq[180:169] == 12'd3074; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_29$read_deq[180:169] == 12'd3074; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_30$read_deq[180:169] == 12'd3074; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d4893 = + m_row_0_31$read_deq[180:169] == 12'd3074; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -22547,6 +22547,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd2048; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_0$read_deq[180:169] == 12'd2049; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_1$read_deq[180:169] == 12'd2049; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_2$read_deq[180:169] == 12'd2049; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_3$read_deq[180:169] == 12'd2049; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_4$read_deq[180:169] == 12'd2049; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_5$read_deq[180:169] == 12'd2049; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_6$read_deq[180:169] == 12'd2049; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_7$read_deq[180:169] == 12'd2049; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_8$read_deq[180:169] == 12'd2049; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_9$read_deq[180:169] == 12'd2049; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_10$read_deq[180:169] == 12'd2049; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_11$read_deq[180:169] == 12'd2049; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_12$read_deq[180:169] == 12'd2049; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_13$read_deq[180:169] == 12'd2049; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_14$read_deq[180:169] == 12'd2049; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_15$read_deq[180:169] == 12'd2049; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_16$read_deq[180:169] == 12'd2049; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_17$read_deq[180:169] == 12'd2049; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_18$read_deq[180:169] == 12'd2049; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_19$read_deq[180:169] == 12'd2049; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_20$read_deq[180:169] == 12'd2049; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_21$read_deq[180:169] == 12'd2049; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_22$read_deq[180:169] == 12'd2049; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_23$read_deq[180:169] == 12'd2049; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_24$read_deq[180:169] == 12'd2049; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_25$read_deq[180:169] == 12'd2049; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_26$read_deq[180:169] == 12'd2049; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_27$read_deq[180:169] == 12'd2049; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_28$read_deq[180:169] == 12'd2049; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_29$read_deq[180:169] == 12'd2049; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_30$read_deq[180:169] == 12'd2049; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = + m_row_0_31$read_deq[180:169] == 12'd2049; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -22809,137 +22940,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd2049; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_0$read_deq[180:169] == 12'd2049; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_1$read_deq[180:169] == 12'd2049; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_2$read_deq[180:169] == 12'd2049; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_3$read_deq[180:169] == 12'd2049; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_4$read_deq[180:169] == 12'd2049; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_5$read_deq[180:169] == 12'd2049; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_6$read_deq[180:169] == 12'd2049; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_7$read_deq[180:169] == 12'd2049; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_8$read_deq[180:169] == 12'd2049; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_9$read_deq[180:169] == 12'd2049; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_10$read_deq[180:169] == 12'd2049; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_11$read_deq[180:169] == 12'd2049; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_12$read_deq[180:169] == 12'd2049; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_13$read_deq[180:169] == 12'd2049; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_14$read_deq[180:169] == 12'd2049; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_15$read_deq[180:169] == 12'd2049; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_16$read_deq[180:169] == 12'd2049; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_17$read_deq[180:169] == 12'd2049; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_18$read_deq[180:169] == 12'd2049; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_19$read_deq[180:169] == 12'd2049; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_20$read_deq[180:169] == 12'd2049; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_21$read_deq[180:169] == 12'd2049; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_22$read_deq[180:169] == 12'd2049; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_23$read_deq[180:169] == 12'd2049; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_24$read_deq[180:169] == 12'd2049; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_25$read_deq[180:169] == 12'd2049; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_26$read_deq[180:169] == 12'd2049; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_27$read_deq[180:169] == 12'd2049; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_28$read_deq[180:169] == 12'd2049; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_29$read_deq[180:169] == 12'd2049; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_30$read_deq[180:169] == 12'd2049; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5033 = - m_row_0_31$read_deq[180:169] == 12'd2049; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -23071,137 +23071,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd256; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_0$read_deq[180:169] == 12'd260; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_1$read_deq[180:169] == 12'd260; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_2$read_deq[180:169] == 12'd260; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_3$read_deq[180:169] == 12'd260; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_4$read_deq[180:169] == 12'd260; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_5$read_deq[180:169] == 12'd260; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_6$read_deq[180:169] == 12'd260; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_7$read_deq[180:169] == 12'd260; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_8$read_deq[180:169] == 12'd260; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_9$read_deq[180:169] == 12'd260; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_10$read_deq[180:169] == 12'd260; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_11$read_deq[180:169] == 12'd260; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_12$read_deq[180:169] == 12'd260; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_13$read_deq[180:169] == 12'd260; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_14$read_deq[180:169] == 12'd260; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_15$read_deq[180:169] == 12'd260; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_16$read_deq[180:169] == 12'd260; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_17$read_deq[180:169] == 12'd260; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_18$read_deq[180:169] == 12'd260; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_19$read_deq[180:169] == 12'd260; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_20$read_deq[180:169] == 12'd260; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_21$read_deq[180:169] == 12'd260; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_22$read_deq[180:169] == 12'd260; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_23$read_deq[180:169] == 12'd260; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_24$read_deq[180:169] == 12'd260; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_25$read_deq[180:169] == 12'd260; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_26$read_deq[180:169] == 12'd260; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_27$read_deq[180:169] == 12'd260; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_28$read_deq[180:169] == 12'd260; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_29$read_deq[180:169] == 12'd260; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_30$read_deq[180:169] == 12'd260; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = - m_row_0_31$read_deq[180:169] == 12'd260; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -23333,6 +23202,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd256; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_0$read_deq[180:169] == 12'd260; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_1$read_deq[180:169] == 12'd260; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_2$read_deq[180:169] == 12'd260; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_3$read_deq[180:169] == 12'd260; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_4$read_deq[180:169] == 12'd260; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_5$read_deq[180:169] == 12'd260; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_6$read_deq[180:169] == 12'd260; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_7$read_deq[180:169] == 12'd260; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_8$read_deq[180:169] == 12'd260; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_9$read_deq[180:169] == 12'd260; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_10$read_deq[180:169] == 12'd260; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_11$read_deq[180:169] == 12'd260; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_12$read_deq[180:169] == 12'd260; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_13$read_deq[180:169] == 12'd260; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_14$read_deq[180:169] == 12'd260; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_15$read_deq[180:169] == 12'd260; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_16$read_deq[180:169] == 12'd260; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_17$read_deq[180:169] == 12'd260; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_18$read_deq[180:169] == 12'd260; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_19$read_deq[180:169] == 12'd260; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_20$read_deq[180:169] == 12'd260; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_21$read_deq[180:169] == 12'd260; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_22$read_deq[180:169] == 12'd260; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_23$read_deq[180:169] == 12'd260; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_24$read_deq[180:169] == 12'd260; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_25$read_deq[180:169] == 12'd260; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_26$read_deq[180:169] == 12'd260; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_27$read_deq[180:169] == 12'd260; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_28$read_deq[180:169] == 12'd260; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_29$read_deq[180:169] == 12'd260; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_30$read_deq[180:169] == 12'd260; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5173 = + m_row_0_31$read_deq[180:169] == 12'd260; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -23988,137 +23988,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd262; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_0$read_deq[180:169] == 12'd320; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_1$read_deq[180:169] == 12'd320; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_2$read_deq[180:169] == 12'd320; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_3$read_deq[180:169] == 12'd320; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_4$read_deq[180:169] == 12'd320; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_5$read_deq[180:169] == 12'd320; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_6$read_deq[180:169] == 12'd320; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_7$read_deq[180:169] == 12'd320; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_8$read_deq[180:169] == 12'd320; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_9$read_deq[180:169] == 12'd320; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_10$read_deq[180:169] == 12'd320; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_11$read_deq[180:169] == 12'd320; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_12$read_deq[180:169] == 12'd320; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_13$read_deq[180:169] == 12'd320; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_14$read_deq[180:169] == 12'd320; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_15$read_deq[180:169] == 12'd320; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_16$read_deq[180:169] == 12'd320; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_17$read_deq[180:169] == 12'd320; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_18$read_deq[180:169] == 12'd320; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_19$read_deq[180:169] == 12'd320; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_20$read_deq[180:169] == 12'd320; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_21$read_deq[180:169] == 12'd320; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_22$read_deq[180:169] == 12'd320; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_23$read_deq[180:169] == 12'd320; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_24$read_deq[180:169] == 12'd320; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_25$read_deq[180:169] == 12'd320; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_26$read_deq[180:169] == 12'd320; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_27$read_deq[180:169] == 12'd320; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_28$read_deq[180:169] == 12'd320; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_29$read_deq[180:169] == 12'd320; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_30$read_deq[180:169] == 12'd320; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = - m_row_0_31$read_deq[180:169] == 12'd320; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -24250,6 +24119,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd320; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_0$read_deq[180:169] == 12'd320; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_1$read_deq[180:169] == 12'd320; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_2$read_deq[180:169] == 12'd320; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_3$read_deq[180:169] == 12'd320; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_4$read_deq[180:169] == 12'd320; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_5$read_deq[180:169] == 12'd320; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_6$read_deq[180:169] == 12'd320; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_7$read_deq[180:169] == 12'd320; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_8$read_deq[180:169] == 12'd320; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_9$read_deq[180:169] == 12'd320; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_10$read_deq[180:169] == 12'd320; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_11$read_deq[180:169] == 12'd320; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_12$read_deq[180:169] == 12'd320; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_13$read_deq[180:169] == 12'd320; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_14$read_deq[180:169] == 12'd320; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_15$read_deq[180:169] == 12'd320; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_16$read_deq[180:169] == 12'd320; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_17$read_deq[180:169] == 12'd320; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_18$read_deq[180:169] == 12'd320; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_19$read_deq[180:169] == 12'd320; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_20$read_deq[180:169] == 12'd320; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_21$read_deq[180:169] == 12'd320; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_22$read_deq[180:169] == 12'd320; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_23$read_deq[180:169] == 12'd320; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_24$read_deq[180:169] == 12'd320; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_25$read_deq[180:169] == 12'd320; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_26$read_deq[180:169] == 12'd320; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_27$read_deq[180:169] == 12'd320; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_28$read_deq[180:169] == 12'd320; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_29$read_deq[180:169] == 12'd320; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_30$read_deq[180:169] == 12'd320; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5383 = + m_row_0_31$read_deq[180:169] == 12'd320; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -24512,137 +24512,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd321; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_0$read_deq[180:169] == 12'd322; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_1$read_deq[180:169] == 12'd322; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_2$read_deq[180:169] == 12'd322; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_3$read_deq[180:169] == 12'd322; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_4$read_deq[180:169] == 12'd322; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_5$read_deq[180:169] == 12'd322; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_6$read_deq[180:169] == 12'd322; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_7$read_deq[180:169] == 12'd322; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_8$read_deq[180:169] == 12'd322; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_9$read_deq[180:169] == 12'd322; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_10$read_deq[180:169] == 12'd322; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_11$read_deq[180:169] == 12'd322; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_12$read_deq[180:169] == 12'd322; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_13$read_deq[180:169] == 12'd322; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_14$read_deq[180:169] == 12'd322; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_15$read_deq[180:169] == 12'd322; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_16$read_deq[180:169] == 12'd322; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_17$read_deq[180:169] == 12'd322; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_18$read_deq[180:169] == 12'd322; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_19$read_deq[180:169] == 12'd322; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_20$read_deq[180:169] == 12'd322; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_21$read_deq[180:169] == 12'd322; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_22$read_deq[180:169] == 12'd322; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_23$read_deq[180:169] == 12'd322; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_24$read_deq[180:169] == 12'd322; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_25$read_deq[180:169] == 12'd322; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_26$read_deq[180:169] == 12'd322; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_27$read_deq[180:169] == 12'd322; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_28$read_deq[180:169] == 12'd322; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_29$read_deq[180:169] == 12'd322; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_30$read_deq[180:169] == 12'd322; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = - m_row_1_31$read_deq[180:169] == 12'd322; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -24774,6 +24643,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd322; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_0$read_deq[180:169] == 12'd322; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_1$read_deq[180:169] == 12'd322; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_2$read_deq[180:169] == 12'd322; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_3$read_deq[180:169] == 12'd322; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_4$read_deq[180:169] == 12'd322; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_5$read_deq[180:169] == 12'd322; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_6$read_deq[180:169] == 12'd322; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_7$read_deq[180:169] == 12'd322; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_8$read_deq[180:169] == 12'd322; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_9$read_deq[180:169] == 12'd322; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_10$read_deq[180:169] == 12'd322; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_11$read_deq[180:169] == 12'd322; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_12$read_deq[180:169] == 12'd322; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_13$read_deq[180:169] == 12'd322; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_14$read_deq[180:169] == 12'd322; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_15$read_deq[180:169] == 12'd322; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_16$read_deq[180:169] == 12'd322; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_17$read_deq[180:169] == 12'd322; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_18$read_deq[180:169] == 12'd322; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_19$read_deq[180:169] == 12'd322; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_20$read_deq[180:169] == 12'd322; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_21$read_deq[180:169] == 12'd322; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_22$read_deq[180:169] == 12'd322; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_23$read_deq[180:169] == 12'd322; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_24$read_deq[180:169] == 12'd322; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_25$read_deq[180:169] == 12'd322; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_26$read_deq[180:169] == 12'd322; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_27$read_deq[180:169] == 12'd322; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_28$read_deq[180:169] == 12'd322; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_29$read_deq[180:169] == 12'd322; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_30$read_deq[180:169] == 12'd322; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d5557 = + m_row_1_31$read_deq[180:169] == 12'd322; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -25036,137 +25036,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd323; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_0$read_deq[180:169] == 12'd324; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_1$read_deq[180:169] == 12'd324; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_2$read_deq[180:169] == 12'd324; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_3$read_deq[180:169] == 12'd324; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_4$read_deq[180:169] == 12'd324; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_5$read_deq[180:169] == 12'd324; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_6$read_deq[180:169] == 12'd324; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_7$read_deq[180:169] == 12'd324; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_8$read_deq[180:169] == 12'd324; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_9$read_deq[180:169] == 12'd324; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_10$read_deq[180:169] == 12'd324; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_11$read_deq[180:169] == 12'd324; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_12$read_deq[180:169] == 12'd324; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_13$read_deq[180:169] == 12'd324; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_14$read_deq[180:169] == 12'd324; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_15$read_deq[180:169] == 12'd324; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_16$read_deq[180:169] == 12'd324; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_17$read_deq[180:169] == 12'd324; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_18$read_deq[180:169] == 12'd324; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_19$read_deq[180:169] == 12'd324; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_20$read_deq[180:169] == 12'd324; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_21$read_deq[180:169] == 12'd324; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_22$read_deq[180:169] == 12'd324; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_23$read_deq[180:169] == 12'd324; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_24$read_deq[180:169] == 12'd324; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_25$read_deq[180:169] == 12'd324; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_26$read_deq[180:169] == 12'd324; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_27$read_deq[180:169] == 12'd324; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_28$read_deq[180:169] == 12'd324; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_29$read_deq[180:169] == 12'd324; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_30$read_deq[180:169] == 12'd324; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = - m_row_0_31$read_deq[180:169] == 12'd324; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -25298,6 +25167,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd324; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_0$read_deq[180:169] == 12'd324; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_1$read_deq[180:169] == 12'd324; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_2$read_deq[180:169] == 12'd324; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_3$read_deq[180:169] == 12'd324; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_4$read_deq[180:169] == 12'd324; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_5$read_deq[180:169] == 12'd324; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_6$read_deq[180:169] == 12'd324; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_7$read_deq[180:169] == 12'd324; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_8$read_deq[180:169] == 12'd324; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_9$read_deq[180:169] == 12'd324; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_10$read_deq[180:169] == 12'd324; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_11$read_deq[180:169] == 12'd324; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_12$read_deq[180:169] == 12'd324; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_13$read_deq[180:169] == 12'd324; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_14$read_deq[180:169] == 12'd324; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_15$read_deq[180:169] == 12'd324; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_16$read_deq[180:169] == 12'd324; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_17$read_deq[180:169] == 12'd324; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_18$read_deq[180:169] == 12'd324; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_19$read_deq[180:169] == 12'd324; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_20$read_deq[180:169] == 12'd324; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_21$read_deq[180:169] == 12'd324; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_22$read_deq[180:169] == 12'd324; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_23$read_deq[180:169] == 12'd324; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_24$read_deq[180:169] == 12'd324; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_25$read_deq[180:169] == 12'd324; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_26$read_deq[180:169] == 12'd324; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_27$read_deq[180:169] == 12'd324; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_28$read_deq[180:169] == 12'd324; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_29$read_deq[180:169] == 12'd324; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_30$read_deq[180:169] == 12'd324; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5663 = + m_row_0_31$read_deq[180:169] == 12'd324; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -25429,6 +25429,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd384; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_0$read_deq[180:169] == 12'd768; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_1$read_deq[180:169] == 12'd768; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_2$read_deq[180:169] == 12'd768; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_3$read_deq[180:169] == 12'd768; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_4$read_deq[180:169] == 12'd768; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_5$read_deq[180:169] == 12'd768; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_6$read_deq[180:169] == 12'd768; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_7$read_deq[180:169] == 12'd768; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_8$read_deq[180:169] == 12'd768; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_9$read_deq[180:169] == 12'd768; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_10$read_deq[180:169] == 12'd768; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_11$read_deq[180:169] == 12'd768; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_12$read_deq[180:169] == 12'd768; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_13$read_deq[180:169] == 12'd768; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_14$read_deq[180:169] == 12'd768; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_15$read_deq[180:169] == 12'd768; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_16$read_deq[180:169] == 12'd768; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_17$read_deq[180:169] == 12'd768; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_18$read_deq[180:169] == 12'd768; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_19$read_deq[180:169] == 12'd768; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_20$read_deq[180:169] == 12'd768; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_21$read_deq[180:169] == 12'd768; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_22$read_deq[180:169] == 12'd768; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_23$read_deq[180:169] == 12'd768; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_24$read_deq[180:169] == 12'd768; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_25$read_deq[180:169] == 12'd768; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_26$read_deq[180:169] == 12'd768; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_27$read_deq[180:169] == 12'd768; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_28$read_deq[180:169] == 12'd768; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_29$read_deq[180:169] == 12'd768; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_30$read_deq[180:169] == 12'd768; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = + m_row_0_31$read_deq[180:169] == 12'd768; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -25691,137 +25822,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd768; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_0$read_deq[180:169] == 12'd768; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_1$read_deq[180:169] == 12'd768; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_2$read_deq[180:169] == 12'd768; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_3$read_deq[180:169] == 12'd768; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_4$read_deq[180:169] == 12'd768; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_5$read_deq[180:169] == 12'd768; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_6$read_deq[180:169] == 12'd768; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_7$read_deq[180:169] == 12'd768; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_8$read_deq[180:169] == 12'd768; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_9$read_deq[180:169] == 12'd768; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_10$read_deq[180:169] == 12'd768; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_11$read_deq[180:169] == 12'd768; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_12$read_deq[180:169] == 12'd768; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_13$read_deq[180:169] == 12'd768; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_14$read_deq[180:169] == 12'd768; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_15$read_deq[180:169] == 12'd768; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_16$read_deq[180:169] == 12'd768; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_17$read_deq[180:169] == 12'd768; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_18$read_deq[180:169] == 12'd768; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_19$read_deq[180:169] == 12'd768; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_20$read_deq[180:169] == 12'd768; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_21$read_deq[180:169] == 12'd768; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_22$read_deq[180:169] == 12'd768; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_23$read_deq[180:169] == 12'd768; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_24$read_deq[180:169] == 12'd768; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_25$read_deq[180:169] == 12'd768; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_26$read_deq[180:169] == 12'd768; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_27$read_deq[180:169] == 12'd768; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_28$read_deq[180:169] == 12'd768; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_29$read_deq[180:169] == 12'd768; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_30$read_deq[180:169] == 12'd768; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5803 = - m_row_0_31$read_deq[180:169] == 12'd768; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -25953,137 +25953,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd769; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_0$read_deq[180:169] == 12'd770; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_1$read_deq[180:169] == 12'd770; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_2$read_deq[180:169] == 12'd770; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_3$read_deq[180:169] == 12'd770; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_4$read_deq[180:169] == 12'd770; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_5$read_deq[180:169] == 12'd770; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_6$read_deq[180:169] == 12'd770; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_7$read_deq[180:169] == 12'd770; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_8$read_deq[180:169] == 12'd770; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_9$read_deq[180:169] == 12'd770; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_10$read_deq[180:169] == 12'd770; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_11$read_deq[180:169] == 12'd770; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_12$read_deq[180:169] == 12'd770; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_13$read_deq[180:169] == 12'd770; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_14$read_deq[180:169] == 12'd770; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_15$read_deq[180:169] == 12'd770; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_16$read_deq[180:169] == 12'd770; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_17$read_deq[180:169] == 12'd770; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_18$read_deq[180:169] == 12'd770; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_19$read_deq[180:169] == 12'd770; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_20$read_deq[180:169] == 12'd770; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_21$read_deq[180:169] == 12'd770; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_22$read_deq[180:169] == 12'd770; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_23$read_deq[180:169] == 12'd770; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_24$read_deq[180:169] == 12'd770; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_25$read_deq[180:169] == 12'd770; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_26$read_deq[180:169] == 12'd770; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_27$read_deq[180:169] == 12'd770; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_28$read_deq[180:169] == 12'd770; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_29$read_deq[180:169] == 12'd770; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_30$read_deq[180:169] == 12'd770; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = - m_row_0_31$read_deq[180:169] == 12'd770; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -26215,6 +26084,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd769; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_0$read_deq[180:169] == 12'd770; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_1$read_deq[180:169] == 12'd770; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_2$read_deq[180:169] == 12'd770; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_3$read_deq[180:169] == 12'd770; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_4$read_deq[180:169] == 12'd770; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_5$read_deq[180:169] == 12'd770; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_6$read_deq[180:169] == 12'd770; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_7$read_deq[180:169] == 12'd770; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_8$read_deq[180:169] == 12'd770; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_9$read_deq[180:169] == 12'd770; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_10$read_deq[180:169] == 12'd770; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_11$read_deq[180:169] == 12'd770; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_12$read_deq[180:169] == 12'd770; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_13$read_deq[180:169] == 12'd770; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_14$read_deq[180:169] == 12'd770; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_15$read_deq[180:169] == 12'd770; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_16$read_deq[180:169] == 12'd770; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_17$read_deq[180:169] == 12'd770; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_18$read_deq[180:169] == 12'd770; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_19$read_deq[180:169] == 12'd770; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_20$read_deq[180:169] == 12'd770; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_21$read_deq[180:169] == 12'd770; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_22$read_deq[180:169] == 12'd770; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_23$read_deq[180:169] == 12'd770; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_24$read_deq[180:169] == 12'd770; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_25$read_deq[180:169] == 12'd770; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_26$read_deq[180:169] == 12'd770; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_27$read_deq[180:169] == 12'd770; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_28$read_deq[180:169] == 12'd770; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_29$read_deq[180:169] == 12'd770; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_30$read_deq[180:169] == 12'd770; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d5943 = + m_row_0_31$read_deq[180:169] == 12'd770; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -26870,137 +26870,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd772; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_0$read_deq[180:169] == 12'd773; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_1$read_deq[180:169] == 12'd773; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_2$read_deq[180:169] == 12'd773; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_3$read_deq[180:169] == 12'd773; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_4$read_deq[180:169] == 12'd773; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_5$read_deq[180:169] == 12'd773; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_6$read_deq[180:169] == 12'd773; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_7$read_deq[180:169] == 12'd773; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_8$read_deq[180:169] == 12'd773; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_9$read_deq[180:169] == 12'd773; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_10$read_deq[180:169] == 12'd773; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_11$read_deq[180:169] == 12'd773; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_12$read_deq[180:169] == 12'd773; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_13$read_deq[180:169] == 12'd773; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_14$read_deq[180:169] == 12'd773; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_15$read_deq[180:169] == 12'd773; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_16$read_deq[180:169] == 12'd773; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_17$read_deq[180:169] == 12'd773; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_18$read_deq[180:169] == 12'd773; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_19$read_deq[180:169] == 12'd773; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_20$read_deq[180:169] == 12'd773; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_21$read_deq[180:169] == 12'd773; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_22$read_deq[180:169] == 12'd773; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_23$read_deq[180:169] == 12'd773; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_24$read_deq[180:169] == 12'd773; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_25$read_deq[180:169] == 12'd773; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_26$read_deq[180:169] == 12'd773; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_27$read_deq[180:169] == 12'd773; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_28$read_deq[180:169] == 12'd773; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_29$read_deq[180:169] == 12'd773; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_30$read_deq[180:169] == 12'd773; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = - m_row_0_31$read_deq[180:169] == 12'd773; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -27132,6 +27001,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd773; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_0$read_deq[180:169] == 12'd773; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_1$read_deq[180:169] == 12'd773; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_2$read_deq[180:169] == 12'd773; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_3$read_deq[180:169] == 12'd773; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_4$read_deq[180:169] == 12'd773; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_5$read_deq[180:169] == 12'd773; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_6$read_deq[180:169] == 12'd773; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_7$read_deq[180:169] == 12'd773; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_8$read_deq[180:169] == 12'd773; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_9$read_deq[180:169] == 12'd773; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_10$read_deq[180:169] == 12'd773; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_11$read_deq[180:169] == 12'd773; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_12$read_deq[180:169] == 12'd773; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_13$read_deq[180:169] == 12'd773; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_14$read_deq[180:169] == 12'd773; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_15$read_deq[180:169] == 12'd773; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_16$read_deq[180:169] == 12'd773; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_17$read_deq[180:169] == 12'd773; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_18$read_deq[180:169] == 12'd773; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_19$read_deq[180:169] == 12'd773; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_20$read_deq[180:169] == 12'd773; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_21$read_deq[180:169] == 12'd773; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_22$read_deq[180:169] == 12'd773; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_23$read_deq[180:169] == 12'd773; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_24$read_deq[180:169] == 12'd773; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_25$read_deq[180:169] == 12'd773; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_26$read_deq[180:169] == 12'd773; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_27$read_deq[180:169] == 12'd773; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_28$read_deq[180:169] == 12'd773; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_29$read_deq[180:169] == 12'd773; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_30$read_deq[180:169] == 12'd773; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6153 = + m_row_0_31$read_deq[180:169] == 12'd773; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -27394,137 +27394,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd774; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_0$read_deq[180:169] == 12'd832; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_1$read_deq[180:169] == 12'd832; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_2$read_deq[180:169] == 12'd832; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_3$read_deq[180:169] == 12'd832; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_4$read_deq[180:169] == 12'd832; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_5$read_deq[180:169] == 12'd832; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_6$read_deq[180:169] == 12'd832; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_7$read_deq[180:169] == 12'd832; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_8$read_deq[180:169] == 12'd832; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_9$read_deq[180:169] == 12'd832; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_10$read_deq[180:169] == 12'd832; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_11$read_deq[180:169] == 12'd832; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_12$read_deq[180:169] == 12'd832; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_13$read_deq[180:169] == 12'd832; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_14$read_deq[180:169] == 12'd832; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_15$read_deq[180:169] == 12'd832; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_16$read_deq[180:169] == 12'd832; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_17$read_deq[180:169] == 12'd832; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_18$read_deq[180:169] == 12'd832; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_19$read_deq[180:169] == 12'd832; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_20$read_deq[180:169] == 12'd832; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_21$read_deq[180:169] == 12'd832; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_22$read_deq[180:169] == 12'd832; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_23$read_deq[180:169] == 12'd832; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_24$read_deq[180:169] == 12'd832; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_25$read_deq[180:169] == 12'd832; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_26$read_deq[180:169] == 12'd832; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_27$read_deq[180:169] == 12'd832; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_28$read_deq[180:169] == 12'd832; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_29$read_deq[180:169] == 12'd832; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_30$read_deq[180:169] == 12'd832; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = - m_row_1_31$read_deq[180:169] == 12'd832; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -27656,6 +27525,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd832; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_0$read_deq[180:169] == 12'd832; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_1$read_deq[180:169] == 12'd832; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_2$read_deq[180:169] == 12'd832; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_3$read_deq[180:169] == 12'd832; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_4$read_deq[180:169] == 12'd832; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_5$read_deq[180:169] == 12'd832; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_6$read_deq[180:169] == 12'd832; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_7$read_deq[180:169] == 12'd832; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_8$read_deq[180:169] == 12'd832; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_9$read_deq[180:169] == 12'd832; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_10$read_deq[180:169] == 12'd832; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_11$read_deq[180:169] == 12'd832; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_12$read_deq[180:169] == 12'd832; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_13$read_deq[180:169] == 12'd832; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_14$read_deq[180:169] == 12'd832; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_15$read_deq[180:169] == 12'd832; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_16$read_deq[180:169] == 12'd832; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_17$read_deq[180:169] == 12'd832; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_18$read_deq[180:169] == 12'd832; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_19$read_deq[180:169] == 12'd832; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_20$read_deq[180:169] == 12'd832; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_21$read_deq[180:169] == 12'd832; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_22$read_deq[180:169] == 12'd832; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_23$read_deq[180:169] == 12'd832; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_24$read_deq[180:169] == 12'd832; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_25$read_deq[180:169] == 12'd832; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_26$read_deq[180:169] == 12'd832; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_27$read_deq[180:169] == 12'd832; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_28$read_deq[180:169] == 12'd832; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_29$read_deq[180:169] == 12'd832; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_30$read_deq[180:169] == 12'd832; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BITS_180_TO_16_ETC___d6327 = + m_row_1_31$read_deq[180:169] == 12'd832; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -27918,137 +27918,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd833; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_0$read_deq[180:169] == 12'd834; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_1$read_deq[180:169] == 12'd834; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_2$read_deq[180:169] == 12'd834; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_3$read_deq[180:169] == 12'd834; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_4$read_deq[180:169] == 12'd834; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_5$read_deq[180:169] == 12'd834; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_6$read_deq[180:169] == 12'd834; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_7$read_deq[180:169] == 12'd834; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_8$read_deq[180:169] == 12'd834; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_9$read_deq[180:169] == 12'd834; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_10$read_deq[180:169] == 12'd834; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_11$read_deq[180:169] == 12'd834; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_12$read_deq[180:169] == 12'd834; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_13$read_deq[180:169] == 12'd834; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_14$read_deq[180:169] == 12'd834; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_15$read_deq[180:169] == 12'd834; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_16$read_deq[180:169] == 12'd834; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_17$read_deq[180:169] == 12'd834; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_18$read_deq[180:169] == 12'd834; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_19$read_deq[180:169] == 12'd834; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_20$read_deq[180:169] == 12'd834; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_21$read_deq[180:169] == 12'd834; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_22$read_deq[180:169] == 12'd834; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_23$read_deq[180:169] == 12'd834; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_24$read_deq[180:169] == 12'd834; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_25$read_deq[180:169] == 12'd834; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_26$read_deq[180:169] == 12'd834; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_27$read_deq[180:169] == 12'd834; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_28$read_deq[180:169] == 12'd834; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_29$read_deq[180:169] == 12'd834; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_30$read_deq[180:169] == 12'd834; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = - m_row_0_31$read_deq[180:169] == 12'd834; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -28180,6 +28049,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd834; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_0$read_deq[180:169] == 12'd834; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_1$read_deq[180:169] == 12'd834; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_2$read_deq[180:169] == 12'd834; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_3$read_deq[180:169] == 12'd834; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_4$read_deq[180:169] == 12'd834; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_5$read_deq[180:169] == 12'd834; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_6$read_deq[180:169] == 12'd834; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_7$read_deq[180:169] == 12'd834; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_8$read_deq[180:169] == 12'd834; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_9$read_deq[180:169] == 12'd834; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_10$read_deq[180:169] == 12'd834; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_11$read_deq[180:169] == 12'd834; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_12$read_deq[180:169] == 12'd834; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_13$read_deq[180:169] == 12'd834; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_14$read_deq[180:169] == 12'd834; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_15$read_deq[180:169] == 12'd834; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_16$read_deq[180:169] == 12'd834; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_17$read_deq[180:169] == 12'd834; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_18$read_deq[180:169] == 12'd834; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_19$read_deq[180:169] == 12'd834; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_20$read_deq[180:169] == 12'd834; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_21$read_deq[180:169] == 12'd834; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_22$read_deq[180:169] == 12'd834; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_23$read_deq[180:169] == 12'd834; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_24$read_deq[180:169] == 12'd834; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_25$read_deq[180:169] == 12'd834; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_26$read_deq[180:169] == 12'd834; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_27$read_deq[180:169] == 12'd834; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_28$read_deq[180:169] == 12'd834; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_29$read_deq[180:169] == 12'd834; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_30$read_deq[180:169] == 12'd834; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6433 = + m_row_0_31$read_deq[180:169] == 12'd834; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -28311,6 +28311,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd835; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_0$read_deq[180:169] == 12'd836; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_1$read_deq[180:169] == 12'd836; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_2$read_deq[180:169] == 12'd836; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_3$read_deq[180:169] == 12'd836; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_4$read_deq[180:169] == 12'd836; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_5$read_deq[180:169] == 12'd836; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_6$read_deq[180:169] == 12'd836; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_7$read_deq[180:169] == 12'd836; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_8$read_deq[180:169] == 12'd836; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_9$read_deq[180:169] == 12'd836; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_10$read_deq[180:169] == 12'd836; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_11$read_deq[180:169] == 12'd836; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_12$read_deq[180:169] == 12'd836; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_13$read_deq[180:169] == 12'd836; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_14$read_deq[180:169] == 12'd836; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_15$read_deq[180:169] == 12'd836; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_16$read_deq[180:169] == 12'd836; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_17$read_deq[180:169] == 12'd836; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_18$read_deq[180:169] == 12'd836; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_19$read_deq[180:169] == 12'd836; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_20$read_deq[180:169] == 12'd836; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_21$read_deq[180:169] == 12'd836; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_22$read_deq[180:169] == 12'd836; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_23$read_deq[180:169] == 12'd836; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_24$read_deq[180:169] == 12'd836; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_25$read_deq[180:169] == 12'd836; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_26$read_deq[180:169] == 12'd836; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_27$read_deq[180:169] == 12'd836; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_28$read_deq[180:169] == 12'd836; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_29$read_deq[180:169] == 12'd836; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_30$read_deq[180:169] == 12'd836; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = + m_row_0_31$read_deq[180:169] == 12'd836; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -28573,137 +28704,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd836; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_0$read_deq[180:169] == 12'd836; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_1$read_deq[180:169] == 12'd836; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_2$read_deq[180:169] == 12'd836; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_3$read_deq[180:169] == 12'd836; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_4$read_deq[180:169] == 12'd836; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_5$read_deq[180:169] == 12'd836; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_6$read_deq[180:169] == 12'd836; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_7$read_deq[180:169] == 12'd836; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_8$read_deq[180:169] == 12'd836; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_9$read_deq[180:169] == 12'd836; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_10$read_deq[180:169] == 12'd836; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_11$read_deq[180:169] == 12'd836; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_12$read_deq[180:169] == 12'd836; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_13$read_deq[180:169] == 12'd836; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_14$read_deq[180:169] == 12'd836; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_15$read_deq[180:169] == 12'd836; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_16$read_deq[180:169] == 12'd836; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_17$read_deq[180:169] == 12'd836; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_18$read_deq[180:169] == 12'd836; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_19$read_deq[180:169] == 12'd836; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_20$read_deq[180:169] == 12'd836; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_21$read_deq[180:169] == 12'd836; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_22$read_deq[180:169] == 12'd836; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_23$read_deq[180:169] == 12'd836; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_24$read_deq[180:169] == 12'd836; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_25$read_deq[180:169] == 12'd836; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_26$read_deq[180:169] == 12'd836; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_27$read_deq[180:169] == 12'd836; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_28$read_deq[180:169] == 12'd836; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_29$read_deq[180:169] == 12'd836; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_30$read_deq[180:169] == 12'd836; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6573 = - m_row_0_31$read_deq[180:169] == 12'd836; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -28835,137 +28835,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[180:169] == 12'd2816; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_0$read_deq[180:169] == 12'd2818; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_1$read_deq[180:169] == 12'd2818; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_2$read_deq[180:169] == 12'd2818; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_3$read_deq[180:169] == 12'd2818; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_4$read_deq[180:169] == 12'd2818; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_5$read_deq[180:169] == 12'd2818; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_6$read_deq[180:169] == 12'd2818; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_7$read_deq[180:169] == 12'd2818; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_8$read_deq[180:169] == 12'd2818; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_9$read_deq[180:169] == 12'd2818; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_10$read_deq[180:169] == 12'd2818; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_11$read_deq[180:169] == 12'd2818; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_12$read_deq[180:169] == 12'd2818; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_13$read_deq[180:169] == 12'd2818; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_14$read_deq[180:169] == 12'd2818; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_15$read_deq[180:169] == 12'd2818; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_16$read_deq[180:169] == 12'd2818; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_17$read_deq[180:169] == 12'd2818; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_18$read_deq[180:169] == 12'd2818; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_19$read_deq[180:169] == 12'd2818; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_20$read_deq[180:169] == 12'd2818; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_21$read_deq[180:169] == 12'd2818; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_22$read_deq[180:169] == 12'd2818; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_23$read_deq[180:169] == 12'd2818; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_24$read_deq[180:169] == 12'd2818; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_25$read_deq[180:169] == 12'd2818; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_26$read_deq[180:169] == 12'd2818; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_27$read_deq[180:169] == 12'd2818; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_28$read_deq[180:169] == 12'd2818; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_29$read_deq[180:169] == 12'd2818; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_30$read_deq[180:169] == 12'd2818; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = - m_row_0_31$read_deq[180:169] == 12'd2818; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -29097,6 +28966,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd2816; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_0$read_deq[180:169] == 12'd2818; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_1$read_deq[180:169] == 12'd2818; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_2$read_deq[180:169] == 12'd2818; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_3$read_deq[180:169] == 12'd2818; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_4$read_deq[180:169] == 12'd2818; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_5$read_deq[180:169] == 12'd2818; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_6$read_deq[180:169] == 12'd2818; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_7$read_deq[180:169] == 12'd2818; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_8$read_deq[180:169] == 12'd2818; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_9$read_deq[180:169] == 12'd2818; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_10$read_deq[180:169] == 12'd2818; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_11$read_deq[180:169] == 12'd2818; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_12$read_deq[180:169] == 12'd2818; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_13$read_deq[180:169] == 12'd2818; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_14$read_deq[180:169] == 12'd2818; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_15$read_deq[180:169] == 12'd2818; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_16$read_deq[180:169] == 12'd2818; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_17$read_deq[180:169] == 12'd2818; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_18$read_deq[180:169] == 12'd2818; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_19$read_deq[180:169] == 12'd2818; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_20$read_deq[180:169] == 12'd2818; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_21$read_deq[180:169] == 12'd2818; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_22$read_deq[180:169] == 12'd2818; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_23$read_deq[180:169] == 12'd2818; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_24$read_deq[180:169] == 12'd2818; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_25$read_deq[180:169] == 12'd2818; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_26$read_deq[180:169] == 12'd2818; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_27$read_deq[180:169] == 12'd2818; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_28$read_deq[180:169] == 12'd2818; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_29$read_deq[180:169] == 12'd2818; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_30$read_deq[180:169] == 12'd2818; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6713 = + m_row_0_31$read_deq[180:169] == 12'd2818; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -29752,137 +29752,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd3858; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_0$read_deq[180:169] == 12'd3859; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_1$read_deq[180:169] == 12'd3859; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_2$read_deq[180:169] == 12'd3859; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_3$read_deq[180:169] == 12'd3859; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_4$read_deq[180:169] == 12'd3859; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_5$read_deq[180:169] == 12'd3859; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_6$read_deq[180:169] == 12'd3859; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_7$read_deq[180:169] == 12'd3859; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_8$read_deq[180:169] == 12'd3859; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_9$read_deq[180:169] == 12'd3859; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_10$read_deq[180:169] == 12'd3859; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_11$read_deq[180:169] == 12'd3859; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_12$read_deq[180:169] == 12'd3859; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_13$read_deq[180:169] == 12'd3859; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_14$read_deq[180:169] == 12'd3859; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_15$read_deq[180:169] == 12'd3859; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_16$read_deq[180:169] == 12'd3859; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_17$read_deq[180:169] == 12'd3859; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_18$read_deq[180:169] == 12'd3859; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_19$read_deq[180:169] == 12'd3859; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_20$read_deq[180:169] == 12'd3859; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_21$read_deq[180:169] == 12'd3859; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_22$read_deq[180:169] == 12'd3859; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_23$read_deq[180:169] == 12'd3859; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_24$read_deq[180:169] == 12'd3859; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_25$read_deq[180:169] == 12'd3859; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_26$read_deq[180:169] == 12'd3859; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_27$read_deq[180:169] == 12'd3859; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_28$read_deq[180:169] == 12'd3859; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_29$read_deq[180:169] == 12'd3859; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_30$read_deq[180:169] == 12'd3859; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = - m_row_0_31$read_deq[180:169] == 12'd3859; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -30014,6 +29883,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd3859; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_0$read_deq[180:169] == 12'd3859; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_1$read_deq[180:169] == 12'd3859; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_2$read_deq[180:169] == 12'd3859; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_3$read_deq[180:169] == 12'd3859; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_4$read_deq[180:169] == 12'd3859; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_5$read_deq[180:169] == 12'd3859; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_6$read_deq[180:169] == 12'd3859; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_7$read_deq[180:169] == 12'd3859; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_8$read_deq[180:169] == 12'd3859; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_9$read_deq[180:169] == 12'd3859; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_10$read_deq[180:169] == 12'd3859; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_11$read_deq[180:169] == 12'd3859; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_12$read_deq[180:169] == 12'd3859; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_13$read_deq[180:169] == 12'd3859; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_14$read_deq[180:169] == 12'd3859; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_15$read_deq[180:169] == 12'd3859; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_16$read_deq[180:169] == 12'd3859; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_17$read_deq[180:169] == 12'd3859; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_18$read_deq[180:169] == 12'd3859; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_19$read_deq[180:169] == 12'd3859; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_20$read_deq[180:169] == 12'd3859; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_21$read_deq[180:169] == 12'd3859; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_22$read_deq[180:169] == 12'd3859; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_23$read_deq[180:169] == 12'd3859; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_24$read_deq[180:169] == 12'd3859; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_25$read_deq[180:169] == 12'd3859; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_26$read_deq[180:169] == 12'd3859; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_27$read_deq[180:169] == 12'd3859; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_28$read_deq[180:169] == 12'd3859; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_29$read_deq[180:169] == 12'd3859; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_30$read_deq[180:169] == 12'd3859; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_180_TO_16_ETC___d6923 = + m_row_0_31$read_deq[180:169] == 12'd3859; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -30276,137 +30276,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[180:169] == 12'd3860; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_0$read_deq[168]; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_1$read_deq[168]; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_2$read_deq[168]; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_3$read_deq[168]; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_4$read_deq[168]; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_5$read_deq[168]; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_6$read_deq[168]; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_7$read_deq[168]; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_8$read_deq[168]; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_9$read_deq[168]; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_10$read_deq[168]; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_11$read_deq[168]; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_12$read_deq[168]; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_13$read_deq[168]; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_14$read_deq[168]; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_15$read_deq[168]; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_16$read_deq[168]; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_17$read_deq[168]; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_18$read_deq[168]; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_19$read_deq[168]; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_20$read_deq[168]; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_21$read_deq[168]; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_22$read_deq[168]; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_23$read_deq[168]; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_24$read_deq[168]; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_25$read_deq[168]; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_26$read_deq[168]; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_27$read_deq[168]; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_28$read_deq[168]; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_29$read_deq[168]; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_30$read_deq[168]; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = - m_row_1_31$read_deq[168]; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -30538,6 +30407,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[168]; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_0$read_deq[168]; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_1$read_deq[168]; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_2$read_deq[168]; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_3$read_deq[168]; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_4$read_deq[168]; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_5$read_deq[168]; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_6$read_deq[168]; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_7$read_deq[168]; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_8$read_deq[168]; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_9$read_deq[168]; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_10$read_deq[168]; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_11$read_deq[168]; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_12$read_deq[168]; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_13$read_deq[168]; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_14$read_deq[168]; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_15$read_deq[168]; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_16$read_deq[168]; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_17$read_deq[168]; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_18$read_deq[168]; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_19$read_deq[168]; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_20$read_deq[168]; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_21$read_deq[168]; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_22$read_deq[168]; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_23$read_deq[168]; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_24$read_deq[168]; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_25$read_deq[168]; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_26$read_deq[168]; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_27$read_deq[168]; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_28$read_deq[168]; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_29$read_deq[168]; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_30$read_deq[168]; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BIT_168_102_m__ETC___d7135 = + m_row_1_31$read_deq[168]; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -30800,137 +30800,6 @@ module mkReorderBufferSynth(CLK, !m_row_1_31$read_deq[167]; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_0$read_deq[166]; - 5'd1: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_1$read_deq[166]; - 5'd2: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_2$read_deq[166]; - 5'd3: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_3$read_deq[166]; - 5'd4: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_4$read_deq[166]; - 5'd5: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_5$read_deq[166]; - 5'd6: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_6$read_deq[166]; - 5'd7: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_7$read_deq[166]; - 5'd8: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_8$read_deq[166]; - 5'd9: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_9$read_deq[166]; - 5'd10: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_10$read_deq[166]; - 5'd11: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_11$read_deq[166]; - 5'd12: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_12$read_deq[166]; - 5'd13: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_13$read_deq[166]; - 5'd14: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_14$read_deq[166]; - 5'd15: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_15$read_deq[166]; - 5'd16: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_16$read_deq[166]; - 5'd17: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_17$read_deq[166]; - 5'd18: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_18$read_deq[166]; - 5'd19: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_19$read_deq[166]; - 5'd20: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_20$read_deq[166]; - 5'd21: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_21$read_deq[166]; - 5'd22: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_22$read_deq[166]; - 5'd23: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_23$read_deq[166]; - 5'd24: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_24$read_deq[166]; - 5'd25: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_25$read_deq[166]; - 5'd26: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_26$read_deq[166]; - 5'd27: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_27$read_deq[166]; - 5'd28: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_28$read_deq[166]; - 5'd29: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_29$read_deq[166]; - 5'd30: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_30$read_deq[166]; - 5'd31: - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = - !m_row_0_31$read_deq[166]; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -31062,6 +30931,137 @@ module mkReorderBufferSynth(CLK, !m_row_1_31$read_deq[166]; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_0$read_deq[166]; + 5'd1: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_1$read_deq[166]; + 5'd2: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_2$read_deq[166]; + 5'd3: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_3$read_deq[166]; + 5'd4: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_4$read_deq[166]; + 5'd5: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_5$read_deq[166]; + 5'd6: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_6$read_deq[166]; + 5'd7: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_7$read_deq[166]; + 5'd8: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_8$read_deq[166]; + 5'd9: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_9$read_deq[166]; + 5'd10: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_10$read_deq[166]; + 5'd11: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_11$read_deq[166]; + 5'd12: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_12$read_deq[166]; + 5'd13: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_13$read_deq[166]; + 5'd14: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_14$read_deq[166]; + 5'd15: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_15$read_deq[166]; + 5'd16: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_16$read_deq[166]; + 5'd17: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_17$read_deq[166]; + 5'd18: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_18$read_deq[166]; + 5'd19: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_19$read_deq[166]; + 5'd20: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_20$read_deq[166]; + 5'd21: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_21$read_deq[166]; + 5'd22: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_22$read_deq[166]; + 5'd23: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_23$read_deq[166]; + 5'd24: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_24$read_deq[166]; + 5'd25: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_25$read_deq[166]; + 5'd26: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_26$read_deq[166]; + 5'd27: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_27$read_deq[166]; + 5'd28: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_28$read_deq[166]; + 5'd29: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_29$read_deq[166]; + 5'd30: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_30$read_deq[166]; + 5'd31: + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 = + !m_row_0_31$read_deq[166]; + endcase + end always@(x__h99963 or SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_166_27_ETC___d7338 or SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_166_33_ETC___d7404) @@ -31091,22 +31091,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_2$read_deq) - begin - case (m_row_0_2$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = - m_row_0_2$read_deq[165:162]; - 4'd11: - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = 4'd10; - 4'd12: - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = 4'd11; - 4'd13: - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = 4'd12; - default: IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = - 4'd13; - endcase - end always@(m_row_0_1$read_deq) begin case (m_row_0_1$read_deq[165:162]) @@ -31123,6 +31107,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_2$read_deq) + begin + case (m_row_0_2$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = + m_row_0_2$read_deq[165:162]; + 4'd11: + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = 4'd10; + 4'd12: + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = 4'd11; + 4'd13: + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = 4'd12; + default: IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 = + 4'd13; + endcase + end always@(m_row_0_3$read_deq) begin case (m_row_0_3$read_deq[165:162]) @@ -31139,22 +31139,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_5$read_deq) - begin - case (m_row_0_5$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = - m_row_0_5$read_deq[165:162]; - 4'd11: - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = 4'd10; - 4'd12: - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = 4'd11; - 4'd13: - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = 4'd12; - default: IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = - 4'd13; - endcase - end always@(m_row_0_4$read_deq) begin case (m_row_0_4$read_deq[165:162]) @@ -31171,6 +31155,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_5$read_deq) + begin + case (m_row_0_5$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = + m_row_0_5$read_deq[165:162]; + 4'd11: + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = 4'd10; + 4'd12: + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = 4'd11; + 4'd13: + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = 4'd12; + default: IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 = + 4'd13; + endcase + end always@(m_row_0_6$read_deq) begin case (m_row_0_6$read_deq[165:162]) @@ -31203,22 +31203,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_8$read_deq) - begin - case (m_row_0_8$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = - m_row_0_8$read_deq[165:162]; - 4'd11: - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = 4'd10; - 4'd12: - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = 4'd11; - 4'd13: - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = 4'd12; - default: IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = - 4'd13; - endcase - end always@(m_row_0_9$read_deq) begin case (m_row_0_9$read_deq[165:162]) @@ -31235,6 +31219,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_8$read_deq) + begin + case (m_row_0_8$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = + m_row_0_8$read_deq[165:162]; + 4'd11: + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = 4'd10; + 4'd12: + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = 4'd11; + 4'd13: + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = 4'd12; + default: IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 = + 4'd13; + endcase + end always@(m_row_0_10$read_deq) begin case (m_row_0_10$read_deq[165:162]) @@ -31251,6 +31251,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_12$read_deq) + begin + case (m_row_0_12$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = + m_row_0_12$read_deq[165:162]; + 4'd11: + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = 4'd10; + 4'd12: + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = 4'd11; + 4'd13: + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = 4'd12; + default: IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = + 4'd13; + endcase + end always@(m_row_0_11$read_deq) begin case (m_row_0_11$read_deq[165:162]) @@ -31283,22 +31299,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_12$read_deq) - begin - case (m_row_0_12$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = - m_row_0_12$read_deq[165:162]; - 4'd11: - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = 4'd10; - 4'd12: - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = 4'd11; - 4'd13: - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = 4'd12; - default: IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 = - 4'd13; - endcase - end always@(m_row_0_14$read_deq) begin case (m_row_0_14$read_deq[165:162]) @@ -31315,22 +31315,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_16$read_deq) - begin - case (m_row_0_16$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = - m_row_0_16$read_deq[165:162]; - 4'd11: - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = 4'd10; - 4'd12: - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = 4'd11; - 4'd13: - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = 4'd12; - default: IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = - 4'd13; - endcase - end always@(m_row_0_15$read_deq) begin case (m_row_0_15$read_deq[165:162]) @@ -31347,6 +31331,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_16$read_deq) + begin + case (m_row_0_16$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = + m_row_0_16$read_deq[165:162]; + 4'd11: + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = 4'd10; + 4'd12: + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = 4'd11; + 4'd13: + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = 4'd12; + default: IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 = + 4'd13; + endcase + end always@(m_row_0_17$read_deq) begin case (m_row_0_17$read_deq[165:162]) @@ -31379,22 +31379,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_19$read_deq) - begin - case (m_row_0_19$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = - m_row_0_19$read_deq[165:162]; - 4'd11: - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = 4'd10; - 4'd12: - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = 4'd11; - 4'd13: - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = 4'd12; - default: IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = - 4'd13; - endcase - end always@(m_row_0_20$read_deq) begin case (m_row_0_20$read_deq[165:162]) @@ -31411,6 +31395,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_19$read_deq) + begin + case (m_row_0_19$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = + m_row_0_19$read_deq[165:162]; + 4'd11: + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = 4'd10; + 4'd12: + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = 4'd11; + 4'd13: + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = 4'd12; + default: IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 = + 4'd13; + endcase + end always@(m_row_0_21$read_deq) begin case (m_row_0_21$read_deq[165:162]) @@ -31427,6 +31427,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_23$read_deq) + begin + case (m_row_0_23$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = + m_row_0_23$read_deq[165:162]; + 4'd11: + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = 4'd10; + 4'd12: + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = 4'd11; + 4'd13: + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = 4'd12; + default: IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = + 4'd13; + endcase + end always@(m_row_0_22$read_deq) begin case (m_row_0_22$read_deq[165:162]) @@ -31459,22 +31475,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_23$read_deq) - begin - case (m_row_0_23$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = - m_row_0_23$read_deq[165:162]; - 4'd11: - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = 4'd10; - 4'd12: - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = 4'd11; - 4'd13: - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = 4'd12; - default: IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 = - 4'd13; - endcase - end always@(m_row_0_25$read_deq) begin case (m_row_0_25$read_deq[165:162]) @@ -31491,22 +31491,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_0_27$read_deq) - begin - case (m_row_0_27$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = - m_row_0_27$read_deq[165:162]; - 4'd11: - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = 4'd10; - 4'd12: - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = 4'd11; - 4'd13: - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = 4'd12; - default: IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = - 4'd13; - endcase - end always@(m_row_0_26$read_deq) begin case (m_row_0_26$read_deq[165:162]) @@ -31523,6 +31507,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_0_27$read_deq) + begin + case (m_row_0_27$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = + m_row_0_27$read_deq[165:162]; + 4'd11: + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = 4'd10; + 4'd12: + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = 4'd11; + 4'd13: + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = 4'd12; + default: IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 = + 4'd13; + endcase + end always@(m_row_0_28$read_deq) begin case (m_row_0_28$read_deq[165:162]) @@ -31603,22 +31603,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_1$read_deq) - begin - case (m_row_1_1$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = - m_row_1_1$read_deq[165:162]; - 4'd11: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = 4'd10; - 4'd12: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = 4'd11; - 4'd13: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = 4'd12; - default: IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = - 4'd13; - endcase - end always@(m_row_1_2$read_deq) begin case (m_row_1_2$read_deq[165:162]) @@ -31635,6 +31619,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_1$read_deq) + begin + case (m_row_1_1$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = + m_row_1_1$read_deq[165:162]; + 4'd11: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = 4'd10; + 4'd12: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = 4'd11; + 4'd13: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = 4'd12; + default: IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 = + 4'd13; + endcase + end always@(m_row_1_3$read_deq) begin case (m_row_1_3$read_deq[165:162]) @@ -31667,22 +31667,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_6$read_deq) - begin - case (m_row_1_6$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = - m_row_1_6$read_deq[165:162]; - 4'd11: - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = 4'd10; - 4'd12: - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = 4'd11; - 4'd13: - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = 4'd12; - default: IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = - 4'd13; - endcase - end always@(m_row_1_5$read_deq) begin case (m_row_1_5$read_deq[165:162]) @@ -31699,6 +31683,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_6$read_deq) + begin + case (m_row_1_6$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = + m_row_1_6$read_deq[165:162]; + 4'd11: + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = 4'd10; + 4'd12: + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = 4'd11; + 4'd13: + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = 4'd12; + default: IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 = + 4'd13; + endcase + end always@(m_row_1_7$read_deq) begin case (m_row_1_7$read_deq[165:162]) @@ -31731,22 +31731,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_9$read_deq) - begin - case (m_row_1_9$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = - m_row_1_9$read_deq[165:162]; - 4'd11: - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = 4'd10; - 4'd12: - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = 4'd11; - 4'd13: - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = 4'd12; - default: IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = - 4'd13; - endcase - end always@(m_row_1_10$read_deq) begin case (m_row_1_10$read_deq[165:162]) @@ -31763,6 +31747,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_9$read_deq) + begin + case (m_row_1_9$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = + m_row_1_9$read_deq[165:162]; + 4'd11: + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = 4'd10; + 4'd12: + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = 4'd11; + 4'd13: + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = 4'd12; + default: IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 = + 4'd13; + endcase + end always@(m_row_1_11$read_deq) begin case (m_row_1_11$read_deq[165:162]) @@ -31779,6 +31779,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_13$read_deq) + begin + case (m_row_1_13$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = + m_row_1_13$read_deq[165:162]; + 4'd11: + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = 4'd10; + 4'd12: + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = 4'd11; + 4'd13: + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = 4'd12; + default: IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = + 4'd13; + endcase + end always@(m_row_1_12$read_deq) begin case (m_row_1_12$read_deq[165:162]) @@ -31811,22 +31827,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_13$read_deq) - begin - case (m_row_1_13$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = - m_row_1_13$read_deq[165:162]; - 4'd11: - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = 4'd10; - 4'd12: - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = 4'd11; - 4'd13: - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = 4'd12; - default: IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 = - 4'd13; - endcase - end always@(m_row_1_15$read_deq) begin case (m_row_1_15$read_deq[165:162]) @@ -31843,22 +31843,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_17$read_deq) - begin - case (m_row_1_17$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = - m_row_1_17$read_deq[165:162]; - 4'd11: - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = 4'd10; - 4'd12: - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = 4'd11; - 4'd13: - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = 4'd12; - default: IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = - 4'd13; - endcase - end always@(m_row_1_16$read_deq) begin case (m_row_1_16$read_deq[165:162]) @@ -31875,6 +31859,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_17$read_deq) + begin + case (m_row_1_17$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = + m_row_1_17$read_deq[165:162]; + 4'd11: + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = 4'd10; + 4'd12: + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = 4'd11; + 4'd13: + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = 4'd12; + default: IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 = + 4'd13; + endcase + end always@(m_row_1_18$read_deq) begin case (m_row_1_18$read_deq[165:162]) @@ -31907,22 +31907,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_20$read_deq) - begin - case (m_row_1_20$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = - m_row_1_20$read_deq[165:162]; - 4'd11: - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = 4'd10; - 4'd12: - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = 4'd11; - 4'd13: - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = 4'd12; - default: IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = - 4'd13; - endcase - end always@(m_row_1_21$read_deq) begin case (m_row_1_21$read_deq[165:162]) @@ -31939,6 +31923,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_20$read_deq) + begin + case (m_row_1_20$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = + m_row_1_20$read_deq[165:162]; + 4'd11: + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = 4'd10; + 4'd12: + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = 4'd11; + 4'd13: + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = 4'd12; + default: IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 = + 4'd13; + endcase + end always@(m_row_1_22$read_deq) begin case (m_row_1_22$read_deq[165:162]) @@ -31955,6 +31955,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_24$read_deq) + begin + case (m_row_1_24$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = + m_row_1_24$read_deq[165:162]; + 4'd11: + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = 4'd10; + 4'd12: + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = 4'd11; + 4'd13: + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = 4'd12; + default: IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = + 4'd13; + endcase + end always@(m_row_1_23$read_deq) begin case (m_row_1_23$read_deq[165:162]) @@ -31987,22 +32003,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_24$read_deq) - begin - case (m_row_1_24$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = - m_row_1_24$read_deq[165:162]; - 4'd11: - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = 4'd10; - 4'd12: - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = 4'd11; - 4'd13: - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = 4'd12; - default: IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 = - 4'd13; - endcase - end always@(m_row_1_26$read_deq) begin case (m_row_1_26$read_deq[165:162]) @@ -32019,22 +32019,6 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_28$read_deq) - begin - case (m_row_1_28$read_deq[165:162]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = - m_row_1_28$read_deq[165:162]; - 4'd11: - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = 4'd10; - 4'd12: - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = 4'd11; - 4'd13: - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = 4'd12; - default: IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = - 4'd13; - endcase - end always@(m_row_1_27$read_deq) begin case (m_row_1_27$read_deq[165:162]) @@ -32051,19 +32035,19 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end - always@(m_row_1_29$read_deq) + always@(m_row_1_28$read_deq) begin - case (m_row_1_29$read_deq[165:162]) + case (m_row_1_28$read_deq[165:162]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = - m_row_1_29$read_deq[165:162]; + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = + m_row_1_28$read_deq[165:162]; 4'd11: - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = 4'd10; + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = 4'd10; 4'd12: - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = 4'd11; + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = 4'd11; 4'd13: - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = 4'd12; - default: IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = 4'd12; + default: IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 = 4'd13; endcase end @@ -32083,6 +32067,22 @@ module mkReorderBufferSynth(CLK, 4'd13; endcase end + always@(m_row_1_29$read_deq) + begin + case (m_row_1_29$read_deq[165:162]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = + m_row_1_29$read_deq[165:162]; + 4'd11: + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = 4'd10; + 4'd12: + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = 4'd11; + 4'd13: + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = 4'd12; + default: IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 = + 4'd13; + endcase + end always@(m_row_1_31$read_deq) begin case (m_row_1_31$read_deq[165:162]) @@ -32594,6 +32594,171 @@ module mkReorderBufferSynth(CLK, 4'd1; endcase end + always@(p__h86623 or + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) + begin + case (p__h86623) + 5'd0: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == + 4'd2; + 5'd1: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == + 4'd2; + 5'd2: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == + 4'd2; + 5'd3: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == + 4'd2; + 5'd4: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == + 4'd2; + 5'd5: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == + 4'd2; + 5'd6: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == + 4'd2; + 5'd7: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == + 4'd2; + 5'd8: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == + 4'd2; + 5'd9: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == + 4'd2; + 5'd10: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == + 4'd2; + 5'd11: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == + 4'd2; + 5'd12: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == + 4'd2; + 5'd13: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == + 4'd2; + 5'd14: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == + 4'd2; + 5'd15: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == + 4'd2; + 5'd16: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == + 4'd2; + 5'd17: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == + 4'd2; + 5'd18: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == + 4'd2; + 5'd19: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == + 4'd2; + 5'd20: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == + 4'd2; + 5'd21: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == + 4'd2; + 5'd22: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == + 4'd2; + 5'd23: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == + 4'd2; + 5'd24: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == + 4'd2; + 5'd25: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == + 4'd2; + 5'd26: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == + 4'd2; + 5'd27: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == + 4'd2; + 5'd28: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == + 4'd2; + 5'd29: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == + 4'd2; + 5'd30: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == + 4'd2; + 5'd31: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == + 4'd2; + endcase + end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or @@ -32924,171 +33089,6 @@ module mkReorderBufferSynth(CLK, 4'd2; endcase end - always@(p__h86623 or - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) - begin - case (p__h86623) - 5'd0: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == - 4'd2; - 5'd1: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == - 4'd2; - 5'd2: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == - 4'd2; - 5'd3: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == - 4'd2; - 5'd4: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == - 4'd2; - 5'd5: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == - 4'd2; - 5'd6: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == - 4'd2; - 5'd7: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == - 4'd2; - 5'd8: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == - 4'd2; - 5'd9: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == - 4'd2; - 5'd10: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == - 4'd2; - 5'd11: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == - 4'd2; - 5'd12: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == - 4'd2; - 5'd13: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == - 4'd2; - 5'd14: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == - 4'd2; - 5'd15: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == - 4'd2; - 5'd16: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == - 4'd2; - 5'd17: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == - 4'd2; - 5'd18: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == - 4'd2; - 5'd19: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == - 4'd2; - 5'd20: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == - 4'd2; - 5'd21: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == - 4'd2; - 5'd22: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == - 4'd2; - 5'd23: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == - 4'd2; - 5'd24: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == - 4'd2; - 5'd25: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == - 4'd2; - 5'd26: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == - 4'd2; - 5'd27: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == - 4'd2; - 5'd28: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == - 4'd2; - 5'd29: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == - 4'd2; - 5'd30: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == - 4'd2; - 5'd31: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9309 = - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == - 4'd2; - endcase - end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or @@ -33254,171 +33254,6 @@ module mkReorderBufferSynth(CLK, 4'd3; endcase end - always@(p__h86623 or - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) - begin - case (p__h86623) - 5'd0: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == - 4'd4; - 5'd1: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == - 4'd4; - 5'd2: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == - 4'd4; - 5'd3: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == - 4'd4; - 5'd4: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == - 4'd4; - 5'd5: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == - 4'd4; - 5'd6: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == - 4'd4; - 5'd7: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == - 4'd4; - 5'd8: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == - 4'd4; - 5'd9: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == - 4'd4; - 5'd10: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == - 4'd4; - 5'd11: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == - 4'd4; - 5'd12: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == - 4'd4; - 5'd13: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == - 4'd4; - 5'd14: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == - 4'd4; - 5'd15: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == - 4'd4; - 5'd16: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == - 4'd4; - 5'd17: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == - 4'd4; - 5'd18: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == - 4'd4; - 5'd19: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == - 4'd4; - 5'd20: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == - 4'd4; - 5'd21: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == - 4'd4; - 5'd22: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == - 4'd4; - 5'd23: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == - 4'd4; - 5'd24: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == - 4'd4; - 5'd25: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == - 4'd4; - 5'd26: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == - 4'd4; - 5'd27: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == - 4'd4; - 5'd28: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == - 4'd4; - 5'd29: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == - 4'd4; - 5'd30: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == - 4'd4; - 5'd31: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == - 4'd4; - endcase - end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or @@ -33584,6 +33419,171 @@ module mkReorderBufferSynth(CLK, 4'd3; endcase end + always@(p__h86623 or + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) + begin + case (p__h86623) + 5'd0: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == + 4'd4; + 5'd1: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == + 4'd4; + 5'd2: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == + 4'd4; + 5'd3: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == + 4'd4; + 5'd4: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == + 4'd4; + 5'd5: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == + 4'd4; + 5'd6: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == + 4'd4; + 5'd7: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == + 4'd4; + 5'd8: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == + 4'd4; + 5'd9: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == + 4'd4; + 5'd10: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == + 4'd4; + 5'd11: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == + 4'd4; + 5'd12: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == + 4'd4; + 5'd13: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == + 4'd4; + 5'd14: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == + 4'd4; + 5'd15: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == + 4'd4; + 5'd16: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == + 4'd4; + 5'd17: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == + 4'd4; + 5'd18: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == + 4'd4; + 5'd19: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == + 4'd4; + 5'd20: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == + 4'd4; + 5'd21: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == + 4'd4; + 5'd22: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == + 4'd4; + 5'd23: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == + 4'd4; + 5'd24: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == + 4'd4; + 5'd25: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == + 4'd4; + 5'd26: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == + 4'd4; + 5'd27: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == + 4'd4; + 5'd28: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == + 4'd4; + 5'd29: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == + 4'd4; + 5'd30: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == + 4'd4; + 5'd31: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9449 = + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == + 4'd4; + endcase + end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or @@ -34409,171 +34409,6 @@ module mkReorderBufferSynth(CLK, 4'd6; endcase end - always@(p__h86623 or - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) - begin - case (p__h86623) - 5'd0: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == - 4'd7; - 5'd1: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == - 4'd7; - 5'd2: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == - 4'd7; - 5'd3: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == - 4'd7; - 5'd4: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == - 4'd7; - 5'd5: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == - 4'd7; - 5'd6: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == - 4'd7; - 5'd7: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == - 4'd7; - 5'd8: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == - 4'd7; - 5'd9: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == - 4'd7; - 5'd10: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == - 4'd7; - 5'd11: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == - 4'd7; - 5'd12: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == - 4'd7; - 5'd13: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == - 4'd7; - 5'd14: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == - 4'd7; - 5'd15: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == - 4'd7; - 5'd16: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == - 4'd7; - 5'd17: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == - 4'd7; - 5'd18: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == - 4'd7; - 5'd19: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == - 4'd7; - 5'd20: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == - 4'd7; - 5'd21: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == - 4'd7; - 5'd22: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == - 4'd7; - 5'd23: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == - 4'd7; - 5'd24: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == - 4'd7; - 5'd25: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == - 4'd7; - 5'd26: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == - 4'd7; - 5'd27: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == - 4'd7; - 5'd28: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == - 4'd7; - 5'd29: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == - 4'd7; - 5'd30: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == - 4'd7; - 5'd31: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == - 4'd7; - endcase - end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or @@ -34739,6 +34574,171 @@ module mkReorderBufferSynth(CLK, 4'd7; endcase end + always@(p__h86623 or + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) + begin + case (p__h86623) + 5'd0: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == + 4'd7; + 5'd1: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == + 4'd7; + 5'd2: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == + 4'd7; + 5'd3: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == + 4'd7; + 5'd4: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == + 4'd7; + 5'd5: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == + 4'd7; + 5'd6: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == + 4'd7; + 5'd7: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == + 4'd7; + 5'd8: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == + 4'd7; + 5'd9: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == + 4'd7; + 5'd10: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == + 4'd7; + 5'd11: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == + 4'd7; + 5'd12: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == + 4'd7; + 5'd13: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == + 4'd7; + 5'd14: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == + 4'd7; + 5'd15: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == + 4'd7; + 5'd16: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == + 4'd7; + 5'd17: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == + 4'd7; + 5'd18: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == + 4'd7; + 5'd19: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == + 4'd7; + 5'd20: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == + 4'd7; + 5'd21: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == + 4'd7; + 5'd22: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == + 4'd7; + 5'd23: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == + 4'd7; + 5'd24: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == + 4'd7; + 5'd25: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == + 4'd7; + 5'd26: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == + 4'd7; + 5'd27: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == + 4'd7; + 5'd28: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == + 4'd7; + 5'd29: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == + 4'd7; + 5'd30: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == + 4'd7; + 5'd31: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9659 = + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == + 4'd7; + endcase + end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or @@ -35069,171 +35069,6 @@ module mkReorderBufferSynth(CLK, 4'd8; endcase end - always@(p__h96619 or - IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or - IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d8388 or - IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d8416 or - IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d8444 or - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d8472 or - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 or - IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d8528 or - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d8556 or - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 or - IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d8612 or - IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d8640 or - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d8668 or - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 or - IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d8724 or - IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d8752 or - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d8780 or - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 or - IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d8836 or - IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d8864 or - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 or - IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d8920 or - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d8948 or - IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d8976 or - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 or - IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d9032 or - IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d9060 or - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d9088 or - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 or - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 or - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d9172 or - IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d9200) - begin - case (p__h96619) - 5'd0: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 == - 4'd9; - 5'd1: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 == - 4'd9; - 5'd2: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d8388 == - 4'd9; - 5'd3: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d8416 == - 4'd9; - 5'd4: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d8444 == - 4'd9; - 5'd5: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d8472 == - 4'd9; - 5'd6: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 == - 4'd9; - 5'd7: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d8528 == - 4'd9; - 5'd8: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d8556 == - 4'd9; - 5'd9: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 == - 4'd9; - 5'd10: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d8612 == - 4'd9; - 5'd11: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d8640 == - 4'd9; - 5'd12: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d8668 == - 4'd9; - 5'd13: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 == - 4'd9; - 5'd14: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d8724 == - 4'd9; - 5'd15: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d8752 == - 4'd9; - 5'd16: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d8780 == - 4'd9; - 5'd17: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 == - 4'd9; - 5'd18: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d8836 == - 4'd9; - 5'd19: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d8864 == - 4'd9; - 5'd20: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 == - 4'd9; - 5'd21: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d8920 == - 4'd9; - 5'd22: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d8948 == - 4'd9; - 5'd23: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d8976 == - 4'd9; - 5'd24: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 == - 4'd9; - 5'd25: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d9032 == - 4'd9; - 5'd26: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d9060 == - 4'd9; - 5'd27: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d9088 == - 4'd9; - 5'd28: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 == - 4'd9; - 5'd29: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 == - 4'd9; - 5'd30: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d9172 == - 4'd9; - 5'd31: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = - IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d9200 == - 4'd9; - endcase - end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or @@ -35399,6 +35234,171 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(p__h96619 or + IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or + IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d8388 or + IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d8416 or + IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d8444 or + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d8472 or + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 or + IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d8528 or + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d8556 or + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 or + IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d8612 or + IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d8640 or + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d8668 or + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 or + IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d8724 or + IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d8752 or + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d8780 or + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 or + IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d8836 or + IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d8864 or + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 or + IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d8920 or + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d8948 or + IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d8976 or + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 or + IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d9032 or + IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d9060 or + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d9088 or + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 or + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 or + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d9172 or + IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d9200) + begin + case (p__h96619) + 5'd0: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 == + 4'd9; + 5'd1: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 == + 4'd9; + 5'd2: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d8388 == + 4'd9; + 5'd3: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d8416 == + 4'd9; + 5'd4: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d8444 == + 4'd9; + 5'd5: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d8472 == + 4'd9; + 5'd6: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d8500 == + 4'd9; + 5'd7: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d8528 == + 4'd9; + 5'd8: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d8556 == + 4'd9; + 5'd9: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d8584 == + 4'd9; + 5'd10: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d8612 == + 4'd9; + 5'd11: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d8640 == + 4'd9; + 5'd12: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d8668 == + 4'd9; + 5'd13: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d8696 == + 4'd9; + 5'd14: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d8724 == + 4'd9; + 5'd15: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d8752 == + 4'd9; + 5'd16: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d8780 == + 4'd9; + 5'd17: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d8808 == + 4'd9; + 5'd18: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d8836 == + 4'd9; + 5'd19: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d8864 == + 4'd9; + 5'd20: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d8892 == + 4'd9; + 5'd21: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d8920 == + 4'd9; + 5'd22: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d8948 == + 4'd9; + 5'd23: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d8976 == + 4'd9; + 5'd24: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d9004 == + 4'd9; + 5'd25: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d9032 == + 4'd9; + 5'd26: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d9060 == + 4'd9; + 5'd27: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d9088 == + 4'd9; + 5'd28: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d9116 == + 4'd9; + 5'd29: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d9144 == + 4'd9; + 5'd30: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d9172 == + 4'd9; + 5'd31: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9833 = + IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d9200 == + 4'd9; + endcase + end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or @@ -35729,171 +35729,6 @@ module mkReorderBufferSynth(CLK, 4'd10; endcase end - always@(p__h86623 or - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) - begin - case (p__h86623) - 5'd0: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == - 4'd11; - 5'd1: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == - 4'd11; - 5'd2: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == - 4'd11; - 5'd3: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == - 4'd11; - 5'd4: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == - 4'd11; - 5'd5: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == - 4'd11; - 5'd6: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == - 4'd11; - 5'd7: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == - 4'd11; - 5'd8: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == - 4'd11; - 5'd9: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == - 4'd11; - 5'd10: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == - 4'd11; - 5'd11: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == - 4'd11; - 5'd12: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == - 4'd11; - 5'd13: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == - 4'd11; - 5'd14: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == - 4'd11; - 5'd15: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == - 4'd11; - 5'd16: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == - 4'd11; - 5'd17: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == - 4'd11; - 5'd18: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == - 4'd11; - 5'd19: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == - 4'd11; - 5'd20: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == - 4'd11; - 5'd21: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == - 4'd11; - 5'd22: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == - 4'd11; - 5'd23: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == - 4'd11; - 5'd24: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == - 4'd11; - 5'd25: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == - 4'd11; - 5'd26: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == - 4'd11; - 5'd27: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == - 4'd11; - 5'd28: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == - 4'd11; - 5'd29: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == - 4'd11; - 5'd30: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == - 4'd11; - 5'd31: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == - 4'd11; - endcase - end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or @@ -36059,6 +35894,171 @@ module mkReorderBufferSynth(CLK, 4'd11; endcase end + always@(p__h86623 or + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 or + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 or + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 or + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 or + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 or + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 or + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 or + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 or + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 or + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 or + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 or + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 or + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 or + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 or + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 or + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 or + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 or + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 or + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 or + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 or + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 or + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 or + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 or + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 or + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 or + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 or + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 or + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 or + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 or + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302) + begin + case (p__h86623) + 5'd0: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 == + 4'd11; + 5'd1: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 == + 4'd11; + 5'd2: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d7490 == + 4'd11; + 5'd3: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d7518 == + 4'd11; + 5'd4: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d7546 == + 4'd11; + 5'd5: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d7574 == + 4'd11; + 5'd6: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d7602 == + 4'd11; + 5'd7: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d7630 == + 4'd11; + 5'd8: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d7658 == + 4'd11; + 5'd9: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d7686 == + 4'd11; + 5'd10: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d7714 == + 4'd11; + 5'd11: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d7742 == + 4'd11; + 5'd12: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d7770 == + 4'd11; + 5'd13: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d7798 == + 4'd11; + 5'd14: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d7826 == + 4'd11; + 5'd15: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d7854 == + 4'd11; + 5'd16: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d7882 == + 4'd11; + 5'd17: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d7910 == + 4'd11; + 5'd18: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d7938 == + 4'd11; + 5'd19: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d7966 == + 4'd11; + 5'd20: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d7994 == + 4'd11; + 5'd21: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d8022 == + 4'd11; + 5'd22: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d8050 == + 4'd11; + 5'd23: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d8078 == + 4'd11; + 5'd24: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d8106 == + 4'd11; + 5'd25: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d8134 == + 4'd11; + 5'd26: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d8162 == + 4'd11; + 5'd27: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d8190 == + 4'd11; + 5'd28: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d8218 == + 4'd11; + 5'd29: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d8246 == + 4'd11; + 5'd30: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d8274 == + 4'd11; + 5'd31: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 = + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d8302 == + 4'd11; + endcase + end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d7434 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d7462 or @@ -36224,6 +36224,30 @@ module mkReorderBufferSynth(CLK, 4'd12; endcase end + always@(m_row_0_0$read_deq) + begin + case (m_row_0_0$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = + m_row_0_0$read_deq[165:162]; + 4'd3: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd2; + 4'd4: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd3; + 4'd5: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd4; + 4'd7: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd5; + 4'd8: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd6; + 4'd9: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd7; + 4'd11: + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd8; + default: IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = + 4'd9; + endcase + end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d8332 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d8360 or @@ -36413,30 +36437,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_0$read_deq) - begin - case (m_row_0_0$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = - m_row_0_0$read_deq[165:162]; - 4'd3: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd2; - 4'd4: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd3; - 4'd5: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd4; - 4'd7: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd5; - 4'd8: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd6; - 4'd9: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd7; - 4'd11: - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = 4'd8; - default: IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 = - 4'd9; - endcase - end always@(m_row_0_2$read_deq) begin case (m_row_0_2$read_deq[165:162]) @@ -36461,30 +36461,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_4$read_deq) - begin - case (m_row_0_4$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = - m_row_0_4$read_deq[165:162]; - 4'd3: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd2; - 4'd4: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd3; - 4'd5: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd4; - 4'd7: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd5; - 4'd8: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd6; - 4'd9: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd7; - 4'd11: - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd8; - default: IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = - 4'd9; - endcase - end always@(m_row_0_3$read_deq) begin case (m_row_0_3$read_deq[165:162]) @@ -36509,6 +36485,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_4$read_deq) + begin + case (m_row_0_4$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = + m_row_0_4$read_deq[165:162]; + 4'd3: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd2; + 4'd4: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd3; + 4'd5: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd4; + 4'd7: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd5; + 4'd8: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd6; + 4'd9: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd7; + 4'd11: + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = 4'd8; + default: IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 = + 4'd9; + endcase + end always@(m_row_0_5$read_deq) begin case (m_row_0_5$read_deq[165:162]) @@ -36557,30 +36557,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_7$read_deq) - begin - case (m_row_0_7$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = - m_row_0_7$read_deq[165:162]; - 4'd3: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd2; - 4'd4: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd3; - 4'd5: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd4; - 4'd7: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd5; - 4'd8: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd6; - 4'd9: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd7; - 4'd11: - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd8; - default: IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = - 4'd9; - endcase - end always@(m_row_0_8$read_deq) begin case (m_row_0_8$read_deq[165:162]) @@ -36605,6 +36581,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_7$read_deq) + begin + case (m_row_0_7$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = + m_row_0_7$read_deq[165:162]; + 4'd3: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd2; + 4'd4: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd3; + 4'd5: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd4; + 4'd7: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd5; + 4'd8: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd6; + 4'd9: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd7; + 4'd11: + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = 4'd8; + default: IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 = + 4'd9; + endcase + end always@(m_row_0_9$read_deq) begin case (m_row_0_9$read_deq[165:162]) @@ -36629,6 +36629,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_11$read_deq) + begin + case (m_row_0_11$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = + m_row_0_11$read_deq[165:162]; + 4'd3: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd2; + 4'd4: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd3; + 4'd5: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd4; + 4'd7: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd5; + 4'd8: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd6; + 4'd9: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd7; + 4'd11: + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd8; + default: IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = + 4'd9; + endcase + end always@(m_row_0_10$read_deq) begin case (m_row_0_10$read_deq[165:162]) @@ -36677,30 +36701,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_11$read_deq) - begin - case (m_row_0_11$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = - m_row_0_11$read_deq[165:162]; - 4'd3: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd2; - 4'd4: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd3; - 4'd5: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd4; - 4'd7: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd5; - 4'd8: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd6; - 4'd9: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd7; - 4'd11: - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = 4'd8; - default: IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 = - 4'd9; - endcase - end always@(m_row_0_13$read_deq) begin case (m_row_0_13$read_deq[165:162]) @@ -36725,30 +36725,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_15$read_deq) - begin - case (m_row_0_15$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = - m_row_0_15$read_deq[165:162]; - 4'd3: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd2; - 4'd4: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd3; - 4'd5: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd4; - 4'd7: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd5; - 4'd8: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd6; - 4'd9: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd7; - 4'd11: - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd8; - default: IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = - 4'd9; - endcase - end always@(m_row_0_14$read_deq) begin case (m_row_0_14$read_deq[165:162]) @@ -36773,6 +36749,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_15$read_deq) + begin + case (m_row_0_15$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = + m_row_0_15$read_deq[165:162]; + 4'd3: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd2; + 4'd4: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd3; + 4'd5: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd4; + 4'd7: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd5; + 4'd8: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd6; + 4'd9: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd7; + 4'd11: + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = 4'd8; + default: IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 = + 4'd9; + endcase + end always@(m_row_0_16$read_deq) begin case (m_row_0_16$read_deq[165:162]) @@ -36821,30 +36821,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_18$read_deq) - begin - case (m_row_0_18$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = - m_row_0_18$read_deq[165:162]; - 4'd3: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd2; - 4'd4: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd3; - 4'd5: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd4; - 4'd7: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd5; - 4'd8: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd6; - 4'd9: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd7; - 4'd11: - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd8; - default: IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = - 4'd9; - endcase - end always@(m_row_0_19$read_deq) begin case (m_row_0_19$read_deq[165:162]) @@ -36869,6 +36845,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_18$read_deq) + begin + case (m_row_0_18$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = + m_row_0_18$read_deq[165:162]; + 4'd3: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd2; + 4'd4: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd3; + 4'd5: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd4; + 4'd7: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd5; + 4'd8: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd6; + 4'd9: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd7; + 4'd11: + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = 4'd8; + default: IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 = + 4'd9; + endcase + end always@(m_row_0_20$read_deq) begin case (m_row_0_20$read_deq[165:162]) @@ -36893,6 +36893,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_22$read_deq) + begin + case (m_row_0_22$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = + m_row_0_22$read_deq[165:162]; + 4'd3: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd2; + 4'd4: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd3; + 4'd5: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd4; + 4'd7: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd5; + 4'd8: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd6; + 4'd9: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd7; + 4'd11: + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd8; + default: IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = + 4'd9; + endcase + end always@(m_row_0_21$read_deq) begin case (m_row_0_21$read_deq[165:162]) @@ -36941,30 +36965,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_22$read_deq) - begin - case (m_row_0_22$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = - m_row_0_22$read_deq[165:162]; - 4'd3: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd2; - 4'd4: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd3; - 4'd5: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd4; - 4'd7: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd5; - 4'd8: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd6; - 4'd9: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd7; - 4'd11: - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = 4'd8; - default: IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 = - 4'd9; - endcase - end always@(m_row_0_24$read_deq) begin case (m_row_0_24$read_deq[165:162]) @@ -36989,30 +36989,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_26$read_deq) - begin - case (m_row_0_26$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = - m_row_0_26$read_deq[165:162]; - 4'd3: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd2; - 4'd4: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd3; - 4'd5: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd4; - 4'd7: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd5; - 4'd8: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd6; - 4'd9: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd7; - 4'd11: - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd8; - default: IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = - 4'd9; - endcase - end always@(m_row_0_25$read_deq) begin case (m_row_0_25$read_deq[165:162]) @@ -37037,6 +37013,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_26$read_deq) + begin + case (m_row_0_26$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = + m_row_0_26$read_deq[165:162]; + 4'd3: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd2; + 4'd4: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd3; + 4'd5: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd4; + 4'd7: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd5; + 4'd8: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd6; + 4'd9: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd7; + 4'd11: + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = 4'd8; + default: IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 = + 4'd9; + endcase + end always@(m_row_0_27$read_deq) begin case (m_row_0_27$read_deq[165:162]) @@ -37085,30 +37085,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_0_29$read_deq) - begin - case (m_row_0_29$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = - m_row_0_29$read_deq[165:162]; - 4'd3: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd2; - 4'd4: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd3; - 4'd5: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd4; - 4'd7: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd5; - 4'd8: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd6; - 4'd9: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd7; - 4'd11: - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd8; - default: IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = - 4'd9; - endcase - end always@(m_row_0_30$read_deq) begin case (m_row_0_30$read_deq[165:162]) @@ -37133,6 +37109,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_0_29$read_deq) + begin + case (m_row_0_29$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = + m_row_0_29$read_deq[165:162]; + 4'd3: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd2; + 4'd4: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd3; + 4'd5: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd4; + 4'd7: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd5; + 4'd8: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd6; + 4'd9: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd7; + 4'd11: + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = 4'd8; + default: IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 = + 4'd9; + endcase + end always@(m_row_0_31$read_deq) begin case (m_row_0_31$read_deq[165:162]) @@ -37157,6 +37157,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_1$read_deq) + begin + case (m_row_1_1$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = + m_row_1_1$read_deq[165:162]; + 4'd3: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd2; + 4'd4: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd3; + 4'd5: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd4; + 4'd7: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd5; + 4'd8: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd6; + 4'd9: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd7; + 4'd11: + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd8; + default: IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = + 4'd9; + endcase + end always@(m_row_1_0$read_deq) begin case (m_row_1_0$read_deq[165:162]) @@ -37205,30 +37229,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_1$read_deq) - begin - case (m_row_1_1$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = - m_row_1_1$read_deq[165:162]; - 4'd3: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd2; - 4'd4: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd3; - 4'd5: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd4; - 4'd7: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd5; - 4'd8: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd6; - 4'd9: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd7; - 4'd11: - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = 4'd8; - default: IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 = - 4'd9; - endcase - end always@(m_row_1_3$read_deq) begin case (m_row_1_3$read_deq[165:162]) @@ -37253,30 +37253,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_5$read_deq) - begin - case (m_row_1_5$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = - m_row_1_5$read_deq[165:162]; - 4'd3: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd2; - 4'd4: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd3; - 4'd5: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd4; - 4'd7: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd5; - 4'd8: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd6; - 4'd9: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd7; - 4'd11: - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd8; - default: IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = - 4'd9; - endcase - end always@(m_row_1_4$read_deq) begin case (m_row_1_4$read_deq[165:162]) @@ -37301,6 +37277,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_5$read_deq) + begin + case (m_row_1_5$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = + m_row_1_5$read_deq[165:162]; + 4'd3: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd2; + 4'd4: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd3; + 4'd5: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd4; + 4'd7: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd5; + 4'd8: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd6; + 4'd9: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd7; + 4'd11: + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = 4'd8; + default: IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 = + 4'd9; + endcase + end always@(m_row_1_6$read_deq) begin case (m_row_1_6$read_deq[165:162]) @@ -37349,30 +37349,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_8$read_deq) - begin - case (m_row_1_8$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = - m_row_1_8$read_deq[165:162]; - 4'd3: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd2; - 4'd4: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd3; - 4'd5: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd4; - 4'd7: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd5; - 4'd8: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd6; - 4'd9: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd7; - 4'd11: - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd8; - default: IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = - 4'd9; - endcase - end always@(m_row_1_9$read_deq) begin case (m_row_1_9$read_deq[165:162]) @@ -37397,6 +37373,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_8$read_deq) + begin + case (m_row_1_8$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = + m_row_1_8$read_deq[165:162]; + 4'd3: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd2; + 4'd4: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd3; + 4'd5: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd4; + 4'd7: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd5; + 4'd8: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd6; + 4'd9: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd7; + 4'd11: + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = 4'd8; + default: IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 = + 4'd9; + endcase + end always@(m_row_1_10$read_deq) begin case (m_row_1_10$read_deq[165:162]) @@ -37421,6 +37421,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_12$read_deq) + begin + case (m_row_1_12$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = + m_row_1_12$read_deq[165:162]; + 4'd3: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd2; + 4'd4: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd3; + 4'd5: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd4; + 4'd7: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd5; + 4'd8: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd6; + 4'd9: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd7; + 4'd11: + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd8; + default: IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = + 4'd9; + endcase + end always@(m_row_1_11$read_deq) begin case (m_row_1_11$read_deq[165:162]) @@ -37469,30 +37493,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_12$read_deq) - begin - case (m_row_1_12$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = - m_row_1_12$read_deq[165:162]; - 4'd3: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd2; - 4'd4: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd3; - 4'd5: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd4; - 4'd7: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd5; - 4'd8: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd6; - 4'd9: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd7; - 4'd11: - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = 4'd8; - default: IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 = - 4'd9; - endcase - end always@(m_row_1_14$read_deq) begin case (m_row_1_14$read_deq[165:162]) @@ -37517,30 +37517,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_16$read_deq) - begin - case (m_row_1_16$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = - m_row_1_16$read_deq[165:162]; - 4'd3: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd2; - 4'd4: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd3; - 4'd5: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd4; - 4'd7: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd5; - 4'd8: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd6; - 4'd9: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd7; - 4'd11: - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd8; - default: IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = - 4'd9; - endcase - end always@(m_row_1_15$read_deq) begin case (m_row_1_15$read_deq[165:162]) @@ -37565,6 +37541,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_16$read_deq) + begin + case (m_row_1_16$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = + m_row_1_16$read_deq[165:162]; + 4'd3: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd2; + 4'd4: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd3; + 4'd5: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd4; + 4'd7: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd5; + 4'd8: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd6; + 4'd9: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd7; + 4'd11: + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = 4'd8; + default: IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 = + 4'd9; + endcase + end always@(m_row_1_17$read_deq) begin case (m_row_1_17$read_deq[165:162]) @@ -37685,30 +37685,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_22$read_deq) - begin - case (m_row_1_22$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = - m_row_1_22$read_deq[165:162]; - 4'd3: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd2; - 4'd4: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd3; - 4'd5: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd4; - 4'd7: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd5; - 4'd8: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd6; - 4'd9: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd7; - 4'd11: - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd8; - default: IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = - 4'd9; - endcase - end always@(m_row_1_23$read_deq) begin case (m_row_1_23$read_deq[165:162]) @@ -37733,6 +37709,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_22$read_deq) + begin + case (m_row_1_22$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = + m_row_1_22$read_deq[165:162]; + 4'd3: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd2; + 4'd4: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd3; + 4'd5: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd4; + 4'd7: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd5; + 4'd8: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd6; + 4'd9: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd7; + 4'd11: + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = 4'd8; + default: IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 = + 4'd9; + endcase + end always@(m_row_1_24$read_deq) begin case (m_row_1_24$read_deq[165:162]) @@ -37781,30 +37781,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_27$read_deq) - begin - case (m_row_1_27$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = - m_row_1_27$read_deq[165:162]; - 4'd3: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd2; - 4'd4: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd3; - 4'd5: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd4; - 4'd7: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd5; - 4'd8: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd6; - 4'd9: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd7; - 4'd11: - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd8; - default: IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = - 4'd9; - endcase - end always@(m_row_1_26$read_deq) begin case (m_row_1_26$read_deq[165:162]) @@ -37829,6 +37805,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_27$read_deq) + begin + case (m_row_1_27$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = + m_row_1_27$read_deq[165:162]; + 4'd3: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd2; + 4'd4: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd3; + 4'd5: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd4; + 4'd7: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd5; + 4'd8: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd6; + 4'd9: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd7; + 4'd11: + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = 4'd8; + default: IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 = + 4'd9; + endcase + end always@(m_row_1_28$read_deq) begin case (m_row_1_28$read_deq[165:162]) @@ -37877,30 +37877,6 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end - always@(m_row_1_30$read_deq) - begin - case (m_row_1_30$read_deq[165:162]) - 4'd0, 4'd1: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = - m_row_1_30$read_deq[165:162]; - 4'd3: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd2; - 4'd4: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd3; - 4'd5: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd4; - 4'd7: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd5; - 4'd8: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd6; - 4'd9: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd7; - 4'd11: - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd8; - default: IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = - 4'd9; - endcase - end always@(m_row_1_31$read_deq) begin case (m_row_1_31$read_deq[165:162]) @@ -37925,6 +37901,30 @@ module mkReorderBufferSynth(CLK, 4'd9; endcase end + always@(m_row_1_30$read_deq) + begin + case (m_row_1_30$read_deq[165:162]) + 4'd0, 4'd1: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = + m_row_1_30$read_deq[165:162]; + 4'd3: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd2; + 4'd4: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd3; + 4'd5: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd4; + 4'd7: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd5; + 4'd8: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd6; + 4'd9: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd7; + 4'd11: + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = 4'd8; + default: IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 = + 4'd9; + endcase + end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 or @@ -38750,171 +38750,6 @@ module mkReorderBufferSynth(CLK, 4'd2; endcase end - always@(p__h86623 or - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 or - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 or - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 or - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 or - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 or - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 or - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 or - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 or - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 or - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 or - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 or - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 or - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 or - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 or - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 or - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 or - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 or - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 or - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 or - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 or - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 or - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 or - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 or - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 or - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 or - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 or - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 or - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 or - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 or - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 or - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 or - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377) - begin - case (p__h86623) - 5'd0: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 == - 4'd3; - 5'd1: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 == - 4'd3; - 5'd2: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 == - 4'd3; - 5'd3: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 == - 4'd3; - 5'd4: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 == - 4'd3; - 5'd5: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 == - 4'd3; - 5'd6: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 == - 4'd3; - 5'd7: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 == - 4'd3; - 5'd8: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 == - 4'd3; - 5'd9: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 == - 4'd3; - 5'd10: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 == - 4'd3; - 5'd11: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 == - 4'd3; - 5'd12: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 == - 4'd3; - 5'd13: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 == - 4'd3; - 5'd14: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 == - 4'd3; - 5'd15: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 == - 4'd3; - 5'd16: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 == - 4'd3; - 5'd17: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 == - 4'd3; - 5'd18: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 == - 4'd3; - 5'd19: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 == - 4'd3; - 5'd20: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 == - 4'd3; - 5'd21: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 == - 4'd3; - 5'd22: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 == - 4'd3; - 5'd23: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 == - 4'd3; - 5'd24: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 == - 4'd3; - 5'd25: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 == - 4'd3; - 5'd26: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 == - 4'd3; - 5'd27: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 == - 4'd3; - 5'd28: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 == - 4'd3; - 5'd29: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 == - 4'd3; - 5'd30: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 == - 4'd3; - 5'd31: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377 == - 4'd3; - endcase - end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d10389 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 or @@ -39080,6 +38915,171 @@ module mkReorderBufferSynth(CLK, 4'd2; endcase end + always@(p__h86623 or + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 or + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 or + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 or + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 or + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 or + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 or + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 or + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 or + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 or + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 or + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 or + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 or + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 or + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 or + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 or + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 or + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 or + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 or + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 or + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 or + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 or + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 or + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 or + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 or + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 or + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 or + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 or + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 or + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 or + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 or + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 or + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377) + begin + case (p__h86623) + 5'd0: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 == + 4'd3; + 5'd1: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 == + 4'd3; + 5'd2: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 == + 4'd3; + 5'd3: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 == + 4'd3; + 5'd4: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 == + 4'd3; + 5'd5: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 == + 4'd3; + 5'd6: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 == + 4'd3; + 5'd7: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 == + 4'd3; + 5'd8: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 == + 4'd3; + 5'd9: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 == + 4'd3; + 5'd10: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 == + 4'd3; + 5'd11: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 == + 4'd3; + 5'd12: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 == + 4'd3; + 5'd13: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 == + 4'd3; + 5'd14: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 == + 4'd3; + 5'd15: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 == + 4'd3; + 5'd16: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 == + 4'd3; + 5'd17: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 == + 4'd3; + 5'd18: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 == + 4'd3; + 5'd19: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 == + 4'd3; + 5'd20: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 == + 4'd3; + 5'd21: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 == + 4'd3; + 5'd22: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 == + 4'd3; + 5'd23: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 == + 4'd3; + 5'd24: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 == + 4'd3; + 5'd25: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 == + 4'd3; + 5'd26: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 == + 4'd3; + 5'd27: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 == + 4'd3; + 5'd28: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 == + 4'd3; + 5'd29: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 == + 4'd3; + 5'd30: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 == + 4'd3; + 5'd31: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d10878 = + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377 == + 4'd3; + endcase + end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d10389 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 or @@ -39905,171 +39905,6 @@ module mkReorderBufferSynth(CLK, 4'd5; endcase end - always@(p__h86623 or - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 or - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 or - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 or - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 or - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 or - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 or - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 or - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 or - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 or - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 or - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 or - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 or - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 or - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 or - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 or - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 or - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 or - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 or - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 or - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 or - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 or - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 or - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 or - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 or - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 or - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 or - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 or - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 or - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 or - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 or - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 or - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377) - begin - case (p__h86623) - 5'd0: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 == - 4'd6; - 5'd1: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 == - 4'd6; - 5'd2: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 == - 4'd6; - 5'd3: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 == - 4'd6; - 5'd4: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 == - 4'd6; - 5'd5: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 == - 4'd6; - 5'd6: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 == - 4'd6; - 5'd7: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 == - 4'd6; - 5'd8: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 == - 4'd6; - 5'd9: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 == - 4'd6; - 5'd10: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 == - 4'd6; - 5'd11: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 == - 4'd6; - 5'd12: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 == - 4'd6; - 5'd13: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 == - 4'd6; - 5'd14: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 == - 4'd6; - 5'd15: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 == - 4'd6; - 5'd16: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 == - 4'd6; - 5'd17: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 == - 4'd6; - 5'd18: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 == - 4'd6; - 5'd19: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 == - 4'd6; - 5'd20: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 == - 4'd6; - 5'd21: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 == - 4'd6; - 5'd22: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 == - 4'd6; - 5'd23: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 == - 4'd6; - 5'd24: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 == - 4'd6; - 5'd25: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 == - 4'd6; - 5'd26: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 == - 4'd6; - 5'd27: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 == - 4'd6; - 5'd28: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 == - 4'd6; - 5'd29: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 == - 4'd6; - 5'd30: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 == - 4'd6; - 5'd31: - SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = - IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377 == - 4'd6; - endcase - end always@(p__h96619 or IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d10389 or IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 or @@ -40235,6 +40070,171 @@ module mkReorderBufferSynth(CLK, 4'd6; endcase end + always@(p__h86623 or + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 or + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 or + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 or + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 or + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 or + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 or + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 or + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 or + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 or + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 or + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 or + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 or + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 or + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 or + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 or + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 or + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 or + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 or + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 or + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 or + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 or + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 or + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 or + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 or + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 or + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 or + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 or + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 or + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 or + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 or + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 or + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377) + begin + case (p__h86623) + 5'd0: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 == + 4'd6; + 5'd1: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 == + 4'd6; + 5'd2: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_2_read_deq__041_BITS_165_TO_162_464_ETC___d10087 == + 4'd6; + 5'd3: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_3_read_deq__043_BITS_165_TO_162_492_ETC___d10097 == + 4'd6; + 5'd4: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_4_read_deq__045_BITS_165_TO_162_520_ETC___d10107 == + 4'd6; + 5'd5: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_5_read_deq__047_BITS_165_TO_162_548_ETC___d10117 == + 4'd6; + 5'd6: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_6_read_deq__049_BITS_165_TO_162_576_ETC___d10127 == + 4'd6; + 5'd7: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_7_read_deq__051_BITS_165_TO_162_604_ETC___d10137 == + 4'd6; + 5'd8: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_8_read_deq__053_BITS_165_TO_162_632_ETC___d10147 == + 4'd6; + 5'd9: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_9_read_deq__055_BITS_165_TO_162_660_ETC___d10157 == + 4'd6; + 5'd10: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_10_read_deq__057_BITS_165_TO_162_68_ETC___d10167 == + 4'd6; + 5'd11: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_11_read_deq__059_BITS_165_TO_162_71_ETC___d10177 == + 4'd6; + 5'd12: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_12_read_deq__061_BITS_165_TO_162_74_ETC___d10187 == + 4'd6; + 5'd13: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_13_read_deq__063_BITS_165_TO_162_77_ETC___d10197 == + 4'd6; + 5'd14: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_14_read_deq__065_BITS_165_TO_162_80_ETC___d10207 == + 4'd6; + 5'd15: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_15_read_deq__067_BITS_165_TO_162_82_ETC___d10217 == + 4'd6; + 5'd16: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_16_read_deq__069_BITS_165_TO_162_85_ETC___d10227 == + 4'd6; + 5'd17: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_17_read_deq__071_BITS_165_TO_162_88_ETC___d10237 == + 4'd6; + 5'd18: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_18_read_deq__073_BITS_165_TO_162_91_ETC___d10247 == + 4'd6; + 5'd19: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_19_read_deq__075_BITS_165_TO_162_94_ETC___d10257 == + 4'd6; + 5'd20: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_20_read_deq__077_BITS_165_TO_162_96_ETC___d10267 == + 4'd6; + 5'd21: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_21_read_deq__079_BITS_165_TO_162_99_ETC___d10277 == + 4'd6; + 5'd22: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_22_read_deq__081_BITS_165_TO_162_02_ETC___d10287 == + 4'd6; + 5'd23: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_23_read_deq__083_BITS_165_TO_162_05_ETC___d10297 == + 4'd6; + 5'd24: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_24_read_deq__085_BITS_165_TO_162_08_ETC___d10307 == + 4'd6; + 5'd25: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_25_read_deq__087_BITS_165_TO_162_10_ETC___d10317 == + 4'd6; + 5'd26: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_26_read_deq__089_BITS_165_TO_162_13_ETC___d10327 == + 4'd6; + 5'd27: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_27_read_deq__091_BITS_165_TO_162_16_ETC___d10337 == + 4'd6; + 5'd28: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_28_read_deq__093_BITS_165_TO_162_19_ETC___d10347 == + 4'd6; + 5'd29: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_29_read_deq__095_BITS_165_TO_162_22_ETC___d10357 == + 4'd6; + 5'd30: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_30_read_deq__097_BITS_165_TO_162_24_ETC___d10367 == + 4'd6; + 5'd31: + SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d11088 = + IF_m_row_0_31_read_deq__099_BITS_165_TO_162_27_ETC___d10377 == + 4'd6; + endcase + end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 or @@ -40565,171 +40565,6 @@ module mkReorderBufferSynth(CLK, 4'd7; endcase end - always@(p__h96619 or - IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d10389 or - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 or - IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d10409 or - IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d10419 or - IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d10429 or - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 or - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d10449 or - IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d10459 or - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 or - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d10479 or - IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d10489 or - IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d10499 or - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 or - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d10519 or - IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d10529 or - IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d10539 or - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 or - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d10559 or - IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d10569 or - IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d10579 or - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d10589 or - IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d10599 or - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 or - IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d10619 or - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d10629 or - IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d10639 or - IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d10649 or - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 or - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d10669 or - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d10679 or - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 or - IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d10699) - begin - case (p__h96619) - 5'd0: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d10389 == - 4'd8; - 5'd1: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 == - 4'd8; - 5'd2: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d10409 == - 4'd8; - 5'd3: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d10419 == - 4'd8; - 5'd4: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d10429 == - 4'd8; - 5'd5: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 == - 4'd8; - 5'd6: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d10449 == - 4'd8; - 5'd7: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d10459 == - 4'd8; - 5'd8: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 == - 4'd8; - 5'd9: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d10479 == - 4'd8; - 5'd10: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d10489 == - 4'd8; - 5'd11: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d10499 == - 4'd8; - 5'd12: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 == - 4'd8; - 5'd13: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d10519 == - 4'd8; - 5'd14: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d10529 == - 4'd8; - 5'd15: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d10539 == - 4'd8; - 5'd16: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 == - 4'd8; - 5'd17: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d10559 == - 4'd8; - 5'd18: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d10569 == - 4'd8; - 5'd19: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d10579 == - 4'd8; - 5'd20: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d10589 == - 4'd8; - 5'd21: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d10599 == - 4'd8; - 5'd22: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 == - 4'd8; - 5'd23: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d10619 == - 4'd8; - 5'd24: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d10629 == - 4'd8; - 5'd25: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d10639 == - 4'd8; - 5'd26: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d10649 == - 4'd8; - 5'd27: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 == - 4'd8; - 5'd28: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d10669 == - 4'd8; - 5'd29: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d10679 == - 4'd8; - 5'd30: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 == - 4'd8; - 5'd31: - SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = - IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d10699 == - 4'd8; - endcase - end always@(p__h86623 or IF_m_row_0_0_read_deq__037_BITS_165_TO_162_408_ETC___d10067 or IF_m_row_0_1_read_deq__039_BITS_165_TO_162_436_ETC___d10077 or @@ -40895,6 +40730,171 @@ module mkReorderBufferSynth(CLK, 4'd8; endcase end + always@(p__h96619 or + IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d10389 or + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 or + IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d10409 or + IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d10419 or + IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d10429 or + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 or + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d10449 or + IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d10459 or + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 or + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d10479 or + IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d10489 or + IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d10499 or + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 or + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d10519 or + IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d10529 or + IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d10539 or + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 or + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d10559 or + IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d10569 or + IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d10579 or + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d10589 or + IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d10599 or + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 or + IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d10619 or + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d10629 or + IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d10639 or + IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d10649 or + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 or + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d10669 or + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d10679 or + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 or + IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d10699) + begin + case (p__h96619) + 5'd0: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_0_read_deq__103_BITS_165_TO_162_306_ETC___d10389 == + 4'd8; + 5'd1: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_1_read_deq__105_BITS_165_TO_162_334_ETC___d10399 == + 4'd8; + 5'd2: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_2_read_deq__107_BITS_165_TO_162_362_ETC___d10409 == + 4'd8; + 5'd3: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_3_read_deq__109_BITS_165_TO_162_390_ETC___d10419 == + 4'd8; + 5'd4: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_4_read_deq__111_BITS_165_TO_162_418_ETC___d10429 == + 4'd8; + 5'd5: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_5_read_deq__113_BITS_165_TO_162_446_ETC___d10439 == + 4'd8; + 5'd6: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_6_read_deq__115_BITS_165_TO_162_474_ETC___d10449 == + 4'd8; + 5'd7: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_7_read_deq__117_BITS_165_TO_162_502_ETC___d10459 == + 4'd8; + 5'd8: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_8_read_deq__119_BITS_165_TO_162_530_ETC___d10469 == + 4'd8; + 5'd9: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_9_read_deq__121_BITS_165_TO_162_558_ETC___d10479 == + 4'd8; + 5'd10: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_10_read_deq__123_BITS_165_TO_162_58_ETC___d10489 == + 4'd8; + 5'd11: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_11_read_deq__125_BITS_165_TO_162_61_ETC___d10499 == + 4'd8; + 5'd12: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_12_read_deq__127_BITS_165_TO_162_64_ETC___d10509 == + 4'd8; + 5'd13: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_13_read_deq__129_BITS_165_TO_162_67_ETC___d10519 == + 4'd8; + 5'd14: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_14_read_deq__131_BITS_165_TO_162_69_ETC___d10529 == + 4'd8; + 5'd15: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_15_read_deq__133_BITS_165_TO_162_72_ETC___d10539 == + 4'd8; + 5'd16: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_16_read_deq__135_BITS_165_TO_162_75_ETC___d10549 == + 4'd8; + 5'd17: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_17_read_deq__137_BITS_165_TO_162_78_ETC___d10559 == + 4'd8; + 5'd18: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_18_read_deq__139_BITS_165_TO_162_81_ETC___d10569 == + 4'd8; + 5'd19: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_19_read_deq__141_BITS_165_TO_162_83_ETC___d10579 == + 4'd8; + 5'd20: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_20_read_deq__143_BITS_165_TO_162_86_ETC___d10589 == + 4'd8; + 5'd21: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_21_read_deq__145_BITS_165_TO_162_89_ETC___d10599 == + 4'd8; + 5'd22: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_22_read_deq__147_BITS_165_TO_162_92_ETC___d10609 == + 4'd8; + 5'd23: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_23_read_deq__149_BITS_165_TO_162_95_ETC___d10619 == + 4'd8; + 5'd24: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_24_read_deq__151_BITS_165_TO_162_97_ETC___d10629 == + 4'd8; + 5'd25: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_25_read_deq__153_BITS_165_TO_162_00_ETC___d10639 == + 4'd8; + 5'd26: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_26_read_deq__155_BITS_165_TO_162_03_ETC___d10649 == + 4'd8; + 5'd27: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_27_read_deq__157_BITS_165_TO_162_06_ETC___d10659 == + 4'd8; + 5'd28: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_28_read_deq__159_BITS_165_TO_162_09_ETC___d10669 == + 4'd8; + 5'd29: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_29_read_deq__161_BITS_165_TO_162_11_ETC___d10679 == + 4'd8; + 5'd30: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_30_read_deq__163_BITS_165_TO_162_14_ETC___d10689 == + 4'd8; + 5'd31: + SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d11262 = + IF_m_row_1_31_read_deq__165_BITS_165_TO_162_17_ETC___d10699 == + 4'd8; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -41576,137 +41576,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[97:96] == 2'd1; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_0$read_deq[97:96] == 2'd1; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_1$read_deq[97:96] == 2'd1; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_2$read_deq[97:96] == 2'd1; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_3$read_deq[97:96] == 2'd1; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_4$read_deq[97:96] == 2'd1; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_5$read_deq[97:96] == 2'd1; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_6$read_deq[97:96] == 2'd1; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_7$read_deq[97:96] == 2'd1; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_8$read_deq[97:96] == 2'd1; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_9$read_deq[97:96] == 2'd1; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_10$read_deq[97:96] == 2'd1; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_11$read_deq[97:96] == 2'd1; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_12$read_deq[97:96] == 2'd1; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_13$read_deq[97:96] == 2'd1; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_14$read_deq[97:96] == 2'd1; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_15$read_deq[97:96] == 2'd1; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_16$read_deq[97:96] == 2'd1; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_17$read_deq[97:96] == 2'd1; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_18$read_deq[97:96] == 2'd1; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_19$read_deq[97:96] == 2'd1; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_20$read_deq[97:96] == 2'd1; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_21$read_deq[97:96] == 2'd1; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_22$read_deq[97:96] == 2'd1; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_23$read_deq[97:96] == 2'd1; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_24$read_deq[97:96] == 2'd1; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_25$read_deq[97:96] == 2'd1; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_26$read_deq[97:96] == 2'd1; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_27$read_deq[97:96] == 2'd1; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_28$read_deq[97:96] == 2'd1; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_29$read_deq[97:96] == 2'd1; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_30$read_deq[97:96] == 2'd1; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = - m_row_1_31$read_deq[97:96] == 2'd1; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -41838,6 +41707,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[95:32]; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_0$read_deq[97:96] == 2'd1; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_1$read_deq[97:96] == 2'd1; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_2$read_deq[97:96] == 2'd1; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_3$read_deq[97:96] == 2'd1; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_4$read_deq[97:96] == 2'd1; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_5$read_deq[97:96] == 2'd1; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_6$read_deq[97:96] == 2'd1; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_7$read_deq[97:96] == 2'd1; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_8$read_deq[97:96] == 2'd1; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_9$read_deq[97:96] == 2'd1; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_10$read_deq[97:96] == 2'd1; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_11$read_deq[97:96] == 2'd1; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_12$read_deq[97:96] == 2'd1; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_13$read_deq[97:96] == 2'd1; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_14$read_deq[97:96] == 2'd1; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_15$read_deq[97:96] == 2'd1; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_16$read_deq[97:96] == 2'd1; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_17$read_deq[97:96] == 2'd1; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_18$read_deq[97:96] == 2'd1; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_19$read_deq[97:96] == 2'd1; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_20$read_deq[97:96] == 2'd1; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_21$read_deq[97:96] == 2'd1; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_22$read_deq[97:96] == 2'd1; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_23$read_deq[97:96] == 2'd1; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_24$read_deq[97:96] == 2'd1; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_25$read_deq[97:96] == 2'd1; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_26$read_deq[97:96] == 2'd1; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_27$read_deq[97:96] == 2'd1; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_28$read_deq[97:96] == 2'd1; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_29$read_deq[97:96] == 2'd1; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_30$read_deq[97:96] == 2'd1; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549 = + m_row_1_31$read_deq[97:96] == 2'd1; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -42519,137 +42519,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[26]; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_0$read_deq[25]; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_1$read_deq[25]; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_2$read_deq[25]; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_3$read_deq[25]; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_4$read_deq[25]; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_5$read_deq[25]; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_6$read_deq[25]; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_7$read_deq[25]; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_8$read_deq[25]; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_9$read_deq[25]; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_10$read_deq[25]; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_11$read_deq[25]; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_12$read_deq[25]; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_13$read_deq[25]; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_14$read_deq[25]; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_15$read_deq[25]; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_16$read_deq[25]; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_17$read_deq[25]; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_18$read_deq[25]; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_19$read_deq[25]; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_20$read_deq[25]; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_21$read_deq[25]; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_22$read_deq[25]; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_23$read_deq[25]; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_24$read_deq[25]; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_25$read_deq[25]; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_26$read_deq[25]; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_27$read_deq[25]; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_28$read_deq[25]; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_29$read_deq[25]; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_30$read_deq[25]; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = - m_row_0_31$read_deq[25]; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -42781,6 +42650,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[25]; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_0$read_deq[25]; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_1$read_deq[25]; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_2$read_deq[25]; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_3$read_deq[25]; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_4$read_deq[25]; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_5$read_deq[25]; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_6$read_deq[25]; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_7$read_deq[25]; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_8$read_deq[25]; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_9$read_deq[25]; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_10$read_deq[25]; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_11$read_deq[25]; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_12$read_deq[25]; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_13$read_deq[25]; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_14$read_deq[25]; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_15$read_deq[25]; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_16$read_deq[25]; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_17$read_deq[25]; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_18$read_deq[25]; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_19$read_deq[25]; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_20$read_deq[25]; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_21$read_deq[25]; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_22$read_deq[25]; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_23$read_deq[25]; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_24$read_deq[25]; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_25$read_deq[25]; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_26$read_deq[25]; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_27$read_deq[25]; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_28$read_deq[25]; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_29$read_deq[25]; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_30$read_deq[25]; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BIT_25_1765_m__ETC___d11798 = + m_row_0_31$read_deq[25]; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -43318,137 +43318,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[23:19]; endcase end - always@(p__h96619 or - m_row_1_0$read_deq or - m_row_1_1$read_deq or - m_row_1_2$read_deq or - m_row_1_3$read_deq or - m_row_1_4$read_deq or - m_row_1_5$read_deq or - m_row_1_6$read_deq or - m_row_1_7$read_deq or - m_row_1_8$read_deq or - m_row_1_9$read_deq or - m_row_1_10$read_deq or - m_row_1_11$read_deq or - m_row_1_12$read_deq or - m_row_1_13$read_deq or - m_row_1_14$read_deq or - m_row_1_15$read_deq or - m_row_1_16$read_deq or - m_row_1_17$read_deq or - m_row_1_18$read_deq or - m_row_1_19$read_deq or - m_row_1_20$read_deq or - m_row_1_21$read_deq or - m_row_1_22$read_deq or - m_row_1_23$read_deq or - m_row_1_24$read_deq or - m_row_1_25$read_deq or - m_row_1_26$read_deq or - m_row_1_27$read_deq or - m_row_1_28$read_deq or - m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) - begin - case (p__h96619) - 5'd0: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_0$read_deq[22:19]; - 5'd1: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_1$read_deq[22:19]; - 5'd2: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_2$read_deq[22:19]; - 5'd3: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_3$read_deq[22:19]; - 5'd4: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_4$read_deq[22:19]; - 5'd5: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_5$read_deq[22:19]; - 5'd6: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_6$read_deq[22:19]; - 5'd7: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_7$read_deq[22:19]; - 5'd8: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_8$read_deq[22:19]; - 5'd9: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_9$read_deq[22:19]; - 5'd10: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_10$read_deq[22:19]; - 5'd11: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_11$read_deq[22:19]; - 5'd12: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_12$read_deq[22:19]; - 5'd13: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_13$read_deq[22:19]; - 5'd14: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_14$read_deq[22:19]; - 5'd15: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_15$read_deq[22:19]; - 5'd16: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_16$read_deq[22:19]; - 5'd17: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_17$read_deq[22:19]; - 5'd18: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_18$read_deq[22:19]; - 5'd19: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_19$read_deq[22:19]; - 5'd20: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_20$read_deq[22:19]; - 5'd21: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_21$read_deq[22:19]; - 5'd22: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_22$read_deq[22:19]; - 5'd23: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_23$read_deq[22:19]; - 5'd24: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_24$read_deq[22:19]; - 5'd25: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_25$read_deq[22:19]; - 5'd26: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_26$read_deq[22:19]; - 5'd27: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_27$read_deq[22:19]; - 5'd28: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_28$read_deq[22:19]; - 5'd29: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_29$read_deq[22:19]; - 5'd30: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_30$read_deq[22:19]; - 5'd31: - SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = - m_row_1_31$read_deq[22:19]; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -43580,6 +43449,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[22:19]; endcase end + always@(p__h96619 or + m_row_1_0$read_deq or + m_row_1_1$read_deq or + m_row_1_2$read_deq or + m_row_1_3$read_deq or + m_row_1_4$read_deq or + m_row_1_5$read_deq or + m_row_1_6$read_deq or + m_row_1_7$read_deq or + m_row_1_8$read_deq or + m_row_1_9$read_deq or + m_row_1_10$read_deq or + m_row_1_11$read_deq or + m_row_1_12$read_deq or + m_row_1_13$read_deq or + m_row_1_14$read_deq or + m_row_1_15$read_deq or + m_row_1_16$read_deq or + m_row_1_17$read_deq or + m_row_1_18$read_deq or + m_row_1_19$read_deq or + m_row_1_20$read_deq or + m_row_1_21$read_deq or + m_row_1_22$read_deq or + m_row_1_23$read_deq or + m_row_1_24$read_deq or + m_row_1_25$read_deq or + m_row_1_26$read_deq or + m_row_1_27$read_deq or + m_row_1_28$read_deq or + m_row_1_29$read_deq or m_row_1_30$read_deq or m_row_1_31$read_deq) + begin + case (p__h96619) + 5'd0: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_0$read_deq[22:19]; + 5'd1: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_1$read_deq[22:19]; + 5'd2: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_2$read_deq[22:19]; + 5'd3: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_3$read_deq[22:19]; + 5'd4: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_4$read_deq[22:19]; + 5'd5: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_5$read_deq[22:19]; + 5'd6: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_6$read_deq[22:19]; + 5'd7: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_7$read_deq[22:19]; + 5'd8: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_8$read_deq[22:19]; + 5'd9: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_9$read_deq[22:19]; + 5'd10: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_10$read_deq[22:19]; + 5'd11: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_11$read_deq[22:19]; + 5'd12: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_12$read_deq[22:19]; + 5'd13: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_13$read_deq[22:19]; + 5'd14: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_14$read_deq[22:19]; + 5'd15: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_15$read_deq[22:19]; + 5'd16: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_16$read_deq[22:19]; + 5'd17: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_17$read_deq[22:19]; + 5'd18: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_18$read_deq[22:19]; + 5'd19: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_19$read_deq[22:19]; + 5'd20: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_20$read_deq[22:19]; + 5'd21: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_21$read_deq[22:19]; + 5'd22: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_22$read_deq[22:19]; + 5'd23: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_23$read_deq[22:19]; + 5'd24: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_24$read_deq[22:19]; + 5'd25: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_25$read_deq[22:19]; + 5'd26: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_26$read_deq[22:19]; + 5'd27: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_27$read_deq[22:19]; + 5'd28: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_28$read_deq[22:19]; + 5'd29: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_29$read_deq[22:19]; + 5'd30: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_30$read_deq[22:19]; + 5'd31: + SEL_ARR_m_row_1_0_read_deq__103_BITS_22_TO_19__ETC___d12107 = + m_row_1_31$read_deq[22:19]; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -43842,137 +43842,6 @@ module mkReorderBufferSynth(CLK, !m_row_1_31$read_deq[18]; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_0$read_deq[17:16]; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_1$read_deq[17:16]; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_2$read_deq[17:16]; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_3$read_deq[17:16]; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_4$read_deq[17:16]; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_5$read_deq[17:16]; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_6$read_deq[17:16]; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_7$read_deq[17:16]; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_8$read_deq[17:16]; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_9$read_deq[17:16]; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_10$read_deq[17:16]; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_11$read_deq[17:16]; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_12$read_deq[17:16]; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_13$read_deq[17:16]; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_14$read_deq[17:16]; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_15$read_deq[17:16]; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_16$read_deq[17:16]; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_17$read_deq[17:16]; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_18$read_deq[17:16]; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_19$read_deq[17:16]; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_20$read_deq[17:16]; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_21$read_deq[17:16]; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_22$read_deq[17:16]; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_23$read_deq[17:16]; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_24$read_deq[17:16]; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_25$read_deq[17:16]; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_26$read_deq[17:16]; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_27$read_deq[17:16]; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_28$read_deq[17:16]; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_29$read_deq[17:16]; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_30$read_deq[17:16]; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = - m_row_0_31$read_deq[17:16]; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -44104,6 +43973,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[17:16]; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_0$read_deq[17:16]; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_1$read_deq[17:16]; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_2$read_deq[17:16]; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_3$read_deq[17:16]; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_4$read_deq[17:16]; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_5$read_deq[17:16]; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_6$read_deq[17:16]; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_7$read_deq[17:16]; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_8$read_deq[17:16]; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_9$read_deq[17:16]; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_10$read_deq[17:16]; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_11$read_deq[17:16]; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_12$read_deq[17:16]; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_13$read_deq[17:16]; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_14$read_deq[17:16]; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_15$read_deq[17:16]; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_16$read_deq[17:16]; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_17$read_deq[17:16]; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_18$read_deq[17:16]; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_19$read_deq[17:16]; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_20$read_deq[17:16]; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_21$read_deq[17:16]; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_22$read_deq[17:16]; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_23$read_deq[17:16]; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_24$read_deq[17:16]; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_25$read_deq[17:16]; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_26$read_deq[17:16]; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_27$read_deq[17:16]; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_28$read_deq[17:16]; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_29$read_deq[17:16]; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_30$read_deq[17:16]; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BITS_17_TO_16__ETC___d12281 = + m_row_0_31$read_deq[17:16]; + endcase + end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -44235,6 +44235,137 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[15]; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_0$read_deq[14]; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_1$read_deq[14]; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_2$read_deq[14]; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_3$read_deq[14]; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_4$read_deq[14]; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_5$read_deq[14]; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_6$read_deq[14]; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_7$read_deq[14]; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_8$read_deq[14]; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_9$read_deq[14]; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_10$read_deq[14]; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_11$read_deq[14]; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_12$read_deq[14]; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_13$read_deq[14]; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_14$read_deq[14]; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_15$read_deq[14]; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_16$read_deq[14]; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_17$read_deq[14]; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_18$read_deq[14]; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_19$read_deq[14]; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_20$read_deq[14]; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_21$read_deq[14]; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_22$read_deq[14]; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_23$read_deq[14]; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_24$read_deq[14]; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_25$read_deq[14]; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_26$read_deq[14]; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_27$read_deq[14]; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_28$read_deq[14]; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_29$read_deq[14]; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_30$read_deq[14]; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = + m_row_0_31$read_deq[14]; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -44497,137 +44628,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[14]; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_0$read_deq[14]; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_1$read_deq[14]; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_2$read_deq[14]; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_3$read_deq[14]; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_4$read_deq[14]; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_5$read_deq[14]; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_6$read_deq[14]; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_7$read_deq[14]; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_8$read_deq[14]; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_9$read_deq[14]; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_10$read_deq[14]; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_11$read_deq[14]; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_12$read_deq[14]; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_13$read_deq[14]; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_14$read_deq[14]; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_15$read_deq[14]; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_16$read_deq[14]; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_17$read_deq[14]; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_18$read_deq[14]; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_19$read_deq[14]; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_20$read_deq[14]; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_21$read_deq[14]; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_22$read_deq[14]; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_23$read_deq[14]; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_24$read_deq[14]; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_25$read_deq[14]; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_26$read_deq[14]; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_27$read_deq[14]; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_28$read_deq[14]; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_29$read_deq[14]; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_30$read_deq[14]; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BIT_14_2389_m__ETC___d12422 = - m_row_0_31$read_deq[14]; - endcase - end always@(p__h86623 or m_row_0_0$read_deq or m_row_0_1$read_deq or @@ -44759,137 +44759,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$read_deq[13]; endcase end - always@(p__h86623 or - m_row_0_0$read_deq or - m_row_0_1$read_deq or - m_row_0_2$read_deq or - m_row_0_3$read_deq or - m_row_0_4$read_deq or - m_row_0_5$read_deq or - m_row_0_6$read_deq or - m_row_0_7$read_deq or - m_row_0_8$read_deq or - m_row_0_9$read_deq or - m_row_0_10$read_deq or - m_row_0_11$read_deq or - m_row_0_12$read_deq or - m_row_0_13$read_deq or - m_row_0_14$read_deq or - m_row_0_15$read_deq or - m_row_0_16$read_deq or - m_row_0_17$read_deq or - m_row_0_18$read_deq or - m_row_0_19$read_deq or - m_row_0_20$read_deq or - m_row_0_21$read_deq or - m_row_0_22$read_deq or - m_row_0_23$read_deq or - m_row_0_24$read_deq or - m_row_0_25$read_deq or - m_row_0_26$read_deq or - m_row_0_27$read_deq or - m_row_0_28$read_deq or - m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) - begin - case (p__h86623) - 5'd0: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_0$read_deq[12]; - 5'd1: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_1$read_deq[12]; - 5'd2: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_2$read_deq[12]; - 5'd3: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_3$read_deq[12]; - 5'd4: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_4$read_deq[12]; - 5'd5: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_5$read_deq[12]; - 5'd6: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_6$read_deq[12]; - 5'd7: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_7$read_deq[12]; - 5'd8: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_8$read_deq[12]; - 5'd9: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_9$read_deq[12]; - 5'd10: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_10$read_deq[12]; - 5'd11: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_11$read_deq[12]; - 5'd12: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_12$read_deq[12]; - 5'd13: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_13$read_deq[12]; - 5'd14: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_14$read_deq[12]; - 5'd15: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_15$read_deq[12]; - 5'd16: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_16$read_deq[12]; - 5'd17: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_17$read_deq[12]; - 5'd18: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_18$read_deq[12]; - 5'd19: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_19$read_deq[12]; - 5'd20: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_20$read_deq[12]; - 5'd21: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_21$read_deq[12]; - 5'd22: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_22$read_deq[12]; - 5'd23: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_23$read_deq[12]; - 5'd24: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_24$read_deq[12]; - 5'd25: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_25$read_deq[12]; - 5'd26: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_26$read_deq[12]; - 5'd27: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_27$read_deq[12]; - 5'd28: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_28$read_deq[12]; - 5'd29: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_29$read_deq[12]; - 5'd30: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_30$read_deq[12]; - 5'd31: - SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = - m_row_0_31$read_deq[12]; - endcase - end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -45021,6 +44890,137 @@ module mkReorderBufferSynth(CLK, m_row_1_31$read_deq[13]; endcase end + always@(p__h86623 or + m_row_0_0$read_deq or + m_row_0_1$read_deq or + m_row_0_2$read_deq or + m_row_0_3$read_deq or + m_row_0_4$read_deq or + m_row_0_5$read_deq or + m_row_0_6$read_deq or + m_row_0_7$read_deq or + m_row_0_8$read_deq or + m_row_0_9$read_deq or + m_row_0_10$read_deq or + m_row_0_11$read_deq or + m_row_0_12$read_deq or + m_row_0_13$read_deq or + m_row_0_14$read_deq or + m_row_0_15$read_deq or + m_row_0_16$read_deq or + m_row_0_17$read_deq or + m_row_0_18$read_deq or + m_row_0_19$read_deq or + m_row_0_20$read_deq or + m_row_0_21$read_deq or + m_row_0_22$read_deq or + m_row_0_23$read_deq or + m_row_0_24$read_deq or + m_row_0_25$read_deq or + m_row_0_26$read_deq or + m_row_0_27$read_deq or + m_row_0_28$read_deq or + m_row_0_29$read_deq or m_row_0_30$read_deq or m_row_0_31$read_deq) + begin + case (p__h86623) + 5'd0: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_0$read_deq[12]; + 5'd1: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_1$read_deq[12]; + 5'd2: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_2$read_deq[12]; + 5'd3: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_3$read_deq[12]; + 5'd4: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_4$read_deq[12]; + 5'd5: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_5$read_deq[12]; + 5'd6: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_6$read_deq[12]; + 5'd7: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_7$read_deq[12]; + 5'd8: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_8$read_deq[12]; + 5'd9: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_9$read_deq[12]; + 5'd10: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_10$read_deq[12]; + 5'd11: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_11$read_deq[12]; + 5'd12: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_12$read_deq[12]; + 5'd13: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_13$read_deq[12]; + 5'd14: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_14$read_deq[12]; + 5'd15: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_15$read_deq[12]; + 5'd16: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_16$read_deq[12]; + 5'd17: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_17$read_deq[12]; + 5'd18: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_18$read_deq[12]; + 5'd19: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_19$read_deq[12]; + 5'd20: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_20$read_deq[12]; + 5'd21: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_21$read_deq[12]; + 5'd22: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_22$read_deq[12]; + 5'd23: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_23$read_deq[12]; + 5'd24: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_24$read_deq[12]; + 5'd25: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_25$read_deq[12]; + 5'd26: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_26$read_deq[12]; + 5'd27: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_27$read_deq[12]; + 5'd28: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_28$read_deq[12]; + 5'd29: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_29$read_deq[12]; + 5'd30: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_30$read_deq[12]; + 5'd31: + SEL_ARR_m_row_0_0_read_deq__037_BIT_12_2529_m__ETC___d12562 = + m_row_0_31$read_deq[12]; + endcase + end always@(p__h96619 or m_row_1_0$read_deq or m_row_1_1$read_deq or @@ -45453,19 +45453,6 @@ module mkReorderBufferSynth(CLK, SEL_ARR_m_row_1_0_read_deq__103_BITS_97_TO_96__ETC___d11549; endcase end - always@(way__h512296 or - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_24_183_ETC___d11900 or - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_24_190_ETC___d11966) - begin - case (way__h512296) - 1'd0: - SEL_ARR_SEL_ARR_NOT_m_row_0_0_read_deq__037_BI_ETC___d12827 = - SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_24_183_ETC___d11900; - 1'd1: - SEL_ARR_SEL_ARR_NOT_m_row_0_0_read_deq__037_BI_ETC___d12827 = - SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_24_190_ETC___d11966; - endcase - end always@(getOrigPC_0_get_x or m_row_0_0$getOrigPC or m_row_0_1$getOrigPC or @@ -45598,6 +45585,19 @@ module mkReorderBufferSynth(CLK, m_row_0_31$getOrigPC; endcase end + always@(way__h512296 or + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_24_183_ETC___d11900 or + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_24_190_ETC___d11966) + begin + case (way__h512296) + 1'd0: + SEL_ARR_SEL_ARR_NOT_m_row_0_0_read_deq__037_BI_ETC___d12827 = + SEL_ARR_NOT_m_row_0_0_read_deq__037_BIT_24_183_ETC___d11900; + 1'd1: + SEL_ARR_SEL_ARR_NOT_m_row_0_0_read_deq__037_BI_ETC___d12827 = + SEL_ARR_NOT_m_row_1_0_read_deq__103_BIT_24_190_ETC___d11966; + endcase + end always@(getOrigPC_1_get_x or m_row_0_0$getOrigPC or m_row_0_1$getOrigPC or @@ -45862,138 +45862,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$getOrigPC; endcase end - always@(getOrigPredPC_1_get_x or - m_row_0_0$getOrigPredPC or - m_row_0_1$getOrigPredPC or - m_row_0_2$getOrigPredPC or - m_row_0_3$getOrigPredPC or - m_row_0_4$getOrigPredPC or - m_row_0_5$getOrigPredPC or - m_row_0_6$getOrigPredPC or - m_row_0_7$getOrigPredPC or - m_row_0_8$getOrigPredPC or - m_row_0_9$getOrigPredPC or - m_row_0_10$getOrigPredPC or - m_row_0_11$getOrigPredPC or - m_row_0_12$getOrigPredPC or - m_row_0_13$getOrigPredPC or - m_row_0_14$getOrigPredPC or - m_row_0_15$getOrigPredPC or - m_row_0_16$getOrigPredPC or - m_row_0_17$getOrigPredPC or - m_row_0_18$getOrigPredPC or - m_row_0_19$getOrigPredPC or - m_row_0_20$getOrigPredPC or - m_row_0_21$getOrigPredPC or - m_row_0_22$getOrigPredPC or - m_row_0_23$getOrigPredPC or - m_row_0_24$getOrigPredPC or - m_row_0_25$getOrigPredPC or - m_row_0_26$getOrigPredPC or - m_row_0_27$getOrigPredPC or - m_row_0_28$getOrigPredPC or - m_row_0_29$getOrigPredPC or - m_row_0_30$getOrigPredPC or m_row_0_31$getOrigPredPC) - begin - case (getOrigPredPC_1_get_x[10:6]) - 5'd0: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_0$getOrigPredPC; - 5'd1: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_1$getOrigPredPC; - 5'd2: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_2$getOrigPredPC; - 5'd3: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_3$getOrigPredPC; - 5'd4: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_4$getOrigPredPC; - 5'd5: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_5$getOrigPredPC; - 5'd6: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_6$getOrigPredPC; - 5'd7: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_7$getOrigPredPC; - 5'd8: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_8$getOrigPredPC; - 5'd9: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_9$getOrigPredPC; - 5'd10: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_10$getOrigPredPC; - 5'd11: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_11$getOrigPredPC; - 5'd12: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_12$getOrigPredPC; - 5'd13: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_13$getOrigPredPC; - 5'd14: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_14$getOrigPredPC; - 5'd15: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_15$getOrigPredPC; - 5'd16: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_16$getOrigPredPC; - 5'd17: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_17$getOrigPredPC; - 5'd18: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_18$getOrigPredPC; - 5'd19: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_19$getOrigPredPC; - 5'd20: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_20$getOrigPredPC; - 5'd21: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_21$getOrigPredPC; - 5'd22: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_22$getOrigPredPC; - 5'd23: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_23$getOrigPredPC; - 5'd24: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_24$getOrigPredPC; - 5'd25: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_25$getOrigPredPC; - 5'd26: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_26$getOrigPredPC; - 5'd27: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_27$getOrigPredPC; - 5'd28: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_28$getOrigPredPC; - 5'd29: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_29$getOrigPredPC; - 5'd30: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_30$getOrigPredPC; - 5'd31: - SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = - m_row_0_31$getOrigPredPC; - endcase - end always@(getOrigPredPC_0_get_x or m_row_0_0$getOrigPredPC or m_row_0_1$getOrigPredPC or @@ -46126,6 +45994,138 @@ module mkReorderBufferSynth(CLK, m_row_0_31$getOrigPredPC; endcase end + always@(getOrigPredPC_1_get_x or + m_row_0_0$getOrigPredPC or + m_row_0_1$getOrigPredPC or + m_row_0_2$getOrigPredPC or + m_row_0_3$getOrigPredPC or + m_row_0_4$getOrigPredPC or + m_row_0_5$getOrigPredPC or + m_row_0_6$getOrigPredPC or + m_row_0_7$getOrigPredPC or + m_row_0_8$getOrigPredPC or + m_row_0_9$getOrigPredPC or + m_row_0_10$getOrigPredPC or + m_row_0_11$getOrigPredPC or + m_row_0_12$getOrigPredPC or + m_row_0_13$getOrigPredPC or + m_row_0_14$getOrigPredPC or + m_row_0_15$getOrigPredPC or + m_row_0_16$getOrigPredPC or + m_row_0_17$getOrigPredPC or + m_row_0_18$getOrigPredPC or + m_row_0_19$getOrigPredPC or + m_row_0_20$getOrigPredPC or + m_row_0_21$getOrigPredPC or + m_row_0_22$getOrigPredPC or + m_row_0_23$getOrigPredPC or + m_row_0_24$getOrigPredPC or + m_row_0_25$getOrigPredPC or + m_row_0_26$getOrigPredPC or + m_row_0_27$getOrigPredPC or + m_row_0_28$getOrigPredPC or + m_row_0_29$getOrigPredPC or + m_row_0_30$getOrigPredPC or m_row_0_31$getOrigPredPC) + begin + case (getOrigPredPC_1_get_x[10:6]) + 5'd0: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_0$getOrigPredPC; + 5'd1: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_1$getOrigPredPC; + 5'd2: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_2$getOrigPredPC; + 5'd3: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_3$getOrigPredPC; + 5'd4: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_4$getOrigPredPC; + 5'd5: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_5$getOrigPredPC; + 5'd6: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_6$getOrigPredPC; + 5'd7: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_7$getOrigPredPC; + 5'd8: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_8$getOrigPredPC; + 5'd9: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_9$getOrigPredPC; + 5'd10: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_10$getOrigPredPC; + 5'd11: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_11$getOrigPredPC; + 5'd12: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_12$getOrigPredPC; + 5'd13: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_13$getOrigPredPC; + 5'd14: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_14$getOrigPredPC; + 5'd15: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_15$getOrigPredPC; + 5'd16: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_16$getOrigPredPC; + 5'd17: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_17$getOrigPredPC; + 5'd18: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_18$getOrigPredPC; + 5'd19: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_19$getOrigPredPC; + 5'd20: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_20$getOrigPredPC; + 5'd21: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_21$getOrigPredPC; + 5'd22: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_22$getOrigPredPC; + 5'd23: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_23$getOrigPredPC; + 5'd24: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_24$getOrigPredPC; + 5'd25: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_25$getOrigPredPC; + 5'd26: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_26$getOrigPredPC; + 5'd27: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_27$getOrigPredPC; + 5'd28: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_28$getOrigPredPC; + 5'd29: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_29$getOrigPredPC; + 5'd30: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_30$getOrigPredPC; + 5'd31: + SEL_ARR_m_row_0_0_getOrigPredPC__3585_m_row_0__ETC___d13657 = + m_row_0_31$getOrigPredPC; + endcase + end always@(getOrig_Inst_0_get_x or m_row_0_0$getOrig_Inst or m_row_0_1$getOrig_Inst or @@ -46390,234 +46390,6 @@ module mkReorderBufferSynth(CLK, m_row_0_31$getOrig_Inst; endcase end - always@(m_enqP_0 or - m_valid_0_0_dummy2_0$Q_OUT or - m_valid_0_0_dummy2_1$Q_OUT or - m_valid_0_0_rl or - m_valid_0_1_dummy2_0$Q_OUT or - m_valid_0_1_dummy2_1$Q_OUT or - m_valid_0_1_rl or - m_valid_0_2_dummy2_0$Q_OUT or - m_valid_0_2_dummy2_1$Q_OUT or - m_valid_0_2_rl or - m_valid_0_3_dummy2_0$Q_OUT or - m_valid_0_3_dummy2_1$Q_OUT or - m_valid_0_3_rl or - m_valid_0_4_dummy2_0$Q_OUT or - m_valid_0_4_dummy2_1$Q_OUT or - m_valid_0_4_rl or - m_valid_0_5_dummy2_0$Q_OUT or - m_valid_0_5_dummy2_1$Q_OUT or - m_valid_0_5_rl or - m_valid_0_6_dummy2_0$Q_OUT or - m_valid_0_6_dummy2_1$Q_OUT or - m_valid_0_6_rl or - m_valid_0_7_dummy2_0$Q_OUT or - m_valid_0_7_dummy2_1$Q_OUT or - m_valid_0_7_rl or - m_valid_0_8_dummy2_0$Q_OUT or - m_valid_0_8_dummy2_1$Q_OUT or - m_valid_0_8_rl or - m_valid_0_9_dummy2_0$Q_OUT or - m_valid_0_9_dummy2_1$Q_OUT or - m_valid_0_9_rl or - m_valid_0_10_dummy2_0$Q_OUT or - m_valid_0_10_dummy2_1$Q_OUT or - m_valid_0_10_rl or - m_valid_0_11_dummy2_0$Q_OUT or - m_valid_0_11_dummy2_1$Q_OUT or - m_valid_0_11_rl or - m_valid_0_12_dummy2_0$Q_OUT or - m_valid_0_12_dummy2_1$Q_OUT or - m_valid_0_12_rl or - m_valid_0_13_dummy2_0$Q_OUT or - m_valid_0_13_dummy2_1$Q_OUT or - m_valid_0_13_rl or - m_valid_0_14_dummy2_0$Q_OUT or - m_valid_0_14_dummy2_1$Q_OUT or - m_valid_0_14_rl or - m_valid_0_15_dummy2_0$Q_OUT or - m_valid_0_15_dummy2_1$Q_OUT or - m_valid_0_15_rl or - m_valid_0_16_dummy2_0$Q_OUT or - m_valid_0_16_dummy2_1$Q_OUT or - m_valid_0_16_rl or - m_valid_0_17_dummy2_0$Q_OUT or - m_valid_0_17_dummy2_1$Q_OUT or - m_valid_0_17_rl or - m_valid_0_18_dummy2_0$Q_OUT or - m_valid_0_18_dummy2_1$Q_OUT or - m_valid_0_18_rl or - m_valid_0_19_dummy2_0$Q_OUT or - m_valid_0_19_dummy2_1$Q_OUT or - m_valid_0_19_rl or - m_valid_0_20_dummy2_0$Q_OUT or - m_valid_0_20_dummy2_1$Q_OUT or - m_valid_0_20_rl or - m_valid_0_21_dummy2_0$Q_OUT or - m_valid_0_21_dummy2_1$Q_OUT or - m_valid_0_21_rl or - m_valid_0_22_dummy2_0$Q_OUT or - m_valid_0_22_dummy2_1$Q_OUT or - m_valid_0_22_rl or - m_valid_0_23_dummy2_0$Q_OUT or - m_valid_0_23_dummy2_1$Q_OUT or - m_valid_0_23_rl or - m_valid_0_24_dummy2_0$Q_OUT or - m_valid_0_24_dummy2_1$Q_OUT or - m_valid_0_24_rl or - m_valid_0_25_dummy2_0$Q_OUT or - m_valid_0_25_dummy2_1$Q_OUT or - m_valid_0_25_rl or - m_valid_0_26_dummy2_0$Q_OUT or - m_valid_0_26_dummy2_1$Q_OUT or - m_valid_0_26_rl or - m_valid_0_27_dummy2_0$Q_OUT or - m_valid_0_27_dummy2_1$Q_OUT or - m_valid_0_27_rl or - m_valid_0_28_dummy2_0$Q_OUT or - m_valid_0_28_dummy2_1$Q_OUT or - m_valid_0_28_rl or - m_valid_0_29_dummy2_0$Q_OUT or - m_valid_0_29_dummy2_1$Q_OUT or - m_valid_0_29_rl or - m_valid_0_30_dummy2_0$Q_OUT or - m_valid_0_30_dummy2_1$Q_OUT or - m_valid_0_30_rl or - m_valid_0_31_dummy2_0$Q_OUT or - m_valid_0_31_dummy2_1$Q_OUT or m_valid_0_31_rl) - begin - case (m_enqP_0) - 5'd0: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_0_dummy2_0$Q_OUT && m_valid_0_0_dummy2_1$Q_OUT && - m_valid_0_0_rl; - 5'd1: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_1_dummy2_0$Q_OUT && m_valid_0_1_dummy2_1$Q_OUT && - m_valid_0_1_rl; - 5'd2: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_2_dummy2_0$Q_OUT && m_valid_0_2_dummy2_1$Q_OUT && - m_valid_0_2_rl; - 5'd3: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_3_dummy2_0$Q_OUT && m_valid_0_3_dummy2_1$Q_OUT && - m_valid_0_3_rl; - 5'd4: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_4_dummy2_0$Q_OUT && m_valid_0_4_dummy2_1$Q_OUT && - m_valid_0_4_rl; - 5'd5: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_5_dummy2_0$Q_OUT && m_valid_0_5_dummy2_1$Q_OUT && - m_valid_0_5_rl; - 5'd6: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_6_dummy2_0$Q_OUT && m_valid_0_6_dummy2_1$Q_OUT && - m_valid_0_6_rl; - 5'd7: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_7_dummy2_0$Q_OUT && m_valid_0_7_dummy2_1$Q_OUT && - m_valid_0_7_rl; - 5'd8: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_8_dummy2_0$Q_OUT && m_valid_0_8_dummy2_1$Q_OUT && - m_valid_0_8_rl; - 5'd9: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_9_dummy2_0$Q_OUT && m_valid_0_9_dummy2_1$Q_OUT && - m_valid_0_9_rl; - 5'd10: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_10_dummy2_0$Q_OUT && m_valid_0_10_dummy2_1$Q_OUT && - m_valid_0_10_rl; - 5'd11: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_11_dummy2_0$Q_OUT && m_valid_0_11_dummy2_1$Q_OUT && - m_valid_0_11_rl; - 5'd12: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_12_dummy2_0$Q_OUT && m_valid_0_12_dummy2_1$Q_OUT && - m_valid_0_12_rl; - 5'd13: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_13_dummy2_0$Q_OUT && m_valid_0_13_dummy2_1$Q_OUT && - m_valid_0_13_rl; - 5'd14: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_14_dummy2_0$Q_OUT && m_valid_0_14_dummy2_1$Q_OUT && - m_valid_0_14_rl; - 5'd15: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_15_dummy2_0$Q_OUT && m_valid_0_15_dummy2_1$Q_OUT && - m_valid_0_15_rl; - 5'd16: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_16_dummy2_0$Q_OUT && m_valid_0_16_dummy2_1$Q_OUT && - m_valid_0_16_rl; - 5'd17: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_17_dummy2_0$Q_OUT && m_valid_0_17_dummy2_1$Q_OUT && - m_valid_0_17_rl; - 5'd18: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_18_dummy2_0$Q_OUT && m_valid_0_18_dummy2_1$Q_OUT && - m_valid_0_18_rl; - 5'd19: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_19_dummy2_0$Q_OUT && m_valid_0_19_dummy2_1$Q_OUT && - m_valid_0_19_rl; - 5'd20: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_20_dummy2_0$Q_OUT && m_valid_0_20_dummy2_1$Q_OUT && - m_valid_0_20_rl; - 5'd21: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_21_dummy2_0$Q_OUT && m_valid_0_21_dummy2_1$Q_OUT && - m_valid_0_21_rl; - 5'd22: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_22_dummy2_0$Q_OUT && m_valid_0_22_dummy2_1$Q_OUT && - m_valid_0_22_rl; - 5'd23: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_23_dummy2_0$Q_OUT && m_valid_0_23_dummy2_1$Q_OUT && - m_valid_0_23_rl; - 5'd24: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_24_dummy2_0$Q_OUT && m_valid_0_24_dummy2_1$Q_OUT && - m_valid_0_24_rl; - 5'd25: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_25_dummy2_0$Q_OUT && m_valid_0_25_dummy2_1$Q_OUT && - m_valid_0_25_rl; - 5'd26: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_26_dummy2_0$Q_OUT && m_valid_0_26_dummy2_1$Q_OUT && - m_valid_0_26_rl; - 5'd27: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_27_dummy2_0$Q_OUT && m_valid_0_27_dummy2_1$Q_OUT && - m_valid_0_27_rl; - 5'd28: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_28_dummy2_0$Q_OUT && m_valid_0_28_dummy2_1$Q_OUT && - m_valid_0_28_rl; - 5'd29: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_29_dummy2_0$Q_OUT && m_valid_0_29_dummy2_1$Q_OUT && - m_valid_0_29_rl; - 5'd30: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_30_dummy2_0$Q_OUT && m_valid_0_30_dummy2_1$Q_OUT && - m_valid_0_30_rl; - 5'd31: - SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = - m_valid_0_31_dummy2_0$Q_OUT && m_valid_0_31_dummy2_1$Q_OUT && - m_valid_0_31_rl; - endcase - end always@(m_enqP_1 or m_valid_1_0_dummy2_0$Q_OUT or m_valid_1_0_dummy2_1$Q_OUT or @@ -46846,6 +46618,234 @@ module mkReorderBufferSynth(CLK, m_valid_1_31_rl; endcase end + always@(m_enqP_0 or + m_valid_0_0_dummy2_0$Q_OUT or + m_valid_0_0_dummy2_1$Q_OUT or + m_valid_0_0_rl or + m_valid_0_1_dummy2_0$Q_OUT or + m_valid_0_1_dummy2_1$Q_OUT or + m_valid_0_1_rl or + m_valid_0_2_dummy2_0$Q_OUT or + m_valid_0_2_dummy2_1$Q_OUT or + m_valid_0_2_rl or + m_valid_0_3_dummy2_0$Q_OUT or + m_valid_0_3_dummy2_1$Q_OUT or + m_valid_0_3_rl or + m_valid_0_4_dummy2_0$Q_OUT or + m_valid_0_4_dummy2_1$Q_OUT or + m_valid_0_4_rl or + m_valid_0_5_dummy2_0$Q_OUT or + m_valid_0_5_dummy2_1$Q_OUT or + m_valid_0_5_rl or + m_valid_0_6_dummy2_0$Q_OUT or + m_valid_0_6_dummy2_1$Q_OUT or + m_valid_0_6_rl or + m_valid_0_7_dummy2_0$Q_OUT or + m_valid_0_7_dummy2_1$Q_OUT or + m_valid_0_7_rl or + m_valid_0_8_dummy2_0$Q_OUT or + m_valid_0_8_dummy2_1$Q_OUT or + m_valid_0_8_rl or + m_valid_0_9_dummy2_0$Q_OUT or + m_valid_0_9_dummy2_1$Q_OUT or + m_valid_0_9_rl or + m_valid_0_10_dummy2_0$Q_OUT or + m_valid_0_10_dummy2_1$Q_OUT or + m_valid_0_10_rl or + m_valid_0_11_dummy2_0$Q_OUT or + m_valid_0_11_dummy2_1$Q_OUT or + m_valid_0_11_rl or + m_valid_0_12_dummy2_0$Q_OUT or + m_valid_0_12_dummy2_1$Q_OUT or + m_valid_0_12_rl or + m_valid_0_13_dummy2_0$Q_OUT or + m_valid_0_13_dummy2_1$Q_OUT or + m_valid_0_13_rl or + m_valid_0_14_dummy2_0$Q_OUT or + m_valid_0_14_dummy2_1$Q_OUT or + m_valid_0_14_rl or + m_valid_0_15_dummy2_0$Q_OUT or + m_valid_0_15_dummy2_1$Q_OUT or + m_valid_0_15_rl or + m_valid_0_16_dummy2_0$Q_OUT or + m_valid_0_16_dummy2_1$Q_OUT or + m_valid_0_16_rl or + m_valid_0_17_dummy2_0$Q_OUT or + m_valid_0_17_dummy2_1$Q_OUT or + m_valid_0_17_rl or + m_valid_0_18_dummy2_0$Q_OUT or + m_valid_0_18_dummy2_1$Q_OUT or + m_valid_0_18_rl or + m_valid_0_19_dummy2_0$Q_OUT or + m_valid_0_19_dummy2_1$Q_OUT or + m_valid_0_19_rl or + m_valid_0_20_dummy2_0$Q_OUT or + m_valid_0_20_dummy2_1$Q_OUT or + m_valid_0_20_rl or + m_valid_0_21_dummy2_0$Q_OUT or + m_valid_0_21_dummy2_1$Q_OUT or + m_valid_0_21_rl or + m_valid_0_22_dummy2_0$Q_OUT or + m_valid_0_22_dummy2_1$Q_OUT or + m_valid_0_22_rl or + m_valid_0_23_dummy2_0$Q_OUT or + m_valid_0_23_dummy2_1$Q_OUT or + m_valid_0_23_rl or + m_valid_0_24_dummy2_0$Q_OUT or + m_valid_0_24_dummy2_1$Q_OUT or + m_valid_0_24_rl or + m_valid_0_25_dummy2_0$Q_OUT or + m_valid_0_25_dummy2_1$Q_OUT or + m_valid_0_25_rl or + m_valid_0_26_dummy2_0$Q_OUT or + m_valid_0_26_dummy2_1$Q_OUT or + m_valid_0_26_rl or + m_valid_0_27_dummy2_0$Q_OUT or + m_valid_0_27_dummy2_1$Q_OUT or + m_valid_0_27_rl or + m_valid_0_28_dummy2_0$Q_OUT or + m_valid_0_28_dummy2_1$Q_OUT or + m_valid_0_28_rl or + m_valid_0_29_dummy2_0$Q_OUT or + m_valid_0_29_dummy2_1$Q_OUT or + m_valid_0_29_rl or + m_valid_0_30_dummy2_0$Q_OUT or + m_valid_0_30_dummy2_1$Q_OUT or + m_valid_0_30_rl or + m_valid_0_31_dummy2_0$Q_OUT or + m_valid_0_31_dummy2_1$Q_OUT or m_valid_0_31_rl) + begin + case (m_enqP_0) + 5'd0: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_0_dummy2_0$Q_OUT && m_valid_0_0_dummy2_1$Q_OUT && + m_valid_0_0_rl; + 5'd1: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_1_dummy2_0$Q_OUT && m_valid_0_1_dummy2_1$Q_OUT && + m_valid_0_1_rl; + 5'd2: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_2_dummy2_0$Q_OUT && m_valid_0_2_dummy2_1$Q_OUT && + m_valid_0_2_rl; + 5'd3: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_3_dummy2_0$Q_OUT && m_valid_0_3_dummy2_1$Q_OUT && + m_valid_0_3_rl; + 5'd4: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_4_dummy2_0$Q_OUT && m_valid_0_4_dummy2_1$Q_OUT && + m_valid_0_4_rl; + 5'd5: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_5_dummy2_0$Q_OUT && m_valid_0_5_dummy2_1$Q_OUT && + m_valid_0_5_rl; + 5'd6: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_6_dummy2_0$Q_OUT && m_valid_0_6_dummy2_1$Q_OUT && + m_valid_0_6_rl; + 5'd7: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_7_dummy2_0$Q_OUT && m_valid_0_7_dummy2_1$Q_OUT && + m_valid_0_7_rl; + 5'd8: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_8_dummy2_0$Q_OUT && m_valid_0_8_dummy2_1$Q_OUT && + m_valid_0_8_rl; + 5'd9: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_9_dummy2_0$Q_OUT && m_valid_0_9_dummy2_1$Q_OUT && + m_valid_0_9_rl; + 5'd10: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_10_dummy2_0$Q_OUT && m_valid_0_10_dummy2_1$Q_OUT && + m_valid_0_10_rl; + 5'd11: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_11_dummy2_0$Q_OUT && m_valid_0_11_dummy2_1$Q_OUT && + m_valid_0_11_rl; + 5'd12: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_12_dummy2_0$Q_OUT && m_valid_0_12_dummy2_1$Q_OUT && + m_valid_0_12_rl; + 5'd13: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_13_dummy2_0$Q_OUT && m_valid_0_13_dummy2_1$Q_OUT && + m_valid_0_13_rl; + 5'd14: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_14_dummy2_0$Q_OUT && m_valid_0_14_dummy2_1$Q_OUT && + m_valid_0_14_rl; + 5'd15: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_15_dummy2_0$Q_OUT && m_valid_0_15_dummy2_1$Q_OUT && + m_valid_0_15_rl; + 5'd16: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_16_dummy2_0$Q_OUT && m_valid_0_16_dummy2_1$Q_OUT && + m_valid_0_16_rl; + 5'd17: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_17_dummy2_0$Q_OUT && m_valid_0_17_dummy2_1$Q_OUT && + m_valid_0_17_rl; + 5'd18: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_18_dummy2_0$Q_OUT && m_valid_0_18_dummy2_1$Q_OUT && + m_valid_0_18_rl; + 5'd19: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_19_dummy2_0$Q_OUT && m_valid_0_19_dummy2_1$Q_OUT && + m_valid_0_19_rl; + 5'd20: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_20_dummy2_0$Q_OUT && m_valid_0_20_dummy2_1$Q_OUT && + m_valid_0_20_rl; + 5'd21: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_21_dummy2_0$Q_OUT && m_valid_0_21_dummy2_1$Q_OUT && + m_valid_0_21_rl; + 5'd22: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_22_dummy2_0$Q_OUT && m_valid_0_22_dummy2_1$Q_OUT && + m_valid_0_22_rl; + 5'd23: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_23_dummy2_0$Q_OUT && m_valid_0_23_dummy2_1$Q_OUT && + m_valid_0_23_rl; + 5'd24: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_24_dummy2_0$Q_OUT && m_valid_0_24_dummy2_1$Q_OUT && + m_valid_0_24_rl; + 5'd25: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_25_dummy2_0$Q_OUT && m_valid_0_25_dummy2_1$Q_OUT && + m_valid_0_25_rl; + 5'd26: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_26_dummy2_0$Q_OUT && m_valid_0_26_dummy2_1$Q_OUT && + m_valid_0_26_rl; + 5'd27: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_27_dummy2_0$Q_OUT && m_valid_0_27_dummy2_1$Q_OUT && + m_valid_0_27_rl; + 5'd28: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_28_dummy2_0$Q_OUT && m_valid_0_28_dummy2_1$Q_OUT && + m_valid_0_28_rl; + 5'd29: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_29_dummy2_0$Q_OUT && m_valid_0_29_dummy2_1$Q_OUT && + m_valid_0_29_rl; + 5'd30: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_30_dummy2_0$Q_OUT && m_valid_0_30_dummy2_1$Q_OUT && + m_valid_0_30_rl; + 5'd31: + SEL_ARR_m_valid_0_0_dummy2_0_read__87_AND_m_va_ETC___d13737 = + m_valid_0_31_dummy2_0$Q_OUT && m_valid_0_31_dummy2_1$Q_OUT && + m_valid_0_31_rl; + endcase + end always@(x__h99963 or SEL_ARR_IF_m_row_0_0_read_deq__037_BITS_165_TO_ETC___d9939 or SEL_ARR_IF_m_row_1_0_read_deq__103_BITS_165_TO_ETC___d9973) @@ -49272,138 +49272,6 @@ module mkReorderBufferSynth(CLK, m_row_1_31$getOrigPC; endcase end - always@(getOrigPC_2_get_x or - m_row_1_0$getOrigPC or - m_row_1_1$getOrigPC or - m_row_1_2$getOrigPC or - m_row_1_3$getOrigPC or - m_row_1_4$getOrigPC or - m_row_1_5$getOrigPC or - m_row_1_6$getOrigPC or - m_row_1_7$getOrigPC or - m_row_1_8$getOrigPC or - m_row_1_9$getOrigPC or - m_row_1_10$getOrigPC or - m_row_1_11$getOrigPC or - m_row_1_12$getOrigPC or - m_row_1_13$getOrigPC or - m_row_1_14$getOrigPC or - m_row_1_15$getOrigPC or - m_row_1_16$getOrigPC or - m_row_1_17$getOrigPC or - m_row_1_18$getOrigPC or - m_row_1_19$getOrigPC or - m_row_1_20$getOrigPC or - m_row_1_21$getOrigPC or - m_row_1_22$getOrigPC or - m_row_1_23$getOrigPC or - m_row_1_24$getOrigPC or - m_row_1_25$getOrigPC or - m_row_1_26$getOrigPC or - m_row_1_27$getOrigPC or - m_row_1_28$getOrigPC or - m_row_1_29$getOrigPC or - m_row_1_30$getOrigPC or m_row_1_31$getOrigPC) - begin - case (getOrigPC_2_get_x[10:6]) - 5'd0: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_0$getOrigPC; - 5'd1: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_1$getOrigPC; - 5'd2: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_2$getOrigPC; - 5'd3: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_3$getOrigPC; - 5'd4: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_4$getOrigPC; - 5'd5: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_5$getOrigPC; - 5'd6: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_6$getOrigPC; - 5'd7: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_7$getOrigPC; - 5'd8: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_8$getOrigPC; - 5'd9: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_9$getOrigPC; - 5'd10: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_10$getOrigPC; - 5'd11: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_11$getOrigPC; - 5'd12: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_12$getOrigPC; - 5'd13: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_13$getOrigPC; - 5'd14: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_14$getOrigPC; - 5'd15: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_15$getOrigPC; - 5'd16: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_16$getOrigPC; - 5'd17: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_17$getOrigPC; - 5'd18: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_18$getOrigPC; - 5'd19: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_19$getOrigPC; - 5'd20: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_20$getOrigPC; - 5'd21: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_21$getOrigPC; - 5'd22: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_22$getOrigPC; - 5'd23: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_23$getOrigPC; - 5'd24: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_24$getOrigPC; - 5'd25: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_25$getOrigPC; - 5'd26: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_26$getOrigPC; - 5'd27: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_27$getOrigPC; - 5'd28: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_28$getOrigPC; - 5'd29: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_29$getOrigPC; - 5'd30: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_30$getOrigPC; - 5'd31: - SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = - m_row_1_31$getOrigPC; - endcase - end always@(getOrigPredPC_0_get_x or m_row_1_0$getOrigPredPC or m_row_1_1$getOrigPredPC or @@ -49536,6 +49404,138 @@ module mkReorderBufferSynth(CLK, m_row_1_31$getOrigPredPC; endcase end + always@(getOrigPC_2_get_x or + m_row_1_0$getOrigPC or + m_row_1_1$getOrigPC or + m_row_1_2$getOrigPC or + m_row_1_3$getOrigPC or + m_row_1_4$getOrigPC or + m_row_1_5$getOrigPC or + m_row_1_6$getOrigPC or + m_row_1_7$getOrigPC or + m_row_1_8$getOrigPC or + m_row_1_9$getOrigPC or + m_row_1_10$getOrigPC or + m_row_1_11$getOrigPC or + m_row_1_12$getOrigPC or + m_row_1_13$getOrigPC or + m_row_1_14$getOrigPC or + m_row_1_15$getOrigPC or + m_row_1_16$getOrigPC or + m_row_1_17$getOrigPC or + m_row_1_18$getOrigPC or + m_row_1_19$getOrigPC or + m_row_1_20$getOrigPC or + m_row_1_21$getOrigPC or + m_row_1_22$getOrigPC or + m_row_1_23$getOrigPC or + m_row_1_24$getOrigPC or + m_row_1_25$getOrigPC or + m_row_1_26$getOrigPC or + m_row_1_27$getOrigPC or + m_row_1_28$getOrigPC or + m_row_1_29$getOrigPC or + m_row_1_30$getOrigPC or m_row_1_31$getOrigPC) + begin + case (getOrigPC_2_get_x[10:6]) + 5'd0: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_0$getOrigPC; + 5'd1: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_1$getOrigPC; + 5'd2: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_2$getOrigPC; + 5'd3: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_3$getOrigPC; + 5'd4: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_4$getOrigPC; + 5'd5: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_5$getOrigPC; + 5'd6: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_6$getOrigPC; + 5'd7: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_7$getOrigPC; + 5'd8: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_8$getOrigPC; + 5'd9: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_9$getOrigPC; + 5'd10: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_10$getOrigPC; + 5'd11: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_11$getOrigPC; + 5'd12: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_12$getOrigPC; + 5'd13: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_13$getOrigPC; + 5'd14: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_14$getOrigPC; + 5'd15: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_15$getOrigPC; + 5'd16: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_16$getOrigPC; + 5'd17: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_17$getOrigPC; + 5'd18: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_18$getOrigPC; + 5'd19: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_19$getOrigPC; + 5'd20: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_20$getOrigPC; + 5'd21: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_21$getOrigPC; + 5'd22: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_22$getOrigPC; + 5'd23: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_23$getOrigPC; + 5'd24: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_24$getOrigPC; + 5'd25: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_25$getOrigPC; + 5'd26: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_26$getOrigPC; + 5'd27: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_27$getOrigPC; + 5'd28: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_28$getOrigPC; + 5'd29: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_29$getOrigPC; + 5'd30: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_30$getOrigPC; + 5'd31: + SEL_ARR_m_row_1_0_getOrigPC__3539_m_row_1_1_ge_ETC___d13582 = + m_row_1_31$getOrigPC; + endcase + end always@(getOrigPredPC_1_get_x or m_row_1_0$getOrigPredPC or m_row_1_1$getOrigPredPC or @@ -50699,6 +50699,17 @@ module mkReorderBufferSynth(CLK, endcase end always@(virtualWay__h147893 or m_enqEn_0$wget or m_enqEn_1$wget) + begin + case (virtualWay__h147893) + 1'd0: + SEL_ARR_NOT_m_enqEn_0_wget__418_BIT_166_634_63_ETC___d3073 = + !m_enqEn_0$wget[166]; + 1'd1: + SEL_ARR_NOT_m_enqEn_0_wget__418_BIT_166_634_63_ETC___d3073 = + !m_enqEn_1$wget[166]; + endcase + end + always@(virtualWay__h147893 or m_enqEn_0$wget or m_enqEn_1$wget) begin case (virtualWay__h147893) 1'd0: @@ -50720,17 +50731,6 @@ module mkReorderBufferSynth(CLK, m_enqEn_1$wget[97:96] == 2'd1; endcase end - always@(virtualWay__h147893 or m_enqEn_0$wget or m_enqEn_1$wget) - begin - case (virtualWay__h147893) - 1'd0: - SEL_ARR_NOT_m_enqEn_0_wget__418_BIT_166_634_63_ETC___d3073 = - !m_enqEn_0$wget[166]; - 1'd1: - SEL_ARR_NOT_m_enqEn_0_wget__418_BIT_166_634_63_ETC___d3073 = - !m_enqEn_1$wget[166]; - endcase - end always@(virtualWay__h147903 or m_enqEn_0$wget or m_enqEn_1$wget) begin case (virtualWay__h147903) diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationAlu.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationAlu.v index 2274ac1..6484f82 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationAlu.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationAlu.v @@ -312,7 +312,7 @@ module mkReservationStationAlu(CLK, m_valid_0_lat_1$whas, m_valid_10_lat_0$whas, m_valid_10_lat_1$whas, - m_valid_11_dummy_1_0$wget, + m_valid_11_lat_0$whas, m_valid_11_lat_1$whas, m_valid_12_lat_0$whas, m_valid_12_lat_1$whas, @@ -324,8 +324,8 @@ module mkReservationStationAlu(CLK, m_valid_15_lat_1$whas, m_valid_1_lat_0$whas, m_valid_1_lat_1$whas, - m_valid_2_dummy_1_0$whas, m_valid_2_lat_0$whas, + m_valid_2_lat_1$whas, m_valid_3_lat_0$whas, m_valid_3_lat_1$whas, m_valid_4_lat_0$whas, @@ -336,10 +336,10 @@ module mkReservationStationAlu(CLK, m_valid_6_lat_1$whas, m_valid_7_lat_0$whas, m_valid_7_lat_1$whas, - m_valid_8_lat_0$whas, + m_valid_8_dummy_1_0$wget, m_valid_8_lat_1$whas, - m_valid_9_dummy_1_0$whas, - m_valid_9_lat_0$whas; + m_valid_9_lat_0$whas, + m_valid_9_lat_1$whas; // register m_data_0 reg [95 : 0] m_data_0; @@ -1820,27 +1820,27 @@ module mkReservationStationAlu(CLK, MUX_m_valid_10_dummy2_0$write_1__SEL_1, MUX_m_valid_10_dummy2_0$write_1__SEL_2, MUX_m_valid_11_dummy2_0$write_1__SEL_1, - MUX_m_valid_11_lat_0$wset_1__SEL_2, + MUX_m_valid_11_dummy2_0$write_1__SEL_2, MUX_m_valid_12_dummy2_0$write_1__SEL_1, MUX_m_valid_12_dummy2_0$write_1__SEL_2, MUX_m_valid_13_dummy2_0$write_1__SEL_1, MUX_m_valid_13_dummy2_0$write_1__SEL_2, MUX_m_valid_14_dummy2_0$write_1__SEL_1, MUX_m_valid_14_dummy2_0$write_1__SEL_2, + MUX_m_valid_15_dummy2_0$write_1__SEL_1, MUX_m_valid_15_dummy2_0$write_1__SEL_2, - MUX_m_valid_15_lat_0$wset_1__SEL_1, MUX_m_valid_1_dummy2_0$write_1__SEL_1, MUX_m_valid_1_dummy2_0$write_1__SEL_2, + MUX_m_valid_2_dummy2_0$write_1__SEL_1, MUX_m_valid_2_dummy2_0$write_1__SEL_2, - MUX_m_valid_2_lat_0$wset_1__SEL_1, MUX_m_valid_3_dummy2_0$write_1__SEL_1, MUX_m_valid_3_dummy2_0$write_1__SEL_2, + MUX_m_valid_4_dummy2_0$write_1__SEL_1, MUX_m_valid_4_dummy2_0$write_1__SEL_2, - MUX_m_valid_4_lat_0$wset_1__SEL_1, - MUX_m_valid_5_dummy2_0$write_1__SEL_1, MUX_m_valid_5_dummy2_0$write_1__SEL_2, + MUX_m_valid_5_lat_0$wset_1__SEL_1, + MUX_m_valid_6_dummy2_0$write_1__SEL_1, MUX_m_valid_6_dummy2_0$write_1__SEL_2, - MUX_m_valid_6_lat_0$wset_1__SEL_1, MUX_m_valid_7_dummy2_0$write_1__SEL_1, MUX_m_valid_7_dummy2_0$write_1__SEL_2, MUX_m_valid_8_dummy2_0$write_1__SEL_1, @@ -3985,7 +3985,7 @@ module mkReservationStationAlu(CLK, bs__h284160[specUpdate_incorrectSpeculation_kill_tag]) ; assign MUX_m_valid_11_dummy2_0$write_1__SEL_1 = EN_doDispatch && idx__h168545 == 4'd11 ; - assign MUX_m_valid_11_lat_0$wset_1__SEL_2 = + assign MUX_m_valid_11_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h284348[specUpdate_incorrectSpeculation_kill_tag]) ; @@ -4007,48 +4007,48 @@ module mkReservationStationAlu(CLK, EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h284912[specUpdate_incorrectSpeculation_kill_tag]) ; + assign MUX_m_valid_15_dummy2_0$write_1__SEL_1 = + EN_doDispatch && idx__h168545 == 4'd15 ; assign MUX_m_valid_15_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h285088[specUpdate_incorrectSpeculation_kill_tag]) ; - assign MUX_m_valid_15_lat_0$wset_1__SEL_1 = - EN_doDispatch && idx__h168545 == 4'd15 ; assign MUX_m_valid_1_dummy2_0$write_1__SEL_1 = EN_doDispatch && idx__h168545 == 4'd1 ; assign MUX_m_valid_1_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h282468[specUpdate_incorrectSpeculation_kill_tag]) ; + assign MUX_m_valid_2_dummy2_0$write_1__SEL_1 = + EN_doDispatch && idx__h168545 == 4'd2 ; assign MUX_m_valid_2_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h282656[specUpdate_incorrectSpeculation_kill_tag]) ; - assign MUX_m_valid_2_lat_0$wset_1__SEL_1 = - EN_doDispatch && idx__h168545 == 4'd2 ; assign MUX_m_valid_3_dummy2_0$write_1__SEL_1 = EN_doDispatch && idx__h168545 == 4'd3 ; assign MUX_m_valid_3_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h282844[specUpdate_incorrectSpeculation_kill_tag]) ; + assign MUX_m_valid_4_dummy2_0$write_1__SEL_1 = + EN_doDispatch && idx__h168545 == 4'd4 ; assign MUX_m_valid_4_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h283032[specUpdate_incorrectSpeculation_kill_tag]) ; - assign MUX_m_valid_4_lat_0$wset_1__SEL_1 = - EN_doDispatch && idx__h168545 == 4'd4 ; - assign MUX_m_valid_5_dummy2_0$write_1__SEL_1 = - EN_doDispatch && idx__h168545 == 4'd5 ; assign MUX_m_valid_5_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h283220[specUpdate_incorrectSpeculation_kill_tag]) ; + assign MUX_m_valid_5_lat_0$wset_1__SEL_1 = + EN_doDispatch && idx__h168545 == 4'd5 ; + assign MUX_m_valid_6_dummy2_0$write_1__SEL_1 = + EN_doDispatch && idx__h168545 == 4'd6 ; assign MUX_m_valid_6_dummy2_0$write_1__SEL_2 = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h283408[specUpdate_incorrectSpeculation_kill_tag]) ; - assign MUX_m_valid_6_lat_0$wset_1__SEL_1 = - EN_doDispatch && idx__h168545 == 4'd6 ; assign MUX_m_valid_7_dummy2_0$write_1__SEL_1 = EN_doDispatch && idx__h168545 == 4'd7 ; assign MUX_m_valid_7_dummy2_0$write_1__SEL_2 = @@ -4078,45 +4078,45 @@ module mkReservationStationAlu(CLK, MUX_m_valid_1_dummy2_0$write_1__SEL_2 ; assign m_valid_1_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd1 ; assign m_valid_2_lat_0$whas = - MUX_m_valid_2_lat_0$wset_1__SEL_1 || + MUX_m_valid_2_dummy2_0$write_1__SEL_1 || MUX_m_valid_2_dummy2_0$write_1__SEL_2 ; - assign m_valid_2_dummy_1_0$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd2 ; + assign m_valid_2_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd2 ; assign m_valid_3_lat_0$whas = MUX_m_valid_3_dummy2_0$write_1__SEL_1 || MUX_m_valid_3_dummy2_0$write_1__SEL_2 ; assign m_valid_3_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd3 ; assign m_valid_4_lat_0$whas = - MUX_m_valid_4_lat_0$wset_1__SEL_1 || + MUX_m_valid_4_dummy2_0$write_1__SEL_1 || MUX_m_valid_4_dummy2_0$write_1__SEL_2 ; assign m_valid_4_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd4 ; assign m_valid_5_lat_0$whas = - MUX_m_valid_5_dummy2_0$write_1__SEL_1 || + MUX_m_valid_5_lat_0$wset_1__SEL_1 || MUX_m_valid_5_dummy2_0$write_1__SEL_2 ; assign m_valid_5_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd5 ; assign m_valid_6_lat_0$whas = - MUX_m_valid_6_lat_0$wset_1__SEL_1 || + MUX_m_valid_6_dummy2_0$write_1__SEL_1 || MUX_m_valid_6_dummy2_0$write_1__SEL_2 ; assign m_valid_6_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd6 ; assign m_valid_7_lat_0$whas = MUX_m_valid_7_dummy2_0$write_1__SEL_1 || MUX_m_valid_7_dummy2_0$write_1__SEL_2 ; assign m_valid_7_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd7 ; - assign m_valid_8_lat_0$whas = + assign m_valid_8_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd8 ; + assign m_valid_8_dummy_1_0$wget = MUX_m_valid_8_dummy2_0$write_1__SEL_1 || MUX_m_valid_8_dummy2_0$write_1__SEL_2 ; - assign m_valid_8_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd8 ; assign m_valid_9_lat_0$whas = MUX_m_valid_9_dummy2_0$write_1__SEL_1 || MUX_m_valid_9_dummy2_0$write_1__SEL_2 ; - assign m_valid_9_dummy_1_0$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd9 ; + assign m_valid_9_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd9 ; assign m_valid_10_lat_0$whas = MUX_m_valid_10_dummy2_0$write_1__SEL_1 || MUX_m_valid_10_dummy2_0$write_1__SEL_2 ; assign m_valid_10_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd10 ; - assign m_valid_11_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd11 ; - assign m_valid_11_dummy_1_0$wget = + assign m_valid_11_lat_0$whas = MUX_m_valid_11_dummy2_0$write_1__SEL_1 || - MUX_m_valid_11_lat_0$wset_1__SEL_2 ; + MUX_m_valid_11_dummy2_0$write_1__SEL_2 ; + assign m_valid_11_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd11 ; assign m_valid_12_lat_0$whas = MUX_m_valid_12_dummy2_0$write_1__SEL_1 || MUX_m_valid_12_dummy2_0$write_1__SEL_2 ; @@ -4130,7 +4130,7 @@ module mkReservationStationAlu(CLK, MUX_m_valid_14_dummy2_0$write_1__SEL_2 ; assign m_valid_14_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd14 ; assign m_valid_15_lat_0$whas = - MUX_m_valid_15_lat_0$wset_1__SEL_1 || + MUX_m_valid_15_dummy2_0$write_1__SEL_1 || MUX_m_valid_15_dummy2_0$write_1__SEL_2 ; assign m_valid_15_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd15 ; assign m_regs_ready_0_lat_0$wget = @@ -5664,7 +5664,7 @@ module mkReservationStationAlu(CLK, // register m_data_2 assign m_data_2$D_IN = m_data_0$D_IN ; - assign m_data_2$EN = m_valid_2_dummy_1_0$whas ; + assign m_data_2$EN = m_valid_2_lat_1$whas ; // register m_data_3 assign m_data_3$D_IN = m_data_0$D_IN ; @@ -5692,7 +5692,7 @@ module mkReservationStationAlu(CLK, // register m_data_9 assign m_data_9$D_IN = m_data_0$D_IN ; - assign m_data_9$EN = m_valid_9_dummy_1_0$whas ; + assign m_data_9$EN = m_valid_9_lat_1$whas ; // register m_regs_0 assign m_regs_0$D_IN = enq_x[65:33] ; @@ -5728,7 +5728,7 @@ module mkReservationStationAlu(CLK, // register m_regs_2 assign m_regs_2$D_IN = enq_x[65:33] ; - assign m_regs_2$EN = m_valid_2_dummy_1_0$whas ; + assign m_regs_2$EN = m_valid_2_lat_1$whas ; // register m_regs_3 assign m_regs_3$D_IN = enq_x[65:33] ; @@ -5756,7 +5756,7 @@ module mkReservationStationAlu(CLK, // register m_regs_9 assign m_regs_9$D_IN = enq_x[65:33] ; - assign m_regs_9$EN = m_valid_9_dummy_1_0$whas ; + assign m_regs_9$EN = m_valid_9_lat_1$whas ; // register m_regs_ready_0_rl assign m_regs_ready_0_rl$D_IN = @@ -5832,7 +5832,7 @@ module mkReservationStationAlu(CLK, // register m_regs_ready_2_rl assign m_regs_ready_2_rl$D_IN = - m_valid_2_dummy_1_0$whas ? + m_valid_2_lat_1$whas ? enq_x[3:0] : (EN_setRegReady_4_put ? m_regs_ready_2_lat_4$wget : @@ -5895,7 +5895,7 @@ module mkReservationStationAlu(CLK, // register m_regs_ready_9_rl assign m_regs_ready_9_rl$D_IN = - m_valid_9_dummy_1_0$whas ? + m_valid_9_lat_1$whas ? enq_x[3:0] : (EN_setRegReady_4_put ? m_regs_ready_9_lat_4$wget : @@ -6048,7 +6048,7 @@ module mkReservationStationAlu(CLK, // register m_spec_tag_2 assign m_spec_tag_2$D_IN = enq_x[8:4] ; - assign m_spec_tag_2$EN = m_valid_2_dummy_1_0$whas ; + assign m_spec_tag_2$EN = m_valid_2_lat_1$whas ; // register m_spec_tag_3 assign m_spec_tag_3$D_IN = enq_x[8:4] ; @@ -6076,7 +6076,7 @@ module mkReservationStationAlu(CLK, // register m_spec_tag_9 assign m_spec_tag_9$D_IN = enq_x[8:4] ; - assign m_spec_tag_9$EN = m_valid_9_dummy_1_0$whas ; + assign m_spec_tag_9$EN = m_valid_9_lat_1$whas ; // register m_tag_0 assign m_tag_0$D_IN = enq_x[32:21] ; @@ -6112,7 +6112,7 @@ module mkReservationStationAlu(CLK, // register m_tag_2 assign m_tag_2$D_IN = enq_x[32:21] ; - assign m_tag_2$EN = m_valid_2_dummy_1_0$whas ; + assign m_tag_2$EN = m_valid_2_lat_1$whas ; // register m_tag_3 assign m_tag_3$D_IN = enq_x[32:21] ; @@ -6140,7 +6140,7 @@ module mkReservationStationAlu(CLK, // register m_tag_9 assign m_tag_9$D_IN = enq_x[32:21] ; - assign m_tag_9$EN = m_valid_9_dummy_1_0$whas ; + assign m_tag_9$EN = m_valid_9_lat_1$whas ; // register m_validEntryCount assign m_validEntryCount$D_IN = @@ -6163,7 +6163,7 @@ module mkReservationStationAlu(CLK, // register m_valid_11_rl assign m_valid_11_rl$D_IN = m_valid_11_lat_1$whas || - (m_valid_11_dummy_1_0$wget ? 1'd0 : m_valid_11_rl) ; + (m_valid_11_lat_0$whas ? 1'd0 : m_valid_11_rl) ; assign m_valid_11_rl$EN = 1'd1 ; // register m_valid_12_rl @@ -6198,7 +6198,7 @@ module mkReservationStationAlu(CLK, // register m_valid_2_rl assign m_valid_2_rl$D_IN = - m_valid_2_dummy_1_0$whas || + m_valid_2_lat_1$whas || (m_valid_2_lat_0$whas ? 1'd0 : m_valid_2_rl) ; assign m_valid_2_rl$EN = 1'd1 ; @@ -6235,12 +6235,12 @@ module mkReservationStationAlu(CLK, // register m_valid_8_rl assign m_valid_8_rl$D_IN = m_valid_8_lat_1$whas || - (m_valid_8_lat_0$whas ? 1'd0 : m_valid_8_rl) ; + (m_valid_8_dummy_1_0$wget ? 1'd0 : m_valid_8_rl) ; assign m_valid_8_rl$EN = 1'd1 ; // register m_valid_9_rl assign m_valid_9_rl$D_IN = - m_valid_9_dummy_1_0$whas || + m_valid_9_lat_1$whas || (m_valid_9_lat_0$whas ? 1'd0 : m_valid_9_rl) ; assign m_valid_9_rl$EN = 1'd1 ; @@ -6458,7 +6458,7 @@ module mkReservationStationAlu(CLK, // submodule m_regs_ready_2_dummy2_5 assign m_regs_ready_2_dummy2_5$D_IN = 1'd1 ; - assign m_regs_ready_2_dummy2_5$EN = m_valid_2_dummy_1_0$whas ; + assign m_regs_ready_2_dummy2_5$EN = m_valid_2_lat_1$whas ; // submodule m_regs_ready_3_dummy2_0 assign m_regs_ready_3_dummy2_0$D_IN = 1'd1 ; @@ -6626,7 +6626,7 @@ module mkReservationStationAlu(CLK, // submodule m_regs_ready_9_dummy2_5 assign m_regs_ready_9_dummy2_5$D_IN = 1'd1 ; - assign m_regs_ready_9_dummy2_5$EN = m_valid_9_dummy_1_0$whas ; + assign m_regs_ready_9_dummy2_5$EN = m_valid_9_lat_1$whas ; // submodule m_spec_bits_0_dummy2_0 assign m_spec_bits_0_dummy2_0$D_IN = 1'd1 ; @@ -6694,7 +6694,7 @@ module mkReservationStationAlu(CLK, // submodule m_spec_bits_2_dummy2_0 assign m_spec_bits_2_dummy2_0$D_IN = 1'd1 ; - assign m_spec_bits_2_dummy2_0$EN = m_valid_2_dummy_1_0$whas ; + assign m_spec_bits_2_dummy2_0$EN = m_valid_2_lat_1$whas ; // submodule m_spec_bits_2_dummy2_1 assign m_spec_bits_2_dummy2_1$D_IN = 1'd1 ; @@ -6750,7 +6750,7 @@ module mkReservationStationAlu(CLK, // submodule m_spec_bits_9_dummy2_0 assign m_spec_bits_9_dummy2_0$D_IN = 1'd1 ; - assign m_spec_bits_9_dummy2_0$EN = m_valid_9_dummy_1_0$whas ; + assign m_spec_bits_9_dummy2_0$EN = m_valid_9_lat_1$whas ; // submodule m_spec_bits_9_dummy2_1 assign m_spec_bits_9_dummy2_1$D_IN = 1'd1 ; @@ -6780,7 +6780,7 @@ module mkReservationStationAlu(CLK, assign m_valid_11_dummy2_0$D_IN = 1'd1 ; assign m_valid_11_dummy2_0$EN = EN_doDispatch && idx__h168545 == 4'd11 || - MUX_m_valid_11_lat_0$wset_1__SEL_2 ; + MUX_m_valid_11_dummy2_0$write_1__SEL_2 ; // submodule m_valid_11_dummy2_1 assign m_valid_11_dummy2_1$D_IN = 1'd1 ; @@ -6844,7 +6844,7 @@ module mkReservationStationAlu(CLK, // submodule m_valid_2_dummy2_1 assign m_valid_2_dummy2_1$D_IN = 1'd1 ; - assign m_valid_2_dummy2_1$EN = m_valid_2_dummy_1_0$whas ; + assign m_valid_2_dummy2_1$EN = m_valid_2_lat_1$whas ; // submodule m_valid_3_dummy2_0 assign m_valid_3_dummy2_0$D_IN = 1'd1 ; @@ -6914,7 +6914,7 @@ module mkReservationStationAlu(CLK, // submodule m_valid_9_dummy2_1 assign m_valid_9_dummy2_1$D_IN = 1'd1 ; - assign m_valid_9_dummy2_1$EN = m_valid_9_dummy_1_0$whas ; + assign m_valid_9_dummy2_1$EN = m_valid_9_lat_1$whas ; // remaining internal signals assign IF_NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT__ETC___d1438 = @@ -8141,7 +8141,7 @@ module mkReservationStationAlu(CLK, assign IF_m_spec_bits_1_lat_0_whas__22_THEN_m_spec_bi_ETC___d125 = m_valid_1_lat_1$whas ? enq_x[20:9] : m_spec_bits_1_rl ; assign IF_m_spec_bits_2_lat_0_whas__29_THEN_m_spec_bi_ETC___d132 = - m_valid_2_dummy_1_0$whas ? enq_x[20:9] : m_spec_bits_2_rl ; + m_valid_2_lat_1$whas ? enq_x[20:9] : m_spec_bits_2_rl ; assign IF_m_spec_bits_3_lat_0_whas__36_THEN_m_spec_bi_ETC___d139 = m_valid_3_lat_1$whas ? enq_x[20:9] : m_spec_bits_3_rl ; assign IF_m_spec_bits_4_lat_0_whas__43_THEN_m_spec_bi_ETC___d146 = @@ -8155,7 +8155,7 @@ module mkReservationStationAlu(CLK, assign IF_m_spec_bits_8_lat_0_whas__71_THEN_m_spec_bi_ETC___d174 = m_valid_8_lat_1$whas ? enq_x[20:9] : m_spec_bits_8_rl ; assign IF_m_spec_bits_9_lat_0_whas__78_THEN_m_spec_bi_ETC___d181 = - m_valid_9_dummy_1_0$whas ? enq_x[20:9] : m_spec_bits_9_rl ; + m_valid_9_lat_1$whas ? enq_x[20:9] : m_spec_bits_9_rl ; assign IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 = (m_tag_0[5:0] < x__read__h100327) ? { 1'd0, m_tag_0[5:0] } + 7'd64 : @@ -9734,6 +9734,1940 @@ module mkReservationStationAlu(CLK, assign upd__h34187 = n__read__h292286 & specUpdate_correctSpeculation_mask ; assign upd__h35116 = n__read__h292714 & specUpdate_correctSpeculation_mask ; assign x__read__h100327 = EN_setRobEnqTime ? setRobEnqTime_t : 6'd0 ; + always@(enq_x) + begin + case (enq_x[139:137]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1 = + enq_x[139:137]; + default: CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1 = 3'd7; + endcase + end + always@(enq_x or CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1) + begin + case (enq_x[156:154]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_enq_x_BITS_156_TO_154_0_enq_x_BITS_156_TO_ETC__q2 = + enq_x[156:136]; + 3'd4: + CASE_enq_x_BITS_156_TO_154_0_enq_x_BITS_156_TO_ETC__q2 = + { enq_x[156:154], + 9'h0AA, + enq_x[144:140], + CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1, + enq_x[136] }; + default: CASE_enq_x_BITS_156_TO_154_0_enq_x_BITS_156_TO_ETC__q2 = + 21'd1485482; + endcase + end + always@(enq_x) + begin + case (enq_x[134:123]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd2048, + 12'd2049, + 12'd2816, + 12'd2818, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_enq_x_BITS_134_TO_123_1_enq_x_BITS_134_TO_ETC__q3 = + enq_x[134:123]; + default: CASE_enq_x_BITS_134_TO_123_1_enq_x_BITS_134_TO_ETC__q3 = + 12'd2303; + endcase + end + always@(a__h169325 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (a__h169325) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(b__h169326 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (b__h169326) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(b__h169326 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (b__h169326) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(a__h169325 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (a__h169325) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(a__h173190 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (a__h173190) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(b__h173191 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (b__h173191) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(b__h173191 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (b__h173191) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(a__h173190 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (a__h173190) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(a__h169313 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (a__h169313) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(b__h169314 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (b__h169314) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(b__h169314 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (b__h169314) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(a__h169313 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (a__h169313) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(a__h173706 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (a__h173706) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(b__h173707 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (b__h173707) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(b__h173707 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (b__h173707) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(a__h173706 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (a__h173706) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(a__h174099 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (a__h174099) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(b__h174100 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (b__h174100) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(b__h174100 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (b__h174100) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(a__h174099 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (a__h174099) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(a__h173694 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (a__h173694) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(b__h173695 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (b__h173695) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(b__h173695 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (b__h173695) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(a__h173694 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (a__h173694) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(a__h169295 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (a__h169295) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end + always@(b__h169296 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (b__h169296) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end + always@(b__h169296 or + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + begin + case (b__h169296) + 4'd0: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; + 4'd1: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; + 4'd2: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; + 4'd3: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; + 4'd4: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; + 4'd5: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; + 4'd6: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; + 4'd7: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; + 4'd8: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; + 4'd9: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; + 4'd10: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; + 4'd11: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; + 4'd12: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; + 4'd13: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; + 4'd14: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; + 4'd15: + SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = + IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; + endcase + end always@(m_data_0) begin case (m_data_0[73:71]) @@ -9744,6 +11678,75 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end + always@(a__h169295 or + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) + begin + case (a__h169295) + 4'd0: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; + 4'd1: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; + 4'd2: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; + 4'd3: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; + 4'd4: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; + 4'd5: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; + 4'd6: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; + 4'd7: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; + 4'd8: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; + 4'd9: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; + 4'd10: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; + 4'd11: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; + 4'd12: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; + 4'd13: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; + 4'd14: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; + 4'd15: + SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = + NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + endcase + end always@(m_data_1) begin case (m_data_1[73:71]) @@ -9764,16 +11767,6 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end - always@(m_data_3) - begin - case (m_data_3[73:71]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 = - m_data_3[73:71]; - default: IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 = - 3'd5; - endcase - end always@(m_data_4) begin case (m_data_4[73:71]) @@ -9784,6 +11777,16 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end + always@(m_data_3) + begin + case (m_data_3[73:71]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 = + m_data_3[73:71]; + default: IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 = + 3'd5; + endcase + end always@(m_data_5) begin case (m_data_5[73:71]) @@ -9804,16 +11807,6 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end - always@(m_data_8) - begin - case (m_data_8[73:71]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 = - m_data_8[73:71]; - default: IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 = - 3'd5; - endcase - end always@(m_data_7) begin case (m_data_7[73:71]) @@ -9824,13 +11817,13 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end - always@(m_data_9) + always@(m_data_8) begin - case (m_data_9[73:71]) + case (m_data_8[73:71]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 = - m_data_9[73:71]; - default: IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 = + IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 = + m_data_8[73:71]; + default: IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 = 3'd5; endcase end @@ -9844,6 +11837,16 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end + always@(m_data_9) + begin + case (m_data_9[73:71]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 = + m_data_9[73:71]; + default: IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 = + 3'd5; + endcase + end always@(m_data_11) begin case (m_data_11[73:71]) @@ -9854,16 +11857,6 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end - always@(m_data_12) - begin - case (m_data_12[73:71]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 = - m_data_12[73:71]; - default: IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 = - 3'd5; - endcase - end always@(m_data_13) begin case (m_data_13[73:71]) @@ -9874,13 +11867,13 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end - always@(m_data_15) + always@(m_data_12) begin - case (m_data_15[73:71]) + case (m_data_12[73:71]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109 = - m_data_15[73:71]; - default: IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109 = + IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 = + m_data_12[73:71]; + default: IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 = 3'd5; endcase end @@ -9894,1936 +11887,14 @@ module mkReservationStationAlu(CLK, 3'd5; endcase end - always@(a__h169325 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) + always@(m_data_15) begin - case (a__h169325) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1400 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(b__h169326 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (b__h169326) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1401 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(a__h173190 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (a__h173190) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1417 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(b__h173191 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (b__h173191) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1418 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(a__h173706 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (a__h173706) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1441 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(b__h173707 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (b__h173707) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1442 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(a__h174099 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (a__h174099) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1458 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(b__h169326 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (b__h169326) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1326 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(a__h169325 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (a__h169325) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1309 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(b__h173191 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (b__h173191) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1416 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(a__h173190 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (a__h173190) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1411 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(a__h169313 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (a__h169313) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1424 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(b__h169314 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (b__h169314) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1423 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(b__h169314 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (b__h169314) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1425 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(a__h169313 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (a__h169313) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1406 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(b__h173707 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (b__h173707) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1440 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(a__h173706 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (a__h173706) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1435 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(b__h174100 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (b__h174100) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1457 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(b__h174100 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (b__h174100) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1459 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(a__h174099 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (a__h174099) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1452 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(a__h173694 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (a__h173694) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1465 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(b__h173695 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (b__h173695) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1464 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(b__h173695 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (b__h173695) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1466 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(a__h173694 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (a__h173694) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1447 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(a__h169295 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (a__h169295) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1472 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(b__h169296 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (b__h169296) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1471 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; - endcase - end - always@(b__h169296 or - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298 or - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304 or - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315 or - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321 or - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332 or - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338 or - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344 or - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350 or - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356 or - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362 or - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368 or - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374 or - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380 or - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386 or - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392 or - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398) - begin - case (b__h169296) - 4'd0: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF_m_robEnq_ETC___d1298; - 4'd1: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_1_299_BITS_5_TO_0_300_ULT_IF_m_robEnq_ETC___d1304; - 4'd2: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_2_310_BITS_5_TO_0_311_ULT_IF_m_robEnq_ETC___d1315; - 4'd3: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_3_316_BITS_5_TO_0_317_ULT_IF_m_robEnq_ETC___d1321; - 4'd4: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_4_327_BITS_5_TO_0_328_ULT_IF_m_robEnq_ETC___d1332; - 4'd5: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_5_333_BITS_5_TO_0_334_ULT_IF_m_robEnq_ETC___d1338; - 4'd6: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_6_339_BITS_5_TO_0_340_ULT_IF_m_robEnq_ETC___d1344; - 4'd7: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_7_345_BITS_5_TO_0_346_ULT_IF_m_robEnq_ETC___d1350; - 4'd8: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_8_351_BITS_5_TO_0_352_ULT_IF_m_robEnq_ETC___d1356; - 4'd9: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_9_357_BITS_5_TO_0_358_ULT_IF_m_robEnq_ETC___d1362; - 4'd10: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_10_363_BITS_5_TO_0_364_ULT_IF_m_robEn_ETC___d1368; - 4'd11: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_11_369_BITS_5_TO_0_370_ULT_IF_m_robEn_ETC___d1374; - 4'd12: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_12_375_BITS_5_TO_0_376_ULT_IF_m_robEn_ETC___d1380; - 4'd13: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_13_381_BITS_5_TO_0_382_ULT_IF_m_robEn_ETC___d1386; - 4'd14: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_14_387_BITS_5_TO_0_388_ULT_IF_m_robEn_ETC___d1392; - 4'd15: - SEL_ARR_IF_m_tag_0_290_BITS_5_TO_0_291_ULT_IF__ETC___d1473 = - IF_m_tag_15_393_BITS_5_TO_0_394_ULT_IF_m_robEn_ETC___d1398; - endcase - end - always@(a__h169295 or - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243 or - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246 or - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249 or - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252 or - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255 or - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258 or - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261 or - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264 or - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267 or - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270 or - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273 or - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276 or - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279 or - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282 or - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285 or - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288) - begin - case (a__h169295) - 4'd0: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_0_dummy2_0_read__29_28_OR_NOT_m_va_ETC___d1243; - 4'd1: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_1_dummy2_0_read__34_33_OR_NOT_m_va_ETC___d1246; - 4'd2: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_2_dummy2_0_read__40_39_OR_NOT_m_va_ETC___d1249; - 4'd3: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_3_dummy2_0_read__45_44_OR_NOT_m_va_ETC___d1252; - 4'd4: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_4_dummy2_0_read__52_51_OR_NOT_m_va_ETC___d1255; - 4'd5: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_5_dummy2_0_read__57_56_OR_NOT_m_va_ETC___d1258; - 4'd6: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_6_dummy2_0_read__63_62_OR_NOT_m_va_ETC___d1261; - 4'd7: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_7_dummy2_0_read__68_67_OR_NOT_m_va_ETC___d1264; - 4'd8: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_8_dummy2_0_read__76_75_OR_NOT_m_va_ETC___d1267; - 4'd9: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_9_dummy2_0_read__81_80_OR_NOT_m_va_ETC___d1270; - 4'd10: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_10_dummy2_0_read__87_86_OR_NOT_m_v_ETC___d1273; - 4'd11: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_11_dummy2_0_read__92_91_OR_NOT_m_v_ETC___d1276; - 4'd12: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_12_dummy2_0_read__99_98_OR_NOT_m_v_ETC___d1279; - 4'd13: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_13_dummy2_0_read__04_003_OR_NOT_m__ETC___d1282; - 4'd14: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_14_dummy2_0_read__10_009_OR_NOT_m__ETC___d1285; - 4'd15: - SEL_ARR_NOT_m_valid_0_dummy2_0_read__29_28_OR__ETC___d1430 = - NOT_m_valid_15_dummy2_0_read__15_014_OR_NOT_m__ETC___d1288; + case (m_data_15[73:71]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109 = + m_data_15[73:71]; + default: IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109 = + 3'd5; endcase end always@(idx__h168545 or @@ -12166,6 +12237,91 @@ module mkReservationStationAlu(CLK, 3'd1; endcase end + always@(idx__h168545 or + IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_920_OR__ETC___d1929 or + IF_m_data_1_210_BITS_73_TO_71_931_EQ_0_932_OR__ETC___d1941 or + IF_m_data_2_212_BITS_73_TO_71_943_EQ_0_944_OR__ETC___d1953 or + IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 or + IF_m_data_4_216_BITS_73_TO_71_967_EQ_0_968_OR__ETC___d1977 or + IF_m_data_5_218_BITS_73_TO_71_979_EQ_0_980_OR__ETC___d1989 or + IF_m_data_6_220_BITS_73_TO_71_991_EQ_0_992_OR__ETC___d2001 or + IF_m_data_7_222_BITS_73_TO_71_003_EQ_0_004_OR__ETC___d2013 or + IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 or + IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 or + IF_m_data_10_228_BITS_73_TO_71_039_EQ_0_040_OR_ETC___d2049 or + IF_m_data_11_230_BITS_73_TO_71_051_EQ_0_052_OR_ETC___d2061 or + IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 or + IF_m_data_13_234_BITS_73_TO_71_075_EQ_0_076_OR_ETC___d2085 or + IF_m_data_14_236_BITS_73_TO_71_087_EQ_0_088_OR_ETC___d2097 or + IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_920_OR__ETC___d1929 == + 3'd0; + 4'd1: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_1_210_BITS_73_TO_71_931_EQ_0_932_OR__ETC___d1941 == + 3'd0; + 4'd2: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_2_212_BITS_73_TO_71_943_EQ_0_944_OR__ETC___d1953 == + 3'd0; + 4'd3: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 == + 3'd0; + 4'd4: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_4_216_BITS_73_TO_71_967_EQ_0_968_OR__ETC___d1977 == + 3'd0; + 4'd5: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_5_218_BITS_73_TO_71_979_EQ_0_980_OR__ETC___d1989 == + 3'd0; + 4'd6: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_6_220_BITS_73_TO_71_991_EQ_0_992_OR__ETC___d2001 == + 3'd0; + 4'd7: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_7_222_BITS_73_TO_71_003_EQ_0_004_OR__ETC___d2013 == + 3'd0; + 4'd8: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 == + 3'd0; + 4'd9: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 == + 3'd0; + 4'd10: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_10_228_BITS_73_TO_71_039_EQ_0_040_OR_ETC___d2049 == + 3'd0; + 4'd11: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_11_230_BITS_73_TO_71_051_EQ_0_052_OR_ETC___d2061 == + 3'd0; + 4'd12: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 == + 3'd0; + 4'd13: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_13_234_BITS_73_TO_71_075_EQ_0_076_OR_ETC___d2085 == + 3'd0; + 4'd14: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_14_236_BITS_73_TO_71_087_EQ_0_088_OR_ETC___d2097 == + 3'd0; + 4'd15: + SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = + IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109 == + 3'd0; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -12232,88 +12388,68 @@ module mkReservationStationAlu(CLK, endcase end always@(idx__h168545 or - IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_920_OR__ETC___d1929 or - IF_m_data_1_210_BITS_73_TO_71_931_EQ_0_932_OR__ETC___d1941 or - IF_m_data_2_212_BITS_73_TO_71_943_EQ_0_944_OR__ETC___d1953 or - IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 or - IF_m_data_4_216_BITS_73_TO_71_967_EQ_0_968_OR__ETC___d1977 or - IF_m_data_5_218_BITS_73_TO_71_979_EQ_0_980_OR__ETC___d1989 or - IF_m_data_6_220_BITS_73_TO_71_991_EQ_0_992_OR__ETC___d2001 or - IF_m_data_7_222_BITS_73_TO_71_003_EQ_0_004_OR__ETC___d2013 or - IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 or - IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 or - IF_m_data_10_228_BITS_73_TO_71_039_EQ_0_040_OR_ETC___d2049 or - IF_m_data_11_230_BITS_73_TO_71_051_EQ_0_052_OR_ETC___d2061 or - IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 or - IF_m_data_13_234_BITS_73_TO_71_075_EQ_0_076_OR_ETC___d2085 or - IF_m_data_14_236_BITS_73_TO_71_087_EQ_0_088_OR_ETC___d2097 or - IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109) + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) begin case (idx__h168545) 4'd0: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_920_OR__ETC___d1929 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_0[90:88] == 3'd3; 4'd1: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_1_210_BITS_73_TO_71_931_EQ_0_932_OR__ETC___d1941 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_1[90:88] == 3'd3; 4'd2: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_2_212_BITS_73_TO_71_943_EQ_0_944_OR__ETC___d1953 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_2[90:88] == 3'd3; 4'd3: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_3_214_BITS_73_TO_71_955_EQ_0_956_OR__ETC___d1965 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_3[90:88] == 3'd3; 4'd4: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_4_216_BITS_73_TO_71_967_EQ_0_968_OR__ETC___d1977 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_4[90:88] == 3'd3; 4'd5: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_5_218_BITS_73_TO_71_979_EQ_0_980_OR__ETC___d1989 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_5[90:88] == 3'd3; 4'd6: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_6_220_BITS_73_TO_71_991_EQ_0_992_OR__ETC___d2001 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_6[90:88] == 3'd3; 4'd7: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_7_222_BITS_73_TO_71_003_EQ_0_004_OR__ETC___d2013 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_7[90:88] == 3'd3; 4'd8: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_8_224_BITS_73_TO_71_015_EQ_0_016_OR__ETC___d2025 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_8[90:88] == 3'd3; 4'd9: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_9_226_BITS_73_TO_71_027_EQ_0_028_OR__ETC___d2037 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_9[90:88] == 3'd3; 4'd10: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_10_228_BITS_73_TO_71_039_EQ_0_040_OR_ETC___d2049 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_10[90:88] == 3'd3; 4'd11: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_11_230_BITS_73_TO_71_051_EQ_0_052_OR_ETC___d2061 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_11[90:88] == 3'd3; 4'd12: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_12_232_BITS_73_TO_71_063_EQ_0_064_OR_ETC___d2073 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_12[90:88] == 3'd3; 4'd13: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_13_234_BITS_73_TO_71_075_EQ_0_076_OR_ETC___d2085 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_13[90:88] == 3'd3; 4'd14: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_14_236_BITS_73_TO_71_087_EQ_0_088_OR_ETC___d2097 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_14[90:88] == 3'd3; 4'd15: - SEL_ARR_IF_m_data_0_208_BITS_73_TO_71_919_EQ_0_ETC___d2112 = - IF_m_data_15_238_BITS_73_TO_71_099_EQ_0_100_OR_ETC___d2109 == - 3'd0; + SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = + m_data_15[90:88] == 3'd3; endcase end always@(idx__h168545 or @@ -12381,71 +12517,6 @@ module mkReservationStationAlu(CLK, m_data_15[90:88] == 3'd4; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_0[90:88] == 3'd3; - 4'd1: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_1[90:88] == 3'd3; - 4'd2: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_2[90:88] == 3'd3; - 4'd3: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_3[90:88] == 3'd3; - 4'd4: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_4[90:88] == 3'd3; - 4'd5: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_5[90:88] == 3'd3; - 4'd6: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_6[90:88] == 3'd3; - 4'd7: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_7[90:88] == 3'd3; - 4'd8: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_8[90:88] == 3'd3; - 4'd9: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_9[90:88] == 3'd3; - 4'd10: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_10[90:88] == 3'd3; - 4'd11: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_11[90:88] == 3'd3; - 4'd12: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_12[90:88] == 3'd3; - 4'd13: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_13[90:88] == 3'd3; - 4'd14: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_14[90:88] == 3'd3; - 4'd15: - SEL_ARR_m_data_0_208_BITS_90_TO_88_479_EQ_3_82_ETC___d1844 = - m_data_15[90:88] == 3'd3; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -12641,71 +12712,6 @@ module mkReservationStationAlu(CLK, m_data_15[90:88] == 3'd0; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_0[68:57] == 12'd3860; - 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_1[68:57] == 12'd3860; - 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_2[68:57] == 12'd3860; - 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_3[68:57] == 12'd3860; - 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_4[68:57] == 12'd3860; - 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_5[68:57] == 12'd3860; - 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_6[68:57] == 12'd3860; - 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_7[68:57] == 12'd3860; - 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_8[68:57] == 12'd3860; - 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_9[68:57] == 12'd3860; - 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_10[68:57] == 12'd3860; - 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_11[68:57] == 12'd3860; - 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_12[68:57] == 12'd3860; - 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_13[68:57] == 12'd3860; - 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_14[68:57] == 12'd3860; - 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = - m_data_15[68:57] == 12'd3860; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -12787,53 +12793,53 @@ module mkReservationStationAlu(CLK, begin case (idx__h168545) 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_0[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_0[68:57] == 12'd3860; 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_1[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_1[68:57] == 12'd3860; 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_2[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_2[68:57] == 12'd3860; 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_3[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_3[68:57] == 12'd3860; 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_4[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_4[68:57] == 12'd3860; 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_5[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_5[68:57] == 12'd3860; 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_6[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_6[68:57] == 12'd3860; 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_7[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_7[68:57] == 12'd3860; 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_8[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_8[68:57] == 12'd3860; 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_9[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_9[68:57] == 12'd3860; 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_10[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_10[68:57] == 12'd3860; 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_11[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_11[68:57] == 12'd3860; 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_12[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_12[68:57] == 12'd3860; 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_13[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_13[68:57] == 12'd3860; 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_14[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_14[68:57] == 12'd3860; 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = - m_data_15[68:57] == 12'd3859; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3860_ETC___d2895 = + m_data_15[68:57] == 12'd3860; endcase end always@(idx__h168545 or @@ -12901,6 +12907,71 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd3858; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_0[68:57] == 12'd3859; + 4'd1: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_1[68:57] == 12'd3859; + 4'd2: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_2[68:57] == 12'd3859; + 4'd3: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_3[68:57] == 12'd3859; + 4'd4: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_4[68:57] == 12'd3859; + 4'd5: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_5[68:57] == 12'd3859; + 4'd6: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_6[68:57] == 12'd3859; + 4'd7: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_7[68:57] == 12'd3859; + 4'd8: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_8[68:57] == 12'd3859; + 4'd9: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_9[68:57] == 12'd3859; + 4'd10: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_10[68:57] == 12'd3859; + 4'd11: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_11[68:57] == 12'd3859; + 4'd12: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_12[68:57] == 12'd3859; + 4'd13: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_13[68:57] == 12'd3859; + 4'd14: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_14[68:57] == 12'd3859; + 4'd15: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3859_ETC___d2877 = + m_data_15[68:57] == 12'd3859; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -13161,71 +13232,6 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd836; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_0[68:57] == 12'd835; - 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_1[68:57] == 12'd835; - 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_2[68:57] == 12'd835; - 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_3[68:57] == 12'd835; - 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_4[68:57] == 12'd835; - 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_5[68:57] == 12'd835; - 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_6[68:57] == 12'd835; - 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_7[68:57] == 12'd835; - 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_8[68:57] == 12'd835; - 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_9[68:57] == 12'd835; - 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_10[68:57] == 12'd835; - 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_11[68:57] == 12'd835; - 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_12[68:57] == 12'd835; - 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_13[68:57] == 12'd835; - 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_14[68:57] == 12'd835; - 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = - m_data_15[68:57] == 12'd835; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -13291,6 +13297,71 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd834; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_0[68:57] == 12'd835; + 4'd1: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_1[68:57] == 12'd835; + 4'd2: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_2[68:57] == 12'd835; + 4'd3: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_3[68:57] == 12'd835; + 4'd4: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_4[68:57] == 12'd835; + 4'd5: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_5[68:57] == 12'd835; + 4'd6: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_6[68:57] == 12'd835; + 4'd7: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_7[68:57] == 12'd835; + 4'd8: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_8[68:57] == 12'd835; + 4'd9: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_9[68:57] == 12'd835; + 4'd10: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_10[68:57] == 12'd835; + 4'd11: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_11[68:57] == 12'd835; + 4'd12: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_12[68:57] == 12'd835; + 4'd13: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_13[68:57] == 12'd835; + 4'd14: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_14[68:57] == 12'd835; + 4'd15: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_835__ETC___d2769 = + m_data_15[68:57] == 12'd835; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -13486,71 +13557,6 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd774; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_0[68:57] == 12'd772; - 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_1[68:57] == 12'd772; - 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_2[68:57] == 12'd772; - 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_3[68:57] == 12'd772; - 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_4[68:57] == 12'd772; - 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_5[68:57] == 12'd772; - 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_6[68:57] == 12'd772; - 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_7[68:57] == 12'd772; - 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_8[68:57] == 12'd772; - 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_9[68:57] == 12'd772; - 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_10[68:57] == 12'd772; - 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_11[68:57] == 12'd772; - 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_12[68:57] == 12'd772; - 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_13[68:57] == 12'd772; - 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_14[68:57] == 12'd772; - 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = - m_data_15[68:57] == 12'd772; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -13632,53 +13638,53 @@ module mkReservationStationAlu(CLK, begin case (idx__h168545) 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_0[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_0[68:57] == 12'd772; 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_1[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_1[68:57] == 12'd772; 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_2[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_2[68:57] == 12'd772; 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_3[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_3[68:57] == 12'd772; 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_4[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_4[68:57] == 12'd772; 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_5[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_5[68:57] == 12'd772; 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_6[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_6[68:57] == 12'd772; 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_7[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_7[68:57] == 12'd772; 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_8[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_8[68:57] == 12'd772; 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_9[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_9[68:57] == 12'd772; 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_10[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_10[68:57] == 12'd772; 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_11[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_11[68:57] == 12'd772; 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_12[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_12[68:57] == 12'd772; 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_13[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_13[68:57] == 12'd772; 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_14[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_14[68:57] == 12'd772; 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = - m_data_15[68:57] == 12'd771; + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_772__ETC___d2661 = + m_data_15[68:57] == 12'd772; endcase end always@(idx__h168545 or @@ -13746,6 +13752,71 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd770; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_0[68:57] == 12'd771; + 4'd1: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_1[68:57] == 12'd771; + 4'd2: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_2[68:57] == 12'd771; + 4'd3: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_3[68:57] == 12'd771; + 4'd4: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_4[68:57] == 12'd771; + 4'd5: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_5[68:57] == 12'd771; + 4'd6: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_6[68:57] == 12'd771; + 4'd7: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_7[68:57] == 12'd771; + 4'd8: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_8[68:57] == 12'd771; + 4'd9: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_9[68:57] == 12'd771; + 4'd10: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_10[68:57] == 12'd771; + 4'd11: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_11[68:57] == 12'd771; + 4'd12: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_12[68:57] == 12'd771; + 4'd13: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_13[68:57] == 12'd771; + 4'd14: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_14[68:57] == 12'd771; + 4'd15: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_771__ETC___d2643 = + m_data_15[68:57] == 12'd771; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -13941,71 +14012,6 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd384; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_0[68:57] == 12'd323; - 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_1[68:57] == 12'd323; - 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_2[68:57] == 12'd323; - 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_3[68:57] == 12'd323; - 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_4[68:57] == 12'd323; - 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_5[68:57] == 12'd323; - 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_6[68:57] == 12'd323; - 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_7[68:57] == 12'd323; - 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_8[68:57] == 12'd323; - 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_9[68:57] == 12'd323; - 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_10[68:57] == 12'd323; - 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_11[68:57] == 12'd323; - 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_12[68:57] == 12'd323; - 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_13[68:57] == 12'd323; - 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_14[68:57] == 12'd323; - 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = - m_data_15[68:57] == 12'd323; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -14136,6 +14142,71 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd322; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_0[68:57] == 12'd323; + 4'd1: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_1[68:57] == 12'd323; + 4'd2: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_2[68:57] == 12'd323; + 4'd3: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_3[68:57] == 12'd323; + 4'd4: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_4[68:57] == 12'd323; + 4'd5: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_5[68:57] == 12'd323; + 4'd6: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_6[68:57] == 12'd323; + 4'd7: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_7[68:57] == 12'd323; + 4'd8: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_8[68:57] == 12'd323; + 4'd9: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_9[68:57] == 12'd323; + 4'd10: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_10[68:57] == 12'd323; + 4'd11: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_11[68:57] == 12'd323; + 4'd12: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_12[68:57] == 12'd323; + 4'd13: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_13[68:57] == 12'd323; + 4'd14: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_14[68:57] == 12'd323; + 4'd15: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_323__ETC___d2535 = + m_data_15[68:57] == 12'd323; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -14396,71 +14467,6 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd261; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_0[68:57] == 12'd256; - 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_1[68:57] == 12'd256; - 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_2[68:57] == 12'd256; - 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_3[68:57] == 12'd256; - 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_4[68:57] == 12'd256; - 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_5[68:57] == 12'd256; - 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_6[68:57] == 12'd256; - 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_7[68:57] == 12'd256; - 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_8[68:57] == 12'd256; - 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_9[68:57] == 12'd256; - 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_10[68:57] == 12'd256; - 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_11[68:57] == 12'd256; - 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_12[68:57] == 12'd256; - 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_13[68:57] == 12'd256; - 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_14[68:57] == 12'd256; - 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = - m_data_15[68:57] == 12'd256; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -14591,6 +14597,71 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd2049; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_0[68:57] == 12'd256; + 4'd1: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_1[68:57] == 12'd256; + 4'd2: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_2[68:57] == 12'd256; + 4'd3: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_3[68:57] == 12'd256; + 4'd4: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_4[68:57] == 12'd256; + 4'd5: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_5[68:57] == 12'd256; + 4'd6: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_6[68:57] == 12'd256; + 4'd7: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_7[68:57] == 12'd256; + 4'd8: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_8[68:57] == 12'd256; + 4'd9: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_9[68:57] == 12'd256; + 4'd10: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_10[68:57] == 12'd256; + 4'd11: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_11[68:57] == 12'd256; + 4'd12: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_12[68:57] == 12'd256; + 4'd13: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_13[68:57] == 12'd256; + 4'd14: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_14[68:57] == 12'd256; + 4'd15: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_256__ETC___d2409 = + m_data_15[68:57] == 12'd256; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -14786,71 +14857,6 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd3073; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_0[68:57] == 12'd3; - 4'd1: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_1[68:57] == 12'd3; - 4'd2: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_2[68:57] == 12'd3; - 4'd3: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_3[68:57] == 12'd3; - 4'd4: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_4[68:57] == 12'd3; - 4'd5: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_5[68:57] == 12'd3; - 4'd6: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_6[68:57] == 12'd3; - 4'd7: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_7[68:57] == 12'd3; - 4'd8: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_8[68:57] == 12'd3; - 4'd9: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_9[68:57] == 12'd3; - 4'd10: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_10[68:57] == 12'd3; - 4'd11: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_11[68:57] == 12'd3; - 4'd12: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_12[68:57] == 12'd3; - 4'd13: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_13[68:57] == 12'd3; - 4'd14: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_14[68:57] == 12'd3; - 4'd15: - SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = - m_data_15[68:57] == 12'd3; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -14981,6 +14987,71 @@ module mkReservationStationAlu(CLK, m_data_15[68:57] == 12'd2; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_0[68:57] == 12'd3; + 4'd1: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_1[68:57] == 12'd3; + 4'd2: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_2[68:57] == 12'd3; + 4'd3: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_3[68:57] == 12'd3; + 4'd4: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_4[68:57] == 12'd3; + 4'd5: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_5[68:57] == 12'd3; + 4'd6: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_6[68:57] == 12'd3; + 4'd7: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_7[68:57] == 12'd3; + 4'd8: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_8[68:57] == 12'd3; + 4'd9: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_9[68:57] == 12'd3; + 4'd10: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_10[68:57] == 12'd3; + 4'd11: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_11[68:57] == 12'd3; + 4'd12: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_12[68:57] == 12'd3; + 4'd13: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_13[68:57] == 12'd3; + 4'd14: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_14[68:57] == 12'd3; + 4'd15: + SEL_ARR_m_data_0_208_BITS_68_TO_57_232_EQ_3_28_ETC___d2301 = + m_data_15[68:57] == 12'd3; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -15241,71 +15312,6 @@ module mkReservationStationAlu(CLK, !m_regs_15[24]; endcase end - always@(idx__h168545 or - m_regs_0 or - m_regs_1 or - m_regs_2 or - m_regs_3 or - m_regs_4 or - m_regs_5 or - m_regs_6 or - m_regs_7 or - m_regs_8 or - m_regs_9 or - m_regs_10 or - m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_0[8]; - 4'd1: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_1[8]; - 4'd2: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_2[8]; - 4'd3: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_3[8]; - 4'd4: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_4[8]; - 4'd5: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_5[8]; - 4'd6: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_6[8]; - 4'd7: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_7[8]; - 4'd8: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_8[8]; - 4'd9: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_9[8]; - 4'd10: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_10[8]; - 4'd11: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_11[8]; - 4'd12: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_12[8]; - 4'd13: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_13[8]; - 4'd14: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_14[8]; - 4'd15: - SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = - !m_regs_15[8]; - endcase - end always@(idx__h168545 or m_regs_0 or m_regs_1 or @@ -15437,6 +15443,71 @@ module mkReservationStationAlu(CLK, !m_spec_tag_15[4]; endcase end + always@(idx__h168545 or + m_regs_0 or + m_regs_1 or + m_regs_2 or + m_regs_3 or + m_regs_4 or + m_regs_5 or + m_regs_6 or + m_regs_7 or + m_regs_8 or + m_regs_9 or + m_regs_10 or + m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_0[8]; + 4'd1: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_1[8]; + 4'd2: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_2[8]; + 4'd3: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_3[8]; + 4'd4: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_4[8]; + 4'd5: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_5[8]; + 4'd6: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_6[8]; + 4'd7: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_7[8]; + 4'd8: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_8[8]; + 4'd9: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_9[8]; + 4'd10: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_10[8]; + 4'd11: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_11[8]; + 4'd12: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_12[8]; + 4'd13: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_13[8]; + 4'd14: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_14[8]; + 4'd15: + SEL_ARR_NOT_m_regs_0_063_BIT_8_242_243_NOT_m_r_ETC___d3275 = + !m_regs_15[8]; + endcase + end always@(idx__h168545 or m_tag_0 or m_tag_1 or @@ -15567,71 +15638,6 @@ module mkReservationStationAlu(CLK, m_data_15[1]; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_0[70]; - 4'd1: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_1[70]; - 4'd2: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_2[70]; - 4'd3: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_3[70]; - 4'd4: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_4[70]; - 4'd5: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_5[70]; - 4'd6: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_6[70]; - 4'd7: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_7[70]; - 4'd8: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_8[70]; - 4'd9: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_9[70]; - 4'd10: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_10[70]; - 4'd11: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_11[70]; - 4'd12: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_12[70]; - 4'd13: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_13[70]; - 4'd14: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_14[70]; - 4'd15: - SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = - m_data_15[70]; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -15697,6 +15703,71 @@ module mkReservationStationAlu(CLK, m_data_15[72]; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_0[70]; + 4'd1: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_1[70]; + 4'd2: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_2[70]; + 4'd3: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_3[70]; + 4'd4: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_4[70]; + 4'd5: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_5[70]; + 4'd6: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_6[70]; + 4'd7: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_7[70]; + 4'd8: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_8[70]; + 4'd9: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_9[70]; + 4'd10: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_10[70]; + 4'd11: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_11[70]; + 4'd12: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_12[70]; + 4'd13: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_13[70]; + 4'd14: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_14[70]; + 4'd15: + SEL_ARR_m_data_0_208_BIT_70_806_m_data_1_210_B_ETC___d1823 = + m_data_15[70]; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -16087,6 +16158,71 @@ module mkReservationStationAlu(CLK, m_data_15[71:70]; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_0[74]; + 4'd1: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_1[74]; + 4'd2: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_2[74]; + 4'd3: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_3[74]; + 4'd4: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_4[74]; + 4'd5: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_5[74]; + 4'd6: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_6[74]; + 4'd7: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_7[74]; + 4'd8: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_8[74]; + 4'd9: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_9[74]; + 4'd10: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_10[74]; + 4'd11: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_11[74]; + 4'd12: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_12[74]; + 4'd13: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_13[74]; + 4'd14: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_14[74]; + 4'd15: + SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = + m_data_15[74]; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -16217,71 +16353,6 @@ module mkReservationStationAlu(CLK, m_data_15[75]; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_0[74]; - 4'd1: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_1[74]; - 4'd2: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_2[74]; - 4'd3: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_3[74]; - 4'd4: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_4[74]; - 4'd5: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_5[74]; - 4'd6: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_6[74]; - 4'd7: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_7[74]; - 4'd8: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_8[74]; - 4'd9: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_9[74]; - 4'd10: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_10[74]; - 4'd11: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_11[74]; - 4'd12: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_12[74]; - 4'd13: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_13[74]; - 4'd14: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_14[74]; - 4'd15: - SEL_ARR_m_data_0_208_BIT_74_733_m_data_1_210_B_ETC___d1750 = - m_data_15[74]; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -16933,71 +17004,6 @@ module mkReservationStationAlu(CLK, m_data_15[80]; endcase end - always@(idx__h168545 or - m_regs_0 or - m_regs_1 or - m_regs_2 or - m_regs_3 or - m_regs_4 or - m_regs_5 or - m_regs_6 or - m_regs_7 or - m_regs_8 or - m_regs_9 or - m_regs_10 or - m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_0[15:9]; - 4'd1: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_1[15:9]; - 4'd2: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_2[15:9]; - 4'd3: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_3[15:9]; - 4'd4: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_4[15:9]; - 4'd5: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_5[15:9]; - 4'd6: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_6[15:9]; - 4'd7: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_7[15:9]; - 4'd8: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_8[15:9]; - 4'd9: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_9[15:9]; - 4'd10: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_10[15:9]; - 4'd11: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_11[15:9]; - 4'd12: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_12[15:9]; - 4'd13: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_13[15:9]; - 4'd14: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_14[15:9]; - 4'd15: - SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = - m_regs_15[15:9]; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -17063,6 +17069,71 @@ module mkReservationStationAlu(CLK, m_data_15[74:70]; endcase end + always@(idx__h168545 or + m_regs_0 or + m_regs_1 or + m_regs_2 or + m_regs_3 or + m_regs_4 or + m_regs_5 or + m_regs_6 or + m_regs_7 or + m_regs_8 or + m_regs_9 or + m_regs_10 or + m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_0[15:9]; + 4'd1: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_1[15:9]; + 4'd2: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_2[15:9]; + 4'd3: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_3[15:9]; + 4'd4: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_4[15:9]; + 4'd5: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_5[15:9]; + 4'd6: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_6[15:9]; + 4'd7: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_7[15:9]; + 4'd8: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_8[15:9]; + 4'd9: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_9[15:9]; + 4'd10: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_10[15:9]; + 4'd11: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_11[15:9]; + 4'd12: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_12[15:9]; + 4'd13: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_13[15:9]; + 4'd14: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_14[15:9]; + 4'd15: + SEL_ARR_m_regs_0_063_BITS_15_TO_9_223_m_regs_1_ETC___d3240 = + m_regs_15[15:9]; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -17128,71 +17199,6 @@ module mkReservationStationAlu(CLK, m_data_15[72:70]; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_0[23:12]; - 4'd1: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_1[23:12]; - 4'd2: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_2[23:12]; - 4'd3: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_3[23:12]; - 4'd4: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_4[23:12]; - 4'd5: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_5[23:12]; - 4'd6: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_6[23:12]; - 4'd7: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_7[23:12]; - 4'd8: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_8[23:12]; - 4'd9: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_9[23:12]; - 4'd10: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_10[23:12]; - 4'd11: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_11[23:12]; - 4'd12: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_12[23:12]; - 4'd13: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_13[23:12]; - 4'd14: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_14[23:12]; - 4'd15: - SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = - m_data_15[23:12]; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -17258,6 +17264,71 @@ module mkReservationStationAlu(CLK, m_data_15[87:85]; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_0[23:12]; + 4'd1: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_1[23:12]; + 4'd2: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_2[23:12]; + 4'd3: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_3[23:12]; + 4'd4: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_4[23:12]; + 4'd5: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_5[23:12]; + 4'd6: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_6[23:12]; + 4'd7: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_7[23:12]; + 4'd8: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_8[23:12]; + 4'd9: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_9[23:12]; + 4'd10: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_10[23:12]; + 4'd11: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_11[23:12]; + 4'd12: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_12[23:12]; + 4'd13: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_13[23:12]; + 4'd14: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_14[23:12]; + 4'd15: + SEL_ARR_m_data_0_208_BITS_23_TO_12_989_m_data__ETC___d3006 = + m_data_15[23:12]; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -17323,71 +17394,6 @@ module mkReservationStationAlu(CLK, m_data_15[11:2]; endcase end - always@(idx__h168545 or - m_regs_0 or - m_regs_1 or - m_regs_2 or - m_regs_3 or - m_regs_4 or - m_regs_5 or - m_regs_6 or - m_regs_7 or - m_regs_8 or - m_regs_9 or - m_regs_10 or - m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_0[31:25]; - 4'd1: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_1[31:25]; - 4'd2: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_2[31:25]; - 4'd3: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_3[31:25]; - 4'd4: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_4[31:25]; - 4'd5: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_5[31:25]; - 4'd6: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_6[31:25]; - 4'd7: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_7[31:25]; - 4'd8: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_8[31:25]; - 4'd9: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_9[31:25]; - 4'd10: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_10[31:25]; - 4'd11: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_11[31:25]; - 4'd12: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_12[31:25]; - 4'd13: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_13[31:25]; - 4'd14: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_14[31:25]; - 4'd15: - SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = - m_regs_15[31:25]; - endcase - end always@(idx__h168545 or bs__h282280 or bs__h282468 or @@ -17454,6 +17460,71 @@ module mkReservationStationAlu(CLK, bs__h285088; endcase end + always@(idx__h168545 or + m_regs_0 or + m_regs_1 or + m_regs_2 or + m_regs_3 or + m_regs_4 or + m_regs_5 or + m_regs_6 or + m_regs_7 or + m_regs_8 or + m_regs_9 or + m_regs_10 or + m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_0[31:25]; + 4'd1: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_1[31:25]; + 4'd2: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_2[31:25]; + 4'd3: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_3[31:25]; + 4'd4: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_4[31:25]; + 4'd5: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_5[31:25]; + 4'd6: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_6[31:25]; + 4'd7: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_7[31:25]; + 4'd8: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_8[31:25]; + 4'd9: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_9[31:25]; + 4'd10: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_10[31:25]; + 4'd11: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_11[31:25]; + 4'd12: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_12[31:25]; + 4'd13: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_13[31:25]; + 4'd14: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_14[31:25]; + 4'd15: + SEL_ARR_m_regs_0_063_BITS_31_TO_25_114_m_regs__ETC___d3131 = + m_regs_15[31:25]; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -17584,77 +17655,6 @@ module mkReservationStationAlu(CLK, m_data_15[95:91]; endcase end - always@(enq_x) - begin - case (enq_x[139:137]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1 = - enq_x[139:137]; - default: CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1 = 3'd7; - endcase - end - always@(enq_x or CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1) - begin - case (enq_x[156:154]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_enq_x_BITS_156_TO_154_0_enq_x_BITS_156_TO_ETC__q2 = - enq_x[156:136]; - 3'd4: - CASE_enq_x_BITS_156_TO_154_0_enq_x_BITS_156_TO_ETC__q2 = - { enq_x[156:154], - 9'h0AA, - enq_x[144:140], - CASE_enq_x_BITS_139_TO_137_0_enq_x_BITS_139_TO_ETC__q1, - enq_x[136] }; - default: CASE_enq_x_BITS_156_TO_154_0_enq_x_BITS_156_TO_ETC__q2 = - 21'd1485482; - endcase - end - always@(enq_x) - begin - case (enq_x[134:123]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_enq_x_BITS_134_TO_123_1_enq_x_BITS_134_TO_ETC__q3 = - enq_x[134:123]; - default: CASE_enq_x_BITS_134_TO_123_1_enq_x_BITS_134_TO_ETC__q3 = - 12'd2303; - endcase - end // handling of inlined registers diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v index e633a5b..65bbb61 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v @@ -680,9 +680,6 @@ module mkSoC_Top(CLK, WILL_FIRE_to_raw_mem_request_get, WILL_FIRE_to_raw_mem_response_put; - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h8723; @@ -1354,26 +1351,22 @@ module mkSoC_Top(CLK, assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; // rule RL_rl_reset_start_2 - assign CAN_FIRE_RL_rl_reset_start_2 = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_2 = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = + assign CAN_FIRE_RL_rl_reset_start_2 = mem0_controller$RDY_server_reset_request_put && uart0$RDY_server_reset_request_put && - fabric$RDY_reset && corew$RDY_cpu_reset_server_request_put && + fabric$RDY_reset && rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && + assign WILL_FIRE_RL_rl_reset_start_2 = CAN_FIRE_RL_rl_reset_start_2 ; + + // rule RL_rl_reset_complete + assign CAN_FIRE_RL_rl_reset_complete = mem0_controller$RDY_server_reset_response_get && uart0$RDY_server_reset_response_get && + mem0_controller$RDY_set_addr_map && corew$RDY_cpu_reset_server_response_get && rg_state == 2'd1 ; + assign WILL_FIRE_RL_rl_reset_complete = CAN_FIRE_RL_rl_reset_complete ; // register rg_state assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_2 ? 2'd1 : 2'd2 ; @@ -1412,7 +1405,7 @@ module mkSoC_Top(CLK, assign boot_rom$slave_wlast = fabric$v_to_slaves_0_wlast ; assign boot_rom$slave_wstrb = fabric$v_to_slaves_0_wstrb ; assign boot_rom$slave_wvalid = fabric$v_to_slaves_0_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + assign boot_rom$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; // submodule corew assign corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = @@ -1477,9 +1470,10 @@ module mkSoC_Top(CLK, assign corew$EN_set_verbosity = EN_set_verbosity ; assign corew$EN_set_htif_addrs = EN_set_watch_tohost && set_watch_tohost_watch_tohost ; - assign corew$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; + assign corew$EN_cpu_reset_server_request_put = + CAN_FIRE_RL_rl_reset_start_2 ; assign corew$EN_cpu_reset_server_response_get = - MUX_rg_state$write_1__SEL_2 ; + CAN_FIRE_RL_rl_reset_complete ; // submodule fabric assign fabric$set_verbosity_verbosity = 4'h0 ; @@ -1574,7 +1568,7 @@ module mkSoC_Top(CLK, assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; + assign fabric$EN_reset = CAN_FIRE_RL_rl_reset_start_2 ; assign fabric$EN_set_verbosity = 1'b0 ; // submodule mem0_controller @@ -1617,10 +1611,10 @@ module mkSoC_Top(CLK, assign mem0_controller$slave_wvalid = fabric$v_to_slaves_1_wvalid ; assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; + CAN_FIRE_RL_rl_reset_start_2 ; assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + CAN_FIRE_RL_rl_reset_complete ; + assign mem0_controller$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; assign mem0_controller$EN_to_raw_mem_request_get = EN_to_raw_mem_request_get ; assign mem0_controller$EN_to_raw_mem_response_put = @@ -1665,9 +1659,9 @@ module mkSoC_Top(CLK, assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + assign uart0$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start_2 ; + assign uart0$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_complete ; + assign uart0$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; assign uart0$EN_get_to_console_get = EN_get_to_console_get ; assign uart0$EN_put_from_console_put = EN_put_from_console_put ; diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSplitLSQ.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSplitLSQ.v index 1a861bb..2b4a2f4 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSplitLSQ.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSplitLSQ.v @@ -17302,7 +17302,7 @@ module mkSplitLSQ(CLK, SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23375, _dfoo1003, _dfoo481, - _dfoo487, + _dfoo485, _dfoo489, _dfoo493, _dfoo497, @@ -17313,7 +17313,7 @@ module mkSplitLSQ(CLK, _dfoo517, _dfoo521, _dfoo525, - _dfoo531, + _dfoo529, _dfoo533, _dfoo537, _dfoo541, @@ -17323,7 +17323,7 @@ module mkSplitLSQ(CLK, _dfoo557, _dfoo561, _dfoo565, - _dfoo571, + _dfoo569, _dfoo573, _dfoo673, _dfoo677, @@ -17332,46 +17332,46 @@ module mkSplitLSQ(CLK, _dfoo689, _dfoo693, _dfoo697, - _dfoo701, + _dfoo703, _dfoo705, - _dfoo711, + _dfoo709, _dfoo713, _dfoo717, _dfoo721, _dfoo725, - _dfoo729, + _dfoo731, _dfoo733, _dfoo737, _dfoo741, - _dfoo745, - _dfoo751, + _dfoo747, + _dfoo749, _dfoo753, _dfoo757, _dfoo761, _dfoo765, - _dfoo867, + _dfoo865, _dfoo871, _dfoo877, _dfoo883, - _dfoo889, + _dfoo891, _dfoo895, _dfoo901, _dfoo907, _dfoo913, _dfoo919, _dfoo925, - _dfoo931, + _dfoo935, _dfoo937, _dfoo943, _dfoo949, _dfoo957, - _dfoo961, + _dfoo963, _dfoo967, _dfoo973, _dfoo979, - _dfoo985, + _dfoo989, _dfoo991, - _dfoo997, + _dfoo999, issueLd_lsqTag_EQ_0_1827_AND_SEL_ARR_ld_valid__ETC___d23186, issueLd_lsqTag_EQ_10_3153_AND_SEL_ARR_ld_valid_ETC___d23196, issueLd_lsqTag_EQ_11_3155_AND_SEL_ARR_ld_valid_ETC___d23197, @@ -30710,7 +30710,7 @@ module mkSplitLSQ(CLK, assign ld_inIssueQ_23_lat_1$whas = WILL_FIRE_RL_enqIssueQ && issueLdInfo$wget[76:72] == 5'd23 ; assign ld_executing_0_lat_0$whas = EN_issueLd && _dfoo573 ; - assign ld_executing_1_dummy_1_0$wget = EN_issueLd && _dfoo571 ; + assign ld_executing_1_dummy_1_0$wget = EN_issueLd && _dfoo569 ; assign ld_executing_2_lat_0$whas = EN_issueLd && _dfoo565 ; assign ld_executing_3_dummy_1_0$wget = EN_issueLd && _dfoo561 ; assign ld_executing_4_lat_0$whas = EN_issueLd && _dfoo557 ; @@ -30720,7 +30720,7 @@ module mkSplitLSQ(CLK, assign ld_executing_8_lat_0$whas = EN_issueLd && _dfoo541 ; assign ld_executing_9_lat_0$whas = EN_issueLd && _dfoo537 ; assign ld_executing_10_lat_0$whas = EN_issueLd && _dfoo533 ; - assign ld_executing_11_lat_0$whas = EN_issueLd && _dfoo531 ; + assign ld_executing_11_lat_0$whas = EN_issueLd && _dfoo529 ; assign ld_executing_12_lat_0$whas = EN_issueLd && _dfoo525 ; assign ld_executing_13_lat_0$whas = EN_issueLd && _dfoo521 ; assign ld_executing_14_dummy_1_0$wget = EN_issueLd && _dfoo517 ; @@ -30731,7 +30731,7 @@ module mkSplitLSQ(CLK, assign ld_executing_19_lat_0$whas = EN_issueLd && _dfoo497 ; assign ld_executing_20_dummy_1_0$wget = EN_issueLd && _dfoo493 ; assign ld_executing_21_lat_0$whas = EN_issueLd && _dfoo489 ; - assign ld_executing_22_lat_0$whas = EN_issueLd && _dfoo487 ; + assign ld_executing_22_lat_0$whas = EN_issueLd && _dfoo485 ; assign ld_executing_23_lat_0$whas = EN_issueLd && _dfoo481 ; assign ld_done_0_lat_0$whas = EN_respLd && respLd_t == 5'd0 && @@ -31367,7 +31367,7 @@ module mkSplitLSQ(CLK, { SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23122, stTag__h1515530 } : 5'd10 ; - assign ld_readFrom_1_lat_0$whas = EN_issueLd && _dfoo571 ; + assign ld_readFrom_1_lat_0$whas = EN_issueLd && _dfoo569 ; assign ld_readFrom_1_lat_1$whas = EN_deqSt && ld_readFrom_1_dummy2_1_read__0229_AND_ld_readF_ETC___d26271 ; @@ -31477,7 +31477,7 @@ module mkSplitLSQ(CLK, { SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23122, stTag__h1515530 } : 5'd10 ; - assign ld_readFrom_11_lat_0$whas = EN_issueLd && _dfoo531 ; + assign ld_readFrom_11_lat_0$whas = EN_issueLd && _dfoo529 ; assign ld_readFrom_11_lat_1$whas = EN_deqSt && ld_readFrom_11_dummy2_1_read__0619_AND_ld_read_ETC___d26371 ; @@ -31598,7 +31598,7 @@ module mkSplitLSQ(CLK, { SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23122, stTag__h1515530 } : 5'd10 ; - assign ld_readFrom_22_lat_0$whas = EN_issueLd && _dfoo487 ; + assign ld_readFrom_22_lat_0$whas = EN_issueLd && _dfoo485 ; assign ld_readFrom_22_lat_1$whas = EN_deqSt && ld_readFrom_22_dummy2_1_read__1048_AND_ld_read_ETC___d26481 ; @@ -31625,7 +31625,7 @@ module mkSplitLSQ(CLK, EN_deqLd && ld_depLdQDeq_1_dummy2_0_read__1744_AND_ld_depL_ETC___d13707 && ld_depLdQDeq_1_rl[4:0] == x__h1062868 ; - assign ld_depLdQDeq_1_lat_1$whas = EN_issueLd && _dfoo997 ; + assign ld_depLdQDeq_1_lat_1$whas = EN_issueLd && _dfoo999 ; assign ld_depLdQDeq_2_lat_0$whas = EN_deqLd && ld_depLdQDeq_2_dummy2_0_read__1828_AND_ld_depL_ETC___d13747 && @@ -31635,7 +31635,7 @@ module mkSplitLSQ(CLK, EN_deqLd && ld_depLdQDeq_3_dummy2_0_read__1912_AND_ld_depL_ETC___d13787 && ld_depLdQDeq_3_rl[4:0] == x__h1062868 ; - assign ld_depLdQDeq_3_lat_1$whas = EN_issueLd && _dfoo985 ; + assign ld_depLdQDeq_3_lat_1$whas = EN_issueLd && _dfoo989 ; assign ld_depLdQDeq_4_lat_0$whas = EN_deqLd && ld_depLdQDeq_4_dummy2_0_read__1996_AND_ld_depL_ETC___d13827 && @@ -31655,7 +31655,7 @@ module mkSplitLSQ(CLK, EN_deqLd && ld_depLdQDeq_7_dummy2_0_read__2248_AND_ld_depL_ETC___d13947 && ld_depLdQDeq_7_rl[4:0] == x__h1062868 ; - assign ld_depLdQDeq_7_lat_1$whas = EN_issueLd && _dfoo961 ; + assign ld_depLdQDeq_7_lat_1$whas = EN_issueLd && _dfoo963 ; assign ld_depLdQDeq_8_lat_0$whas = EN_deqLd && ld_depLdQDeq_8_dummy2_0_read__2332_AND_ld_depL_ETC___d13987 && @@ -31680,7 +31680,7 @@ module mkSplitLSQ(CLK, EN_deqLd && ld_depLdQDeq_12_dummy2_0_read__2668_AND_ld_dep_ETC___d14147 && ld_depLdQDeq_12_rl[4:0] == x__h1062868 ; - assign ld_depLdQDeq_12_lat_1$whas = EN_issueLd && _dfoo931 ; + assign ld_depLdQDeq_12_lat_1$whas = EN_issueLd && _dfoo935 ; assign ld_depLdQDeq_13_lat_0$whas = EN_deqLd && ld_depLdQDeq_13_dummy2_0_read__2752_AND_ld_dep_ETC___d14187 && @@ -31715,7 +31715,7 @@ module mkSplitLSQ(CLK, EN_deqLd && ld_depLdQDeq_19_dummy2_0_read__3256_AND_ld_dep_ETC___d14427 && ld_depLdQDeq_19_rl[4:0] == x__h1062868 ; - assign ld_depLdQDeq_19_lat_1$whas = EN_issueLd && _dfoo889 ; + assign ld_depLdQDeq_19_lat_1$whas = EN_issueLd && _dfoo891 ; assign ld_depLdQDeq_20_lat_0$whas = EN_deqLd && ld_depLdQDeq_20_dummy2_0_read__3340_AND_ld_dep_ETC___d14467 && @@ -31735,7 +31735,7 @@ module mkSplitLSQ(CLK, EN_deqLd && ld_depLdQDeq_23_dummy2_0_read__3592_AND_ld_dep_ETC___d14587 && ld_depLdQDeq_23_rl[4:0] == x__h1062868 ; - assign ld_depLdQDeq_23_lat_1$whas = EN_issueLd && _dfoo867 ; + assign ld_depLdQDeq_23_lat_1$whas = EN_issueLd && _dfoo865 ; assign ld_depStQDeq_0_lat_0$wget = { SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23122, stTag__h1515530 } ; @@ -31755,11 +31755,11 @@ module mkSplitLSQ(CLK, assign ld_depStQDeq_3_lat_1$whas = EN_deqSt && ld_depStQDeq_3_dummy2_1_read__1944_AND_ld_depS_ETC___d26295 ; - assign ld_depStQDeq_4_lat_0$whas = EN_issueLd && _dfoo751 ; + assign ld_depStQDeq_4_lat_0$whas = EN_issueLd && _dfoo749 ; assign ld_depStQDeq_4_lat_1$whas = EN_deqSt && ld_depStQDeq_4_dummy2_1_read__2028_AND_ld_depS_ETC___d26305 ; - assign ld_depStQDeq_5_lat_0$whas = EN_issueLd && _dfoo745 ; + assign ld_depStQDeq_5_lat_0$whas = EN_issueLd && _dfoo747 ; assign ld_depStQDeq_5_lat_1$whas = EN_deqSt && ld_depStQDeq_5_dummy2_1_read__2112_AND_ld_depS_ETC___d26315 ; @@ -31775,7 +31775,7 @@ module mkSplitLSQ(CLK, assign ld_depStQDeq_8_lat_1$whas = EN_deqSt && ld_depStQDeq_8_dummy2_1_read__2364_AND_ld_depS_ETC___d26345 ; - assign ld_depStQDeq_9_lat_0$whas = EN_issueLd && _dfoo729 ; + assign ld_depStQDeq_9_lat_0$whas = EN_issueLd && _dfoo731 ; assign ld_depStQDeq_9_lat_1$whas = EN_deqSt && ld_depStQDeq_9_dummy2_1_read__2448_AND_ld_depS_ETC___d26355 ; @@ -31795,7 +31795,7 @@ module mkSplitLSQ(CLK, assign ld_depStQDeq_13_lat_1$whas = EN_deqSt && ld_depStQDeq_13_dummy2_1_read__2784_AND_ld_dep_ETC___d26395 ; - assign ld_depStQDeq_14_lat_0$whas = EN_issueLd && _dfoo711 ; + assign ld_depStQDeq_14_lat_0$whas = EN_issueLd && _dfoo709 ; assign ld_depStQDeq_14_lat_1$whas = EN_deqSt && ld_depStQDeq_14_dummy2_1_read__2868_AND_ld_dep_ETC___d26405 ; @@ -31803,7 +31803,7 @@ module mkSplitLSQ(CLK, assign ld_depStQDeq_15_lat_1$whas = EN_deqSt && ld_depStQDeq_15_dummy2_1_read__2952_AND_ld_dep_ETC___d26415 ; - assign ld_depStQDeq_16_lat_0$whas = EN_issueLd && _dfoo701 ; + assign ld_depStQDeq_16_lat_0$whas = EN_issueLd && _dfoo703 ; assign ld_depStQDeq_16_lat_1$whas = EN_deqSt && ld_depStQDeq_16_dummy2_1_read__3036_AND_ld_dep_ETC___d26425 ; @@ -38913,7 +38913,7 @@ module mkSplitLSQ(CLK, // submodule ld_depLdQDeq_12_dummy2_1 assign ld_depLdQDeq_12_dummy2_1$D_IN = 1'd1 ; - assign ld_depLdQDeq_12_dummy2_1$EN = EN_issueLd && _dfoo931 ; + assign ld_depLdQDeq_12_dummy2_1$EN = EN_issueLd && _dfoo935 ; // submodule ld_depLdQDeq_12_dummy2_2 assign ld_depLdQDeq_12_dummy2_2$D_IN = 1'd1 ; @@ -38997,7 +38997,7 @@ module mkSplitLSQ(CLK, // submodule ld_depLdQDeq_19_dummy2_1 assign ld_depLdQDeq_19_dummy2_1$D_IN = 1'd1 ; - assign ld_depLdQDeq_19_dummy2_1$EN = EN_issueLd && _dfoo889 ; + assign ld_depLdQDeq_19_dummy2_1$EN = EN_issueLd && _dfoo891 ; // submodule ld_depLdQDeq_19_dummy2_2 assign ld_depLdQDeq_19_dummy2_2$D_IN = 1'd1 ; @@ -39009,7 +39009,7 @@ module mkSplitLSQ(CLK, // submodule ld_depLdQDeq_1_dummy2_1 assign ld_depLdQDeq_1_dummy2_1$D_IN = 1'd1 ; - assign ld_depLdQDeq_1_dummy2_1$EN = EN_issueLd && _dfoo997 ; + assign ld_depLdQDeq_1_dummy2_1$EN = EN_issueLd && _dfoo999 ; // submodule ld_depLdQDeq_1_dummy2_2 assign ld_depLdQDeq_1_dummy2_2$D_IN = 1'd1 ; @@ -39057,7 +39057,7 @@ module mkSplitLSQ(CLK, // submodule ld_depLdQDeq_23_dummy2_1 assign ld_depLdQDeq_23_dummy2_1$D_IN = 1'd1 ; - assign ld_depLdQDeq_23_dummy2_1$EN = EN_issueLd && _dfoo867 ; + assign ld_depLdQDeq_23_dummy2_1$EN = EN_issueLd && _dfoo865 ; // submodule ld_depLdQDeq_23_dummy2_2 assign ld_depLdQDeq_23_dummy2_2$D_IN = 1'd1 ; @@ -39081,7 +39081,7 @@ module mkSplitLSQ(CLK, // submodule ld_depLdQDeq_3_dummy2_1 assign ld_depLdQDeq_3_dummy2_1$D_IN = 1'd1 ; - assign ld_depLdQDeq_3_dummy2_1$EN = EN_issueLd && _dfoo985 ; + assign ld_depLdQDeq_3_dummy2_1$EN = EN_issueLd && _dfoo989 ; // submodule ld_depLdQDeq_3_dummy2_2 assign ld_depLdQDeq_3_dummy2_2$D_IN = 1'd1 ; @@ -39129,7 +39129,7 @@ module mkSplitLSQ(CLK, // submodule ld_depLdQDeq_7_dummy2_1 assign ld_depLdQDeq_7_dummy2_1$D_IN = 1'd1 ; - assign ld_depLdQDeq_7_dummy2_1$EN = EN_issueLd && _dfoo961 ; + assign ld_depLdQDeq_7_dummy2_1$EN = EN_issueLd && _dfoo963 ; // submodule ld_depLdQDeq_7_dummy2_2 assign ld_depLdQDeq_7_dummy2_2$D_IN = 1'd1 ; @@ -39509,7 +39509,7 @@ module mkSplitLSQ(CLK, // submodule ld_depStQDeq_14_dummy2_0 assign ld_depStQDeq_14_dummy2_0$D_IN = 1'd1 ; - assign ld_depStQDeq_14_dummy2_0$EN = EN_issueLd && _dfoo711 ; + assign ld_depStQDeq_14_dummy2_0$EN = EN_issueLd && _dfoo709 ; // submodule ld_depStQDeq_14_dummy2_1 assign ld_depStQDeq_14_dummy2_1$D_IN = 1'd1 ; @@ -39533,7 +39533,7 @@ module mkSplitLSQ(CLK, // submodule ld_depStQDeq_16_dummy2_0 assign ld_depStQDeq_16_dummy2_0$D_IN = 1'd1 ; - assign ld_depStQDeq_16_dummy2_0$EN = EN_issueLd && _dfoo701 ; + assign ld_depStQDeq_16_dummy2_0$EN = EN_issueLd && _dfoo703 ; // submodule ld_depStQDeq_16_dummy2_1 assign ld_depStQDeq_16_dummy2_1$D_IN = 1'd1 ; @@ -39665,7 +39665,7 @@ module mkSplitLSQ(CLK, // submodule ld_depStQDeq_4_dummy2_0 assign ld_depStQDeq_4_dummy2_0$D_IN = 1'd1 ; - assign ld_depStQDeq_4_dummy2_0$EN = EN_issueLd && _dfoo751 ; + assign ld_depStQDeq_4_dummy2_0$EN = EN_issueLd && _dfoo749 ; // submodule ld_depStQDeq_4_dummy2_1 assign ld_depStQDeq_4_dummy2_1$D_IN = 1'd1 ; @@ -39677,7 +39677,7 @@ module mkSplitLSQ(CLK, // submodule ld_depStQDeq_5_dummy2_0 assign ld_depStQDeq_5_dummy2_0$D_IN = 1'd1 ; - assign ld_depStQDeq_5_dummy2_0$EN = EN_issueLd && _dfoo745 ; + assign ld_depStQDeq_5_dummy2_0$EN = EN_issueLd && _dfoo747 ; // submodule ld_depStQDeq_5_dummy2_1 assign ld_depStQDeq_5_dummy2_1$D_IN = 1'd1 ; @@ -39725,7 +39725,7 @@ module mkSplitLSQ(CLK, // submodule ld_depStQDeq_9_dummy2_0 assign ld_depStQDeq_9_dummy2_0$D_IN = 1'd1 ; - assign ld_depStQDeq_9_dummy2_0$EN = EN_issueLd && _dfoo729 ; + assign ld_depStQDeq_9_dummy2_0$EN = EN_issueLd && _dfoo731 ; // submodule ld_depStQDeq_9_dummy2_1 assign ld_depStQDeq_9_dummy2_1$D_IN = 1'd1 ; @@ -39953,7 +39953,7 @@ module mkSplitLSQ(CLK, // submodule ld_executing_11_dummy2_0 assign ld_executing_11_dummy2_0$D_IN = 1'd1 ; - assign ld_executing_11_dummy2_0$EN = EN_issueLd && _dfoo531 ; + assign ld_executing_11_dummy2_0$EN = EN_issueLd && _dfoo529 ; // submodule ld_executing_11_dummy2_1 assign ld_executing_11_dummy2_1$D_IN = 1'd1 ; @@ -40025,7 +40025,7 @@ module mkSplitLSQ(CLK, // submodule ld_executing_1_dummy2_0 assign ld_executing_1_dummy2_0$D_IN = 1'd1 ; - assign ld_executing_1_dummy2_0$EN = EN_issueLd && _dfoo571 ; + assign ld_executing_1_dummy2_0$EN = EN_issueLd && _dfoo569 ; // submodule ld_executing_1_dummy2_1 assign ld_executing_1_dummy2_1$D_IN = 1'd1 ; @@ -40049,7 +40049,7 @@ module mkSplitLSQ(CLK, // submodule ld_executing_22_dummy2_0 assign ld_executing_22_dummy2_0$D_IN = 1'd1 ; - assign ld_executing_22_dummy2_0$EN = EN_issueLd && _dfoo487 ; + assign ld_executing_22_dummy2_0$EN = EN_issueLd && _dfoo485 ; // submodule ld_executing_22_dummy2_1 assign ld_executing_22_dummy2_1$D_IN = 1'd1 ; @@ -41703,7 +41703,7 @@ module mkSplitLSQ(CLK, // submodule ld_readFrom_11_dummy2_0 assign ld_readFrom_11_dummy2_0$D_IN = 1'd1 ; - assign ld_readFrom_11_dummy2_0$EN = EN_issueLd && _dfoo531 ; + assign ld_readFrom_11_dummy2_0$EN = EN_issueLd && _dfoo529 ; // submodule ld_readFrom_11_dummy2_1 assign ld_readFrom_11_dummy2_1$D_IN = 1'd1 ; @@ -41811,7 +41811,7 @@ module mkSplitLSQ(CLK, // submodule ld_readFrom_1_dummy2_0 assign ld_readFrom_1_dummy2_0$D_IN = 1'd1 ; - assign ld_readFrom_1_dummy2_0$EN = EN_issueLd && _dfoo571 ; + assign ld_readFrom_1_dummy2_0$EN = EN_issueLd && _dfoo569 ; // submodule ld_readFrom_1_dummy2_1 assign ld_readFrom_1_dummy2_1$D_IN = 1'd1 ; @@ -41847,7 +41847,7 @@ module mkSplitLSQ(CLK, // submodule ld_readFrom_22_dummy2_0 assign ld_readFrom_22_dummy2_0$D_IN = 1'd1 ; - assign ld_readFrom_22_dummy2_0$EN = EN_issueLd && _dfoo487 ; + assign ld_readFrom_22_dummy2_0$EN = EN_issueLd && _dfoo485 ; // submodule ld_readFrom_22_dummy2_1 assign ld_readFrom_22_dummy2_1$D_IN = 1'd1 ; @@ -56108,7 +56108,7 @@ module mkSplitLSQ(CLK, NOT_SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_ETC___d23382 && !issueLd_sbRes[64] && !issueLd_sbRes[67] ; - assign _dfoo487 = + assign _dfoo485 = issueLd_lsqTag == 5'd22 && NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23314 || @@ -56251,7 +56251,7 @@ module mkSplitLSQ(CLK, NOT_SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_ETC___d23382 && !issueLd_sbRes[64] && !issueLd_sbRes[67] ; - assign _dfoo531 = + assign _dfoo529 = issueLd_lsqTag == 5'd11 && NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23314 || @@ -56381,7 +56381,7 @@ module mkSplitLSQ(CLK, NOT_SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_ETC___d23382 && !issueLd_sbRes[64] && !issueLd_sbRes[67] ; - assign _dfoo571 = + assign _dfoo569 = issueLd_lsqTag == 5'd1 && NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23314 || @@ -56442,7 +56442,7 @@ module mkSplitLSQ(CLK, (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ; - assign _dfoo701 = + assign _dfoo703 = issueLd_lsqTag == 5'd16 && (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && @@ -56452,7 +56452,7 @@ module mkSplitLSQ(CLK, (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ; - assign _dfoo711 = + assign _dfoo709 = issueLd_lsqTag == 5'd14 && (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && @@ -56477,7 +56477,7 @@ module mkSplitLSQ(CLK, (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ; - assign _dfoo729 = + assign _dfoo731 = issueLd_lsqTag == 5'd9 && (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && @@ -56497,12 +56497,12 @@ module mkSplitLSQ(CLK, (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ; - assign _dfoo745 = + assign _dfoo747 = issueLd_lsqTag == 5'd5 && (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ; - assign _dfoo751 = + assign _dfoo749 = issueLd_lsqTag == 5'd4 && (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && @@ -56527,7 +56527,7 @@ module mkSplitLSQ(CLK, (NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 || NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 && SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ; - assign _dfoo867 = + assign _dfoo865 = issueLd_lsqTag == 5'd23 && (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || @@ -56547,7 +56547,7 @@ module mkSplitLSQ(CLK, (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ; - assign _dfoo889 = + assign _dfoo891 = issueLd_lsqTag == 5'd19 && (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || @@ -56582,7 +56582,7 @@ module mkSplitLSQ(CLK, (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ; - assign _dfoo931 = + assign _dfoo935 = issueLd_lsqTag == 5'd12 && (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || @@ -56607,7 +56607,7 @@ module mkSplitLSQ(CLK, (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ; - assign _dfoo961 = + assign _dfoo963 = issueLd_lsqTag == 5'd7 && (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || @@ -56627,7 +56627,7 @@ module mkSplitLSQ(CLK, (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ; - assign _dfoo985 = + assign _dfoo989 = issueLd_lsqTag == 5'd3 && (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || @@ -56637,7 +56637,7 @@ module mkSplitLSQ(CLK, (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ; - assign _dfoo997 = + assign _dfoo999 = issueLd_lsqTag == 5'd1 && (SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 && SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 || @@ -69113,110 +69113,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_0_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_0_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_0_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -69325,6 +69221,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_0_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_0_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18553 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_1_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -69429,6 +69429,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_1_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_1_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_1_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -69537,110 +69641,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_1_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_1_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18568 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_2_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -70905,110 +70905,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_6_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_6_rl[3:0]) - 4'd0: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_0_dummy2_0$Q_OUT && st_valid_0_dummy2_1$Q_OUT && - st_valid_0_rl; - 4'd1: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_1_dummy2_0$Q_OUT && st_valid_1_dummy2_1$Q_OUT && - st_valid_1_rl; - 4'd2: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_2_dummy2_0$Q_OUT && st_valid_2_dummy2_1$Q_OUT && - st_valid_2_rl; - 4'd3: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_3_dummy2_0$Q_OUT && st_valid_3_dummy2_1$Q_OUT && - st_valid_3_rl; - 4'd4: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_4_dummy2_0$Q_OUT && st_valid_4_dummy2_1$Q_OUT && - st_valid_4_rl; - 4'd5: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_5_dummy2_0$Q_OUT && st_valid_5_dummy2_1$Q_OUT && - st_valid_5_rl; - 4'd6: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_6_dummy2_0$Q_OUT && st_valid_6_dummy2_1$Q_OUT && - st_valid_6_rl; - 4'd7: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_7_dummy2_0$Q_OUT && st_valid_7_dummy2_1$Q_OUT && - st_valid_7_rl; - 4'd8: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_8_dummy2_0$Q_OUT && st_valid_8_dummy2_1$Q_OUT && - st_valid_8_rl; - 4'd9: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_9_dummy2_0$Q_OUT && st_valid_9_dummy2_1$Q_OUT && - st_valid_9_rl; - 4'd10: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_10_dummy2_0$Q_OUT && st_valid_10_dummy2_1$Q_OUT && - st_valid_10_rl; - 4'd11: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_11_dummy2_0$Q_OUT && st_valid_11_dummy2_1$Q_OUT && - st_valid_11_rl; - 4'd12: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_12_dummy2_0$Q_OUT && st_valid_12_dummy2_1$Q_OUT && - st_valid_12_rl; - 4'd13: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - st_valid_13_dummy2_0$Q_OUT && st_valid_13_dummy2_1$Q_OUT && - st_valid_13_rl; - default: SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_6_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -71113,6 +71009,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_6_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_6_rl[3:0]) + 4'd0: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_0_dummy2_0$Q_OUT && st_valid_0_dummy2_1$Q_OUT && + st_valid_0_rl; + 4'd1: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_1_dummy2_0$Q_OUT && st_valid_1_dummy2_1$Q_OUT && + st_valid_1_rl; + 4'd2: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_2_dummy2_0$Q_OUT && st_valid_2_dummy2_1$Q_OUT && + st_valid_2_rl; + 4'd3: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_3_dummy2_0$Q_OUT && st_valid_3_dummy2_1$Q_OUT && + st_valid_3_rl; + 4'd4: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_4_dummy2_0$Q_OUT && st_valid_4_dummy2_1$Q_OUT && + st_valid_4_rl; + 4'd5: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_5_dummy2_0$Q_OUT && st_valid_5_dummy2_1$Q_OUT && + st_valid_5_rl; + 4'd6: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_6_dummy2_0$Q_OUT && st_valid_6_dummy2_1$Q_OUT && + st_valid_6_rl; + 4'd7: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_7_dummy2_0$Q_OUT && st_valid_7_dummy2_1$Q_OUT && + st_valid_7_rl; + 4'd8: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_8_dummy2_0$Q_OUT && st_valid_8_dummy2_1$Q_OUT && + st_valid_8_rl; + 4'd9: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_9_dummy2_0$Q_OUT && st_valid_9_dummy2_1$Q_OUT && + st_valid_9_rl; + 4'd10: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_10_dummy2_0$Q_OUT && st_valid_10_dummy2_1$Q_OUT && + st_valid_10_rl; + 4'd11: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_11_dummy2_0$Q_OUT && st_valid_11_dummy2_1$Q_OUT && + st_valid_11_rl; + 4'd12: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_12_dummy2_0$Q_OUT && st_valid_12_dummy2_1$Q_OUT && + st_valid_12_rl; + 4'd13: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + st_valid_13_dummy2_0$Q_OUT && st_valid_13_dummy2_1$Q_OUT && + st_valid_13_rl; + default: SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18640 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_6_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -71221,110 +71221,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_7_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_7_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_7_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -71429,6 +71325,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_7_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_7_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18652 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_7_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -72273,110 +72273,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_10_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_10_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_10_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -72485,6 +72381,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_10_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_10_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18694 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_11_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -73117,110 +73117,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_13_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_13_rl[3:0]) - 4'd0: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_0_dummy2_0$Q_OUT && st_valid_0_dummy2_1$Q_OUT && - st_valid_0_rl; - 4'd1: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_1_dummy2_0$Q_OUT && st_valid_1_dummy2_1$Q_OUT && - st_valid_1_rl; - 4'd2: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_2_dummy2_0$Q_OUT && st_valid_2_dummy2_1$Q_OUT && - st_valid_2_rl; - 4'd3: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_3_dummy2_0$Q_OUT && st_valid_3_dummy2_1$Q_OUT && - st_valid_3_rl; - 4'd4: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_4_dummy2_0$Q_OUT && st_valid_4_dummy2_1$Q_OUT && - st_valid_4_rl; - 4'd5: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_5_dummy2_0$Q_OUT && st_valid_5_dummy2_1$Q_OUT && - st_valid_5_rl; - 4'd6: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_6_dummy2_0$Q_OUT && st_valid_6_dummy2_1$Q_OUT && - st_valid_6_rl; - 4'd7: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_7_dummy2_0$Q_OUT && st_valid_7_dummy2_1$Q_OUT && - st_valid_7_rl; - 4'd8: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_8_dummy2_0$Q_OUT && st_valid_8_dummy2_1$Q_OUT && - st_valid_8_rl; - 4'd9: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_9_dummy2_0$Q_OUT && st_valid_9_dummy2_1$Q_OUT && - st_valid_9_rl; - 4'd10: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_10_dummy2_0$Q_OUT && st_valid_10_dummy2_1$Q_OUT && - st_valid_10_rl; - 4'd11: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_11_dummy2_0$Q_OUT && st_valid_11_dummy2_1$Q_OUT && - st_valid_11_rl; - 4'd12: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_12_dummy2_0$Q_OUT && st_valid_12_dummy2_1$Q_OUT && - st_valid_12_rl; - 4'd13: - SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - st_valid_13_dummy2_0$Q_OUT && st_valid_13_dummy2_1$Q_OUT && - st_valid_13_rl; - default: SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_13_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -73325,6 +73221,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_13_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_13_rl[3:0]) + 4'd0: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_0_dummy2_0$Q_OUT && st_valid_0_dummy2_1$Q_OUT && + st_valid_0_rl; + 4'd1: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_1_dummy2_0$Q_OUT && st_valid_1_dummy2_1$Q_OUT && + st_valid_1_rl; + 4'd2: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_2_dummy2_0$Q_OUT && st_valid_2_dummy2_1$Q_OUT && + st_valid_2_rl; + 4'd3: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_3_dummy2_0$Q_OUT && st_valid_3_dummy2_1$Q_OUT && + st_valid_3_rl; + 4'd4: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_4_dummy2_0$Q_OUT && st_valid_4_dummy2_1$Q_OUT && + st_valid_4_rl; + 4'd5: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_5_dummy2_0$Q_OUT && st_valid_5_dummy2_1$Q_OUT && + st_valid_5_rl; + 4'd6: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_6_dummy2_0$Q_OUT && st_valid_6_dummy2_1$Q_OUT && + st_valid_6_rl; + 4'd7: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_7_dummy2_0$Q_OUT && st_valid_7_dummy2_1$Q_OUT && + st_valid_7_rl; + 4'd8: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_8_dummy2_0$Q_OUT && st_valid_8_dummy2_1$Q_OUT && + st_valid_8_rl; + 4'd9: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_9_dummy2_0$Q_OUT && st_valid_9_dummy2_1$Q_OUT && + st_valid_9_rl; + 4'd10: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_10_dummy2_0$Q_OUT && st_valid_10_dummy2_1$Q_OUT && + st_valid_10_rl; + 4'd11: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_11_dummy2_0$Q_OUT && st_valid_11_dummy2_1$Q_OUT && + st_valid_11_rl; + 4'd12: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_12_dummy2_0$Q_OUT && st_valid_12_dummy2_1$Q_OUT && + st_valid_12_rl; + 4'd13: + SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + st_valid_13_dummy2_0$Q_OUT && st_valid_13_dummy2_1$Q_OUT && + st_valid_13_rl; + default: SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d18738 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_13_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -73433,110 +73433,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_14_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_14_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_14_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -73641,6 +73537,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_14_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_14_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18750 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_14_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -74485,110 +74485,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_17_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_17_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_17_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -74697,6 +74593,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_17_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_17_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18792 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_18_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -74801,6 +74801,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_18_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_18_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = + 1'b0 /* unspecified value */ ; + endcase + end always@(ld_olderSt_18_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -74909,110 +75013,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_18_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_18_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18806 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_19_rl or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -76381,110 +76381,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(ld_olderSt_23_rl or - st_valid_0_dummy2_0$Q_OUT or - st_valid_0_dummy2_1$Q_OUT or - st_valid_0_rl or - st_valid_1_dummy2_0$Q_OUT or - st_valid_1_dummy2_1$Q_OUT or - st_valid_1_rl or - st_valid_2_dummy2_0$Q_OUT or - st_valid_2_dummy2_1$Q_OUT or - st_valid_2_rl or - st_valid_3_dummy2_0$Q_OUT or - st_valid_3_dummy2_1$Q_OUT or - st_valid_3_rl or - st_valid_4_dummy2_0$Q_OUT or - st_valid_4_dummy2_1$Q_OUT or - st_valid_4_rl or - st_valid_5_dummy2_0$Q_OUT or - st_valid_5_dummy2_1$Q_OUT or - st_valid_5_rl or - st_valid_6_dummy2_0$Q_OUT or - st_valid_6_dummy2_1$Q_OUT or - st_valid_6_rl or - st_valid_7_dummy2_0$Q_OUT or - st_valid_7_dummy2_1$Q_OUT or - st_valid_7_rl or - st_valid_8_dummy2_0$Q_OUT or - st_valid_8_dummy2_1$Q_OUT or - st_valid_8_rl or - st_valid_9_dummy2_0$Q_OUT or - st_valid_9_dummy2_1$Q_OUT or - st_valid_9_rl or - st_valid_10_dummy2_0$Q_OUT or - st_valid_10_dummy2_1$Q_OUT or - st_valid_10_rl or - st_valid_11_dummy2_0$Q_OUT or - st_valid_11_dummy2_1$Q_OUT or - st_valid_11_rl or - st_valid_12_dummy2_0$Q_OUT or - st_valid_12_dummy2_1$Q_OUT or - st_valid_12_rl or - st_valid_13_dummy2_0$Q_OUT or - st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) - begin - case (ld_olderSt_23_rl[3:0]) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || - !st_valid_0_rl; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || - !st_valid_1_rl; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || - !st_valid_2_rl; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || - !st_valid_3_rl; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || - !st_valid_4_rl; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || - !st_valid_5_rl; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || - !st_valid_6_rl; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || - !st_valid_7_rl; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || - !st_valid_8_rl; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || - !st_valid_9_rl; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || - !st_valid_10_rl; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || - !st_valid_11_rl; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || - !st_valid_12_rl; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || - !st_valid_13_rl; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = - 1'b0 /* unspecified value */ ; - endcase - end always@(ld_olderSt_23_rl or st_verified_0_dummy2_0$Q_OUT or st_verified_0_dummy2_1$Q_OUT or @@ -76593,6 +76489,110 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(ld_olderSt_23_rl or + st_valid_0_dummy2_0$Q_OUT or + st_valid_0_dummy2_1$Q_OUT or + st_valid_0_rl or + st_valid_1_dummy2_0$Q_OUT or + st_valid_1_dummy2_1$Q_OUT or + st_valid_1_rl or + st_valid_2_dummy2_0$Q_OUT or + st_valid_2_dummy2_1$Q_OUT or + st_valid_2_rl or + st_valid_3_dummy2_0$Q_OUT or + st_valid_3_dummy2_1$Q_OUT or + st_valid_3_rl or + st_valid_4_dummy2_0$Q_OUT or + st_valid_4_dummy2_1$Q_OUT or + st_valid_4_rl or + st_valid_5_dummy2_0$Q_OUT or + st_valid_5_dummy2_1$Q_OUT or + st_valid_5_rl or + st_valid_6_dummy2_0$Q_OUT or + st_valid_6_dummy2_1$Q_OUT or + st_valid_6_rl or + st_valid_7_dummy2_0$Q_OUT or + st_valid_7_dummy2_1$Q_OUT or + st_valid_7_rl or + st_valid_8_dummy2_0$Q_OUT or + st_valid_8_dummy2_1$Q_OUT or + st_valid_8_rl or + st_valid_9_dummy2_0$Q_OUT or + st_valid_9_dummy2_1$Q_OUT or + st_valid_9_rl or + st_valid_10_dummy2_0$Q_OUT or + st_valid_10_dummy2_1$Q_OUT or + st_valid_10_rl or + st_valid_11_dummy2_0$Q_OUT or + st_valid_11_dummy2_1$Q_OUT or + st_valid_11_rl or + st_valid_12_dummy2_0$Q_OUT or + st_valid_12_dummy2_1$Q_OUT or + st_valid_12_rl or + st_valid_13_dummy2_0$Q_OUT or + st_valid_13_dummy2_1$Q_OUT or st_valid_13_rl) + begin + case (ld_olderSt_23_rl[3:0]) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_0_dummy2_0$Q_OUT || !st_valid_0_dummy2_1$Q_OUT || + !st_valid_0_rl; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_1_dummy2_0$Q_OUT || !st_valid_1_dummy2_1$Q_OUT || + !st_valid_1_rl; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_2_dummy2_0$Q_OUT || !st_valid_2_dummy2_1$Q_OUT || + !st_valid_2_rl; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_3_dummy2_0$Q_OUT || !st_valid_3_dummy2_1$Q_OUT || + !st_valid_3_rl; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_4_dummy2_0$Q_OUT || !st_valid_4_dummy2_1$Q_OUT || + !st_valid_4_rl; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_5_dummy2_0$Q_OUT || !st_valid_5_dummy2_1$Q_OUT || + !st_valid_5_rl; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_6_dummy2_0$Q_OUT || !st_valid_6_dummy2_1$Q_OUT || + !st_valid_6_rl; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_7_dummy2_0$Q_OUT || !st_valid_7_dummy2_1$Q_OUT || + !st_valid_7_rl; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_8_dummy2_0$Q_OUT || !st_valid_8_dummy2_1$Q_OUT || + !st_valid_8_rl; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_9_dummy2_0$Q_OUT || !st_valid_9_dummy2_1$Q_OUT || + !st_valid_9_rl; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_10_dummy2_0$Q_OUT || !st_valid_10_dummy2_1$Q_OUT || + !st_valid_10_rl; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_11_dummy2_0$Q_OUT || !st_valid_11_dummy2_1$Q_OUT || + !st_valid_11_rl; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_12_dummy2_0$Q_OUT || !st_valid_12_dummy2_1$Q_OUT || + !st_valid_12_rl; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + !st_valid_13_dummy2_0$Q_OUT || !st_valid_13_dummy2_1$Q_OUT || + !st_valid_13_rl; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d18876 = + 1'b0 /* unspecified value */ ; + endcase + end always@(getOrigBE_t or st_byteEn_0 or st_byteEn_1 or @@ -77222,6 +77222,66 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(getOrigBE_t or + st_byteEn_0 or + st_byteEn_1 or + st_byteEn_2 or + st_byteEn_3 or + st_byteEn_4 or + st_byteEn_5 or + st_byteEn_6 or + st_byteEn_7 or + st_byteEn_8 or + st_byteEn_9 or + st_byteEn_10 or st_byteEn_11 or st_byteEn_12 or st_byteEn_13) + begin + case (getOrigBE_t[3:0]) + 4'd0: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_0[4]; + 4'd1: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_1[4]; + 4'd2: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_2[4]; + 4'd3: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_3[4]; + 4'd4: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_4[4]; + 4'd5: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_5[4]; + 4'd6: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_6[4]; + 4'd7: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_7[4]; + 4'd8: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_8[4]; + 4'd9: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_9[4]; + 4'd10: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_10[4]; + 4'd11: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_11[4]; + 4'd12: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_12[4]; + 4'd13: + SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + st_byteEn_13[4]; + default: SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + 1'b0 /* unspecified value */ ; + endcase + end always@(tag__h848913 or ld_shiftedBE_0_dummy2_0$Q_OUT or ld_shiftedBE_0_dummy2_1$Q_OUT or @@ -77435,48 +77495,48 @@ module mkSplitLSQ(CLK, begin case (getOrigBE_t[3:0]) 4'd0: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_0[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_0[3]; 4'd1: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_1[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_1[3]; 4'd2: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_2[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_2[3]; 4'd3: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_3[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_3[3]; 4'd4: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_4[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_4[3]; 4'd5: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_5[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_5[3]; 4'd6: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_6[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_6[3]; 4'd7: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_7[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_7[3]; 4'd8: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_8[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_8[3]; 4'd9: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_9[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_9[3]; 4'd10: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_10[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_10[3]; 4'd11: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_11[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_11[3]; 4'd12: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_12[4]; + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_12[3]; 4'd13: - SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = - st_byteEn_13[4]; - default: SEL_ARR_st_byteEn_0_9112_BIT_4_9176_st_byteEn__ETC___d19191 = + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = + st_byteEn_13[3]; + default: SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = 1'b0 /* unspecified value */ ; endcase end @@ -77678,66 +77738,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(getOrigBE_t or - st_byteEn_0 or - st_byteEn_1 or - st_byteEn_2 or - st_byteEn_3 or - st_byteEn_4 or - st_byteEn_5 or - st_byteEn_6 or - st_byteEn_7 or - st_byteEn_8 or - st_byteEn_9 or - st_byteEn_10 or st_byteEn_11 or st_byteEn_12 or st_byteEn_13) - begin - case (getOrigBE_t[3:0]) - 4'd0: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_0[3]; - 4'd1: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_1[3]; - 4'd2: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_2[3]; - 4'd3: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_3[3]; - 4'd4: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_4[3]; - 4'd5: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_5[3]; - 4'd6: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_6[3]; - 4'd7: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_7[3]; - 4'd8: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_8[3]; - 4'd9: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_9[3]; - 4'd10: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_10[3]; - 4'd11: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_11[3]; - 4'd12: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_12[3]; - 4'd13: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - st_byteEn_13[3]; - default: SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d19208 = - 1'b0 /* unspecified value */ ; - endcase - end always@(getOrigBE_t or st_byteEn_0 or st_byteEn_1 or @@ -78194,106 +78194,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(getOrigBE_t or - ld_byteEn_0 or - ld_byteEn_1 or - ld_byteEn_2 or - ld_byteEn_3 or - ld_byteEn_4 or - ld_byteEn_5 or - ld_byteEn_6 or - ld_byteEn_7 or - ld_byteEn_8 or - ld_byteEn_9 or - ld_byteEn_10 or - ld_byteEn_11 or - ld_byteEn_12 or - ld_byteEn_13 or - ld_byteEn_14 or - ld_byteEn_15 or - ld_byteEn_16 or - ld_byteEn_17 or - ld_byteEn_18 or - ld_byteEn_19 or - ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) - begin - case (getOrigBE_t[4:0]) - 5'd0: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_0[6]; - 5'd1: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_1[6]; - 5'd2: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_2[6]; - 5'd3: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_3[6]; - 5'd4: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_4[6]; - 5'd5: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_5[6]; - 5'd6: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_6[6]; - 5'd7: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_7[6]; - 5'd8: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_8[6]; - 5'd9: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_9[6]; - 5'd10: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_10[6]; - 5'd11: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_11[6]; - 5'd12: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_12[6]; - 5'd13: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_13[6]; - 5'd14: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_14[6]; - 5'd15: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_15[6]; - 5'd16: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_16[6]; - 5'd17: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_17[6]; - 5'd18: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_18[6]; - 5'd19: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_19[6]; - 5'd20: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_20[6]; - 5'd21: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_21[6]; - 5'd22: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_22[6]; - 5'd23: - SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - ld_byteEn_23[6]; - default: SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = - 1'b0 /* unspecified value */ ; - endcase - end always@(getOrigBE_t or ld_byteEn_0 or ld_byteEn_1 or @@ -78394,6 +78294,106 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(getOrigBE_t or + ld_byteEn_0 or + ld_byteEn_1 or + ld_byteEn_2 or + ld_byteEn_3 or + ld_byteEn_4 or + ld_byteEn_5 or + ld_byteEn_6 or + ld_byteEn_7 or + ld_byteEn_8 or + ld_byteEn_9 or + ld_byteEn_10 or + ld_byteEn_11 or + ld_byteEn_12 or + ld_byteEn_13 or + ld_byteEn_14 or + ld_byteEn_15 or + ld_byteEn_16 or + ld_byteEn_17 or + ld_byteEn_18 or + ld_byteEn_19 or + ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) + begin + case (getOrigBE_t[4:0]) + 5'd0: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_0[6]; + 5'd1: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_1[6]; + 5'd2: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_2[6]; + 5'd3: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_3[6]; + 5'd4: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_4[6]; + 5'd5: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_5[6]; + 5'd6: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_6[6]; + 5'd7: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_7[6]; + 5'd8: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_8[6]; + 5'd9: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_9[6]; + 5'd10: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_10[6]; + 5'd11: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_11[6]; + 5'd12: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_12[6]; + 5'd13: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_13[6]; + 5'd14: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_14[6]; + 5'd15: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_15[6]; + 5'd16: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_16[6]; + 5'd17: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_17[6]; + 5'd18: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_18[6]; + 5'd19: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_19[6]; + 5'd20: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_20[6]; + 5'd21: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_21[6]; + 5'd22: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_22[6]; + 5'd23: + SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + ld_byteEn_23[6]; + default: SEL_ARR_ld_byteEn_0_9259_BIT_6_9310_ld_byteEn__ETC___d19335 = + 1'b0 /* unspecified value */ ; + endcase + end always@(getOrigBE_t or ld_byteEn_0 or ld_byteEn_1 or @@ -78494,106 +78494,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(getOrigBE_t or - ld_byteEn_0 or - ld_byteEn_1 or - ld_byteEn_2 or - ld_byteEn_3 or - ld_byteEn_4 or - ld_byteEn_5 or - ld_byteEn_6 or - ld_byteEn_7 or - ld_byteEn_8 or - ld_byteEn_9 or - ld_byteEn_10 or - ld_byteEn_11 or - ld_byteEn_12 or - ld_byteEn_13 or - ld_byteEn_14 or - ld_byteEn_15 or - ld_byteEn_16 or - ld_byteEn_17 or - ld_byteEn_18 or - ld_byteEn_19 or - ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) - begin - case (getOrigBE_t[4:0]) - 5'd0: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_0[4]; - 5'd1: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_1[4]; - 5'd2: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_2[4]; - 5'd3: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_3[4]; - 5'd4: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_4[4]; - 5'd5: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_5[4]; - 5'd6: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_6[4]; - 5'd7: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_7[4]; - 5'd8: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_8[4]; - 5'd9: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_9[4]; - 5'd10: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_10[4]; - 5'd11: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_11[4]; - 5'd12: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_12[4]; - 5'd13: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_13[4]; - 5'd14: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_14[4]; - 5'd15: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_15[4]; - 5'd16: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_16[4]; - 5'd17: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_17[4]; - 5'd18: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_18[4]; - 5'd19: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_19[4]; - 5'd20: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_20[4]; - 5'd21: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_21[4]; - 5'd22: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_22[4]; - 5'd23: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - ld_byteEn_23[4]; - default: SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = - 1'b0 /* unspecified value */ ; - endcase - end always@(getOrigBE_t or ld_byteEn_0 or ld_byteEn_1 or @@ -78694,6 +78594,106 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(getOrigBE_t or + ld_byteEn_0 or + ld_byteEn_1 or + ld_byteEn_2 or + ld_byteEn_3 or + ld_byteEn_4 or + ld_byteEn_5 or + ld_byteEn_6 or + ld_byteEn_7 or + ld_byteEn_8 or + ld_byteEn_9 or + ld_byteEn_10 or + ld_byteEn_11 or + ld_byteEn_12 or + ld_byteEn_13 or + ld_byteEn_14 or + ld_byteEn_15 or + ld_byteEn_16 or + ld_byteEn_17 or + ld_byteEn_18 or + ld_byteEn_19 or + ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) + begin + case (getOrigBE_t[4:0]) + 5'd0: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_0[4]; + 5'd1: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_1[4]; + 5'd2: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_2[4]; + 5'd3: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_3[4]; + 5'd4: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_4[4]; + 5'd5: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_5[4]; + 5'd6: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_6[4]; + 5'd7: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_7[4]; + 5'd8: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_8[4]; + 5'd9: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_9[4]; + 5'd10: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_10[4]; + 5'd11: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_11[4]; + 5'd12: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_12[4]; + 5'd13: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_13[4]; + 5'd14: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_14[4]; + 5'd15: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_15[4]; + 5'd16: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_16[4]; + 5'd17: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_17[4]; + 5'd18: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_18[4]; + 5'd19: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_19[4]; + 5'd20: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_20[4]; + 5'd21: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_21[4]; + 5'd22: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_22[4]; + 5'd23: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + ld_byteEn_23[4]; + default: SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d19388 = + 1'b0 /* unspecified value */ ; + endcase + end always@(getOrigBE_t or ld_byteEn_0 or ld_byteEn_1 or @@ -78952,65 +78952,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(getHit_t or - st_dst_0 or - st_dst_1 or - st_dst_2 or - st_dst_3 or - st_dst_4 or - st_dst_5 or - st_dst_6 or - st_dst_7 or - st_dst_8 or - st_dst_9 or st_dst_10 or st_dst_11 or st_dst_12 or st_dst_13) - begin - case (getHit_t[3:0]) - 4'd0: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_0[7:1]; - 4'd1: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_1[7:1]; - 4'd2: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_2[7:1]; - 4'd3: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_3[7:1]; - 4'd4: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_4[7:1]; - 4'd5: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_5[7:1]; - 4'd6: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_6[7:1]; - 4'd7: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_7[7:1]; - 4'd8: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_8[7:1]; - 4'd9: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_9[7:1]; - 4'd10: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_10[7:1]; - 4'd11: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_11[7:1]; - 4'd12: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_12[7:1]; - 4'd13: - SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - st_dst_13[7:1]; - default: SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = - 7'b0101010 /* unspecified value */ ; - endcase - end always@(getHit_t or ld_dst_0 or ld_dst_1 or @@ -79110,6 +79051,65 @@ module mkSplitLSQ(CLK, 7'b0101010 /* unspecified value */ ; endcase end + always@(getHit_t or + st_dst_0 or + st_dst_1 or + st_dst_2 or + st_dst_3 or + st_dst_4 or + st_dst_5 or + st_dst_6 or + st_dst_7 or + st_dst_8 or + st_dst_9 or st_dst_10 or st_dst_11 or st_dst_12 or st_dst_13) + begin + case (getHit_t[3:0]) + 4'd0: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_0[7:1]; + 4'd1: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_1[7:1]; + 4'd2: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_2[7:1]; + 4'd3: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_3[7:1]; + 4'd4: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_4[7:1]; + 4'd5: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_5[7:1]; + 4'd6: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_6[7:1]; + 4'd7: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_7[7:1]; + 4'd8: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_8[7:1]; + 4'd9: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_9[7:1]; + 4'd10: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_10[7:1]; + 4'd11: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_11[7:1]; + 4'd12: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_12[7:1]; + 4'd13: + SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + st_dst_13[7:1]; + default: SEL_ARR_st_dst_0_9501_BITS_7_TO_1_9624_st_dst__ETC___d19639 = + 7'b0101010 /* unspecified value */ ; + endcase + end always@(updateAddr_lsqTag or st_valid_0_dummy2_0$Q_OUT or st_valid_0_dummy2_1$Q_OUT or @@ -82929,106 +82929,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h1062868 or - ld_byteEn_0 or - ld_byteEn_1 or - ld_byteEn_2 or - ld_byteEn_3 or - ld_byteEn_4 or - ld_byteEn_5 or - ld_byteEn_6 or - ld_byteEn_7 or - ld_byteEn_8 or - ld_byteEn_9 or - ld_byteEn_10 or - ld_byteEn_11 or - ld_byteEn_12 or - ld_byteEn_13 or - ld_byteEn_14 or - ld_byteEn_15 or - ld_byteEn_16 or - ld_byteEn_17 or - ld_byteEn_18 or - ld_byteEn_19 or - ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) - begin - case (x__h1062868) - 5'd0: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_0[4]; - 5'd1: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_1[4]; - 5'd2: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_2[4]; - 5'd3: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_3[4]; - 5'd4: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_4[4]; - 5'd5: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_5[4]; - 5'd6: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_6[4]; - 5'd7: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_7[4]; - 5'd8: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_8[4]; - 5'd9: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_9[4]; - 5'd10: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_10[4]; - 5'd11: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_11[4]; - 5'd12: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_12[4]; - 5'd13: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_13[4]; - 5'd14: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_14[4]; - 5'd15: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_15[4]; - 5'd16: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_16[4]; - 5'd17: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_17[4]; - 5'd18: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_18[4]; - 5'd19: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_19[4]; - 5'd20: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_20[4]; - 5'd21: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_21[4]; - 5'd22: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_22[4]; - 5'd23: - SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - ld_byteEn_23[4]; - default: SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or ld_byteEn_0 or ld_byteEn_1 or @@ -83129,6 +83029,106 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(x__h1062868 or + ld_byteEn_0 or + ld_byteEn_1 or + ld_byteEn_2 or + ld_byteEn_3 or + ld_byteEn_4 or + ld_byteEn_5 or + ld_byteEn_6 or + ld_byteEn_7 or + ld_byteEn_8 or + ld_byteEn_9 or + ld_byteEn_10 or + ld_byteEn_11 or + ld_byteEn_12 or + ld_byteEn_13 or + ld_byteEn_14 or + ld_byteEn_15 or + ld_byteEn_16 or + ld_byteEn_17 or + ld_byteEn_18 or + ld_byteEn_19 or + ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) + begin + case (x__h1062868) + 5'd0: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_0[4]; + 5'd1: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_1[4]; + 5'd2: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_2[4]; + 5'd3: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_3[4]; + 5'd4: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_4[4]; + 5'd5: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_5[4]; + 5'd6: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_6[4]; + 5'd7: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_7[4]; + 5'd8: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_8[4]; + 5'd9: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_9[4]; + 5'd10: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_10[4]; + 5'd11: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_11[4]; + 5'd12: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_12[4]; + 5'd13: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_13[4]; + 5'd14: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_14[4]; + 5'd15: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_15[4]; + 5'd16: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_16[4]; + 5'd17: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_17[4]; + 5'd18: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_18[4]; + 5'd19: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_19[4]; + 5'd20: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_20[4]; + 5'd21: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_21[4]; + 5'd22: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_22[4]; + 5'd23: + SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + ld_byteEn_23[4]; + default: SEL_ARR_ld_byteEn_0_9259_BIT_4_9363_ld_byteEn__ETC___d23899 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_byteEn_0 or ld_byteEn_1 or @@ -83427,6 +83427,204 @@ module mkSplitLSQ(CLK, 7'b0101010 /* unspecified value */ ; endcase end + always@(x__h1062868 or + ld_shiftedBE_0_dummy2_0$Q_OUT or + ld_shiftedBE_0_dummy2_1$Q_OUT or + ld_shiftedBE_0_rl or + ld_shiftedBE_1_dummy2_0$Q_OUT or + ld_shiftedBE_1_dummy2_1$Q_OUT or + ld_shiftedBE_1_rl or + ld_shiftedBE_2_dummy2_0$Q_OUT or + ld_shiftedBE_2_dummy2_1$Q_OUT or + ld_shiftedBE_2_rl or + ld_shiftedBE_3_dummy2_0$Q_OUT or + ld_shiftedBE_3_dummy2_1$Q_OUT or + ld_shiftedBE_3_rl or + ld_shiftedBE_4_dummy2_0$Q_OUT or + ld_shiftedBE_4_dummy2_1$Q_OUT or + ld_shiftedBE_4_rl or + ld_shiftedBE_5_dummy2_0$Q_OUT or + ld_shiftedBE_5_dummy2_1$Q_OUT or + ld_shiftedBE_5_rl or + ld_shiftedBE_6_dummy2_0$Q_OUT or + ld_shiftedBE_6_dummy2_1$Q_OUT or + ld_shiftedBE_6_rl or + ld_shiftedBE_7_dummy2_0$Q_OUT or + ld_shiftedBE_7_dummy2_1$Q_OUT or + ld_shiftedBE_7_rl or + ld_shiftedBE_8_dummy2_0$Q_OUT or + ld_shiftedBE_8_dummy2_1$Q_OUT or + ld_shiftedBE_8_rl or + ld_shiftedBE_9_dummy2_0$Q_OUT or + ld_shiftedBE_9_dummy2_1$Q_OUT or + ld_shiftedBE_9_rl or + ld_shiftedBE_10_dummy2_0$Q_OUT or + ld_shiftedBE_10_dummy2_1$Q_OUT or + ld_shiftedBE_10_rl or + ld_shiftedBE_11_dummy2_0$Q_OUT or + ld_shiftedBE_11_dummy2_1$Q_OUT or + ld_shiftedBE_11_rl or + ld_shiftedBE_12_dummy2_0$Q_OUT or + ld_shiftedBE_12_dummy2_1$Q_OUT or + ld_shiftedBE_12_rl or + ld_shiftedBE_13_dummy2_0$Q_OUT or + ld_shiftedBE_13_dummy2_1$Q_OUT or + ld_shiftedBE_13_rl or + ld_shiftedBE_14_dummy2_0$Q_OUT or + ld_shiftedBE_14_dummy2_1$Q_OUT or + ld_shiftedBE_14_rl or + ld_shiftedBE_15_dummy2_0$Q_OUT or + ld_shiftedBE_15_dummy2_1$Q_OUT or + ld_shiftedBE_15_rl or + ld_shiftedBE_16_dummy2_0$Q_OUT or + ld_shiftedBE_16_dummy2_1$Q_OUT or + ld_shiftedBE_16_rl or + ld_shiftedBE_17_dummy2_0$Q_OUT or + ld_shiftedBE_17_dummy2_1$Q_OUT or + ld_shiftedBE_17_rl or + ld_shiftedBE_18_dummy2_0$Q_OUT or + ld_shiftedBE_18_dummy2_1$Q_OUT or + ld_shiftedBE_18_rl or + ld_shiftedBE_19_dummy2_0$Q_OUT or + ld_shiftedBE_19_dummy2_1$Q_OUT or + ld_shiftedBE_19_rl or + ld_shiftedBE_20_dummy2_0$Q_OUT or + ld_shiftedBE_20_dummy2_1$Q_OUT or + ld_shiftedBE_20_rl or + ld_shiftedBE_21_dummy2_0$Q_OUT or + ld_shiftedBE_21_dummy2_1$Q_OUT or + ld_shiftedBE_21_rl or + ld_shiftedBE_22_dummy2_0$Q_OUT or + ld_shiftedBE_22_dummy2_1$Q_OUT or + ld_shiftedBE_22_rl or + ld_shiftedBE_23_dummy2_0$Q_OUT or + ld_shiftedBE_23_dummy2_1$Q_OUT or ld_shiftedBE_23_rl) + begin + case (x__h1062868) + 5'd0: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_0_dummy2_0$Q_OUT && + ld_shiftedBE_0_dummy2_1$Q_OUT && + ld_shiftedBE_0_rl[5]; + 5'd1: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_1_dummy2_0$Q_OUT && + ld_shiftedBE_1_dummy2_1$Q_OUT && + ld_shiftedBE_1_rl[5]; + 5'd2: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_2_dummy2_0$Q_OUT && + ld_shiftedBE_2_dummy2_1$Q_OUT && + ld_shiftedBE_2_rl[5]; + 5'd3: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_3_dummy2_0$Q_OUT && + ld_shiftedBE_3_dummy2_1$Q_OUT && + ld_shiftedBE_3_rl[5]; + 5'd4: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_4_dummy2_0$Q_OUT && + ld_shiftedBE_4_dummy2_1$Q_OUT && + ld_shiftedBE_4_rl[5]; + 5'd5: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_5_dummy2_0$Q_OUT && + ld_shiftedBE_5_dummy2_1$Q_OUT && + ld_shiftedBE_5_rl[5]; + 5'd6: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_6_dummy2_0$Q_OUT && + ld_shiftedBE_6_dummy2_1$Q_OUT && + ld_shiftedBE_6_rl[5]; + 5'd7: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_7_dummy2_0$Q_OUT && + ld_shiftedBE_7_dummy2_1$Q_OUT && + ld_shiftedBE_7_rl[5]; + 5'd8: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_8_dummy2_0$Q_OUT && + ld_shiftedBE_8_dummy2_1$Q_OUT && + ld_shiftedBE_8_rl[5]; + 5'd9: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_9_dummy2_0$Q_OUT && + ld_shiftedBE_9_dummy2_1$Q_OUT && + ld_shiftedBE_9_rl[5]; + 5'd10: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_10_dummy2_0$Q_OUT && + ld_shiftedBE_10_dummy2_1$Q_OUT && + ld_shiftedBE_10_rl[5]; + 5'd11: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_11_dummy2_0$Q_OUT && + ld_shiftedBE_11_dummy2_1$Q_OUT && + ld_shiftedBE_11_rl[5]; + 5'd12: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_12_dummy2_0$Q_OUT && + ld_shiftedBE_12_dummy2_1$Q_OUT && + ld_shiftedBE_12_rl[5]; + 5'd13: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_13_dummy2_0$Q_OUT && + ld_shiftedBE_13_dummy2_1$Q_OUT && + ld_shiftedBE_13_rl[5]; + 5'd14: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_14_dummy2_0$Q_OUT && + ld_shiftedBE_14_dummy2_1$Q_OUT && + ld_shiftedBE_14_rl[5]; + 5'd15: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_15_dummy2_0$Q_OUT && + ld_shiftedBE_15_dummy2_1$Q_OUT && + ld_shiftedBE_15_rl[5]; + 5'd16: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_16_dummy2_0$Q_OUT && + ld_shiftedBE_16_dummy2_1$Q_OUT && + ld_shiftedBE_16_rl[5]; + 5'd17: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_17_dummy2_0$Q_OUT && + ld_shiftedBE_17_dummy2_1$Q_OUT && + ld_shiftedBE_17_rl[5]; + 5'd18: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_18_dummy2_0$Q_OUT && + ld_shiftedBE_18_dummy2_1$Q_OUT && + ld_shiftedBE_18_rl[5]; + 5'd19: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_19_dummy2_0$Q_OUT && + ld_shiftedBE_19_dummy2_1$Q_OUT && + ld_shiftedBE_19_rl[5]; + 5'd20: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_20_dummy2_0$Q_OUT && + ld_shiftedBE_20_dummy2_1$Q_OUT && + ld_shiftedBE_20_rl[5]; + 5'd21: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_21_dummy2_0$Q_OUT && + ld_shiftedBE_21_dummy2_1$Q_OUT && + ld_shiftedBE_21_rl[5]; + 5'd22: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_22_dummy2_0$Q_OUT && + ld_shiftedBE_22_dummy2_1$Q_OUT && + ld_shiftedBE_22_rl[5]; + 5'd23: + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_23_dummy2_0$Q_OUT && + ld_shiftedBE_23_dummy2_1$Q_OUT && + ld_shiftedBE_23_rl[5]; + default: SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_shiftedBE_0_dummy2_0$Q_OUT or ld_shiftedBE_0_dummy2_1$Q_OUT or @@ -83898,126 +84096,126 @@ module mkSplitLSQ(CLK, begin case (x__h1062868) 5'd0: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_0_dummy2_0$Q_OUT && ld_shiftedBE_0_dummy2_1$Q_OUT && - ld_shiftedBE_0_rl[5]; + ld_shiftedBE_0_rl[4]; 5'd1: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_1_dummy2_0$Q_OUT && ld_shiftedBE_1_dummy2_1$Q_OUT && - ld_shiftedBE_1_rl[5]; + ld_shiftedBE_1_rl[4]; 5'd2: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_2_dummy2_0$Q_OUT && ld_shiftedBE_2_dummy2_1$Q_OUT && - ld_shiftedBE_2_rl[5]; + ld_shiftedBE_2_rl[4]; 5'd3: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_3_dummy2_0$Q_OUT && ld_shiftedBE_3_dummy2_1$Q_OUT && - ld_shiftedBE_3_rl[5]; + ld_shiftedBE_3_rl[4]; 5'd4: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_4_dummy2_0$Q_OUT && ld_shiftedBE_4_dummy2_1$Q_OUT && - ld_shiftedBE_4_rl[5]; + ld_shiftedBE_4_rl[4]; 5'd5: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_5_dummy2_0$Q_OUT && ld_shiftedBE_5_dummy2_1$Q_OUT && - ld_shiftedBE_5_rl[5]; + ld_shiftedBE_5_rl[4]; 5'd6: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_6_dummy2_0$Q_OUT && ld_shiftedBE_6_dummy2_1$Q_OUT && - ld_shiftedBE_6_rl[5]; + ld_shiftedBE_6_rl[4]; 5'd7: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_7_dummy2_0$Q_OUT && ld_shiftedBE_7_dummy2_1$Q_OUT && - ld_shiftedBE_7_rl[5]; + ld_shiftedBE_7_rl[4]; 5'd8: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_8_dummy2_0$Q_OUT && ld_shiftedBE_8_dummy2_1$Q_OUT && - ld_shiftedBE_8_rl[5]; + ld_shiftedBE_8_rl[4]; 5'd9: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_9_dummy2_0$Q_OUT && ld_shiftedBE_9_dummy2_1$Q_OUT && - ld_shiftedBE_9_rl[5]; + ld_shiftedBE_9_rl[4]; 5'd10: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_10_dummy2_0$Q_OUT && ld_shiftedBE_10_dummy2_1$Q_OUT && - ld_shiftedBE_10_rl[5]; + ld_shiftedBE_10_rl[4]; 5'd11: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_11_dummy2_0$Q_OUT && ld_shiftedBE_11_dummy2_1$Q_OUT && - ld_shiftedBE_11_rl[5]; + ld_shiftedBE_11_rl[4]; 5'd12: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_12_dummy2_0$Q_OUT && ld_shiftedBE_12_dummy2_1$Q_OUT && - ld_shiftedBE_12_rl[5]; + ld_shiftedBE_12_rl[4]; 5'd13: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_13_dummy2_0$Q_OUT && ld_shiftedBE_13_dummy2_1$Q_OUT && - ld_shiftedBE_13_rl[5]; + ld_shiftedBE_13_rl[4]; 5'd14: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_14_dummy2_0$Q_OUT && ld_shiftedBE_14_dummy2_1$Q_OUT && - ld_shiftedBE_14_rl[5]; + ld_shiftedBE_14_rl[4]; 5'd15: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_15_dummy2_0$Q_OUT && ld_shiftedBE_15_dummy2_1$Q_OUT && - ld_shiftedBE_15_rl[5]; + ld_shiftedBE_15_rl[4]; 5'd16: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_16_dummy2_0$Q_OUT && ld_shiftedBE_16_dummy2_1$Q_OUT && - ld_shiftedBE_16_rl[5]; + ld_shiftedBE_16_rl[4]; 5'd17: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_17_dummy2_0$Q_OUT && ld_shiftedBE_17_dummy2_1$Q_OUT && - ld_shiftedBE_17_rl[5]; + ld_shiftedBE_17_rl[4]; 5'd18: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_18_dummy2_0$Q_OUT && ld_shiftedBE_18_dummy2_1$Q_OUT && - ld_shiftedBE_18_rl[5]; + ld_shiftedBE_18_rl[4]; 5'd19: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_19_dummy2_0$Q_OUT && ld_shiftedBE_19_dummy2_1$Q_OUT && - ld_shiftedBE_19_rl[5]; + ld_shiftedBE_19_rl[4]; 5'd20: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_20_dummy2_0$Q_OUT && ld_shiftedBE_20_dummy2_1$Q_OUT && - ld_shiftedBE_20_rl[5]; + ld_shiftedBE_20_rl[4]; 5'd21: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_21_dummy2_0$Q_OUT && ld_shiftedBE_21_dummy2_1$Q_OUT && - ld_shiftedBE_21_rl[5]; + ld_shiftedBE_21_rl[4]; 5'd22: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_22_dummy2_0$Q_OUT && ld_shiftedBE_22_dummy2_1$Q_OUT && - ld_shiftedBE_22_rl[5]; + ld_shiftedBE_22_rl[4]; 5'd23: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = ld_shiftedBE_23_dummy2_0$Q_OUT && ld_shiftedBE_23_dummy2_1$Q_OUT && - ld_shiftedBE_23_rl[5]; - default: SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23945 = + ld_shiftedBE_23_rl[4]; + default: SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = 1'b0 /* unspecified value */ ; endcase end @@ -84219,204 +84417,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h1062868 or - ld_shiftedBE_0_dummy2_0$Q_OUT or - ld_shiftedBE_0_dummy2_1$Q_OUT or - ld_shiftedBE_0_rl or - ld_shiftedBE_1_dummy2_0$Q_OUT or - ld_shiftedBE_1_dummy2_1$Q_OUT or - ld_shiftedBE_1_rl or - ld_shiftedBE_2_dummy2_0$Q_OUT or - ld_shiftedBE_2_dummy2_1$Q_OUT or - ld_shiftedBE_2_rl or - ld_shiftedBE_3_dummy2_0$Q_OUT or - ld_shiftedBE_3_dummy2_1$Q_OUT or - ld_shiftedBE_3_rl or - ld_shiftedBE_4_dummy2_0$Q_OUT or - ld_shiftedBE_4_dummy2_1$Q_OUT or - ld_shiftedBE_4_rl or - ld_shiftedBE_5_dummy2_0$Q_OUT or - ld_shiftedBE_5_dummy2_1$Q_OUT or - ld_shiftedBE_5_rl or - ld_shiftedBE_6_dummy2_0$Q_OUT or - ld_shiftedBE_6_dummy2_1$Q_OUT or - ld_shiftedBE_6_rl or - ld_shiftedBE_7_dummy2_0$Q_OUT or - ld_shiftedBE_7_dummy2_1$Q_OUT or - ld_shiftedBE_7_rl or - ld_shiftedBE_8_dummy2_0$Q_OUT or - ld_shiftedBE_8_dummy2_1$Q_OUT or - ld_shiftedBE_8_rl or - ld_shiftedBE_9_dummy2_0$Q_OUT or - ld_shiftedBE_9_dummy2_1$Q_OUT or - ld_shiftedBE_9_rl or - ld_shiftedBE_10_dummy2_0$Q_OUT or - ld_shiftedBE_10_dummy2_1$Q_OUT or - ld_shiftedBE_10_rl or - ld_shiftedBE_11_dummy2_0$Q_OUT or - ld_shiftedBE_11_dummy2_1$Q_OUT or - ld_shiftedBE_11_rl or - ld_shiftedBE_12_dummy2_0$Q_OUT or - ld_shiftedBE_12_dummy2_1$Q_OUT or - ld_shiftedBE_12_rl or - ld_shiftedBE_13_dummy2_0$Q_OUT or - ld_shiftedBE_13_dummy2_1$Q_OUT or - ld_shiftedBE_13_rl or - ld_shiftedBE_14_dummy2_0$Q_OUT or - ld_shiftedBE_14_dummy2_1$Q_OUT or - ld_shiftedBE_14_rl or - ld_shiftedBE_15_dummy2_0$Q_OUT or - ld_shiftedBE_15_dummy2_1$Q_OUT or - ld_shiftedBE_15_rl or - ld_shiftedBE_16_dummy2_0$Q_OUT or - ld_shiftedBE_16_dummy2_1$Q_OUT or - ld_shiftedBE_16_rl or - ld_shiftedBE_17_dummy2_0$Q_OUT or - ld_shiftedBE_17_dummy2_1$Q_OUT or - ld_shiftedBE_17_rl or - ld_shiftedBE_18_dummy2_0$Q_OUT or - ld_shiftedBE_18_dummy2_1$Q_OUT or - ld_shiftedBE_18_rl or - ld_shiftedBE_19_dummy2_0$Q_OUT or - ld_shiftedBE_19_dummy2_1$Q_OUT or - ld_shiftedBE_19_rl or - ld_shiftedBE_20_dummy2_0$Q_OUT or - ld_shiftedBE_20_dummy2_1$Q_OUT or - ld_shiftedBE_20_rl or - ld_shiftedBE_21_dummy2_0$Q_OUT or - ld_shiftedBE_21_dummy2_1$Q_OUT or - ld_shiftedBE_21_rl or - ld_shiftedBE_22_dummy2_0$Q_OUT or - ld_shiftedBE_22_dummy2_1$Q_OUT or - ld_shiftedBE_22_rl or - ld_shiftedBE_23_dummy2_0$Q_OUT or - ld_shiftedBE_23_dummy2_1$Q_OUT or ld_shiftedBE_23_rl) - begin - case (x__h1062868) - 5'd0: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_0_dummy2_0$Q_OUT && - ld_shiftedBE_0_dummy2_1$Q_OUT && - ld_shiftedBE_0_rl[4]; - 5'd1: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_1_dummy2_0$Q_OUT && - ld_shiftedBE_1_dummy2_1$Q_OUT && - ld_shiftedBE_1_rl[4]; - 5'd2: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_2_dummy2_0$Q_OUT && - ld_shiftedBE_2_dummy2_1$Q_OUT && - ld_shiftedBE_2_rl[4]; - 5'd3: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_3_dummy2_0$Q_OUT && - ld_shiftedBE_3_dummy2_1$Q_OUT && - ld_shiftedBE_3_rl[4]; - 5'd4: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_4_dummy2_0$Q_OUT && - ld_shiftedBE_4_dummy2_1$Q_OUT && - ld_shiftedBE_4_rl[4]; - 5'd5: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_5_dummy2_0$Q_OUT && - ld_shiftedBE_5_dummy2_1$Q_OUT && - ld_shiftedBE_5_rl[4]; - 5'd6: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_6_dummy2_0$Q_OUT && - ld_shiftedBE_6_dummy2_1$Q_OUT && - ld_shiftedBE_6_rl[4]; - 5'd7: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_7_dummy2_0$Q_OUT && - ld_shiftedBE_7_dummy2_1$Q_OUT && - ld_shiftedBE_7_rl[4]; - 5'd8: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_8_dummy2_0$Q_OUT && - ld_shiftedBE_8_dummy2_1$Q_OUT && - ld_shiftedBE_8_rl[4]; - 5'd9: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_9_dummy2_0$Q_OUT && - ld_shiftedBE_9_dummy2_1$Q_OUT && - ld_shiftedBE_9_rl[4]; - 5'd10: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_10_dummy2_0$Q_OUT && - ld_shiftedBE_10_dummy2_1$Q_OUT && - ld_shiftedBE_10_rl[4]; - 5'd11: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_11_dummy2_0$Q_OUT && - ld_shiftedBE_11_dummy2_1$Q_OUT && - ld_shiftedBE_11_rl[4]; - 5'd12: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_12_dummy2_0$Q_OUT && - ld_shiftedBE_12_dummy2_1$Q_OUT && - ld_shiftedBE_12_rl[4]; - 5'd13: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_13_dummy2_0$Q_OUT && - ld_shiftedBE_13_dummy2_1$Q_OUT && - ld_shiftedBE_13_rl[4]; - 5'd14: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_14_dummy2_0$Q_OUT && - ld_shiftedBE_14_dummy2_1$Q_OUT && - ld_shiftedBE_14_rl[4]; - 5'd15: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_15_dummy2_0$Q_OUT && - ld_shiftedBE_15_dummy2_1$Q_OUT && - ld_shiftedBE_15_rl[4]; - 5'd16: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_16_dummy2_0$Q_OUT && - ld_shiftedBE_16_dummy2_1$Q_OUT && - ld_shiftedBE_16_rl[4]; - 5'd17: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_17_dummy2_0$Q_OUT && - ld_shiftedBE_17_dummy2_1$Q_OUT && - ld_shiftedBE_17_rl[4]; - 5'd18: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_18_dummy2_0$Q_OUT && - ld_shiftedBE_18_dummy2_1$Q_OUT && - ld_shiftedBE_18_rl[4]; - 5'd19: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_19_dummy2_0$Q_OUT && - ld_shiftedBE_19_dummy2_1$Q_OUT && - ld_shiftedBE_19_rl[4]; - 5'd20: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_20_dummy2_0$Q_OUT && - ld_shiftedBE_20_dummy2_1$Q_OUT && - ld_shiftedBE_20_rl[4]; - 5'd21: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_21_dummy2_0$Q_OUT && - ld_shiftedBE_21_dummy2_1$Q_OUT && - ld_shiftedBE_21_rl[4]; - 5'd22: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_22_dummy2_0$Q_OUT && - ld_shiftedBE_22_dummy2_1$Q_OUT && - ld_shiftedBE_22_rl[4]; - 5'd23: - SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - ld_shiftedBE_23_dummy2_0$Q_OUT && - ld_shiftedBE_23_dummy2_1$Q_OUT && - ld_shiftedBE_23_rl[4]; - default: SEL_ARR_ld_shiftedBE_0_dummy2_0_read__4892_AND_ETC___d23946 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or ld_shiftedBE_0_dummy2_0$Q_OUT or ld_shiftedBE_0_dummy2_1$Q_OUT or @@ -84821,22 +84821,6 @@ module mkSplitLSQ(CLK, 4'd13; endcase end - always@(ld_fault_2_rl) - begin - case (ld_fault_2_rl[3:0]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = - ld_fault_2_rl[3:0]; - 4'd11: - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = 4'd10; - 4'd12: - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = 4'd11; - 4'd13: - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = 4'd12; - default: IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = - 4'd13; - endcase - end always@(ld_fault_3_rl) begin case (ld_fault_3_rl[3:0]) @@ -84853,6 +84837,22 @@ module mkSplitLSQ(CLK, 4'd13; endcase end + always@(ld_fault_2_rl) + begin + case (ld_fault_2_rl[3:0]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = + ld_fault_2_rl[3:0]; + 4'd11: + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = 4'd10; + 4'd12: + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = 4'd11; + 4'd13: + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = 4'd12; + default: IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 = + 4'd13; + endcase + end always@(ld_fault_4_rl) begin case (ld_fault_4_rl[3:0]) @@ -84933,22 +84933,6 @@ module mkSplitLSQ(CLK, 4'd13; endcase end - always@(ld_fault_10_rl) - begin - case (ld_fault_10_rl[3:0]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = - ld_fault_10_rl[3:0]; - 4'd11: - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = 4'd10; - 4'd12: - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = 4'd11; - 4'd13: - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = 4'd12; - default: IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = - 4'd13; - endcase - end always@(ld_fault_9_rl) begin case (ld_fault_9_rl[3:0]) @@ -84965,6 +84949,22 @@ module mkSplitLSQ(CLK, 4'd13; endcase end + always@(ld_fault_10_rl) + begin + case (ld_fault_10_rl[3:0]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = + ld_fault_10_rl[3:0]; + 4'd11: + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = 4'd10; + 4'd12: + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = 4'd11; + 4'd13: + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = 4'd12; + default: IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 = + 4'd13; + endcase + end always@(ld_fault_11_rl) begin case (ld_fault_11_rl[3:0]) @@ -85013,6 +85013,22 @@ module mkSplitLSQ(CLK, 4'd13; endcase end + always@(ld_fault_16_rl) + begin + case (ld_fault_16_rl[3:0]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = + ld_fault_16_rl[3:0]; + 4'd11: + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = 4'd10; + 4'd12: + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = 4'd11; + 4'd13: + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = 4'd12; + default: IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = + 4'd13; + endcase + end always@(ld_fault_14_rl) begin case (ld_fault_14_rl[3:0]) @@ -85045,19 +85061,19 @@ module mkSplitLSQ(CLK, 4'd13; endcase end - always@(ld_fault_16_rl) + always@(ld_fault_17_rl) begin - case (ld_fault_16_rl[3:0]) + case (ld_fault_17_rl[3:0]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = - ld_fault_16_rl[3:0]; + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = + ld_fault_17_rl[3:0]; 4'd11: - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = 4'd10; + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = 4'd10; 4'd12: - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = 4'd11; + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = 4'd11; 4'd13: - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = 4'd12; - default: IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 = + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = 4'd12; + default: IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = 4'd13; endcase end @@ -85077,22 +85093,6 @@ module mkSplitLSQ(CLK, 4'd13; endcase end - always@(ld_fault_17_rl) - begin - case (ld_fault_17_rl[3:0]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = - ld_fault_17_rl[3:0]; - 4'd11: - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = 4'd10; - 4'd12: - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = 4'd11; - 4'd13: - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = 4'd12; - default: IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 = - 4'd13; - endcase - end always@(ld_fault_19_rl) begin case (ld_fault_19_rl[3:0]) @@ -85109,22 +85109,6 @@ module mkSplitLSQ(CLK, 4'd13; endcase end - always@(ld_fault_21_rl) - begin - case (ld_fault_21_rl[3:0]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = - ld_fault_21_rl[3:0]; - 4'd11: - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = 4'd10; - 4'd12: - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = 4'd11; - 4'd13: - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = 4'd12; - default: IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = - 4'd13; - endcase - end always@(ld_fault_20_rl) begin case (ld_fault_20_rl[3:0]) @@ -85141,6 +85125,22 @@ module mkSplitLSQ(CLK, 4'd13; endcase end + always@(ld_fault_21_rl) + begin + case (ld_fault_21_rl[3:0]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = + ld_fault_21_rl[3:0]; + 4'd11: + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = 4'd10; + 4'd12: + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = 4'd11; + 4'd13: + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = 4'd12; + default: IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 = + 4'd13; + endcase + end always@(ld_fault_22_rl) begin case (ld_fault_22_rl[3:0]) @@ -86316,133 +86316,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h1062868 or - IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 or - IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 or - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 or - IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 or - IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 or - IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 or - IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 or - IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 or - IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 or - IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 or - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 or - IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 or - IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 or - IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 or - IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 or - IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 or - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 or - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 or - IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 or - IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 or - IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 or - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 or - IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 or - IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387) - begin - case (x__h1062868) - 5'd0: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 == - 4'd3; - 5'd1: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 == - 4'd3; - 5'd2: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 == - 4'd3; - 5'd3: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 == - 4'd3; - 5'd4: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 == - 4'd3; - 5'd5: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 == - 4'd3; - 5'd6: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 == - 4'd3; - 5'd7: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 == - 4'd3; - 5'd8: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 == - 4'd3; - 5'd9: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 == - 4'd3; - 5'd10: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 == - 4'd3; - 5'd11: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 == - 4'd3; - 5'd12: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 == - 4'd3; - 5'd13: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 == - 4'd3; - 5'd14: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 == - 4'd3; - 5'd15: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 == - 4'd3; - 5'd16: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 == - 4'd3; - 5'd17: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 == - 4'd3; - 5'd18: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 == - 4'd3; - 5'd19: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 == - 4'd3; - 5'd20: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 == - 4'd3; - 5'd21: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 == - 4'd3; - 5'd22: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 == - 4'd3; - 5'd23: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387 == - 4'd3; - default: SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 or IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 or @@ -86570,6 +86443,133 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(x__h1062868 or + IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 or + IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 or + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 or + IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 or + IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 or + IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 or + IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 or + IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 or + IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 or + IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 or + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 or + IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 or + IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 or + IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 or + IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 or + IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 or + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 or + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 or + IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 or + IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 or + IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 or + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 or + IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 or + IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387) + begin + case (x__h1062868) + 5'd0: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 == + 4'd3; + 5'd1: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 == + 4'd3; + 5'd2: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 == + 4'd3; + 5'd3: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 == + 4'd3; + 5'd4: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 == + 4'd3; + 5'd5: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 == + 4'd3; + 5'd6: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 == + 4'd3; + 5'd7: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 == + 4'd3; + 5'd8: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 == + 4'd3; + 5'd9: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 == + 4'd3; + 5'd10: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 == + 4'd3; + 5'd11: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 == + 4'd3; + 5'd12: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 == + 4'd3; + 5'd13: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 == + 4'd3; + 5'd14: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 == + 4'd3; + 5'd15: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 == + 4'd3; + 5'd16: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 == + 4'd3; + 5'd17: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 == + 4'd3; + 5'd18: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 == + 4'd3; + 5'd19: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 == + 4'd3; + 5'd20: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 == + 4'd3; + 5'd21: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 == + 4'd3; + 5'd22: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 == + 4'd3; + 5'd23: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387 == + 4'd3; + default: SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24468 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 or IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 or @@ -86697,133 +86697,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h1062868 or - IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 or - IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 or - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 or - IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 or - IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 or - IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 or - IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 or - IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 or - IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 or - IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 or - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 or - IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 or - IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 or - IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 or - IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 or - IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 or - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 or - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 or - IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 or - IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 or - IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 or - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 or - IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 or - IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387) - begin - case (x__h1062868) - 5'd0: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 == - 4'd0; - 5'd1: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 == - 4'd0; - 5'd2: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 == - 4'd0; - 5'd3: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 == - 4'd0; - 5'd4: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 == - 4'd0; - 5'd5: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 == - 4'd0; - 5'd6: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 == - 4'd0; - 5'd7: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 == - 4'd0; - 5'd8: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 == - 4'd0; - 5'd9: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 == - 4'd0; - 5'd10: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 == - 4'd0; - 5'd11: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 == - 4'd0; - 5'd12: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 == - 4'd0; - 5'd13: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 == - 4'd0; - 5'd14: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 == - 4'd0; - 5'd15: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 == - 4'd0; - 5'd16: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 == - 4'd0; - 5'd17: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 == - 4'd0; - 5'd18: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 == - 4'd0; - 5'd19: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 == - 4'd0; - 5'd20: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 == - 4'd0; - 5'd21: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 == - 4'd0; - 5'd22: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 == - 4'd0; - 5'd23: - SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387 == - 4'd0; - default: SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or ld_killed_0_dummy2_0$Q_OUT or ld_killed_0_dummy2_1$Q_OUT or @@ -87046,6 +86919,133 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(x__h1062868 or + IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 or + IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 or + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 or + IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 or + IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 or + IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 or + IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 or + IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 or + IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 or + IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 or + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 or + IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 or + IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 or + IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 or + IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 or + IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 or + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 or + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 or + IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 or + IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 or + IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 or + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 or + IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 or + IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387) + begin + case (x__h1062868) + 5'd0: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ_0_93_OR__ETC___d24065 == + 4'd0; + 5'd1: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_1_rl_77_BITS_3_TO_0_90_EQ_0_91_OR__ETC___d24079 == + 4'd0; + 5'd2: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_2_rl_75_BITS_3_TO_0_88_EQ_0_89_OR__ETC___d24093 == + 4'd0; + 5'd3: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_3_rl_73_BITS_3_TO_0_86_EQ_0_87_OR__ETC___d24107 == + 4'd0; + 5'd4: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_4_rl_071_BITS_3_TO_0_084_EQ_0_085__ETC___d24121 == + 4'd0; + 5'd5: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_5_rl_169_BITS_3_TO_0_182_EQ_0_183__ETC___d24135 == + 4'd0; + 5'd6: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_6_rl_267_BITS_3_TO_0_280_EQ_0_281__ETC___d24149 == + 4'd0; + 5'd7: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_7_rl_365_BITS_3_TO_0_378_EQ_0_379__ETC___d24163 == + 4'd0; + 5'd8: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_8_rl_463_BITS_3_TO_0_476_EQ_0_477__ETC___d24177 == + 4'd0; + 5'd9: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_9_rl_561_BITS_3_TO_0_574_EQ_0_575__ETC___d24191 == + 4'd0; + 5'd10: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_10_rl_659_BITS_3_TO_0_672_EQ_0_673_ETC___d24205 == + 4'd0; + 5'd11: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_11_rl_757_BITS_3_TO_0_770_EQ_0_771_ETC___d24219 == + 4'd0; + 5'd12: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_12_rl_855_BITS_3_TO_0_868_EQ_0_869_ETC___d24233 == + 4'd0; + 5'd13: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_13_rl_953_BITS_3_TO_0_966_EQ_0_967_ETC___d24247 == + 4'd0; + 5'd14: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_14_rl_051_BITS_3_TO_0_064_EQ_0_065_ETC___d24261 == + 4'd0; + 5'd15: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_15_rl_149_BITS_3_TO_0_162_EQ_0_163_ETC___d24275 == + 4'd0; + 5'd16: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_16_rl_247_BITS_3_TO_0_260_EQ_0_261_ETC___d24289 == + 4'd0; + 5'd17: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_17_rl_345_BITS_3_TO_0_358_EQ_0_359_ETC___d24303 == + 4'd0; + 5'd18: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_18_rl_443_BITS_3_TO_0_456_EQ_0_457_ETC___d24317 == + 4'd0; + 5'd19: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_19_rl_541_BITS_3_TO_0_554_EQ_0_555_ETC___d24331 == + 4'd0; + 5'd20: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_20_rl_639_BITS_3_TO_0_652_EQ_0_653_ETC___d24345 == + 4'd0; + 5'd21: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_21_rl_737_BITS_3_TO_0_750_EQ_0_751_ETC___d24359 == + 4'd0; + 5'd22: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_22_rl_835_BITS_3_TO_0_848_EQ_0_849_ETC___d24373 == + 4'd0; + 5'd23: + SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + IF_ld_fault_23_rl_933_BITS_3_TO_0_946_EQ_0_947_ETC___d24387 == + 4'd0; + default: SEL_ARR_IF_ld_fault_0_rl_79_BITS_3_TO_0_92_EQ__ETC___d24390 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_valid_0_dummy2_0$Q_OUT or ld_valid_0_dummy2_1$Q_OUT or @@ -87220,6 +87220,106 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(x__h1062868 or + ld_memFunc_0 or + ld_memFunc_1 or + ld_memFunc_2 or + ld_memFunc_3 or + ld_memFunc_4 or + ld_memFunc_5 or + ld_memFunc_6 or + ld_memFunc_7 or + ld_memFunc_8 or + ld_memFunc_9 or + ld_memFunc_10 or + ld_memFunc_11 or + ld_memFunc_12 or + ld_memFunc_13 or + ld_memFunc_14 or + ld_memFunc_15 or + ld_memFunc_16 or + ld_memFunc_17 or + ld_memFunc_18 or + ld_memFunc_19 or + ld_memFunc_20 or ld_memFunc_21 or ld_memFunc_22 or ld_memFunc_23) + begin + case (x__h1062868) + 5'd0: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_0; + 5'd1: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_1; + 5'd2: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_2; + 5'd3: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_3; + 5'd4: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_4; + 5'd5: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_5; + 5'd6: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_6; + 5'd7: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_7; + 5'd8: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_8; + 5'd9: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_9; + 5'd10: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_10; + 5'd11: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_11; + 5'd12: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_12; + 5'd13: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_13; + 5'd14: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_14; + 5'd15: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_15; + 5'd16: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_16; + 5'd17: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_17; + 5'd18: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_18; + 5'd19: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_19; + 5'd20: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_20; + 5'd21: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_21; + 5'd22: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_22; + 5'd23: + SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + !ld_memFunc_23; + default: SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_olderSt_0_dummy2_0$Q_OUT or ld_olderSt_0_dummy2_1$Q_OUT or @@ -87408,106 +87508,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h1062868 or - ld_memFunc_0 or - ld_memFunc_1 or - ld_memFunc_2 or - ld_memFunc_3 or - ld_memFunc_4 or - ld_memFunc_5 or - ld_memFunc_6 or - ld_memFunc_7 or - ld_memFunc_8 or - ld_memFunc_9 or - ld_memFunc_10 or - ld_memFunc_11 or - ld_memFunc_12 or - ld_memFunc_13 or - ld_memFunc_14 or - ld_memFunc_15 or - ld_memFunc_16 or - ld_memFunc_17 or - ld_memFunc_18 or - ld_memFunc_19 or - ld_memFunc_20 or ld_memFunc_21 or ld_memFunc_22 or ld_memFunc_23) - begin - case (x__h1062868) - 5'd0: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_0; - 5'd1: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_1; - 5'd2: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_2; - 5'd3: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_3; - 5'd4: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_4; - 5'd5: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_5; - 5'd6: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_6; - 5'd7: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_7; - 5'd8: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_8; - 5'd9: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_9; - 5'd10: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_10; - 5'd11: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_11; - 5'd12: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_12; - 5'd13: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_13; - 5'd14: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_14; - 5'd15: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_15; - 5'd16: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_16; - 5'd17: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_17; - 5'd18: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_18; - 5'd19: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_19; - 5'd20: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_20; - 5'd21: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_21; - 5'd22: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_22; - 5'd23: - SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - !ld_memFunc_23; - default: SEL_ARR_NOT_ld_memFunc_0_1633_1634_NOT_ld_memF_ETC___d24900 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or ld_done_0_dummy2_0$Q_OUT or ld_done_0_dummy2_1$Q_OUT or @@ -88841,132 +88841,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h1062868 or - ld_waitWPResp_0_dummy2_0$Q_OUT or - ld_waitWPResp_0_rl or - ld_waitWPResp_1_dummy2_0$Q_OUT or - ld_waitWPResp_1_rl or - ld_waitWPResp_2_dummy2_0$Q_OUT or - ld_waitWPResp_2_rl or - ld_waitWPResp_3_dummy2_0$Q_OUT or - ld_waitWPResp_3_rl or - ld_waitWPResp_4_dummy2_0$Q_OUT or - ld_waitWPResp_4_rl or - ld_waitWPResp_5_dummy2_0$Q_OUT or - ld_waitWPResp_5_rl or - ld_waitWPResp_6_dummy2_0$Q_OUT or - ld_waitWPResp_6_rl or - ld_waitWPResp_7_dummy2_0$Q_OUT or - ld_waitWPResp_7_rl or - ld_waitWPResp_8_dummy2_0$Q_OUT or - ld_waitWPResp_8_rl or - ld_waitWPResp_9_dummy2_0$Q_OUT or - ld_waitWPResp_9_rl or - ld_waitWPResp_10_dummy2_0$Q_OUT or - ld_waitWPResp_10_rl or - ld_waitWPResp_11_dummy2_0$Q_OUT or - ld_waitWPResp_11_rl or - ld_waitWPResp_12_dummy2_0$Q_OUT or - ld_waitWPResp_12_rl or - ld_waitWPResp_13_dummy2_0$Q_OUT or - ld_waitWPResp_13_rl or - ld_waitWPResp_14_dummy2_0$Q_OUT or - ld_waitWPResp_14_rl or - ld_waitWPResp_15_dummy2_0$Q_OUT or - ld_waitWPResp_15_rl or - ld_waitWPResp_16_dummy2_0$Q_OUT or - ld_waitWPResp_16_rl or - ld_waitWPResp_17_dummy2_0$Q_OUT or - ld_waitWPResp_17_rl or - ld_waitWPResp_18_dummy2_0$Q_OUT or - ld_waitWPResp_18_rl or - ld_waitWPResp_19_dummy2_0$Q_OUT or - ld_waitWPResp_19_rl or - ld_waitWPResp_20_dummy2_0$Q_OUT or - ld_waitWPResp_20_rl or - ld_waitWPResp_21_dummy2_0$Q_OUT or - ld_waitWPResp_21_rl or - ld_waitWPResp_22_dummy2_0$Q_OUT or - ld_waitWPResp_22_rl or - ld_waitWPResp_23_dummy2_0$Q_OUT or ld_waitWPResp_23_rl) - begin - case (x__h1062868) - 5'd0: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_0_dummy2_0$Q_OUT || !ld_waitWPResp_0_rl; - 5'd1: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_1_dummy2_0$Q_OUT || !ld_waitWPResp_1_rl; - 5'd2: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_2_dummy2_0$Q_OUT || !ld_waitWPResp_2_rl; - 5'd3: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_3_dummy2_0$Q_OUT || !ld_waitWPResp_3_rl; - 5'd4: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_4_dummy2_0$Q_OUT || !ld_waitWPResp_4_rl; - 5'd5: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_5_dummy2_0$Q_OUT || !ld_waitWPResp_5_rl; - 5'd6: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_6_dummy2_0$Q_OUT || !ld_waitWPResp_6_rl; - 5'd7: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_7_dummy2_0$Q_OUT || !ld_waitWPResp_7_rl; - 5'd8: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_8_dummy2_0$Q_OUT || !ld_waitWPResp_8_rl; - 5'd9: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_9_dummy2_0$Q_OUT || !ld_waitWPResp_9_rl; - 5'd10: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_10_dummy2_0$Q_OUT || !ld_waitWPResp_10_rl; - 5'd11: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_11_dummy2_0$Q_OUT || !ld_waitWPResp_11_rl; - 5'd12: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_12_dummy2_0$Q_OUT || !ld_waitWPResp_12_rl; - 5'd13: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_13_dummy2_0$Q_OUT || !ld_waitWPResp_13_rl; - 5'd14: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_14_dummy2_0$Q_OUT || !ld_waitWPResp_14_rl; - 5'd15: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_15_dummy2_0$Q_OUT || !ld_waitWPResp_15_rl; - 5'd16: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_16_dummy2_0$Q_OUT || !ld_waitWPResp_16_rl; - 5'd17: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_17_dummy2_0$Q_OUT || !ld_waitWPResp_17_rl; - 5'd18: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_18_dummy2_0$Q_OUT || !ld_waitWPResp_18_rl; - 5'd19: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_19_dummy2_0$Q_OUT || !ld_waitWPResp_19_rl; - 5'd20: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_20_dummy2_0$Q_OUT || !ld_waitWPResp_20_rl; - 5'd21: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_21_dummy2_0$Q_OUT || !ld_waitWPResp_21_rl; - 5'd22: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_22_dummy2_0$Q_OUT || !ld_waitWPResp_22_rl; - 5'd23: - SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - !ld_waitWPResp_23_dummy2_0$Q_OUT || !ld_waitWPResp_23_rl; - default: SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or ld_waitWPResp_0_dummy2_0$Q_OUT or ld_waitWPResp_0_rl or @@ -89093,6 +88967,132 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(x__h1062868 or + ld_waitWPResp_0_dummy2_0$Q_OUT or + ld_waitWPResp_0_rl or + ld_waitWPResp_1_dummy2_0$Q_OUT or + ld_waitWPResp_1_rl or + ld_waitWPResp_2_dummy2_0$Q_OUT or + ld_waitWPResp_2_rl or + ld_waitWPResp_3_dummy2_0$Q_OUT or + ld_waitWPResp_3_rl or + ld_waitWPResp_4_dummy2_0$Q_OUT or + ld_waitWPResp_4_rl or + ld_waitWPResp_5_dummy2_0$Q_OUT or + ld_waitWPResp_5_rl or + ld_waitWPResp_6_dummy2_0$Q_OUT or + ld_waitWPResp_6_rl or + ld_waitWPResp_7_dummy2_0$Q_OUT or + ld_waitWPResp_7_rl or + ld_waitWPResp_8_dummy2_0$Q_OUT or + ld_waitWPResp_8_rl or + ld_waitWPResp_9_dummy2_0$Q_OUT or + ld_waitWPResp_9_rl or + ld_waitWPResp_10_dummy2_0$Q_OUT or + ld_waitWPResp_10_rl or + ld_waitWPResp_11_dummy2_0$Q_OUT or + ld_waitWPResp_11_rl or + ld_waitWPResp_12_dummy2_0$Q_OUT or + ld_waitWPResp_12_rl or + ld_waitWPResp_13_dummy2_0$Q_OUT or + ld_waitWPResp_13_rl or + ld_waitWPResp_14_dummy2_0$Q_OUT or + ld_waitWPResp_14_rl or + ld_waitWPResp_15_dummy2_0$Q_OUT or + ld_waitWPResp_15_rl or + ld_waitWPResp_16_dummy2_0$Q_OUT or + ld_waitWPResp_16_rl or + ld_waitWPResp_17_dummy2_0$Q_OUT or + ld_waitWPResp_17_rl or + ld_waitWPResp_18_dummy2_0$Q_OUT or + ld_waitWPResp_18_rl or + ld_waitWPResp_19_dummy2_0$Q_OUT or + ld_waitWPResp_19_rl or + ld_waitWPResp_20_dummy2_0$Q_OUT or + ld_waitWPResp_20_rl or + ld_waitWPResp_21_dummy2_0$Q_OUT or + ld_waitWPResp_21_rl or + ld_waitWPResp_22_dummy2_0$Q_OUT or + ld_waitWPResp_22_rl or + ld_waitWPResp_23_dummy2_0$Q_OUT or ld_waitWPResp_23_rl) + begin + case (x__h1062868) + 5'd0: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_0_dummy2_0$Q_OUT || !ld_waitWPResp_0_rl; + 5'd1: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_1_dummy2_0$Q_OUT || !ld_waitWPResp_1_rl; + 5'd2: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_2_dummy2_0$Q_OUT || !ld_waitWPResp_2_rl; + 5'd3: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_3_dummy2_0$Q_OUT || !ld_waitWPResp_3_rl; + 5'd4: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_4_dummy2_0$Q_OUT || !ld_waitWPResp_4_rl; + 5'd5: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_5_dummy2_0$Q_OUT || !ld_waitWPResp_5_rl; + 5'd6: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_6_dummy2_0$Q_OUT || !ld_waitWPResp_6_rl; + 5'd7: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_7_dummy2_0$Q_OUT || !ld_waitWPResp_7_rl; + 5'd8: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_8_dummy2_0$Q_OUT || !ld_waitWPResp_8_rl; + 5'd9: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_9_dummy2_0$Q_OUT || !ld_waitWPResp_9_rl; + 5'd10: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_10_dummy2_0$Q_OUT || !ld_waitWPResp_10_rl; + 5'd11: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_11_dummy2_0$Q_OUT || !ld_waitWPResp_11_rl; + 5'd12: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_12_dummy2_0$Q_OUT || !ld_waitWPResp_12_rl; + 5'd13: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_13_dummy2_0$Q_OUT || !ld_waitWPResp_13_rl; + 5'd14: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_14_dummy2_0$Q_OUT || !ld_waitWPResp_14_rl; + 5'd15: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_15_dummy2_0$Q_OUT || !ld_waitWPResp_15_rl; + 5'd16: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_16_dummy2_0$Q_OUT || !ld_waitWPResp_16_rl; + 5'd17: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_17_dummy2_0$Q_OUT || !ld_waitWPResp_17_rl; + 5'd18: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_18_dummy2_0$Q_OUT || !ld_waitWPResp_18_rl; + 5'd19: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_19_dummy2_0$Q_OUT || !ld_waitWPResp_19_rl; + 5'd20: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_20_dummy2_0$Q_OUT || !ld_waitWPResp_20_rl; + 5'd21: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_21_dummy2_0$Q_OUT || !ld_waitWPResp_21_rl; + 5'd22: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_22_dummy2_0$Q_OUT || !ld_waitWPResp_22_rl; + 5'd23: + SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + !ld_waitWPResp_23_dummy2_0$Q_OUT || !ld_waitWPResp_23_rl; + default: SEL_ARR_NOT_ld_waitWPResp_0_dummy2_0_read__170_ETC___d25152 = + 1'b0 /* unspecified value */ ; + endcase + end always@(st_deqP or st_instTag_0 or st_instTag_1 or @@ -89153,6 +89153,65 @@ module mkSplitLSQ(CLK, 5'b01010 /* unspecified value */ ; endcase end + always@(st_deqP or + st_dst_0 or + st_dst_1 or + st_dst_2 or + st_dst_3 or + st_dst_4 or + st_dst_5 or + st_dst_6 or + st_dst_7 or + st_dst_8 or + st_dst_9 or st_dst_10 or st_dst_11 or st_dst_12 or st_dst_13) + begin + case (st_deqP) + 4'd0: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_0[8]; + 4'd1: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_1[8]; + 4'd2: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_2[8]; + 4'd3: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_3[8]; + 4'd4: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_4[8]; + 4'd5: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_5[8]; + 4'd6: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_6[8]; + 4'd7: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_7[8]; + 4'd8: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_8[8]; + 4'd9: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_9[8]; + 4'd10: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_10[8]; + 4'd11: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_11[8]; + 4'd12: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_12[8]; + 4'd13: + SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + !st_dst_13[8]; + default: SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_instTag_0 or ld_instTag_1 or @@ -89253,65 +89312,6 @@ module mkSplitLSQ(CLK, 5'b01010 /* unspecified value */ ; endcase end - always@(st_deqP or - st_dst_0 or - st_dst_1 or - st_dst_2 or - st_dst_3 or - st_dst_4 or - st_dst_5 or - st_dst_6 or - st_dst_7 or - st_dst_8 or - st_dst_9 or st_dst_10 or st_dst_11 or st_dst_12 or st_dst_13) - begin - case (st_deqP) - 4'd0: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_0[8]; - 4'd1: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_1[8]; - 4'd2: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_2[8]; - 4'd3: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_3[8]; - 4'd4: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_4[8]; - 4'd5: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_5[8]; - 4'd6: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_6[8]; - 4'd7: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_7[8]; - 4'd8: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_8[8]; - 4'd9: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_9[8]; - 4'd10: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_10[8]; - 4'd11: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_11[8]; - 4'd12: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_12[8]; - 4'd13: - SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - !st_dst_13[8]; - default: SEL_ARR_NOT_st_dst_0_9501_BIT_8_9502_9503_NOT__ETC___d25325 = - 1'b0 /* unspecified value */ ; - endcase - end always@(st_deqP or st_dst_0 or st_dst_1 or @@ -89431,6 +89431,66 @@ module mkSplitLSQ(CLK, 2'b10 /* unspecified value */ ; endcase end + always@(st_deqP or + st_byteEn_0 or + st_byteEn_1 or + st_byteEn_2 or + st_byteEn_3 or + st_byteEn_4 or + st_byteEn_5 or + st_byteEn_6 or + st_byteEn_7 or + st_byteEn_8 or + st_byteEn_9 or + st_byteEn_10 or st_byteEn_11 or st_byteEn_12 or st_byteEn_13) + begin + case (st_deqP) + 4'd0: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_0[3]; + 4'd1: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_1[3]; + 4'd2: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_2[3]; + 4'd3: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_3[3]; + 4'd4: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_4[3]; + 4'd5: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_5[3]; + 4'd6: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_6[3]; + 4'd7: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_7[3]; + 4'd8: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_8[3]; + 4'd9: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_9[3]; + 4'd10: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_10[3]; + 4'd11: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_11[3]; + 4'd12: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_12[3]; + 4'd13: + SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + st_byteEn_13[3]; + default: SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = + 1'b0 /* unspecified value */ ; + endcase + end always@(st_deqP or st_byteEn_0 or st_byteEn_1 or @@ -89551,66 +89611,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(st_deqP or - st_byteEn_0 or - st_byteEn_1 or - st_byteEn_2 or - st_byteEn_3 or - st_byteEn_4 or - st_byteEn_5 or - st_byteEn_6 or - st_byteEn_7 or - st_byteEn_8 or - st_byteEn_9 or - st_byteEn_10 or st_byteEn_11 or st_byteEn_12 or st_byteEn_13) - begin - case (st_deqP) - 4'd0: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_0[3]; - 4'd1: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_1[3]; - 4'd2: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_2[3]; - 4'd3: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_3[3]; - 4'd4: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_4[3]; - 4'd5: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_5[3]; - 4'd6: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_6[3]; - 4'd7: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_7[3]; - 4'd8: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_8[3]; - 4'd9: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_9[3]; - 4'd10: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_10[3]; - 4'd11: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_11[3]; - 4'd12: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_12[3]; - 4'd13: - SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - st_byteEn_13[3]; - default: SEL_ARR_st_byteEn_0_9112_BIT_3_9193_st_byteEn__ETC___d26144 = - 1'b0 /* unspecified value */ ; - endcase - end always@(st_deqP or st_byteEn_0 or st_byteEn_1 or @@ -91173,109 +91173,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(a__h1787017 or - NOT_ld_valid_0_dummy2_0_read__1629_3646_OR_NOT_ETC___d27299 or - NOT_ld_valid_1_dummy2_0_read__1713_3686_OR_NOT_ETC___d27302 or - NOT_ld_valid_2_dummy2_0_read__1797_3726_OR_NOT_ETC___d27305 or - NOT_ld_valid_3_dummy2_0_read__1881_3766_OR_NOT_ETC___d27308 or - NOT_ld_valid_4_dummy2_0_read__1965_3806_OR_NOT_ETC___d27311 or - NOT_ld_valid_5_dummy2_0_read__2049_3846_OR_NOT_ETC___d27314 or - NOT_ld_valid_6_dummy2_0_read__2133_3886_OR_NOT_ETC___d27317 or - NOT_ld_valid_7_dummy2_0_read__2217_3926_OR_NOT_ETC___d27320 or - NOT_ld_valid_8_dummy2_0_read__2301_3966_OR_NOT_ETC___d27323 or - NOT_ld_valid_9_dummy2_0_read__2385_4006_OR_NOT_ETC___d27326 or - NOT_ld_valid_10_dummy2_0_read__2469_4046_OR_NO_ETC___d27329 or - NOT_ld_valid_11_dummy2_0_read__2553_4086_OR_NO_ETC___d27332 or - NOT_ld_valid_12_dummy2_0_read__2637_4126_OR_NO_ETC___d27335 or - NOT_ld_valid_13_dummy2_0_read__2721_4166_OR_NO_ETC___d27338 or - NOT_ld_valid_14_dummy2_0_read__2805_4206_OR_NO_ETC___d27341 or - NOT_ld_valid_15_dummy2_0_read__2889_4246_OR_NO_ETC___d27344 or - NOT_ld_valid_16_dummy2_0_read__2973_4286_OR_NO_ETC___d27347 or - NOT_ld_valid_17_dummy2_0_read__3057_4326_OR_NO_ETC___d27350 or - NOT_ld_valid_18_dummy2_0_read__3141_4366_OR_NO_ETC___d27353 or - NOT_ld_valid_19_dummy2_0_read__3225_4406_OR_NO_ETC___d27356 or - NOT_ld_valid_20_dummy2_0_read__3309_4446_OR_NO_ETC___d27359 or - NOT_ld_valid_21_dummy2_0_read__3393_4486_OR_NO_ETC___d27362 or - NOT_ld_valid_22_dummy2_0_read__3477_4526_OR_NO_ETC___d27365 or - NOT_ld_valid_23_dummy2_0_read__3561_4566_OR_NO_ETC___d27368) - begin - case (a__h1787017) - 5'd0: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_0_dummy2_0_read__1629_3646_OR_NOT_ETC___d27299; - 5'd1: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_1_dummy2_0_read__1713_3686_OR_NOT_ETC___d27302; - 5'd2: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_2_dummy2_0_read__1797_3726_OR_NOT_ETC___d27305; - 5'd3: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_3_dummy2_0_read__1881_3766_OR_NOT_ETC___d27308; - 5'd4: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_4_dummy2_0_read__1965_3806_OR_NOT_ETC___d27311; - 5'd5: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_5_dummy2_0_read__2049_3846_OR_NOT_ETC___d27314; - 5'd6: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_6_dummy2_0_read__2133_3886_OR_NOT_ETC___d27317; - 5'd7: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_7_dummy2_0_read__2217_3926_OR_NOT_ETC___d27320; - 5'd8: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_8_dummy2_0_read__2301_3966_OR_NOT_ETC___d27323; - 5'd9: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_9_dummy2_0_read__2385_4006_OR_NOT_ETC___d27326; - 5'd10: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_10_dummy2_0_read__2469_4046_OR_NO_ETC___d27329; - 5'd11: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_11_dummy2_0_read__2553_4086_OR_NO_ETC___d27332; - 5'd12: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_12_dummy2_0_read__2637_4126_OR_NO_ETC___d27335; - 5'd13: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_13_dummy2_0_read__2721_4166_OR_NO_ETC___d27338; - 5'd14: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_14_dummy2_0_read__2805_4206_OR_NO_ETC___d27341; - 5'd15: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_15_dummy2_0_read__2889_4246_OR_NO_ETC___d27344; - 5'd16: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_16_dummy2_0_read__2973_4286_OR_NO_ETC___d27347; - 5'd17: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_17_dummy2_0_read__3057_4326_OR_NO_ETC___d27350; - 5'd18: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_18_dummy2_0_read__3141_4366_OR_NO_ETC___d27353; - 5'd19: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_19_dummy2_0_read__3225_4406_OR_NO_ETC___d27356; - 5'd20: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_20_dummy2_0_read__3309_4446_OR_NO_ETC___d27359; - 5'd21: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_21_dummy2_0_read__3393_4486_OR_NO_ETC___d27362; - 5'd22: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_22_dummy2_0_read__3477_4526_OR_NO_ETC___d27365; - 5'd23: - SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - NOT_ld_valid_23_dummy2_0_read__3561_4566_OR_NO_ETC___d27368; - default: SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = - 1'b0 /* unspecified value */ ; - endcase - end always@(b__h1787018 or IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609 or IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611 or @@ -91379,6 +91276,109 @@ module mkSplitLSQ(CLK, 6'b101010 /* unspecified value */ ; endcase end + always@(a__h1787017 or + NOT_ld_valid_0_dummy2_0_read__1629_3646_OR_NOT_ETC___d27299 or + NOT_ld_valid_1_dummy2_0_read__1713_3686_OR_NOT_ETC___d27302 or + NOT_ld_valid_2_dummy2_0_read__1797_3726_OR_NOT_ETC___d27305 or + NOT_ld_valid_3_dummy2_0_read__1881_3766_OR_NOT_ETC___d27308 or + NOT_ld_valid_4_dummy2_0_read__1965_3806_OR_NOT_ETC___d27311 or + NOT_ld_valid_5_dummy2_0_read__2049_3846_OR_NOT_ETC___d27314 or + NOT_ld_valid_6_dummy2_0_read__2133_3886_OR_NOT_ETC___d27317 or + NOT_ld_valid_7_dummy2_0_read__2217_3926_OR_NOT_ETC___d27320 or + NOT_ld_valid_8_dummy2_0_read__2301_3966_OR_NOT_ETC___d27323 or + NOT_ld_valid_9_dummy2_0_read__2385_4006_OR_NOT_ETC___d27326 or + NOT_ld_valid_10_dummy2_0_read__2469_4046_OR_NO_ETC___d27329 or + NOT_ld_valid_11_dummy2_0_read__2553_4086_OR_NO_ETC___d27332 or + NOT_ld_valid_12_dummy2_0_read__2637_4126_OR_NO_ETC___d27335 or + NOT_ld_valid_13_dummy2_0_read__2721_4166_OR_NO_ETC___d27338 or + NOT_ld_valid_14_dummy2_0_read__2805_4206_OR_NO_ETC___d27341 or + NOT_ld_valid_15_dummy2_0_read__2889_4246_OR_NO_ETC___d27344 or + NOT_ld_valid_16_dummy2_0_read__2973_4286_OR_NO_ETC___d27347 or + NOT_ld_valid_17_dummy2_0_read__3057_4326_OR_NO_ETC___d27350 or + NOT_ld_valid_18_dummy2_0_read__3141_4366_OR_NO_ETC___d27353 or + NOT_ld_valid_19_dummy2_0_read__3225_4406_OR_NO_ETC___d27356 or + NOT_ld_valid_20_dummy2_0_read__3309_4446_OR_NO_ETC___d27359 or + NOT_ld_valid_21_dummy2_0_read__3393_4486_OR_NO_ETC___d27362 or + NOT_ld_valid_22_dummy2_0_read__3477_4526_OR_NO_ETC___d27365 or + NOT_ld_valid_23_dummy2_0_read__3561_4566_OR_NO_ETC___d27368) + begin + case (a__h1787017) + 5'd0: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_0_dummy2_0_read__1629_3646_OR_NOT_ETC___d27299; + 5'd1: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_1_dummy2_0_read__1713_3686_OR_NOT_ETC___d27302; + 5'd2: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_2_dummy2_0_read__1797_3726_OR_NOT_ETC___d27305; + 5'd3: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_3_dummy2_0_read__1881_3766_OR_NOT_ETC___d27308; + 5'd4: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_4_dummy2_0_read__1965_3806_OR_NOT_ETC___d27311; + 5'd5: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_5_dummy2_0_read__2049_3846_OR_NOT_ETC___d27314; + 5'd6: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_6_dummy2_0_read__2133_3886_OR_NOT_ETC___d27317; + 5'd7: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_7_dummy2_0_read__2217_3926_OR_NOT_ETC___d27320; + 5'd8: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_8_dummy2_0_read__2301_3966_OR_NOT_ETC___d27323; + 5'd9: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_9_dummy2_0_read__2385_4006_OR_NOT_ETC___d27326; + 5'd10: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_10_dummy2_0_read__2469_4046_OR_NO_ETC___d27329; + 5'd11: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_11_dummy2_0_read__2553_4086_OR_NO_ETC___d27332; + 5'd12: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_12_dummy2_0_read__2637_4126_OR_NO_ETC___d27335; + 5'd13: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_13_dummy2_0_read__2721_4166_OR_NO_ETC___d27338; + 5'd14: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_14_dummy2_0_read__2805_4206_OR_NO_ETC___d27341; + 5'd15: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_15_dummy2_0_read__2889_4246_OR_NO_ETC___d27344; + 5'd16: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_16_dummy2_0_read__2973_4286_OR_NO_ETC___d27347; + 5'd17: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_17_dummy2_0_read__3057_4326_OR_NO_ETC___d27350; + 5'd18: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_18_dummy2_0_read__3141_4366_OR_NO_ETC___d27353; + 5'd19: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_19_dummy2_0_read__3225_4406_OR_NO_ETC___d27356; + 5'd20: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_20_dummy2_0_read__3309_4446_OR_NO_ETC___d27359; + 5'd21: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_21_dummy2_0_read__3393_4486_OR_NO_ETC___d27362; + 5'd22: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_22_dummy2_0_read__3477_4526_OR_NO_ETC___d27365; + 5'd23: + SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + NOT_ld_valid_23_dummy2_0_read__3561_4566_OR_NO_ETC___d27368; + default: SEL_ARR_NOT_ld_valid_0_dummy2_0_read__1629_364_ETC___d27410 = + 1'b0 /* unspecified value */ ; + endcase + end always@(a__h1787522 or IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609 or IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611 or @@ -92615,6 +92615,109 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(b__h1788366 or + IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609 or + IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611 or + IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618 or + IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620 or + IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627 or + IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629 or + IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631 or + IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633 or + IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635 or + IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637 or + IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639 or + IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641 or + IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643 or + IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645 or + IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647 or + IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649 or + IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651 or + IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653 or + IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655 or + IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657 or + IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659 or + IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661 or + IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663 or + IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665) + begin + case (b__h1788366) + 5'd0: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609; + 5'd1: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611; + 5'd2: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618; + 5'd3: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620; + 5'd4: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627; + 5'd5: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629; + 5'd6: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631; + 5'd7: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633; + 5'd8: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635; + 5'd9: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637; + 5'd10: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639; + 5'd11: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641; + 5'd12: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643; + 5'd13: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645; + 5'd14: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647; + 5'd15: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649; + 5'd16: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651; + 5'd17: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653; + 5'd18: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655; + 5'd19: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657; + 5'd20: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659; + 5'd21: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661; + 5'd22: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663; + 5'd23: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665; + default: SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = + 6'b101010 /* unspecified value */ ; + endcase + end always@(a__h1788365 or IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609 or IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611 or @@ -92821,109 +92924,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(b__h1788366 or - IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609 or - IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611 or - IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618 or - IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620 or - IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627 or - IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629 or - IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631 or - IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633 or - IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635 or - IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637 or - IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639 or - IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641 or - IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643 or - IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645 or - IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647 or - IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649 or - IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651 or - IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653 or - IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655 or - IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657 or - IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659 or - IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661 or - IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663 or - IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665) - begin - case (b__h1788366) - 5'd0: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609; - 5'd1: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611; - 5'd2: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618; - 5'd3: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620; - 5'd4: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627; - 5'd5: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629; - 5'd6: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631; - 5'd7: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633; - 5'd8: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635; - 5'd9: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637; - 5'd10: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639; - 5'd11: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641; - 5'd12: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643; - 5'd13: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645; - 5'd14: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647; - 5'd15: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649; - 5'd16: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651; - 5'd17: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653; - 5'd18: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655; - 5'd19: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657; - 5'd20: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659; - 5'd21: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661; - 5'd22: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663; - 5'd23: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665; - default: SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27460 = - 6'b101010 /* unspecified value */ ; - endcase - end always@(a__h1788365 or NOT_ld_valid_0_dummy2_0_read__1629_3646_OR_NOT_ETC___d27299 or NOT_ld_valid_1_dummy2_0_read__1713_3686_OR_NOT_ETC___d27302 or @@ -93130,109 +93130,6 @@ module mkSplitLSQ(CLK, 6'b101010 /* unspecified value */ ; endcase end - always@(b__h1788871 or - IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609 or - IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611 or - IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618 or - IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620 or - IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627 or - IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629 or - IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631 or - IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633 or - IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635 or - IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637 or - IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639 or - IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641 or - IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643 or - IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645 or - IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647 or - IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649 or - IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651 or - IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653 or - IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655 or - IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657 or - IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659 or - IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661 or - IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663 or - IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665) - begin - case (b__h1788871) - 5'd0: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609; - 5'd1: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611; - 5'd2: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618; - 5'd3: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620; - 5'd4: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627; - 5'd5: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629; - 5'd6: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631; - 5'd7: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633; - 5'd8: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635; - 5'd9: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637; - 5'd10: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639; - 5'd11: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641; - 5'd12: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643; - 5'd13: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645; - 5'd14: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647; - 5'd15: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649; - 5'd16: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651; - 5'd17: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653; - 5'd18: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655; - 5'd19: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657; - 5'd20: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659; - 5'd21: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661; - 5'd22: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663; - 5'd23: - SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665; - default: SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = - 6'b101010 /* unspecified value */ ; - endcase - end always@(b__h1788871 or NOT_ld_valid_0_dummy2_0_read__1629_3646_OR_NOT_ETC___d27299 or NOT_ld_valid_1_dummy2_0_read__1713_3686_OR_NOT_ETC___d27302 or @@ -93336,6 +93233,109 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(b__h1788871 or + IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609 or + IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611 or + IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618 or + IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620 or + IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627 or + IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629 or + IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631 or + IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633 or + IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635 or + IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637 or + IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639 or + IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641 or + IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643 or + IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645 or + IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647 or + IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649 or + IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651 or + IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653 or + IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655 or + IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657 or + IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659 or + IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661 or + IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663 or + IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665) + begin + case (b__h1788871) + 5'd0: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24___d14609; + 5'd1: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25___d14611; + 5'd2: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26___d14618; + 5'd3: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27___d14620; + 5'd4: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28___d14627; + 5'd5: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29___d14629; + 5'd6: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30___d14631; + 5'd7: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31___d14633; + 5'd8: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32___d14635; + 5'd9: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33___d14637; + 5'd10: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34___d14639; + 5'd11: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35___d14641; + 5'd12: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36___d14643; + 5'd13: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37___d14645; + 5'd14: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38___d14647; + 5'd15: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39___d14649; + 5'd16: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40___d14651; + 5'd17: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41___d14653; + 5'd18: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42___d14655; + 5'd19: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43___d14657; + 5'd20: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44___d14659; + 5'd21: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45___d14661; + 5'd22: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46___d14663; + 5'd23: + SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47___d14665; + default: SEL_ARR_IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE__ETC___d27475 = + 6'b101010 /* unspecified value */ ; + endcase + end always@(a__h1788870 or NOT_ld_valid_0_dummy2_0_read__1629_3646_OR_NOT_ETC___d27299 or NOT_ld_valid_1_dummy2_0_read__1713_3686_OR_NOT_ETC___d27302 or @@ -95305,69 +95305,6 @@ module mkSplitLSQ(CLK, 5'b01010 /* unspecified value */ ; endcase end - always@(b__h1796812 or - NOT_st_valid_0_dummy2_0_read__7443_8009_OR_NOT_ETC___d27513 or - NOT_st_valid_1_dummy2_0_read__7447_8014_OR_NOT_ETC___d27516 or - NOT_st_valid_2_dummy2_0_read__7451_8019_OR_NOT_ETC___d27519 or - NOT_st_valid_3_dummy2_0_read__7455_8024_OR_NOT_ETC___d27522 or - NOT_st_valid_4_dummy2_0_read__7459_8029_OR_NOT_ETC___d27525 or - NOT_st_valid_5_dummy2_0_read__7463_8034_OR_NOT_ETC___d27528 or - NOT_st_valid_6_dummy2_0_read__7467_8039_OR_NOT_ETC___d27531 or - NOT_st_valid_7_dummy2_0_read__7471_8044_OR_NOT_ETC___d27534 or - NOT_st_valid_8_dummy2_0_read__7475_8049_OR_NOT_ETC___d27537 or - NOT_st_valid_9_dummy2_0_read__7479_8054_OR_NOT_ETC___d27540 or - NOT_st_valid_10_dummy2_0_read__7483_8059_OR_NO_ETC___d27543 or - NOT_st_valid_11_dummy2_0_read__7487_8064_OR_NO_ETC___d27546 or - NOT_st_valid_12_dummy2_0_read__7491_8069_OR_NO_ETC___d27549 or - NOT_st_valid_13_dummy2_0_read__7495_8074_OR_NO_ETC___d27552) - begin - case (b__h1796812) - 4'd0: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_0_dummy2_0_read__7443_8009_OR_NOT_ETC___d27513; - 4'd1: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_1_dummy2_0_read__7447_8014_OR_NOT_ETC___d27516; - 4'd2: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_2_dummy2_0_read__7451_8019_OR_NOT_ETC___d27519; - 4'd3: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_3_dummy2_0_read__7455_8024_OR_NOT_ETC___d27522; - 4'd4: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_4_dummy2_0_read__7459_8029_OR_NOT_ETC___d27525; - 4'd5: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_5_dummy2_0_read__7463_8034_OR_NOT_ETC___d27528; - 4'd6: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_6_dummy2_0_read__7467_8039_OR_NOT_ETC___d27531; - 4'd7: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_7_dummy2_0_read__7471_8044_OR_NOT_ETC___d27534; - 4'd8: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_8_dummy2_0_read__7475_8049_OR_NOT_ETC___d27537; - 4'd9: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_9_dummy2_0_read__7479_8054_OR_NOT_ETC___d27540; - 4'd10: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_10_dummy2_0_read__7483_8059_OR_NO_ETC___d27543; - 4'd11: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_11_dummy2_0_read__7487_8064_OR_NO_ETC___d27546; - 4'd12: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_12_dummy2_0_read__7491_8069_OR_NO_ETC___d27549; - 4'd13: - SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - NOT_st_valid_13_dummy2_0_read__7495_8074_OR_NO_ETC___d27552; - default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = - 1'b0 /* unspecified value */ ; - endcase - end always@(b__h1796812 or IF_st_enqP_8093_EQ_0_8112_THEN_0_ELSE_14___d20154 or IF_st_enqP_8093_ULE_1_8121_THEN_1_ELSE_15___d20155 or @@ -95431,6 +95368,69 @@ module mkSplitLSQ(CLK, 5'b01010 /* unspecified value */ ; endcase end + always@(b__h1796812 or + NOT_st_valid_0_dummy2_0_read__7443_8009_OR_NOT_ETC___d27513 or + NOT_st_valid_1_dummy2_0_read__7447_8014_OR_NOT_ETC___d27516 or + NOT_st_valid_2_dummy2_0_read__7451_8019_OR_NOT_ETC___d27519 or + NOT_st_valid_3_dummy2_0_read__7455_8024_OR_NOT_ETC___d27522 or + NOT_st_valid_4_dummy2_0_read__7459_8029_OR_NOT_ETC___d27525 or + NOT_st_valid_5_dummy2_0_read__7463_8034_OR_NOT_ETC___d27528 or + NOT_st_valid_6_dummy2_0_read__7467_8039_OR_NOT_ETC___d27531 or + NOT_st_valid_7_dummy2_0_read__7471_8044_OR_NOT_ETC___d27534 or + NOT_st_valid_8_dummy2_0_read__7475_8049_OR_NOT_ETC___d27537 or + NOT_st_valid_9_dummy2_0_read__7479_8054_OR_NOT_ETC___d27540 or + NOT_st_valid_10_dummy2_0_read__7483_8059_OR_NO_ETC___d27543 or + NOT_st_valid_11_dummy2_0_read__7487_8064_OR_NO_ETC___d27546 or + NOT_st_valid_12_dummy2_0_read__7491_8069_OR_NO_ETC___d27549 or + NOT_st_valid_13_dummy2_0_read__7495_8074_OR_NO_ETC___d27552) + begin + case (b__h1796812) + 4'd0: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_0_dummy2_0_read__7443_8009_OR_NOT_ETC___d27513; + 4'd1: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_1_dummy2_0_read__7447_8014_OR_NOT_ETC___d27516; + 4'd2: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_2_dummy2_0_read__7451_8019_OR_NOT_ETC___d27519; + 4'd3: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_3_dummy2_0_read__7455_8024_OR_NOT_ETC___d27522; + 4'd4: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_4_dummy2_0_read__7459_8029_OR_NOT_ETC___d27525; + 4'd5: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_5_dummy2_0_read__7463_8034_OR_NOT_ETC___d27528; + 4'd6: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_6_dummy2_0_read__7467_8039_OR_NOT_ETC___d27531; + 4'd7: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_7_dummy2_0_read__7471_8044_OR_NOT_ETC___d27534; + 4'd8: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_8_dummy2_0_read__7475_8049_OR_NOT_ETC___d27537; + 4'd9: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_9_dummy2_0_read__7479_8054_OR_NOT_ETC___d27540; + 4'd10: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_10_dummy2_0_read__7483_8059_OR_NO_ETC___d27543; + 4'd11: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_11_dummy2_0_read__7487_8064_OR_NO_ETC___d27546; + 4'd12: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_12_dummy2_0_read__7491_8069_OR_NO_ETC___d27549; + 4'd13: + SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + NOT_st_valid_13_dummy2_0_read__7495_8074_OR_NO_ETC___d27552; + default: SEL_ARR_NOT_st_valid_0_dummy2_0_read__7443_800_ETC___d27598 = + 1'b0 /* unspecified value */ ; + endcase + end always@(a__h1796811 or NOT_st_valid_0_dummy2_0_read__7443_8009_OR_NOT_ETC___d27513 or NOT_st_valid_1_dummy2_0_read__7447_8014_OR_NOT_ETC___d27516 or @@ -97706,6 +97706,206 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(issueLd_lsqTag or + ld_memFunc_0 or + ld_memFunc_1 or + ld_memFunc_2 or + ld_memFunc_3 or + ld_memFunc_4 or + ld_memFunc_5 or + ld_memFunc_6 or + ld_memFunc_7 or + ld_memFunc_8 or + ld_memFunc_9 or + ld_memFunc_10 or + ld_memFunc_11 or + ld_memFunc_12 or + ld_memFunc_13 or + ld_memFunc_14 or + ld_memFunc_15 or + ld_memFunc_16 or + ld_memFunc_17 or + ld_memFunc_18 or + ld_memFunc_19 or + ld_memFunc_20 or ld_memFunc_21 or ld_memFunc_22 or ld_memFunc_23) + begin + case (issueLd_lsqTag) + 5'd0: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_0; + 5'd1: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_1; + 5'd2: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_2; + 5'd3: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_3; + 5'd4: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_4; + 5'd5: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_5; + 5'd6: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_6; + 5'd7: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_7; + 5'd8: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_8; + 5'd9: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_9; + 5'd10: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_10; + 5'd11: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_11; + 5'd12: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_12; + 5'd13: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_13; + 5'd14: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_14; + 5'd15: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_15; + 5'd16: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_16; + 5'd17: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_17; + 5'd18: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_18; + 5'd19: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_19; + 5'd20: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_20; + 5'd21: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_21; + 5'd22: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_22; + 5'd23: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + ld_memFunc_23; + default: SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(issueLdQ$first or + ld_memFunc_0 or + ld_memFunc_1 or + ld_memFunc_2 or + ld_memFunc_3 or + ld_memFunc_4 or + ld_memFunc_5 or + ld_memFunc_6 or + ld_memFunc_7 or + ld_memFunc_8 or + ld_memFunc_9 or + ld_memFunc_10 or + ld_memFunc_11 or + ld_memFunc_12 or + ld_memFunc_13 or + ld_memFunc_14 or + ld_memFunc_15 or + ld_memFunc_16 or + ld_memFunc_17 or + ld_memFunc_18 or + ld_memFunc_19 or + ld_memFunc_20 or ld_memFunc_21 or ld_memFunc_22 or ld_memFunc_23) + begin + case (issueLdQ$first[88:84]) + 5'd0: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_0; + 5'd1: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_1; + 5'd2: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_2; + 5'd3: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_3; + 5'd4: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_4; + 5'd5: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_5; + 5'd6: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_6; + 5'd7: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_7; + 5'd8: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_8; + 5'd9: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_9; + 5'd10: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_10; + 5'd11: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_11; + 5'd12: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_12; + 5'd13: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_13; + 5'd14: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_14; + 5'd15: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_15; + 5'd16: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_16; + 5'd17: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_17; + 5'd18: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_18; + 5'd19: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_19; + 5'd20: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_20; + 5'd21: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_21; + 5'd22: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_22; + 5'd23: + SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + ld_memFunc_23; + default: SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_olderStVerified_0_dummy2_0$Q_OUT or ld_olderStVerified_0_dummy2_1$Q_OUT or @@ -97967,203 +98167,106 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(issueLd_lsqTag or - ld_memFunc_0 or - ld_memFunc_1 or - ld_memFunc_2 or - ld_memFunc_3 or - ld_memFunc_4 or - ld_memFunc_5 or - ld_memFunc_6 or - ld_memFunc_7 or - ld_memFunc_8 or - ld_memFunc_9 or - ld_memFunc_10 or - ld_memFunc_11 or - ld_memFunc_12 or - ld_memFunc_13 or - ld_memFunc_14 or - ld_memFunc_15 or - ld_memFunc_16 or - ld_memFunc_17 or - ld_memFunc_18 or - ld_memFunc_19 or - ld_memFunc_20 or ld_memFunc_21 or ld_memFunc_22 or ld_memFunc_23) - begin - case (issueLd_lsqTag) - 5'd0: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_0; - 5'd1: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_1; - 5'd2: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_2; - 5'd3: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_3; - 5'd4: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_4; - 5'd5: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_5; - 5'd6: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_6; - 5'd7: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_7; - 5'd8: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_8; - 5'd9: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_9; - 5'd10: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_10; - 5'd11: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_11; - 5'd12: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_12; - 5'd13: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_13; - 5'd14: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_14; - 5'd15: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_15; - 5'd16: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_16; - 5'd17: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_17; - 5'd18: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_18; - 5'd19: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_19; - 5'd20: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_20; - 5'd21: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_21; - 5'd22: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_22; - 5'd23: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - ld_memFunc_23; - default: SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d21757 = - 1'b0 /* unspecified value */ ; - endcase - end always@(issueLdQ$first or - ld_memFunc_0 or - ld_memFunc_1 or - ld_memFunc_2 or - ld_memFunc_3 or - ld_memFunc_4 or - ld_memFunc_5 or - ld_memFunc_6 or - ld_memFunc_7 or - ld_memFunc_8 or - ld_memFunc_9 or - ld_memFunc_10 or - ld_memFunc_11 or - ld_memFunc_12 or - ld_memFunc_13 or - ld_memFunc_14 or - ld_memFunc_15 or - ld_memFunc_16 or - ld_memFunc_17 or - ld_memFunc_18 or - ld_memFunc_19 or - ld_memFunc_20 or ld_memFunc_21 or ld_memFunc_22 or ld_memFunc_23) + NOT_ld_inIssueQ_0_dummy2_0_read__1641_1642_OR__ETC___d11650 or + NOT_ld_inIssueQ_1_dummy2_0_read__1725_1726_OR__ETC___d11734 or + NOT_ld_inIssueQ_2_dummy2_0_read__1809_1810_OR__ETC___d11818 or + NOT_ld_inIssueQ_3_dummy2_0_read__1893_1894_OR__ETC___d11902 or + NOT_ld_inIssueQ_4_dummy2_0_read__1977_1978_OR__ETC___d11986 or + NOT_ld_inIssueQ_5_dummy2_0_read__2061_2062_OR__ETC___d12070 or + NOT_ld_inIssueQ_6_dummy2_0_read__2145_2146_OR__ETC___d12154 or + NOT_ld_inIssueQ_7_dummy2_0_read__2229_2230_OR__ETC___d12238 or + NOT_ld_inIssueQ_8_dummy2_0_read__2313_2314_OR__ETC___d12322 or + NOT_ld_inIssueQ_9_dummy2_0_read__2397_2398_OR__ETC___d12406 or + NOT_ld_inIssueQ_10_dummy2_0_read__2481_2482_OR_ETC___d12490 or + NOT_ld_inIssueQ_11_dummy2_0_read__2565_2566_OR_ETC___d12574 or + NOT_ld_inIssueQ_12_dummy2_0_read__2649_2650_OR_ETC___d12658 or + NOT_ld_inIssueQ_13_dummy2_0_read__2733_2734_OR_ETC___d12742 or + NOT_ld_inIssueQ_14_dummy2_0_read__2817_2818_OR_ETC___d12826 or + NOT_ld_inIssueQ_15_dummy2_0_read__2901_2902_OR_ETC___d12910 or + NOT_ld_inIssueQ_16_dummy2_0_read__2985_2986_OR_ETC___d12994 or + NOT_ld_inIssueQ_17_dummy2_0_read__3069_3070_OR_ETC___d13078 or + NOT_ld_inIssueQ_18_dummy2_0_read__3153_3154_OR_ETC___d13162 or + NOT_ld_inIssueQ_19_dummy2_0_read__3237_3238_OR_ETC___d13246 or + NOT_ld_inIssueQ_20_dummy2_0_read__3321_3322_OR_ETC___d13330 or + NOT_ld_inIssueQ_21_dummy2_0_read__3405_3406_OR_ETC___d13414 or + NOT_ld_inIssueQ_22_dummy2_0_read__3489_3490_OR_ETC___d13498 or + NOT_ld_inIssueQ_23_dummy2_0_read__3573_3574_OR_ETC___d13582) begin case (issueLdQ$first[88:84]) 5'd0: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_0; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_0_dummy2_0_read__1641_1642_OR__ETC___d11650; 5'd1: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_1; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_1_dummy2_0_read__1725_1726_OR__ETC___d11734; 5'd2: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_2; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_2_dummy2_0_read__1809_1810_OR__ETC___d11818; 5'd3: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_3; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_3_dummy2_0_read__1893_1894_OR__ETC___d11902; 5'd4: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_4; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_4_dummy2_0_read__1977_1978_OR__ETC___d11986; 5'd5: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_5; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_5_dummy2_0_read__2061_2062_OR__ETC___d12070; 5'd6: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_6; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_6_dummy2_0_read__2145_2146_OR__ETC___d12154; 5'd7: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_7; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_7_dummy2_0_read__2229_2230_OR__ETC___d12238; 5'd8: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_8; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_8_dummy2_0_read__2313_2314_OR__ETC___d12322; 5'd9: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_9; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_9_dummy2_0_read__2397_2398_OR__ETC___d12406; 5'd10: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_10; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_10_dummy2_0_read__2481_2482_OR_ETC___d12490; 5'd11: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_11; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_11_dummy2_0_read__2565_2566_OR_ETC___d12574; 5'd12: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_12; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_12_dummy2_0_read__2649_2650_OR_ETC___d12658; 5'd13: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_13; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_13_dummy2_0_read__2733_2734_OR_ETC___d12742; 5'd14: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_14; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_14_dummy2_0_read__2817_2818_OR_ETC___d12826; 5'd15: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_15; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_15_dummy2_0_read__2901_2902_OR_ETC___d12910; 5'd16: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_16; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_16_dummy2_0_read__2985_2986_OR_ETC___d12994; 5'd17: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_17; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_17_dummy2_0_read__3069_3070_OR_ETC___d13078; 5'd18: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_18; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_18_dummy2_0_read__3153_3154_OR_ETC___d13162; 5'd19: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_19; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_19_dummy2_0_read__3237_3238_OR_ETC___d13246; 5'd20: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_20; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_20_dummy2_0_read__3321_3322_OR_ETC___d13330; 5'd21: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_21; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_21_dummy2_0_read__3405_3406_OR_ETC___d13414; 5'd22: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_22; + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_22_dummy2_0_read__3489_3490_OR_ETC___d13498; 5'd23: - SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = - ld_memFunc_23; - default: SEL_ARR_ld_memFunc_0_1633_ld_memFunc_1_1717_ld_ETC___d23624 = + SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = + NOT_ld_inIssueQ_23_dummy2_0_read__3573_3574_OR_ETC___d13582; + default: SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = 1'b0 /* unspecified value */ ; endcase end @@ -98468,66 +98571,6 @@ module mkSplitLSQ(CLK, 2'b10 /* unspecified value */ ; endcase end - always@(getOrigBE_t or - st_byteEn_0 or - st_byteEn_1 or - st_byteEn_2 or - st_byteEn_3 or - st_byteEn_4 or - st_byteEn_5 or - st_byteEn_6 or - st_byteEn_7 or - st_byteEn_8 or - st_byteEn_9 or - st_byteEn_10 or st_byteEn_11 or st_byteEn_12 or st_byteEn_13) - begin - case (getOrigBE_t[3:0]) - 4'd0: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_0[0]; - 4'd1: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_1[0]; - 4'd2: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_2[0]; - 4'd3: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_3[0]; - 4'd4: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_4[0]; - 4'd5: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_5[0]; - 4'd6: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_6[0]; - 4'd7: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_7[0]; - 4'd8: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_8[0]; - 4'd9: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_9[0]; - 4'd10: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_10[0]; - 4'd11: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_11[0]; - 4'd12: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_12[0]; - 4'd13: - SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - st_byteEn_13[0]; - default: SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = - 1'b0 /* unspecified value */ ; - endcase - end always@(getOrigBE_t or st_byteEn_0 or st_byteEn_1 or @@ -98588,6 +98631,166 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(getOrigBE_t or + ld_byteEn_0 or + ld_byteEn_1 or + ld_byteEn_2 or + ld_byteEn_3 or + ld_byteEn_4 or + ld_byteEn_5 or + ld_byteEn_6 or + ld_byteEn_7 or + ld_byteEn_8 or + ld_byteEn_9 or + ld_byteEn_10 or + ld_byteEn_11 or + ld_byteEn_12 or + ld_byteEn_13 or + ld_byteEn_14 or + ld_byteEn_15 or + ld_byteEn_16 or + ld_byteEn_17 or + ld_byteEn_18 or + ld_byteEn_19 or + ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) + begin + case (getOrigBE_t[4:0]) + 5'd0: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_0[1]; + 5'd1: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_1[1]; + 5'd2: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_2[1]; + 5'd3: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_3[1]; + 5'd4: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_4[1]; + 5'd5: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_5[1]; + 5'd6: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_6[1]; + 5'd7: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_7[1]; + 5'd8: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_8[1]; + 5'd9: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_9[1]; + 5'd10: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_10[1]; + 5'd11: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_11[1]; + 5'd12: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_12[1]; + 5'd13: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_13[1]; + 5'd14: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_14[1]; + 5'd15: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_15[1]; + 5'd16: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_16[1]; + 5'd17: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_17[1]; + 5'd18: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_18[1]; + 5'd19: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_19[1]; + 5'd20: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_20[1]; + 5'd21: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_21[1]; + 5'd22: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_22[1]; + 5'd23: + SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + ld_byteEn_23[1]; + default: SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(getOrigBE_t or + st_byteEn_0 or + st_byteEn_1 or + st_byteEn_2 or + st_byteEn_3 or + st_byteEn_4 or + st_byteEn_5 or + st_byteEn_6 or + st_byteEn_7 or + st_byteEn_8 or + st_byteEn_9 or + st_byteEn_10 or st_byteEn_11 or st_byteEn_12 or st_byteEn_13) + begin + case (getOrigBE_t[3:0]) + 4'd0: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_0[0]; + 4'd1: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_1[0]; + 4'd2: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_2[0]; + 4'd3: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_3[0]; + 4'd4: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_4[0]; + 4'd5: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_5[0]; + 4'd6: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_6[0]; + 4'd7: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_7[0]; + 4'd8: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_8[0]; + 4'd9: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_9[0]; + 4'd10: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_10[0]; + 4'd11: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_11[0]; + 4'd12: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_12[0]; + 4'd13: + SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + st_byteEn_13[0]; + default: SEL_ARR_st_byteEn_0_9112_BIT_0_9242_st_byteEn__ETC___d19257 = + 1'b0 /* unspecified value */ ; + endcase + end always@(tag__h848913 or ld_shiftedBE_0_dummy2_0$Q_OUT or ld_shiftedBE_0_dummy2_1$Q_OUT or @@ -99084,106 +99287,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(getOrigBE_t or - ld_byteEn_0 or - ld_byteEn_1 or - ld_byteEn_2 or - ld_byteEn_3 or - ld_byteEn_4 or - ld_byteEn_5 or - ld_byteEn_6 or - ld_byteEn_7 or - ld_byteEn_8 or - ld_byteEn_9 or - ld_byteEn_10 or - ld_byteEn_11 or - ld_byteEn_12 or - ld_byteEn_13 or - ld_byteEn_14 or - ld_byteEn_15 or - ld_byteEn_16 or - ld_byteEn_17 or - ld_byteEn_18 or - ld_byteEn_19 or - ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) - begin - case (getOrigBE_t[4:0]) - 5'd0: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_0[1]; - 5'd1: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_1[1]; - 5'd2: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_2[1]; - 5'd3: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_3[1]; - 5'd4: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_4[1]; - 5'd5: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_5[1]; - 5'd6: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_6[1]; - 5'd7: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_7[1]; - 5'd8: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_8[1]; - 5'd9: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_9[1]; - 5'd10: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_10[1]; - 5'd11: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_11[1]; - 5'd12: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_12[1]; - 5'd13: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_13[1]; - 5'd14: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_14[1]; - 5'd15: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_15[1]; - 5'd16: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_16[1]; - 5'd17: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_17[1]; - 5'd18: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_18[1]; - 5'd19: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_19[1]; - 5'd20: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_20[1]; - 5'd21: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_21[1]; - 5'd22: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_22[1]; - 5'd23: - SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - ld_byteEn_23[1]; - default: SEL_ARR_ld_byteEn_0_9259_BIT_1_9443_ld_byteEn__ETC___d19468 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or ld_shiftedBE_0_dummy2_0$Q_OUT or ld_shiftedBE_0_dummy2_1$Q_OUT or @@ -99738,105 +99841,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(respLd_t or - ld_dst_0 or - ld_dst_1 or - ld_dst_2 or - ld_dst_3 or - ld_dst_4 or - ld_dst_5 or - ld_dst_6 or - ld_dst_7 or - ld_dst_8 or - ld_dst_9 or - ld_dst_10 or - ld_dst_11 or - ld_dst_12 or - ld_dst_13 or - ld_dst_14 or - ld_dst_15 or - ld_dst_16 or - ld_dst_17 or - ld_dst_18 or - ld_dst_19 or ld_dst_20 or ld_dst_21 or ld_dst_22 or ld_dst_23) - begin - case (respLd_t) - 5'd0: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_0[0]; - 5'd1: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_1[0]; - 5'd2: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_2[0]; - 5'd3: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_3[0]; - 5'd4: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_4[0]; - 5'd5: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_5[0]; - 5'd6: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_6[0]; - 5'd7: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_7[0]; - 5'd8: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_8[0]; - 5'd9: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_9[0]; - 5'd10: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_10[0]; - 5'd11: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_11[0]; - 5'd12: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_12[0]; - 5'd13: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_13[0]; - 5'd14: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_14[0]; - 5'd15: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_15[0]; - 5'd16: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_16[0]; - 5'd17: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_17[0]; - 5'd18: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_18[0]; - 5'd19: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_19[0]; - 5'd20: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_20[0]; - 5'd21: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_21[0]; - 5'd22: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_22[0]; - 5'd23: - SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - ld_dst_23[0]; - default: SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = - 1'b0 /* unspecified value */ ; - endcase - end always@(issueLd_lsqTag or ld_dst_0 or ld_dst_1 or @@ -99936,6 +99940,105 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(respLd_t or + ld_dst_0 or + ld_dst_1 or + ld_dst_2 or + ld_dst_3 or + ld_dst_4 or + ld_dst_5 or + ld_dst_6 or + ld_dst_7 or + ld_dst_8 or + ld_dst_9 or + ld_dst_10 or + ld_dst_11 or + ld_dst_12 or + ld_dst_13 or + ld_dst_14 or + ld_dst_15 or + ld_dst_16 or + ld_dst_17 or + ld_dst_18 or + ld_dst_19 or ld_dst_20 or ld_dst_21 or ld_dst_22 or ld_dst_23) + begin + case (respLd_t) + 5'd0: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_0[0]; + 5'd1: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_1[0]; + 5'd2: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_2[0]; + 5'd3: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_3[0]; + 5'd4: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_4[0]; + 5'd5: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_5[0]; + 5'd6: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_6[0]; + 5'd7: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_7[0]; + 5'd8: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_8[0]; + 5'd9: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_9[0]; + 5'd10: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_10[0]; + 5'd11: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_11[0]; + 5'd12: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_12[0]; + 5'd13: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_13[0]; + 5'd14: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_14[0]; + 5'd15: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_15[0]; + 5'd16: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_16[0]; + 5'd17: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_17[0]; + 5'd18: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_18[0]; + 5'd19: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_19[0]; + 5'd20: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_20[0]; + 5'd21: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_21[0]; + 5'd22: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_22[0]; + 5'd23: + SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + ld_dst_23[0]; + default: SEL_ARR_ld_dst_0_9547_BIT_0_9683_ld_dst_1_9550_ETC___d23721 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_dst_0 or ld_dst_1 or @@ -100035,65 +100138,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(st_deqP or - st_dst_0 or - st_dst_1 or - st_dst_2 or - st_dst_3 or - st_dst_4 or - st_dst_5 or - st_dst_6 or - st_dst_7 or - st_dst_8 or - st_dst_9 or st_dst_10 or st_dst_11 or st_dst_12 or st_dst_13) - begin - case (st_deqP) - 4'd0: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_0[0]; - 4'd1: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_1[0]; - 4'd2: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_2[0]; - 4'd3: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_3[0]; - 4'd4: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_4[0]; - 4'd5: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_5[0]; - 4'd6: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_6[0]; - 4'd7: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_7[0]; - 4'd8: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_8[0]; - 4'd9: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_9[0]; - 4'd10: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_10[0]; - 4'd11: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_11[0]; - 4'd12: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_12[0]; - 4'd13: - SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - st_dst_13[0]; - default: SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = - 1'b0 /* unspecified value */ ; - endcase - end always@(st_deqP or st_instTag_0 or st_instTag_1 or @@ -100154,6 +100198,65 @@ module mkSplitLSQ(CLK, 6'b101010 /* unspecified value */ ; endcase end + always@(st_deqP or + st_dst_0 or + st_dst_1 or + st_dst_2 or + st_dst_3 or + st_dst_4 or + st_dst_5 or + st_dst_6 or + st_dst_7 or + st_dst_8 or + st_dst_9 or st_dst_10 or st_dst_11 or st_dst_12 or st_dst_13) + begin + case (st_deqP) + 4'd0: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_0[0]; + 4'd1: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_1[0]; + 4'd2: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_2[0]; + 4'd3: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_3[0]; + 4'd4: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_4[0]; + 4'd5: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_5[0]; + 4'd6: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_6[0]; + 4'd7: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_7[0]; + 4'd8: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_8[0]; + 4'd9: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_9[0]; + 4'd10: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_10[0]; + 4'd11: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_11[0]; + 4'd12: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_12[0]; + 4'd13: + SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + st_dst_13[0]; + default: SEL_ARR_st_dst_0_9501_BIT_0_9640_st_dst_1_9504_ETC___d25328 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_instTag_0 or ld_instTag_1 or @@ -100727,6 +100830,106 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(x__h1062868 or + ld_byteEn_0 or + ld_byteEn_1 or + ld_byteEn_2 or + ld_byteEn_3 or + ld_byteEn_4 or + ld_byteEn_5 or + ld_byteEn_6 or + ld_byteEn_7 or + ld_byteEn_8 or + ld_byteEn_9 or + ld_byteEn_10 or + ld_byteEn_11 or + ld_byteEn_12 or + ld_byteEn_13 or + ld_byteEn_14 or + ld_byteEn_15 or + ld_byteEn_16 or + ld_byteEn_17 or + ld_byteEn_18 or + ld_byteEn_19 or + ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) + begin + case (x__h1062868) + 5'd0: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_0[0]; + 5'd1: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_1[0]; + 5'd2: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_2[0]; + 5'd3: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_3[0]; + 5'd4: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_4[0]; + 5'd5: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_5[0]; + 5'd6: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_6[0]; + 5'd7: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_7[0]; + 5'd8: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_8[0]; + 5'd9: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_9[0]; + 5'd10: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_10[0]; + 5'd11: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_11[0]; + 5'd12: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_12[0]; + 5'd13: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_13[0]; + 5'd14: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_14[0]; + 5'd15: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_15[0]; + 5'd16: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_16[0]; + 5'd17: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_17[0]; + 5'd18: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_18[0]; + 5'd19: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_19[0]; + 5'd20: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_20[0]; + 5'd21: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_21[0]; + 5'd22: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_22[0]; + 5'd23: + SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + ld_byteEn_23[0]; + default: SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = + 1'b0 /* unspecified value */ ; + endcase + end always@(x__h1062868 or ld_unsigned_0 or ld_unsigned_1 or @@ -100828,104 +101031,64 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h1062868 or - ld_byteEn_0 or - ld_byteEn_1 or - ld_byteEn_2 or - ld_byteEn_3 or - ld_byteEn_4 or - ld_byteEn_5 or - ld_byteEn_6 or - ld_byteEn_7 or - ld_byteEn_8 or - ld_byteEn_9 or - ld_byteEn_10 or - ld_byteEn_11 or - ld_byteEn_12 or - ld_byteEn_13 or - ld_byteEn_14 or - ld_byteEn_15 or - ld_byteEn_16 or - ld_byteEn_17 or - ld_byteEn_18 or - ld_byteEn_19 or - ld_byteEn_20 or ld_byteEn_21 or ld_byteEn_22 or ld_byteEn_23) + always@(st_deqP or + st_amoFunc_0 or + st_amoFunc_1 or + st_amoFunc_2 or + st_amoFunc_3 or + st_amoFunc_4 or + st_amoFunc_5 or + st_amoFunc_6 or + st_amoFunc_7 or + st_amoFunc_8 or + st_amoFunc_9 or + st_amoFunc_10 or st_amoFunc_11 or st_amoFunc_12 or st_amoFunc_13) begin - case (x__h1062868) - 5'd0: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_0[0]; - 5'd1: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_1[0]; - 5'd2: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_2[0]; - 5'd3: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_3[0]; - 5'd4: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_4[0]; - 5'd5: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_5[0]; - 5'd6: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_6[0]; - 5'd7: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_7[0]; - 5'd8: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_8[0]; - 5'd9: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_9[0]; - 5'd10: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_10[0]; - 5'd11: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_11[0]; - 5'd12: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_12[0]; - 5'd13: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_13[0]; - 5'd14: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_14[0]; - 5'd15: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_15[0]; - 5'd16: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_16[0]; - 5'd17: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_17[0]; - 5'd18: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_18[0]; - 5'd19: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_19[0]; - 5'd20: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_20[0]; - 5'd21: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_21[0]; - 5'd22: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_22[0]; - 5'd23: - SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - ld_byteEn_23[0]; - default: SEL_ARR_ld_byteEn_0_9259_BIT_0_9469_ld_byteEn__ETC___d23905 = - 1'b0 /* unspecified value */ ; + case (st_deqP) + 4'd0: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_0; + 4'd1: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_1; + 4'd2: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_2; + 4'd3: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_3; + 4'd4: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_4; + 4'd5: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_5; + 4'd6: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_6; + 4'd7: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_7; + 4'd8: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_8; + 4'd9: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_9; + 4'd10: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_10; + 4'd11: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_11; + 4'd12: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_12; + 4'd13: + SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + st_amoFunc_13; + default: SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = + 4'b1010 /* unspecified value */ ; endcase end always@(st_deqP or @@ -100987,66 +101150,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(st_deqP or - st_amoFunc_0 or - st_amoFunc_1 or - st_amoFunc_2 or - st_amoFunc_3 or - st_amoFunc_4 or - st_amoFunc_5 or - st_amoFunc_6 or - st_amoFunc_7 or - st_amoFunc_8 or - st_amoFunc_9 or - st_amoFunc_10 or st_amoFunc_11 or st_amoFunc_12 or st_amoFunc_13) - begin - case (st_deqP) - 4'd0: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_0; - 4'd1: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_1; - 4'd2: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_2; - 4'd3: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_3; - 4'd4: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_4; - 4'd5: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_5; - 4'd6: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_6; - 4'd7: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_7; - 4'd8: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_8; - 4'd9: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_9; - 4'd10: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_10; - 4'd11: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_11; - 4'd12: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_12; - 4'd13: - SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - st_amoFunc_13; - default: SEL_ARR_st_amoFunc_0_5292_st_amoFunc_1_5293_st_ETC___d25307 = - 4'b1010 /* unspecified value */ ; - endcase - end always@(st_deqP or st_acq_0 or st_acq_1 or @@ -101453,6 +101556,132 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(issueLd_lsqTag or + ld_waitWPResp_0_dummy2_0$Q_OUT or + ld_waitWPResp_0_rl or + ld_waitWPResp_1_dummy2_0$Q_OUT or + ld_waitWPResp_1_rl or + ld_waitWPResp_2_dummy2_0$Q_OUT or + ld_waitWPResp_2_rl or + ld_waitWPResp_3_dummy2_0$Q_OUT or + ld_waitWPResp_3_rl or + ld_waitWPResp_4_dummy2_0$Q_OUT or + ld_waitWPResp_4_rl or + ld_waitWPResp_5_dummy2_0$Q_OUT or + ld_waitWPResp_5_rl or + ld_waitWPResp_6_dummy2_0$Q_OUT or + ld_waitWPResp_6_rl or + ld_waitWPResp_7_dummy2_0$Q_OUT or + ld_waitWPResp_7_rl or + ld_waitWPResp_8_dummy2_0$Q_OUT or + ld_waitWPResp_8_rl or + ld_waitWPResp_9_dummy2_0$Q_OUT or + ld_waitWPResp_9_rl or + ld_waitWPResp_10_dummy2_0$Q_OUT or + ld_waitWPResp_10_rl or + ld_waitWPResp_11_dummy2_0$Q_OUT or + ld_waitWPResp_11_rl or + ld_waitWPResp_12_dummy2_0$Q_OUT or + ld_waitWPResp_12_rl or + ld_waitWPResp_13_dummy2_0$Q_OUT or + ld_waitWPResp_13_rl or + ld_waitWPResp_14_dummy2_0$Q_OUT or + ld_waitWPResp_14_rl or + ld_waitWPResp_15_dummy2_0$Q_OUT or + ld_waitWPResp_15_rl or + ld_waitWPResp_16_dummy2_0$Q_OUT or + ld_waitWPResp_16_rl or + ld_waitWPResp_17_dummy2_0$Q_OUT or + ld_waitWPResp_17_rl or + ld_waitWPResp_18_dummy2_0$Q_OUT or + ld_waitWPResp_18_rl or + ld_waitWPResp_19_dummy2_0$Q_OUT or + ld_waitWPResp_19_rl or + ld_waitWPResp_20_dummy2_0$Q_OUT or + ld_waitWPResp_20_rl or + ld_waitWPResp_21_dummy2_0$Q_OUT or + ld_waitWPResp_21_rl or + ld_waitWPResp_22_dummy2_0$Q_OUT or + ld_waitWPResp_22_rl or + ld_waitWPResp_23_dummy2_0$Q_OUT or ld_waitWPResp_23_rl) + begin + case (issueLd_lsqTag) + 5'd0: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_0_dummy2_0$Q_OUT && ld_waitWPResp_0_rl; + 5'd1: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_1_dummy2_0$Q_OUT && ld_waitWPResp_1_rl; + 5'd2: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_2_dummy2_0$Q_OUT && ld_waitWPResp_2_rl; + 5'd3: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_3_dummy2_0$Q_OUT && ld_waitWPResp_3_rl; + 5'd4: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_4_dummy2_0$Q_OUT && ld_waitWPResp_4_rl; + 5'd5: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_5_dummy2_0$Q_OUT && ld_waitWPResp_5_rl; + 5'd6: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_6_dummy2_0$Q_OUT && ld_waitWPResp_6_rl; + 5'd7: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_7_dummy2_0$Q_OUT && ld_waitWPResp_7_rl; + 5'd8: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_8_dummy2_0$Q_OUT && ld_waitWPResp_8_rl; + 5'd9: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_9_dummy2_0$Q_OUT && ld_waitWPResp_9_rl; + 5'd10: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_10_dummy2_0$Q_OUT && ld_waitWPResp_10_rl; + 5'd11: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_11_dummy2_0$Q_OUT && ld_waitWPResp_11_rl; + 5'd12: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_12_dummy2_0$Q_OUT && ld_waitWPResp_12_rl; + 5'd13: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_13_dummy2_0$Q_OUT && ld_waitWPResp_13_rl; + 5'd14: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_14_dummy2_0$Q_OUT && ld_waitWPResp_14_rl; + 5'd15: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_15_dummy2_0$Q_OUT && ld_waitWPResp_15_rl; + 5'd16: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_16_dummy2_0$Q_OUT && ld_waitWPResp_16_rl; + 5'd17: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_17_dummy2_0$Q_OUT && ld_waitWPResp_17_rl; + 5'd18: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_18_dummy2_0$Q_OUT && ld_waitWPResp_18_rl; + 5'd19: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_19_dummy2_0$Q_OUT && ld_waitWPResp_19_rl; + 5'd20: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_20_dummy2_0$Q_OUT && ld_waitWPResp_20_rl; + 5'd21: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_21_dummy2_0$Q_OUT && ld_waitWPResp_21_rl; + 5'd22: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_22_dummy2_0$Q_OUT && ld_waitWPResp_22_rl; + 5'd23: + SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + ld_waitWPResp_23_dummy2_0$Q_OUT && ld_waitWPResp_23_rl; + default: SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = + 1'b0 /* unspecified value */ ; + endcase + end always@(updateAddr_lsqTag or ld_waitWPResp_0_dummy2_0$Q_OUT or ld_waitWPResp_0_rl or @@ -101951,235 +102180,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(issueLd_lsqTag or - ld_waitWPResp_0_dummy2_0$Q_OUT or - ld_waitWPResp_0_rl or - ld_waitWPResp_1_dummy2_0$Q_OUT or - ld_waitWPResp_1_rl or - ld_waitWPResp_2_dummy2_0$Q_OUT or - ld_waitWPResp_2_rl or - ld_waitWPResp_3_dummy2_0$Q_OUT or - ld_waitWPResp_3_rl or - ld_waitWPResp_4_dummy2_0$Q_OUT or - ld_waitWPResp_4_rl or - ld_waitWPResp_5_dummy2_0$Q_OUT or - ld_waitWPResp_5_rl or - ld_waitWPResp_6_dummy2_0$Q_OUT or - ld_waitWPResp_6_rl or - ld_waitWPResp_7_dummy2_0$Q_OUT or - ld_waitWPResp_7_rl or - ld_waitWPResp_8_dummy2_0$Q_OUT or - ld_waitWPResp_8_rl or - ld_waitWPResp_9_dummy2_0$Q_OUT or - ld_waitWPResp_9_rl or - ld_waitWPResp_10_dummy2_0$Q_OUT or - ld_waitWPResp_10_rl or - ld_waitWPResp_11_dummy2_0$Q_OUT or - ld_waitWPResp_11_rl or - ld_waitWPResp_12_dummy2_0$Q_OUT or - ld_waitWPResp_12_rl or - ld_waitWPResp_13_dummy2_0$Q_OUT or - ld_waitWPResp_13_rl or - ld_waitWPResp_14_dummy2_0$Q_OUT or - ld_waitWPResp_14_rl or - ld_waitWPResp_15_dummy2_0$Q_OUT or - ld_waitWPResp_15_rl or - ld_waitWPResp_16_dummy2_0$Q_OUT or - ld_waitWPResp_16_rl or - ld_waitWPResp_17_dummy2_0$Q_OUT or - ld_waitWPResp_17_rl or - ld_waitWPResp_18_dummy2_0$Q_OUT or - ld_waitWPResp_18_rl or - ld_waitWPResp_19_dummy2_0$Q_OUT or - ld_waitWPResp_19_rl or - ld_waitWPResp_20_dummy2_0$Q_OUT or - ld_waitWPResp_20_rl or - ld_waitWPResp_21_dummy2_0$Q_OUT or - ld_waitWPResp_21_rl or - ld_waitWPResp_22_dummy2_0$Q_OUT or - ld_waitWPResp_22_rl or - ld_waitWPResp_23_dummy2_0$Q_OUT or ld_waitWPResp_23_rl) - begin - case (issueLd_lsqTag) - 5'd0: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_0_dummy2_0$Q_OUT && ld_waitWPResp_0_rl; - 5'd1: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_1_dummy2_0$Q_OUT && ld_waitWPResp_1_rl; - 5'd2: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_2_dummy2_0$Q_OUT && ld_waitWPResp_2_rl; - 5'd3: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_3_dummy2_0$Q_OUT && ld_waitWPResp_3_rl; - 5'd4: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_4_dummy2_0$Q_OUT && ld_waitWPResp_4_rl; - 5'd5: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_5_dummy2_0$Q_OUT && ld_waitWPResp_5_rl; - 5'd6: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_6_dummy2_0$Q_OUT && ld_waitWPResp_6_rl; - 5'd7: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_7_dummy2_0$Q_OUT && ld_waitWPResp_7_rl; - 5'd8: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_8_dummy2_0$Q_OUT && ld_waitWPResp_8_rl; - 5'd9: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_9_dummy2_0$Q_OUT && ld_waitWPResp_9_rl; - 5'd10: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_10_dummy2_0$Q_OUT && ld_waitWPResp_10_rl; - 5'd11: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_11_dummy2_0$Q_OUT && ld_waitWPResp_11_rl; - 5'd12: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_12_dummy2_0$Q_OUT && ld_waitWPResp_12_rl; - 5'd13: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_13_dummy2_0$Q_OUT && ld_waitWPResp_13_rl; - 5'd14: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_14_dummy2_0$Q_OUT && ld_waitWPResp_14_rl; - 5'd15: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_15_dummy2_0$Q_OUT && ld_waitWPResp_15_rl; - 5'd16: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_16_dummy2_0$Q_OUT && ld_waitWPResp_16_rl; - 5'd17: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_17_dummy2_0$Q_OUT && ld_waitWPResp_17_rl; - 5'd18: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_18_dummy2_0$Q_OUT && ld_waitWPResp_18_rl; - 5'd19: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_19_dummy2_0$Q_OUT && ld_waitWPResp_19_rl; - 5'd20: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_20_dummy2_0$Q_OUT && ld_waitWPResp_20_rl; - 5'd21: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_21_dummy2_0$Q_OUT && ld_waitWPResp_21_rl; - 5'd22: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_22_dummy2_0$Q_OUT && ld_waitWPResp_22_rl; - 5'd23: - SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - ld_waitWPResp_23_dummy2_0$Q_OUT && ld_waitWPResp_23_rl; - default: SEL_ARR_ld_waitWPResp_0_dummy2_0_read__1700_AN_ETC___d21824 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(issueLdQ$first or - NOT_ld_inIssueQ_0_dummy2_0_read__1641_1642_OR__ETC___d11650 or - NOT_ld_inIssueQ_1_dummy2_0_read__1725_1726_OR__ETC___d11734 or - NOT_ld_inIssueQ_2_dummy2_0_read__1809_1810_OR__ETC___d11818 or - NOT_ld_inIssueQ_3_dummy2_0_read__1893_1894_OR__ETC___d11902 or - NOT_ld_inIssueQ_4_dummy2_0_read__1977_1978_OR__ETC___d11986 or - NOT_ld_inIssueQ_5_dummy2_0_read__2061_2062_OR__ETC___d12070 or - NOT_ld_inIssueQ_6_dummy2_0_read__2145_2146_OR__ETC___d12154 or - NOT_ld_inIssueQ_7_dummy2_0_read__2229_2230_OR__ETC___d12238 or - NOT_ld_inIssueQ_8_dummy2_0_read__2313_2314_OR__ETC___d12322 or - NOT_ld_inIssueQ_9_dummy2_0_read__2397_2398_OR__ETC___d12406 or - NOT_ld_inIssueQ_10_dummy2_0_read__2481_2482_OR_ETC___d12490 or - NOT_ld_inIssueQ_11_dummy2_0_read__2565_2566_OR_ETC___d12574 or - NOT_ld_inIssueQ_12_dummy2_0_read__2649_2650_OR_ETC___d12658 or - NOT_ld_inIssueQ_13_dummy2_0_read__2733_2734_OR_ETC___d12742 or - NOT_ld_inIssueQ_14_dummy2_0_read__2817_2818_OR_ETC___d12826 or - NOT_ld_inIssueQ_15_dummy2_0_read__2901_2902_OR_ETC___d12910 or - NOT_ld_inIssueQ_16_dummy2_0_read__2985_2986_OR_ETC___d12994 or - NOT_ld_inIssueQ_17_dummy2_0_read__3069_3070_OR_ETC___d13078 or - NOT_ld_inIssueQ_18_dummy2_0_read__3153_3154_OR_ETC___d13162 or - NOT_ld_inIssueQ_19_dummy2_0_read__3237_3238_OR_ETC___d13246 or - NOT_ld_inIssueQ_20_dummy2_0_read__3321_3322_OR_ETC___d13330 or - NOT_ld_inIssueQ_21_dummy2_0_read__3405_3406_OR_ETC___d13414 or - NOT_ld_inIssueQ_22_dummy2_0_read__3489_3490_OR_ETC___d13498 or - NOT_ld_inIssueQ_23_dummy2_0_read__3573_3574_OR_ETC___d13582) - begin - case (issueLdQ$first[88:84]) - 5'd0: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_0_dummy2_0_read__1641_1642_OR__ETC___d11650; - 5'd1: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_1_dummy2_0_read__1725_1726_OR__ETC___d11734; - 5'd2: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_2_dummy2_0_read__1809_1810_OR__ETC___d11818; - 5'd3: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_3_dummy2_0_read__1893_1894_OR__ETC___d11902; - 5'd4: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_4_dummy2_0_read__1977_1978_OR__ETC___d11986; - 5'd5: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_5_dummy2_0_read__2061_2062_OR__ETC___d12070; - 5'd6: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_6_dummy2_0_read__2145_2146_OR__ETC___d12154; - 5'd7: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_7_dummy2_0_read__2229_2230_OR__ETC___d12238; - 5'd8: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_8_dummy2_0_read__2313_2314_OR__ETC___d12322; - 5'd9: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_9_dummy2_0_read__2397_2398_OR__ETC___d12406; - 5'd10: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_10_dummy2_0_read__2481_2482_OR_ETC___d12490; - 5'd11: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_11_dummy2_0_read__2565_2566_OR_ETC___d12574; - 5'd12: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_12_dummy2_0_read__2649_2650_OR_ETC___d12658; - 5'd13: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_13_dummy2_0_read__2733_2734_OR_ETC___d12742; - 5'd14: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_14_dummy2_0_read__2817_2818_OR_ETC___d12826; - 5'd15: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_15_dummy2_0_read__2901_2902_OR_ETC___d12910; - 5'd16: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_16_dummy2_0_read__2985_2986_OR_ETC___d12994; - 5'd17: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_17_dummy2_0_read__3069_3070_OR_ETC___d13078; - 5'd18: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_18_dummy2_0_read__3153_3154_OR_ETC___d13162; - 5'd19: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_19_dummy2_0_read__3237_3238_OR_ETC___d13246; - 5'd20: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_20_dummy2_0_read__3321_3322_OR_ETC___d13330; - 5'd21: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_21_dummy2_0_read__3405_3406_OR_ETC___d13414; - 5'd22: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_22_dummy2_0_read__3489_3490_OR_ETC___d13498; - 5'd23: - SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - NOT_ld_inIssueQ_23_dummy2_0_read__3573_3574_OR_ETC___d13582; - default: SEL_ARR_NOT_ld_inIssueQ_0_dummy2_0_read__1641__ETC___d23620 = - 1'b0 /* unspecified value */ ; - endcase - end always@(x__h1062868 or ld_instTag_0 or ld_instTag_1 or @@ -110932,6 +110932,205 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(b__h1519810 or + NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or + IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or + ld_acq_0 or + NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 or + IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 or + ld_acq_1 or + NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 or + IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 or + ld_acq_2 or + NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 or + IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 or + ld_acq_3 or + NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 or + IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 or + ld_acq_4 or + NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 or + IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 or + ld_acq_5 or + NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 or + IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 or + ld_acq_6 or + NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 or + IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 or + ld_acq_7 or + NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 or + IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 or + ld_acq_8 or + NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 or + IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 or + ld_acq_9 or + NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 or + IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 or + ld_acq_10 or + NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 or + IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 or + ld_acq_11 or + NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 or + IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 or + ld_acq_12 or + NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 or + IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 or + ld_acq_13 or + NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 or + IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 or + ld_acq_14 or + NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 or + IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 or + ld_acq_15 or + NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 or + IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 or + ld_acq_16 or + NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 or + IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 or + ld_acq_17 or + NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 or + IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 or + ld_acq_18 or + NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 or + IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 or + ld_acq_19 or + NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 or + IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 or + ld_acq_20 or + NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 or + IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 or + ld_acq_21 or + NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 or + IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 or + ld_acq_22 or + NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 or + IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 or + ld_acq_23) + begin + case (b__h1519810) + 5'd0: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 || + !IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 || + !ld_acq_0; + 5'd1: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 || + !IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 || + !ld_acq_1; + 5'd2: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 || + !IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 || + !ld_acq_2; + 5'd3: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 || + !IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 || + !ld_acq_3; + 5'd4: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 || + !IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 || + !ld_acq_4; + 5'd5: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 || + !IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 || + !ld_acq_5; + 5'd6: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 || + !IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 || + !ld_acq_6; + 5'd7: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 || + !IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 || + !ld_acq_7; + 5'd8: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 || + !IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 || + !ld_acq_8; + 5'd9: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 || + !IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 || + !ld_acq_9; + 5'd10: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 || + !IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 || + !ld_acq_10; + 5'd11: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 || + !IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 || + !ld_acq_11; + 5'd12: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 || + !IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 || + !ld_acq_12; + 5'd13: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 || + !IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 || + !ld_acq_13; + 5'd14: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 || + !IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 || + !ld_acq_14; + 5'd15: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 || + !IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 || + !ld_acq_15; + 5'd16: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 || + !IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 || + !ld_acq_16; + 5'd17: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 || + !IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 || + !ld_acq_17; + 5'd18: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 || + !IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 || + !ld_acq_18; + 5'd19: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 || + !IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 || + !ld_acq_19; + 5'd20: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 || + !IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 || + !ld_acq_20; + 5'd21: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 || + !IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 || + !ld_acq_21; + 5'd22: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 || + !IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 || + !ld_acq_22; + 5'd23: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 || + !IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 || + !ld_acq_23; + default: SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = + 1'b0 /* unspecified value */ ; + endcase + end always@(b__h1516698 or NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or @@ -111330,205 +111529,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(b__h1519810 or - NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or - IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or - ld_acq_0 or - NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 or - IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 or - ld_acq_1 or - NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 or - IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 or - ld_acq_2 or - NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 or - IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 or - ld_acq_3 or - NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 or - IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 or - ld_acq_4 or - NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 or - IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 or - ld_acq_5 or - NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 or - IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 or - ld_acq_6 or - NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 or - IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 or - ld_acq_7 or - NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 or - IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 or - ld_acq_8 or - NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 or - IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 or - ld_acq_9 or - NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 or - IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 or - ld_acq_10 or - NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 or - IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 or - ld_acq_11 or - NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 or - IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 or - ld_acq_12 or - NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 or - IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 or - ld_acq_13 or - NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 or - IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 or - ld_acq_14 or - NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 or - IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 or - ld_acq_15 or - NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 or - IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 or - ld_acq_16 or - NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 or - IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 or - ld_acq_17 or - NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 or - IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 or - ld_acq_18 or - NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 or - IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 or - ld_acq_19 or - NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 or - IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 or - ld_acq_20 or - NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 or - IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 or - ld_acq_21 or - NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 or - IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 or - ld_acq_22 or - NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 or - IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 or - ld_acq_23) - begin - case (b__h1519810) - 5'd0: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 || - !IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 || - !ld_acq_0; - 5'd1: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 || - !IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 || - !ld_acq_1; - 5'd2: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 || - !IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 || - !ld_acq_2; - 5'd3: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 || - !IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 || - !ld_acq_3; - 5'd4: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 || - !IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 || - !ld_acq_4; - 5'd5: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 || - !IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 || - !ld_acq_5; - 5'd6: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 || - !IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 || - !ld_acq_6; - 5'd7: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 || - !IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 || - !ld_acq_7; - 5'd8: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 || - !IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 || - !ld_acq_8; - 5'd9: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 || - !IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 || - !ld_acq_9; - 5'd10: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 || - !IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 || - !ld_acq_10; - 5'd11: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 || - !IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 || - !ld_acq_11; - 5'd12: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 || - !IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 || - !ld_acq_12; - 5'd13: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 || - !IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 || - !ld_acq_13; - 5'd14: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 || - !IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 || - !ld_acq_14; - 5'd15: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 || - !IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 || - !ld_acq_15; - 5'd16: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 || - !IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 || - !ld_acq_16; - 5'd17: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 || - !IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 || - !ld_acq_17; - 5'd18: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 || - !IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 || - !ld_acq_18; - 5'd19: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 || - !IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 || - !ld_acq_19; - 5'd20: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 || - !IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 || - !ld_acq_20; - 5'd21: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 || - !IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 || - !ld_acq_21; - 5'd22: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 || - !IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 || - !ld_acq_22; - 5'd23: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 || - !IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 || - !ld_acq_23; - default: SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22045 = - 1'b0 /* unspecified value */ ; - endcase - end always@(a__h1519809 or NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or @@ -112531,205 +112531,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(a__h1520485 or - NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or - IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or - ld_acq_0 or - NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 or - IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 or - ld_acq_1 or - NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 or - IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 or - ld_acq_2 or - NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 or - IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 or - ld_acq_3 or - NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 or - IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 or - ld_acq_4 or - NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 or - IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 or - ld_acq_5 or - NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 or - IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 or - ld_acq_6 or - NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 or - IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 or - ld_acq_7 or - NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 or - IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 or - ld_acq_8 or - NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 or - IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 or - ld_acq_9 or - NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 or - IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 or - ld_acq_10 or - NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 or - IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 or - ld_acq_11 or - NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 or - IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 or - ld_acq_12 or - NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 or - IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 or - ld_acq_13 or - NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 or - IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 or - ld_acq_14 or - NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 or - IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 or - ld_acq_15 or - NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 or - IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 or - ld_acq_16 or - NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 or - IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 or - ld_acq_17 or - NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 or - IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 or - ld_acq_18 or - NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 or - IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 or - ld_acq_19 or - NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 or - IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 or - ld_acq_20 or - NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 or - IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 or - ld_acq_21 or - NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 or - IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 or - ld_acq_22 or - NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 or - IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 or - ld_acq_23) - begin - case (a__h1520485) - 5'd0: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 || - !IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 || - !ld_acq_0; - 5'd1: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 || - !IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 || - !ld_acq_1; - 5'd2: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 || - !IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 || - !ld_acq_2; - 5'd3: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 || - !IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 || - !ld_acq_3; - 5'd4: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 || - !IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 || - !ld_acq_4; - 5'd5: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 || - !IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 || - !ld_acq_5; - 5'd6: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 || - !IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 || - !ld_acq_6; - 5'd7: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 || - !IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 || - !ld_acq_7; - 5'd8: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 || - !IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 || - !ld_acq_8; - 5'd9: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 || - !IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 || - !ld_acq_9; - 5'd10: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 || - !IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 || - !ld_acq_10; - 5'd11: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 || - !IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 || - !ld_acq_11; - 5'd12: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 || - !IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 || - !ld_acq_12; - 5'd13: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 || - !IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 || - !ld_acq_13; - 5'd14: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 || - !IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 || - !ld_acq_14; - 5'd15: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 || - !IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 || - !ld_acq_15; - 5'd16: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 || - !IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 || - !ld_acq_16; - 5'd17: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 || - !IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 || - !ld_acq_17; - 5'd18: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 || - !IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 || - !ld_acq_18; - 5'd19: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 || - !IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 || - !ld_acq_19; - 5'd20: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 || - !IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 || - !ld_acq_20; - 5'd21: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 || - !IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 || - !ld_acq_21; - 5'd22: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 || - !IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 || - !ld_acq_22; - 5'd23: - SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 || - !IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 || - !ld_acq_23; - default: SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = - 1'b0 /* unspecified value */ ; - endcase - end always@(b__h1520991 or NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or @@ -112929,6 +112730,205 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(a__h1520485 or + NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or + IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or + ld_acq_0 or + NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 or + IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 or + ld_acq_1 or + NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 or + IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 or + ld_acq_2 or + NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 or + IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 or + ld_acq_3 or + NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 or + IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 or + ld_acq_4 or + NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 or + IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 or + ld_acq_5 or + NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 or + IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 or + ld_acq_6 or + NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 or + IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 or + ld_acq_7 or + NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 or + IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 or + ld_acq_8 or + NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 or + IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 or + ld_acq_9 or + NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 or + IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 or + ld_acq_10 or + NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 or + IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 or + ld_acq_11 or + NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 or + IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 or + ld_acq_12 or + NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 or + IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 or + ld_acq_13 or + NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 or + IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 or + ld_acq_14 or + NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 or + IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 or + ld_acq_15 or + NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 or + IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 or + ld_acq_16 or + NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 or + IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 or + ld_acq_17 or + NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 or + IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 or + ld_acq_18 or + NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 or + IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 or + ld_acq_19 or + NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 or + IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 or + ld_acq_20 or + NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 or + IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 or + ld_acq_21 or + NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 or + IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 or + ld_acq_22 or + NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 or + IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 or + ld_acq_23) + begin + case (a__h1520485) + 5'd0: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 || + !IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 || + !ld_acq_0; + 5'd1: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_1_dummy2_1_read__1714_3687_OR_IF__ETC___d15377 || + !IF_ld_enqP_4607_ULE_1_4610_THEN_1_ELSE_25_4611_ETC___d21833 || + !ld_acq_1; + 5'd2: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_2_dummy2_1_read__1798_3727_OR_IF__ETC___d15380 || + !IF_ld_enqP_4607_ULE_2_4617_THEN_2_ELSE_26_4618_ETC___d21837 || + !ld_acq_2; + 5'd3: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_3_dummy2_1_read__1882_3767_OR_IF__ETC___d15383 || + !IF_ld_enqP_4607_ULE_3_4619_THEN_3_ELSE_27_4620_ETC___d21841 || + !ld_acq_3; + 5'd4: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_4_dummy2_1_read__1966_3807_OR_IF__ETC___d15386 || + !IF_ld_enqP_4607_ULE_4_4626_THEN_4_ELSE_28_4627_ETC___d21845 || + !ld_acq_4; + 5'd5: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_5_dummy2_1_read__2050_3847_OR_IF__ETC___d15389 || + !IF_ld_enqP_4607_ULE_5_4628_THEN_5_ELSE_29_4629_ETC___d21849 || + !ld_acq_5; + 5'd6: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_6_dummy2_1_read__2134_3887_OR_IF__ETC___d15392 || + !IF_ld_enqP_4607_ULE_6_4630_THEN_6_ELSE_30_4631_ETC___d21853 || + !ld_acq_6; + 5'd7: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_7_dummy2_1_read__2218_3927_OR_IF__ETC___d15395 || + !IF_ld_enqP_4607_ULE_7_4632_THEN_7_ELSE_31_4633_ETC___d21857 || + !ld_acq_7; + 5'd8: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_8_dummy2_1_read__2302_3967_OR_IF__ETC___d15398 || + !IF_ld_enqP_4607_ULE_8_4634_THEN_8_ELSE_32_4635_ETC___d21861 || + !ld_acq_8; + 5'd9: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_9_dummy2_1_read__2386_4007_OR_IF__ETC___d15401 || + !IF_ld_enqP_4607_ULE_9_4636_THEN_9_ELSE_33_4637_ETC___d21865 || + !ld_acq_9; + 5'd10: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_10_dummy2_1_read__2470_4047_OR_IF_ETC___d15404 || + !IF_ld_enqP_4607_ULE_10_4638_THEN_10_ELSE_34_46_ETC___d21869 || + !ld_acq_10; + 5'd11: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_11_dummy2_1_read__2554_4087_OR_IF_ETC___d15407 || + !IF_ld_enqP_4607_ULE_11_4640_THEN_11_ELSE_35_46_ETC___d21873 || + !ld_acq_11; + 5'd12: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_12_dummy2_1_read__2638_4127_OR_IF_ETC___d15410 || + !IF_ld_enqP_4607_ULE_12_4642_THEN_12_ELSE_36_46_ETC___d21877 || + !ld_acq_12; + 5'd13: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_13_dummy2_1_read__2722_4167_OR_IF_ETC___d15413 || + !IF_ld_enqP_4607_ULE_13_4644_THEN_13_ELSE_37_46_ETC___d21881 || + !ld_acq_13; + 5'd14: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_14_dummy2_1_read__2806_4207_OR_IF_ETC___d15416 || + !IF_ld_enqP_4607_ULE_14_4646_THEN_14_ELSE_38_46_ETC___d21885 || + !ld_acq_14; + 5'd15: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_15_dummy2_1_read__2890_4247_OR_IF_ETC___d15419 || + !IF_ld_enqP_4607_ULE_15_4648_THEN_15_ELSE_39_46_ETC___d21889 || + !ld_acq_15; + 5'd16: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_16_dummy2_1_read__2974_4287_OR_IF_ETC___d15422 || + !IF_ld_enqP_4607_ULE_16_4650_THEN_16_ELSE_40_46_ETC___d21893 || + !ld_acq_16; + 5'd17: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_17_dummy2_1_read__3058_4327_OR_IF_ETC___d15425 || + !IF_ld_enqP_4607_ULE_17_4652_THEN_17_ELSE_41_46_ETC___d21897 || + !ld_acq_17; + 5'd18: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_18_dummy2_1_read__3142_4367_OR_IF_ETC___d15428 || + !IF_ld_enqP_4607_ULE_18_4654_THEN_18_ELSE_42_46_ETC___d21901 || + !ld_acq_18; + 5'd19: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_19_dummy2_1_read__3226_4407_OR_IF_ETC___d15431 || + !IF_ld_enqP_4607_ULE_19_4656_THEN_19_ELSE_43_46_ETC___d21905 || + !ld_acq_19; + 5'd20: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_20_dummy2_1_read__3310_4447_OR_IF_ETC___d15434 || + !IF_ld_enqP_4607_ULE_20_4658_THEN_20_ELSE_44_46_ETC___d21909 || + !ld_acq_20; + 5'd21: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_21_dummy2_1_read__3394_4487_OR_IF_ETC___d15437 || + !IF_ld_enqP_4607_ULE_21_4660_THEN_21_ELSE_45_46_ETC___d21913 || + !ld_acq_21; + 5'd22: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_22_dummy2_1_read__3478_4527_OR_IF_ETC___d15440 || + !IF_ld_enqP_4607_ULE_22_4662_THEN_22_ELSE_46_46_ETC___d21917 || + !ld_acq_22; + 5'd23: + SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + NOT_ld_valid_23_dummy2_1_read__3562_4567_OR_IF_ETC___d15443 || + !IF_ld_enqP_4607_ULE_23_4664_THEN_23_ELSE_47_46_ETC___d21921 || + !ld_acq_23; + default: SEL_ARR_NOT_ld_valid_0_dummy2_1_read__1630_364_ETC___d22063 = + 1'b0 /* unspecified value */ ; + endcase + end always@(a__h1520990 or NOT_ld_valid_0_dummy2_1_read__1630_3647_OR_IF__ETC___d15374 or IF_ld_enqP_4607_EQ_0_4608_THEN_0_ELSE_24_4609__ETC___d21829 or @@ -119965,17 +119965,6 @@ module mkSplitLSQ(CLK, endcase end always@(addr__h1630586 or respLd_alignedData) - begin - case (addr__h1630586[2]) - 1'd0: - SEL_ARR_respLd_alignedData_BITS_31_TO_0_3753_r_ETC___d23758 = - respLd_alignedData[31:0]; - 1'd1: - SEL_ARR_respLd_alignedData_BITS_31_TO_0_3753_r_ETC___d23758 = - respLd_alignedData[63:32]; - endcase - end - always@(addr__h1630586 or respLd_alignedData) begin case (addr__h1630586[2:0]) 3'd0: @@ -120004,6 +119993,17 @@ module mkSplitLSQ(CLK, respLd_alignedData[63:56]; endcase end + always@(addr__h1630586 or respLd_alignedData) + begin + case (addr__h1630586[2]) + 1'd0: + SEL_ARR_respLd_alignedData_BITS_31_TO_0_3753_r_ETC___d23758 = + respLd_alignedData[31:0]; + 1'd1: + SEL_ARR_respLd_alignedData_BITS_31_TO_0_3753_r_ETC___d23758 = + respLd_alignedData[63:32]; + endcase + end always@(issueLd_lsqTag or NOT_ld_computed_0_dummy2_1_read__1637_3653_OR__ETC___d15580 or NOT_ld_computed_1_dummy2_1_read__1721_3693_OR__ETC___d15583 or @@ -124304,69 +124304,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(stTag__h1515530 or - st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22190 or - st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22246 or - st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22301 or - st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22356 or - st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22411 or - st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22466 or - st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22521 or - st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22576 or - st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22631 or - st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22686 or - st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22741 or - st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22796 or - st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22851 or - st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22906) - begin - case (stTag__h1515530) - 4'd0: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22190; - 4'd1: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22246; - 4'd2: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22301; - 4'd3: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22356; - 4'd4: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22411; - 4'd5: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22466; - 4'd6: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22521; - 4'd7: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22576; - 4'd8: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22631; - 4'd9: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22686; - 4'd10: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22741; - 4'd11: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22796; - 4'd12: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22851; - 4'd13: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22906; - default: SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = - 1'b0 /* unspecified value */ ; - endcase - end always@(stTag__h1515530 or st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22196 or st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22252 or @@ -124430,66 +124367,66 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(st_deqP or - st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22164 or - st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22220 or - st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22275 or - st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22330 or - st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22385 or - st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22440 or - st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22495 or - st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22550 or - st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22605 or - st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22660 or - st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22715 or - st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22770 or - st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22825 or - st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22880) + always@(stTag__h1515530 or + st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22190 or + st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22246 or + st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22301 or + st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22356 or + st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22411 or + st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22466 or + st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22521 or + st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22576 or + st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22631 or + st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22686 or + st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22741 or + st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22796 or + st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22851 or + st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22906) begin - case (st_deqP) + case (stTag__h1515530) 4'd0: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22164; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22190; 4'd1: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22220; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22246; 4'd2: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22275; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22301; 4'd3: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22330; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22356; 4'd4: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22385; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22411; 4'd5: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22440; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22466; 4'd6: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22495; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22521; 4'd7: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22550; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22576; 4'd8: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22605; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22631; 4'd9: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22660; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22686; 4'd10: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22715; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22741; 4'd11: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22770; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22796; 4'd12: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22825; + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22851; 4'd13: - SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = - st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22880; - default: SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = + st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22906; + default: SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d23304 = 1'b0 /* unspecified value */ ; endcase end @@ -124556,6 +124493,69 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(st_deqP or + st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22164 or + st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22220 or + st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22275 or + st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22330 or + st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22385 or + st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22440 or + st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22495 or + st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22550 or + st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22605 or + st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22660 or + st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22715 or + st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22770 or + st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22825 or + st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22880) + begin + case (st_deqP) + 4'd0: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22164; + 4'd1: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22220; + 4'd2: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_2_dummy2_1_read__2271_AND_IF_st_s_ETC___d22275; + 4'd3: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_3_dummy2_1_read__2326_AND_IF_st_s_ETC___d22330; + 4'd4: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_4_dummy2_1_read__2381_AND_IF_st_s_ETC___d22385; + 4'd5: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_5_dummy2_1_read__2436_AND_IF_st_s_ETC___d22440; + 4'd6: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_6_dummy2_1_read__2491_AND_IF_st_s_ETC___d22495; + 4'd7: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_7_dummy2_1_read__2546_AND_IF_st_s_ETC___d22550; + 4'd8: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_8_dummy2_1_read__2601_AND_IF_st_s_ETC___d22605; + 4'd9: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_9_dummy2_1_read__2656_AND_IF_st_s_ETC___d22660; + 4'd10: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_10_dummy2_1_read__2711_AND_IF_st__ETC___d22715; + 4'd11: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_11_dummy2_1_read__2766_AND_IF_st__ETC___d22770; + 4'd12: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_12_dummy2_1_read__2821_AND_IF_st__ETC___d22825; + 4'd13: + SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + st_shiftedBE_13_dummy2_1_read__2876_AND_IF_st__ETC___d22880; + default: SEL_ARR_st_shiftedBE_0_dummy2_1_read__2160_AND_ETC___d25364 = + 1'b0 /* unspecified value */ ; + endcase + end always@(st_deqP or st_shiftedBE_0_dummy2_1_read__2160_AND_IF_st_s_ETC___d22172 or st_shiftedBE_1_dummy2_1_read__2216_AND_IF_st_s_ETC___d22228 or @@ -125129,83 +125129,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(st_deqP or - IF_st_fault_0_lat_0_whas__819_THEN_IF_st_fault_ETC___d25447 or - IF_st_fault_1_lat_0_whas__917_THEN_IF_st_fault_ETC___d25475 or - IF_st_fault_2_lat_0_whas__0015_THEN_IF_st_faul_ETC___d25503 or - IF_st_fault_3_lat_0_whas__0113_THEN_IF_st_faul_ETC___d25531 or - IF_st_fault_4_lat_0_whas__0211_THEN_IF_st_faul_ETC___d25559 or - IF_st_fault_5_lat_0_whas__0309_THEN_IF_st_faul_ETC___d25587 or - IF_st_fault_6_lat_0_whas__0407_THEN_IF_st_faul_ETC___d25615 or - IF_st_fault_7_lat_0_whas__0505_THEN_IF_st_faul_ETC___d25643 or - IF_st_fault_8_lat_0_whas__0603_THEN_IF_st_faul_ETC___d25671 or - IF_st_fault_9_lat_0_whas__0701_THEN_IF_st_faul_ETC___d25699 or - IF_st_fault_10_lat_0_whas__0799_THEN_IF_st_fau_ETC___d25727 or - IF_st_fault_11_lat_0_whas__0897_THEN_IF_st_fau_ETC___d25755 or - IF_st_fault_12_lat_0_whas__0995_THEN_IF_st_fau_ETC___d25783 or - IF_st_fault_13_lat_0_whas__1093_THEN_IF_st_fau_ETC___d25811) - begin - case (st_deqP) - 4'd0: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_0_lat_0_whas__819_THEN_IF_st_fault_ETC___d25447 == - 4'd8; - 4'd1: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_1_lat_0_whas__917_THEN_IF_st_fault_ETC___d25475 == - 4'd8; - 4'd2: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_2_lat_0_whas__0015_THEN_IF_st_faul_ETC___d25503 == - 4'd8; - 4'd3: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_3_lat_0_whas__0113_THEN_IF_st_faul_ETC___d25531 == - 4'd8; - 4'd4: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_4_lat_0_whas__0211_THEN_IF_st_faul_ETC___d25559 == - 4'd8; - 4'd5: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_5_lat_0_whas__0309_THEN_IF_st_faul_ETC___d25587 == - 4'd8; - 4'd6: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_6_lat_0_whas__0407_THEN_IF_st_faul_ETC___d25615 == - 4'd8; - 4'd7: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_7_lat_0_whas__0505_THEN_IF_st_faul_ETC___d25643 == - 4'd8; - 4'd8: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_8_lat_0_whas__0603_THEN_IF_st_faul_ETC___d25671 == - 4'd8; - 4'd9: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_9_lat_0_whas__0701_THEN_IF_st_faul_ETC___d25699 == - 4'd8; - 4'd10: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_10_lat_0_whas__0799_THEN_IF_st_fau_ETC___d25727 == - 4'd8; - 4'd11: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_11_lat_0_whas__0897_THEN_IF_st_fau_ETC___d25755 == - 4'd8; - 4'd12: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_12_lat_0_whas__0995_THEN_IF_st_fau_ETC___d25783 == - 4'd8; - 4'd13: - SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - IF_st_fault_13_lat_0_whas__1093_THEN_IF_st_fau_ETC___d25811 == - 4'd8; - default: SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = - 1'b0 /* unspecified value */ ; - endcase - end always@(st_deqP or IF_st_fault_0_lat_0_whas__819_THEN_IF_st_fault_ETC___d25447 or IF_st_fault_1_lat_0_whas__917_THEN_IF_st_fault_ETC___d25475 or @@ -125283,6 +125206,83 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(st_deqP or + IF_st_fault_0_lat_0_whas__819_THEN_IF_st_fault_ETC___d25447 or + IF_st_fault_1_lat_0_whas__917_THEN_IF_st_fault_ETC___d25475 or + IF_st_fault_2_lat_0_whas__0015_THEN_IF_st_faul_ETC___d25503 or + IF_st_fault_3_lat_0_whas__0113_THEN_IF_st_faul_ETC___d25531 or + IF_st_fault_4_lat_0_whas__0211_THEN_IF_st_faul_ETC___d25559 or + IF_st_fault_5_lat_0_whas__0309_THEN_IF_st_faul_ETC___d25587 or + IF_st_fault_6_lat_0_whas__0407_THEN_IF_st_faul_ETC___d25615 or + IF_st_fault_7_lat_0_whas__0505_THEN_IF_st_faul_ETC___d25643 or + IF_st_fault_8_lat_0_whas__0603_THEN_IF_st_faul_ETC___d25671 or + IF_st_fault_9_lat_0_whas__0701_THEN_IF_st_faul_ETC___d25699 or + IF_st_fault_10_lat_0_whas__0799_THEN_IF_st_fau_ETC___d25727 or + IF_st_fault_11_lat_0_whas__0897_THEN_IF_st_fau_ETC___d25755 or + IF_st_fault_12_lat_0_whas__0995_THEN_IF_st_fau_ETC___d25783 or + IF_st_fault_13_lat_0_whas__1093_THEN_IF_st_fau_ETC___d25811) + begin + case (st_deqP) + 4'd0: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_0_lat_0_whas__819_THEN_IF_st_fault_ETC___d25447 == + 4'd8; + 4'd1: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_1_lat_0_whas__917_THEN_IF_st_fault_ETC___d25475 == + 4'd8; + 4'd2: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_2_lat_0_whas__0015_THEN_IF_st_faul_ETC___d25503 == + 4'd8; + 4'd3: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_3_lat_0_whas__0113_THEN_IF_st_faul_ETC___d25531 == + 4'd8; + 4'd4: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_4_lat_0_whas__0211_THEN_IF_st_faul_ETC___d25559 == + 4'd8; + 4'd5: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_5_lat_0_whas__0309_THEN_IF_st_faul_ETC___d25587 == + 4'd8; + 4'd6: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_6_lat_0_whas__0407_THEN_IF_st_faul_ETC___d25615 == + 4'd8; + 4'd7: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_7_lat_0_whas__0505_THEN_IF_st_faul_ETC___d25643 == + 4'd8; + 4'd8: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_8_lat_0_whas__0603_THEN_IF_st_faul_ETC___d25671 == + 4'd8; + 4'd9: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_9_lat_0_whas__0701_THEN_IF_st_faul_ETC___d25699 == + 4'd8; + 4'd10: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_10_lat_0_whas__0799_THEN_IF_st_fau_ETC___d25727 == + 4'd8; + 4'd11: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_11_lat_0_whas__0897_THEN_IF_st_fau_ETC___d25755 == + 4'd8; + 4'd12: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_12_lat_0_whas__0995_THEN_IF_st_fau_ETC___d25783 == + 4'd8; + 4'd13: + SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + IF_st_fault_13_lat_0_whas__1093_THEN_IF_st_fau_ETC___d25811 == + 4'd8; + default: SEL_ARR_IF_st_fault_0_lat_0_whas__819_THEN_IF__ETC___d25942 = + 1'b0 /* unspecified value */ ; + endcase + end always@(st_deqP or IF_st_fault_0_lat_0_whas__819_THEN_IF_st_fault_ETC___d25447 or IF_st_fault_1_lat_0_whas__917_THEN_IF_st_fault_ETC___d25475 or @@ -129666,6 +129666,109 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(issueLdInfo$wget or + NOT_ld_computed_0_dummy2_1_read__1637_3653_OR__ETC___d15580 or + NOT_ld_computed_1_dummy2_1_read__1721_3693_OR__ETC___d15583 or + NOT_ld_computed_2_dummy2_1_read__1805_3733_OR__ETC___d15586 or + NOT_ld_computed_3_dummy2_1_read__1889_3773_OR__ETC___d15589 or + NOT_ld_computed_4_dummy2_1_read__1973_3813_OR__ETC___d15592 or + NOT_ld_computed_5_dummy2_1_read__2057_3853_OR__ETC___d15595 or + NOT_ld_computed_6_dummy2_1_read__2141_3893_OR__ETC___d15598 or + NOT_ld_computed_7_dummy2_1_read__2225_3933_OR__ETC___d15601 or + NOT_ld_computed_8_dummy2_1_read__2309_3973_OR__ETC___d15604 or + NOT_ld_computed_9_dummy2_1_read__2393_4013_OR__ETC___d15607 or + NOT_ld_computed_10_dummy2_1_read__2477_4053_OR_ETC___d15610 or + NOT_ld_computed_11_dummy2_1_read__2561_4093_OR_ETC___d15613 or + NOT_ld_computed_12_dummy2_1_read__2645_4133_OR_ETC___d15616 or + NOT_ld_computed_13_dummy2_1_read__2729_4173_OR_ETC___d15619 or + NOT_ld_computed_14_dummy2_1_read__2813_4213_OR_ETC___d15622 or + NOT_ld_computed_15_dummy2_1_read__2897_4253_OR_ETC___d15625 or + NOT_ld_computed_16_dummy2_1_read__2981_4293_OR_ETC___d15628 or + NOT_ld_computed_17_dummy2_1_read__3065_4333_OR_ETC___d15631 or + NOT_ld_computed_18_dummy2_1_read__3149_4373_OR_ETC___d15634 or + NOT_ld_computed_19_dummy2_1_read__3233_4413_OR_ETC___d15637 or + NOT_ld_computed_20_dummy2_1_read__3317_4453_OR_ETC___d15640 or + NOT_ld_computed_21_dummy2_1_read__3401_4493_OR_ETC___d15643 or + NOT_ld_computed_22_dummy2_1_read__3485_4533_OR_ETC___d15646 or + NOT_ld_computed_23_dummy2_1_read__3569_4573_OR_ETC___d15649) + begin + case (issueLdInfo$wget[76:72]) + 5'd0: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_0_dummy2_1_read__1637_3653_OR__ETC___d15580; + 5'd1: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_1_dummy2_1_read__1721_3693_OR__ETC___d15583; + 5'd2: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_2_dummy2_1_read__1805_3733_OR__ETC___d15586; + 5'd3: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_3_dummy2_1_read__1889_3773_OR__ETC___d15589; + 5'd4: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_4_dummy2_1_read__1973_3813_OR__ETC___d15592; + 5'd5: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_5_dummy2_1_read__2057_3853_OR__ETC___d15595; + 5'd6: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_6_dummy2_1_read__2141_3893_OR__ETC___d15598; + 5'd7: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_7_dummy2_1_read__2225_3933_OR__ETC___d15601; + 5'd8: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_8_dummy2_1_read__2309_3973_OR__ETC___d15604; + 5'd9: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_9_dummy2_1_read__2393_4013_OR__ETC___d15607; + 5'd10: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_10_dummy2_1_read__2477_4053_OR_ETC___d15610; + 5'd11: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_11_dummy2_1_read__2561_4093_OR_ETC___d15613; + 5'd12: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_12_dummy2_1_read__2645_4133_OR_ETC___d15616; + 5'd13: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_13_dummy2_1_read__2729_4173_OR_ETC___d15619; + 5'd14: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_14_dummy2_1_read__2813_4213_OR_ETC___d15622; + 5'd15: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_15_dummy2_1_read__2897_4253_OR_ETC___d15625; + 5'd16: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_16_dummy2_1_read__2981_4293_OR_ETC___d15628; + 5'd17: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_17_dummy2_1_read__3065_4333_OR_ETC___d15631; + 5'd18: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_18_dummy2_1_read__3149_4373_OR_ETC___d15634; + 5'd19: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_19_dummy2_1_read__3233_4413_OR_ETC___d15637; + 5'd20: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_20_dummy2_1_read__3317_4453_OR_ETC___d15640; + 5'd21: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_21_dummy2_1_read__3401_4493_OR_ETC___d15643; + 5'd22: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_22_dummy2_1_read__3485_4533_OR_ETC___d15646; + 5'd23: + SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + NOT_ld_computed_23_dummy2_1_read__3569_4573_OR_ETC___d15649; + default: SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = + 1'b0 /* unspecified value */ ; + endcase + end always@(issueLdInfo$wget or ld_fault_0_dummy2_1$Q_OUT or IF_ld_fault_0_lat_0_whas__76_THEN_ld_fault_0_l_ETC___d681 or @@ -129817,109 +129920,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(issueLdInfo$wget or - NOT_ld_computed_0_dummy2_1_read__1637_3653_OR__ETC___d15580 or - NOT_ld_computed_1_dummy2_1_read__1721_3693_OR__ETC___d15583 or - NOT_ld_computed_2_dummy2_1_read__1805_3733_OR__ETC___d15586 or - NOT_ld_computed_3_dummy2_1_read__1889_3773_OR__ETC___d15589 or - NOT_ld_computed_4_dummy2_1_read__1973_3813_OR__ETC___d15592 or - NOT_ld_computed_5_dummy2_1_read__2057_3853_OR__ETC___d15595 or - NOT_ld_computed_6_dummy2_1_read__2141_3893_OR__ETC___d15598 or - NOT_ld_computed_7_dummy2_1_read__2225_3933_OR__ETC___d15601 or - NOT_ld_computed_8_dummy2_1_read__2309_3973_OR__ETC___d15604 or - NOT_ld_computed_9_dummy2_1_read__2393_4013_OR__ETC___d15607 or - NOT_ld_computed_10_dummy2_1_read__2477_4053_OR_ETC___d15610 or - NOT_ld_computed_11_dummy2_1_read__2561_4093_OR_ETC___d15613 or - NOT_ld_computed_12_dummy2_1_read__2645_4133_OR_ETC___d15616 or - NOT_ld_computed_13_dummy2_1_read__2729_4173_OR_ETC___d15619 or - NOT_ld_computed_14_dummy2_1_read__2813_4213_OR_ETC___d15622 or - NOT_ld_computed_15_dummy2_1_read__2897_4253_OR_ETC___d15625 or - NOT_ld_computed_16_dummy2_1_read__2981_4293_OR_ETC___d15628 or - NOT_ld_computed_17_dummy2_1_read__3065_4333_OR_ETC___d15631 or - NOT_ld_computed_18_dummy2_1_read__3149_4373_OR_ETC___d15634 or - NOT_ld_computed_19_dummy2_1_read__3233_4413_OR_ETC___d15637 or - NOT_ld_computed_20_dummy2_1_read__3317_4453_OR_ETC___d15640 or - NOT_ld_computed_21_dummy2_1_read__3401_4493_OR_ETC___d15643 or - NOT_ld_computed_22_dummy2_1_read__3485_4533_OR_ETC___d15646 or - NOT_ld_computed_23_dummy2_1_read__3569_4573_OR_ETC___d15649) - begin - case (issueLdInfo$wget[76:72]) - 5'd0: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_0_dummy2_1_read__1637_3653_OR__ETC___d15580; - 5'd1: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_1_dummy2_1_read__1721_3693_OR__ETC___d15583; - 5'd2: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_2_dummy2_1_read__1805_3733_OR__ETC___d15586; - 5'd3: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_3_dummy2_1_read__1889_3773_OR__ETC___d15589; - 5'd4: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_4_dummy2_1_read__1973_3813_OR__ETC___d15592; - 5'd5: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_5_dummy2_1_read__2057_3853_OR__ETC___d15595; - 5'd6: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_6_dummy2_1_read__2141_3893_OR__ETC___d15598; - 5'd7: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_7_dummy2_1_read__2225_3933_OR__ETC___d15601; - 5'd8: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_8_dummy2_1_read__2309_3973_OR__ETC___d15604; - 5'd9: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_9_dummy2_1_read__2393_4013_OR__ETC___d15607; - 5'd10: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_10_dummy2_1_read__2477_4053_OR_ETC___d15610; - 5'd11: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_11_dummy2_1_read__2561_4093_OR_ETC___d15613; - 5'd12: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_12_dummy2_1_read__2645_4133_OR_ETC___d15616; - 5'd13: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_13_dummy2_1_read__2729_4173_OR_ETC___d15619; - 5'd14: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_14_dummy2_1_read__2813_4213_OR_ETC___d15622; - 5'd15: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_15_dummy2_1_read__2897_4253_OR_ETC___d15625; - 5'd16: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_16_dummy2_1_read__2981_4293_OR_ETC___d15628; - 5'd17: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_17_dummy2_1_read__3065_4333_OR_ETC___d15631; - 5'd18: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_18_dummy2_1_read__3149_4373_OR_ETC___d15634; - 5'd19: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_19_dummy2_1_read__3233_4413_OR_ETC___d15637; - 5'd20: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_20_dummy2_1_read__3317_4453_OR_ETC___d15640; - 5'd21: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_21_dummy2_1_read__3401_4493_OR_ETC___d15643; - 5'd22: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_22_dummy2_1_read__3485_4533_OR_ETC___d15646; - 5'd23: - SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - NOT_ld_computed_23_dummy2_1_read__3569_4573_OR_ETC___d15649; - default: SEL_ARR_NOT_ld_computed_0_dummy2_1_read__1637__ETC___d15651 = - 1'b0 /* unspecified value */ ; - endcase - end always@(issueLdInfo$wget or ld_executing_0_dummy2_1$Q_OUT or IF_ld_executing_0_lat_0_whas__435_THEN_ld_exec_ETC___d3438 or @@ -130071,6 +130071,180 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(issueLdInfo$wget or + ld_done_0_dummy2_0$Q_OUT or + ld_done_0_dummy2_1$Q_OUT or + ld_done_0_rl or + ld_done_1_dummy2_0$Q_OUT or + ld_done_1_dummy2_1$Q_OUT or + ld_done_1_rl or + ld_done_2_dummy2_0$Q_OUT or + ld_done_2_dummy2_1$Q_OUT or + ld_done_2_rl or + ld_done_3_dummy2_0$Q_OUT or + ld_done_3_dummy2_1$Q_OUT or + ld_done_3_rl or + ld_done_4_dummy2_0$Q_OUT or + ld_done_4_dummy2_1$Q_OUT or + ld_done_4_rl or + ld_done_5_dummy2_0$Q_OUT or + ld_done_5_dummy2_1$Q_OUT or + ld_done_5_rl or + ld_done_6_dummy2_0$Q_OUT or + ld_done_6_dummy2_1$Q_OUT or + ld_done_6_rl or + ld_done_7_dummy2_0$Q_OUT or + ld_done_7_dummy2_1$Q_OUT or + ld_done_7_rl or + ld_done_8_dummy2_0$Q_OUT or + ld_done_8_dummy2_1$Q_OUT or + ld_done_8_rl or + ld_done_9_dummy2_0$Q_OUT or + ld_done_9_dummy2_1$Q_OUT or + ld_done_9_rl or + ld_done_10_dummy2_0$Q_OUT or + ld_done_10_dummy2_1$Q_OUT or + ld_done_10_rl or + ld_done_11_dummy2_0$Q_OUT or + ld_done_11_dummy2_1$Q_OUT or + ld_done_11_rl or + ld_done_12_dummy2_0$Q_OUT or + ld_done_12_dummy2_1$Q_OUT or + ld_done_12_rl or + ld_done_13_dummy2_0$Q_OUT or + ld_done_13_dummy2_1$Q_OUT or + ld_done_13_rl or + ld_done_14_dummy2_0$Q_OUT or + ld_done_14_dummy2_1$Q_OUT or + ld_done_14_rl or + ld_done_15_dummy2_0$Q_OUT or + ld_done_15_dummy2_1$Q_OUT or + ld_done_15_rl or + ld_done_16_dummy2_0$Q_OUT or + ld_done_16_dummy2_1$Q_OUT or + ld_done_16_rl or + ld_done_17_dummy2_0$Q_OUT or + ld_done_17_dummy2_1$Q_OUT or + ld_done_17_rl or + ld_done_18_dummy2_0$Q_OUT or + ld_done_18_dummy2_1$Q_OUT or + ld_done_18_rl or + ld_done_19_dummy2_0$Q_OUT or + ld_done_19_dummy2_1$Q_OUT or + ld_done_19_rl or + ld_done_20_dummy2_0$Q_OUT or + ld_done_20_dummy2_1$Q_OUT or + ld_done_20_rl or + ld_done_21_dummy2_0$Q_OUT or + ld_done_21_dummy2_1$Q_OUT or + ld_done_21_rl or + ld_done_22_dummy2_0$Q_OUT or + ld_done_22_dummy2_1$Q_OUT or + ld_done_22_rl or + ld_done_23_dummy2_0$Q_OUT or + ld_done_23_dummy2_1$Q_OUT or ld_done_23_rl) + begin + case (issueLdInfo$wget[76:72]) + 5'd0: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_0_dummy2_0$Q_OUT && ld_done_0_dummy2_1$Q_OUT && + ld_done_0_rl; + 5'd1: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_1_dummy2_0$Q_OUT && ld_done_1_dummy2_1$Q_OUT && + ld_done_1_rl; + 5'd2: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_2_dummy2_0$Q_OUT && ld_done_2_dummy2_1$Q_OUT && + ld_done_2_rl; + 5'd3: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_3_dummy2_0$Q_OUT && ld_done_3_dummy2_1$Q_OUT && + ld_done_3_rl; + 5'd4: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_4_dummy2_0$Q_OUT && ld_done_4_dummy2_1$Q_OUT && + ld_done_4_rl; + 5'd5: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_5_dummy2_0$Q_OUT && ld_done_5_dummy2_1$Q_OUT && + ld_done_5_rl; + 5'd6: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_6_dummy2_0$Q_OUT && ld_done_6_dummy2_1$Q_OUT && + ld_done_6_rl; + 5'd7: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_7_dummy2_0$Q_OUT && ld_done_7_dummy2_1$Q_OUT && + ld_done_7_rl; + 5'd8: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_8_dummy2_0$Q_OUT && ld_done_8_dummy2_1$Q_OUT && + ld_done_8_rl; + 5'd9: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_9_dummy2_0$Q_OUT && ld_done_9_dummy2_1$Q_OUT && + ld_done_9_rl; + 5'd10: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_10_dummy2_0$Q_OUT && ld_done_10_dummy2_1$Q_OUT && + ld_done_10_rl; + 5'd11: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_11_dummy2_0$Q_OUT && ld_done_11_dummy2_1$Q_OUT && + ld_done_11_rl; + 5'd12: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_12_dummy2_0$Q_OUT && ld_done_12_dummy2_1$Q_OUT && + ld_done_12_rl; + 5'd13: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_13_dummy2_0$Q_OUT && ld_done_13_dummy2_1$Q_OUT && + ld_done_13_rl; + 5'd14: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_14_dummy2_0$Q_OUT && ld_done_14_dummy2_1$Q_OUT && + ld_done_14_rl; + 5'd15: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_15_dummy2_0$Q_OUT && ld_done_15_dummy2_1$Q_OUT && + ld_done_15_rl; + 5'd16: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_16_dummy2_0$Q_OUT && ld_done_16_dummy2_1$Q_OUT && + ld_done_16_rl; + 5'd17: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_17_dummy2_0$Q_OUT && ld_done_17_dummy2_1$Q_OUT && + ld_done_17_rl; + 5'd18: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_18_dummy2_0$Q_OUT && ld_done_18_dummy2_1$Q_OUT && + ld_done_18_rl; + 5'd19: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_19_dummy2_0$Q_OUT && ld_done_19_dummy2_1$Q_OUT && + ld_done_19_rl; + 5'd20: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_20_dummy2_0$Q_OUT && ld_done_20_dummy2_1$Q_OUT && + ld_done_20_rl; + 5'd21: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_21_dummy2_0$Q_OUT && ld_done_21_dummy2_1$Q_OUT && + ld_done_21_rl; + 5'd22: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_22_dummy2_0$Q_OUT && ld_done_22_dummy2_1$Q_OUT && + ld_done_22_rl; + 5'd23: + SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + ld_done_23_dummy2_0$Q_OUT && ld_done_23_dummy2_1$Q_OUT && + ld_done_23_rl; + default: SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = + 1'b0 /* unspecified value */ ; + endcase + end always@(issueLdInfo$wget or ld_inIssueQ_0_dummy2_1$Q_OUT or ld_inIssueQ_0_dummy2_2$Q_OUT or @@ -130260,180 +130434,6 @@ module mkSplitLSQ(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(issueLdInfo$wget or - ld_done_0_dummy2_0$Q_OUT or - ld_done_0_dummy2_1$Q_OUT or - ld_done_0_rl or - ld_done_1_dummy2_0$Q_OUT or - ld_done_1_dummy2_1$Q_OUT or - ld_done_1_rl or - ld_done_2_dummy2_0$Q_OUT or - ld_done_2_dummy2_1$Q_OUT or - ld_done_2_rl or - ld_done_3_dummy2_0$Q_OUT or - ld_done_3_dummy2_1$Q_OUT or - ld_done_3_rl or - ld_done_4_dummy2_0$Q_OUT or - ld_done_4_dummy2_1$Q_OUT or - ld_done_4_rl or - ld_done_5_dummy2_0$Q_OUT or - ld_done_5_dummy2_1$Q_OUT or - ld_done_5_rl or - ld_done_6_dummy2_0$Q_OUT or - ld_done_6_dummy2_1$Q_OUT or - ld_done_6_rl or - ld_done_7_dummy2_0$Q_OUT or - ld_done_7_dummy2_1$Q_OUT or - ld_done_7_rl or - ld_done_8_dummy2_0$Q_OUT or - ld_done_8_dummy2_1$Q_OUT or - ld_done_8_rl or - ld_done_9_dummy2_0$Q_OUT or - ld_done_9_dummy2_1$Q_OUT or - ld_done_9_rl or - ld_done_10_dummy2_0$Q_OUT or - ld_done_10_dummy2_1$Q_OUT or - ld_done_10_rl or - ld_done_11_dummy2_0$Q_OUT or - ld_done_11_dummy2_1$Q_OUT or - ld_done_11_rl or - ld_done_12_dummy2_0$Q_OUT or - ld_done_12_dummy2_1$Q_OUT or - ld_done_12_rl or - ld_done_13_dummy2_0$Q_OUT or - ld_done_13_dummy2_1$Q_OUT or - ld_done_13_rl or - ld_done_14_dummy2_0$Q_OUT or - ld_done_14_dummy2_1$Q_OUT or - ld_done_14_rl or - ld_done_15_dummy2_0$Q_OUT or - ld_done_15_dummy2_1$Q_OUT or - ld_done_15_rl or - ld_done_16_dummy2_0$Q_OUT or - ld_done_16_dummy2_1$Q_OUT or - ld_done_16_rl or - ld_done_17_dummy2_0$Q_OUT or - ld_done_17_dummy2_1$Q_OUT or - ld_done_17_rl or - ld_done_18_dummy2_0$Q_OUT or - ld_done_18_dummy2_1$Q_OUT or - ld_done_18_rl or - ld_done_19_dummy2_0$Q_OUT or - ld_done_19_dummy2_1$Q_OUT or - ld_done_19_rl or - ld_done_20_dummy2_0$Q_OUT or - ld_done_20_dummy2_1$Q_OUT or - ld_done_20_rl or - ld_done_21_dummy2_0$Q_OUT or - ld_done_21_dummy2_1$Q_OUT or - ld_done_21_rl or - ld_done_22_dummy2_0$Q_OUT or - ld_done_22_dummy2_1$Q_OUT or - ld_done_22_rl or - ld_done_23_dummy2_0$Q_OUT or - ld_done_23_dummy2_1$Q_OUT or ld_done_23_rl) - begin - case (issueLdInfo$wget[76:72]) - 5'd0: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_0_dummy2_0$Q_OUT && ld_done_0_dummy2_1$Q_OUT && - ld_done_0_rl; - 5'd1: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_1_dummy2_0$Q_OUT && ld_done_1_dummy2_1$Q_OUT && - ld_done_1_rl; - 5'd2: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_2_dummy2_0$Q_OUT && ld_done_2_dummy2_1$Q_OUT && - ld_done_2_rl; - 5'd3: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_3_dummy2_0$Q_OUT && ld_done_3_dummy2_1$Q_OUT && - ld_done_3_rl; - 5'd4: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_4_dummy2_0$Q_OUT && ld_done_4_dummy2_1$Q_OUT && - ld_done_4_rl; - 5'd5: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_5_dummy2_0$Q_OUT && ld_done_5_dummy2_1$Q_OUT && - ld_done_5_rl; - 5'd6: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_6_dummy2_0$Q_OUT && ld_done_6_dummy2_1$Q_OUT && - ld_done_6_rl; - 5'd7: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_7_dummy2_0$Q_OUT && ld_done_7_dummy2_1$Q_OUT && - ld_done_7_rl; - 5'd8: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_8_dummy2_0$Q_OUT && ld_done_8_dummy2_1$Q_OUT && - ld_done_8_rl; - 5'd9: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_9_dummy2_0$Q_OUT && ld_done_9_dummy2_1$Q_OUT && - ld_done_9_rl; - 5'd10: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_10_dummy2_0$Q_OUT && ld_done_10_dummy2_1$Q_OUT && - ld_done_10_rl; - 5'd11: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_11_dummy2_0$Q_OUT && ld_done_11_dummy2_1$Q_OUT && - ld_done_11_rl; - 5'd12: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_12_dummy2_0$Q_OUT && ld_done_12_dummy2_1$Q_OUT && - ld_done_12_rl; - 5'd13: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_13_dummy2_0$Q_OUT && ld_done_13_dummy2_1$Q_OUT && - ld_done_13_rl; - 5'd14: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_14_dummy2_0$Q_OUT && ld_done_14_dummy2_1$Q_OUT && - ld_done_14_rl; - 5'd15: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_15_dummy2_0$Q_OUT && ld_done_15_dummy2_1$Q_OUT && - ld_done_15_rl; - 5'd16: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_16_dummy2_0$Q_OUT && ld_done_16_dummy2_1$Q_OUT && - ld_done_16_rl; - 5'd17: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_17_dummy2_0$Q_OUT && ld_done_17_dummy2_1$Q_OUT && - ld_done_17_rl; - 5'd18: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_18_dummy2_0$Q_OUT && ld_done_18_dummy2_1$Q_OUT && - ld_done_18_rl; - 5'd19: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_19_dummy2_0$Q_OUT && ld_done_19_dummy2_1$Q_OUT && - ld_done_19_rl; - 5'd20: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_20_dummy2_0$Q_OUT && ld_done_20_dummy2_1$Q_OUT && - ld_done_20_rl; - 5'd21: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_21_dummy2_0$Q_OUT && ld_done_21_dummy2_1$Q_OUT && - ld_done_21_rl; - 5'd22: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_22_dummy2_0$Q_OUT && ld_done_22_dummy2_1$Q_OUT && - ld_done_22_rl; - 5'd23: - SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - ld_done_23_dummy2_0$Q_OUT && ld_done_23_dummy2_1$Q_OUT && - ld_done_23_rl; - default: SEL_ARR_ld_done_0_dummy2_0_read__5780_AND_ld_d_ETC___d15877 = - 1'b0 /* unspecified value */ ; - endcase - end always@(issueLdInfo$wget or ld_killed_0_dummy2_2$Q_OUT or IF_ld_killed_0_lat_1_whas__772_THEN_ld_killed__ETC___d3781 or diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index e5e4e7d..48946ed 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -182,12 +182,51 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); `endif endrule + function Bool fn_ArchReg_is_FpuReg (Maybe #(ArchRIndx) m_arch_r_indx); + Bool result = False; + if (m_arch_r_indx matches tagged Valid .arch_r_indx) + if (arch_r_indx matches tagged Fpu .fpu_r_index) + result = True; + return result; + endfunction + // check for exceptions and interrupts function Maybe#(Trap) getTrap(FromFetchStage x); Maybe#(Trap) trap = tagged Invalid; let csr_state = csrf.decodeInfo; let pending_interrupt = csrf.pending_interrupt; let new_exception = checkForException(x.dInst, x.regs, csr_state); + + // If Fpu regs are accessed, trap if mstatus_fs is "Off" (2'b00) + Bool fpr_access = ( fn_ArchReg_is_FpuReg (x.regs.src1) + || fn_ArchReg_is_FpuReg (x.regs.src2) + || isValid (x.regs.src3) + || fn_ArchReg_is_FpuReg (x.regs.dst)); + let mstatus = csrf.rd (CSRmstatus); + Bool fs_trap = ((mstatus [14:13] == 2'b00) && fpr_access); + + // Check CSR access permission + Bool csr_access_trap = False; + if (x.dInst.iType == Csr) begin + Bit #(12) csr_addr = case (x.dInst.csr) matches + tagged Valid .c: pack (c); + default: 12'hCFF; + endcase; + let rs1 = case (x.regs.src2) matches + tagged Valid (tagged Gpr .r) : r; + default: 0; + endcase; + let imm = case (x.dInst.imm) matches + tagged Valid .n: n; + default: 0; + endcase; + Bool writes_csr = ((x.dInst.execFunc == tagged Alu Csrw) || (rs1 != 0) || (imm != 0)); + Bool read_only = (csr_addr [11:10] == 2'b11); + Bool write_deny = (writes_csr && read_only); + Bool priv_deny = (csrf.decodeInfo.prv < csr_addr [9:8]); + csr_access_trap = (write_deny || priv_deny); + end + if (isValid(x.cause)) begin // previously found exception trap = tagged Valid (tagged Exception fromMaybe(?, x.cause)); @@ -198,6 +237,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); // newly found exception trap = tagged Valid (tagged Exception fromMaybe(?, new_exception)); end + else if (fs_trap || csr_access_trap) begin + trap = tagged Valid (tagged Exception IllegalInst); + end return trap; endfunction @@ -411,6 +453,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); csr: dInst.csr, claimed_phy_reg: True, // XXX we always claim a free reg in rename trap: Invalid, // no trap + tval: 0, // default values of FullResult ppc_vaddr_csrData: PPC (ppc), // default use PPC fflags: 0, @@ -906,6 +949,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); csr: dInst.csr, claimed_phy_reg: True, // XXX we always claim a free reg in rename trap: Invalid, // no trap + tval: 0, // default values of FullResult ppc_vaddr_csrData: PPC (ppc), // default use PPC fflags: 0, diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv index e0a79a5..a3ce618 100644 --- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv @@ -108,6 +108,7 @@ function Bit#(2) getXLBits = 2'b10; // MXL/SXL/UXL fix to RV64 function Bit#(26) getExtensionBits(RiscVISASubset isa); // include S and I by default Bit#(26) ext = 26'b00000001000000000100000000; + if (isa.u) ext = ext | 26'b00000100000000000000000000; if (isa.m) ext = ext | 26'b00000000000001000000000000; if (isa.a) ext = ext | 26'b00000000000000000000000001; if (isa.f) ext = ext | 26'b00000000000000000000100000;