Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Check the bounds on PCC and report the correct exception in Xcause registers.

Browse Source 
This required makeing the Exception type wider by one.
The actual "inBounds" check is currently implemented in the reorder buffer rows, which duplicates the logic ~80 times (number of outstanding instructions), which isn't ideal, but it's using the quick in-bounds check that only compares the mantissa-sized things.
This commit is contained in:
Jonathan Woodruff
2020-03-25 15:20:03 +00:00
parent 88ca03f4ed
commit f2f2285f75
3 changed files with 70 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
View File

@@ -1,7 +1,7 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
// Portions (c) 2020 Bluespec, Inc.
//
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
@@ -9,10 +9,10 @@
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
@@ -195,7 +195,7 @@ function Opcode unpackOpcode(Bit#(7) x);
return (case(x)
pack(Opcode'(Load )): (Load );
pack(Opcode'(LoadFp )): (LoadFp );
pack(Opcode'(MiscMem)): (MiscMem);
pack(Opcode'(MiscMem)): (MiscMem);
pack(Opcode'(OpImm )): (OpImm );
pack(Opcode'(Auipc )): (Auipc );
pack(Opcode'(OpImm32)): (OpImm32);
@@ -455,20 +455,21 @@ typedef enum {
} RVRoundMode deriving(Bits, Eq, FShow);
typedef enum {
InstAddrMisaligned = 4'd0,
InstAccessFault = 4'd1,
IllegalInst = 4'd2,
Breakpoint = 4'd3,
LoadAddrMisaligned = 4'd4,
LoadAccessFault = 4'd5,
StoreAddrMisaligned = 4'd6,
StoreAccessFault = 4'd7,
EnvCallU = 4'd8,
EnvCallS = 4'd9,
EnvCallM = 4'd11,
InstPageFault = 4'd12,
LoadPageFault = 4'd13,
StorePageFault = 4'd15
InstAddrMisaligned = 5'd0,
InstAccessFault = 5'd1,
IllegalInst = 5'd2,
Breakpoint = 5'd3,
LoadAddrMisaligned = 5'd4,
LoadAccessFault = 5'd5,
StoreAddrMisaligned = 5'd6,
StoreAccessFault = 5'd7,
EnvCallU = 5'd8,
EnvCallS = 5'd9,
EnvCallM = 5'd11,
InstPageFault = 5'd12,
LoadPageFault = 5'd13,
StorePageFault = 5'd15,
CapabilityFault = 5'd28
} Exception deriving(Bits, Eq, FShow);
typedef enum {
@@ -968,7 +969,7 @@ function Fmt showInst(Instruction inst);
privMRET: fshow("mret");
privWFI: fshow("wfi");
default: (
funct7 == privSFENCEVMA ?
funct7 == privSFENCEVMA ?
(fshow("sfence.vma ") + fshow(rs1) + fshow(" ") + fshow(rs2)) :
fshow("SYSTEM not implemented")
);
@@ -985,4 +986,3 @@ function Fmt showInst(Instruction inst);
return ret;
endfunction

43
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -178,9 +178,10 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
);
Integer trap_deq_port = 0;
function Integer trap_finishAlu_port(Integer i) = i;
Integer trap_deqLSQ_port = valueof(aluExeNum);
Integer trap_finishMem_port = valueof(aluExeNum); // write trap
Integer trap_enq_port = 1 + valueof(aluExeNum);
function Integer trap_finishFpuMulDiv_port(Integer i) = valueof(aluExeNum) + i;
Integer trap_deqLSQ_port = valueof(TAdd#(aluExeNum, TDiv#(aluExeNum,2)));
Integer trap_finishMem_port = valueof(TAdd#(aluExeNum, TDiv#(aluExeNum,2))); // write trap
Integer trap_enq_port = 1 + valueof(TAdd#(aluExeNum, TDiv#(aluExeNum,2)));
Integer pc_deq_port = 0;
function Integer pc_finishAlu_port(Integer i) = i;
@@ -241,8 +242,8 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
`endif
Reg#(Maybe#(CSR)) csr <- mkRegU;
Reg#(Bool) claimed_phy_reg <- mkRegU;
Ehr#(TAdd#(2, aluExeNum), Maybe#(Trap)) trap <- mkEhr(?);
Ehr#(TAdd#(2, aluExeNum), Addr) tval <- mkEhr(?);
Ehr#(TAdd#(TAdd#(2, TDiv#(aluExeNum,2)), aluExeNum), Maybe#(Trap)) trap <- mkEhr(?);
Ehr#(TAdd#(TAdd#(2, TDiv#(aluExeNum,2)), aluExeNum), Addr) tval <- mkEhr(?);
Ehr#(TAdd#(2, aluExeNum), PPCVAddrCSRData) ppc_vaddr_csrData <- mkEhr(?);
Ehr#(TAdd#(1, fpuMulDivExeNum), Bit#(5)) fflags <- mkEhr(?);
Reg#(Bool) will_dirty_fpu_state <- mkRegU;
@@ -294,9 +295,15 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
else begin
ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= PPC (setAddr(almightyCap, cf.nextPc).value);
end
pc[pc_finishAlu_port(i)] <= setAddrUnsafe(pcc, getAddr(pc[pc_finishAlu_port(i)]));
trap[trap_finishAlu_port(i)] <= trap[trap_finishAlu_port(i)];
tval[trap_finishAlu_port(i)] <= tval[trap_finishAlu_port(i)];
CapPipe new_pcc = setAddrUnsafe(pcc, getAddr(pc[pc_finishAlu_port(i)]));
pc[pc_finishAlu_port(i)] <= new_pcc;
if (!isInBounds(new_pcc, False)) begin
trap[trap_finishAlu_port(i)] <= Valid (tagged Exception CapabilityFault);
tval[trap_finishAlu_port(i)] <= tval[trap_finishAlu_port(i)];
end else if (cause matches tagged Valid .exp) begin
trap[trap_finishAlu_port(i)] <= Valid (tagged Exception exp);
tval[trap_finishAlu_port(i)] <= tval[trap_finishAlu_port(i)];
end
`ifdef RVFI
//$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
traceBundle[pvc_finishAlu_port(i)] <= tb;
@@ -315,7 +322,15 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
rg_dst_data <= dst_data;
// update fflags
fflags[fflags_finishFpuMulDiv_port(i)] <= new_fflags;
//pc[pc_finishFpuMulDiv_port(i)] <= setAddrUnsafe(pcc, getAddr(pc[pc_finishFpuMulDiv_port(i)])).value; //XXX add pcc checks on FPU instructions
CapPipe new_pcc = setAddrUnsafe(pcc, getAddr(pc[pc_finishAlu_port(i)]));
if (!isInBounds(new_pcc, False)) begin
trap[trap_finishFpuMulDiv_port(i)] <= Valid (tagged Exception CapabilityFault);
tval[trap_finishFpuMulDiv_port(i)] <= tval[trap_finishAlu_port(i)];
end else if (cause matches tagged Valid .exp) begin
trap[trap_finishFpuMulDiv_port(i)] <= Valid (tagged Exception exp);
tval[trap_finishFpuMulDiv_port(i)] <= tval[trap_finishAlu_port(i)];
end
//pc[pc_finishFpuMulDiv_port(i)] <= newPcc; //XXX add pcc checks on FPU instructions
endmethod
endinterface);
end
@@ -359,7 +374,15 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
memAccessAtCommit[accessCom_finishMem_port] <= access_at_commit;
// udpate non mmio st
nonMMIOStDone[nonMMIOSt_finishMem_port] <= non_mmio_st_done;
pc[pc_finishMem_port] <= setAddrUnsafe(pcc, getAddr(pc[pc_finishMem_port]));
CapPipe new_pcc = setAddrUnsafe(pcc, getAddr(pc[pc_finishMem_port]));
pc[pc_finishMem_port] <= new_pcc;
if (!isInBounds(new_pcc, False)) begin
trap[trap_finishMem_port] <= Valid (tagged Exception CapabilityFault);
tval[trap_finishMem_port] <= tval[trap_finishMem_port];
end else if (cause matches tagged Valid .exp) begin
trap[trap_finishMem_port] <= Valid (tagged Exception exp);
tval[trap_finishMem_port] <= tval[trap_finishMem_port];
end
endmethod
`ifdef INCLUDE_TANDEM_VERIF