diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index 9bf6b60..ef618b7 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -3990,7 +3990,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; - wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, + wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; wire MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, @@ -4045,14 +4045,20 @@ module mkCore(CLK, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fs_reg$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_1, - MUX_csrf_ie_vec_1$write_1__VAL_2, + MUX_csrf_ie_vec_1$write_1__SEL_2, + MUX_csrf_ie_vec_1$write_1__VAL_1, MUX_csrf_ie_vec_3$write_1__SEL_1, - MUX_csrf_ie_vec_3$write_1__VAL_2, - MUX_csrf_prev_ie_vec_1$write_1__VAL_2, - MUX_csrf_prev_ie_vec_3$write_1__VAL_2, + MUX_csrf_ie_vec_3$write_1__SEL_2, + MUX_csrf_ie_vec_3$write_1__VAL_1, + MUX_csrf_mpp_reg$write_1__SEL_1, + MUX_csrf_prev_ie_vec_1$write_1__SEL_1, + MUX_csrf_prev_ie_vec_1$write_1__VAL_1, + MUX_csrf_prev_ie_vec_3$write_1__SEL_1, + MUX_csrf_prev_ie_vec_3$write_1__VAL_1, MUX_csrf_prv_reg$write_1__SEL_1, MUX_csrf_software_int_pend_vec_3$write_1__VAL_2, - MUX_csrf_spp_reg$write_1__VAL_2, + MUX_csrf_spp_reg$write_1__SEL_1, + MUX_csrf_spp_reg$write_1__VAL_1, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_flush_reservation$write_1__SEL_1, @@ -4121,8 +4127,8 @@ module mkCore(CLK, CASE_guard84913_0b0_sfdin93133_BITS_56_TO_5_0b_ETC__q216, CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q217, CASE_guard93982_0b0_theResult___snd01918_BITS__ETC__q218, - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q205, - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q206, + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207, + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10693, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10719, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10738, @@ -4154,8 +4160,8 @@ module mkCore(CLK, CASE_guard67102_0b0_sfdin75324_BITS_56_TO_34_0_ETC__q45, CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q117, CASE_guard67316_0b0_theResult___snd75339_BITS__ETC__q118, + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46, CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47, - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q48, CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q77, CASE_guard95155_0b0_sfdin03248_BITS_56_TO_34_0_ETC__q78, _theResult___fst_sfd__h349436, @@ -4198,8 +4204,8 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q203, CASE_guard06911_0b0_theResult___fst_exp15137_0_ETC__q204, - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q207, - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q208, + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205, + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206, CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q175, CASE_guard36400_0b0_theResult___fst_exp44361_0_ETC__q176, CASE_guard45712_0b0_theResult___fst_exp53938_0_ETC__q177, @@ -4208,10 +4214,10 @@ module mkCore(CLK, CASE_guard54781_0b0_theResult___fst_exp62771_0_ETC__q180, CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q152, CASE_guard75601_0b0_theResult___fst_exp83562_0_ETC__q153, - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q183, - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q184, - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q181, - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q182, + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181, + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182, + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183, + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184, CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q135, CASE_guard97599_0b0_theResult___fst_exp05560_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10598, @@ -4342,13 +4348,13 @@ module mkCore(CLK, CASE_guard40843_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119, CASE_guard40843_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q116, CASE_guard45712_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, CASE_guard49463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46, + CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, CASE_guard49550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, CASE_guard49550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, CASE_guard54781_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, CASE_guard58172_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, CASE_guard58172_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, CASE_guard58480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, @@ -6088,7 +6094,7 @@ module mkCore(CLK, csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422, csrf_prv_reg_read__2863_ULE_1___d14382, fetchStage_RDY_pipelines_0_first__2832_AND_NOT_ETC___d13381, - fetchStage_RDY_pipelines_0_first__2832_AND_epo_ETC___d13285, + fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13285, fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13447, fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964, fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d14069, @@ -9140,16 +9146,16 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = + l2Tlb$RDY_toChildren_rqFromC_put && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && - l2Tlb$RDY_toChildren_rqFromC_put ; + coreFix_memExe_dTlb$RDY_toParent_rqToP_first ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + l2Tlb$RDY_toChildren_rqFromC_put && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - l2Tlb$RDY_toChildren_rqFromC_put ; + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; @@ -9163,30 +9169,30 @@ module mkCore(CLK, // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && + fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = - coreFix_memExe_dTlb$RDY_toParent_flush_request_get && - l2Tlb$RDY_toChildren_dTlbReqFlush_put ; + l2Tlb$RDY_toChildren_dTlbReqFlush_put && + coreFix_memExe_dTlb$RDY_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - fetchStage$RDY_iTlbIfc_toParent_flush_request_get && - l2Tlb$RDY_toChildren_iTlbReqFlush_put ; + l2Tlb$RDY_toChildren_iTlbReqFlush_put && + fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - fetchStage$RDY_iTlbIfc_toParent_flush_response_put && + l2Tlb$RDY_toChildren_flushDone_get && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9225,9 +9231,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_first_snd ; + fetchStage$RDY_mmioIfc_instReq_deq ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -10286,8 +10292,8 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - fetchStage$RDY_iTlbIfc_flush && - coreFix_memExe_dTlb$RDY_flush) && + coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; @@ -10573,9 +10579,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_first && + fetchStage$RDY_pipelines_0_deq && rob$RDY_enqPort_0_enq && mmio_pRqQ_empty && epochManager$checkEpoch_0_check && @@ -10588,8 +10594,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - fetchStage$RDY_pipelines_0_deq && - fetchStage_RDY_pipelines_0_first__2832_AND_epo_ETC___d13285 && + epochManager$RDY_incrementEpoch && + fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13285 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13308 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10670,8 +10676,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -10899,15 +10904,27 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; + assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; + assign MUX_csrf_mpp_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; + assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) ; + assign MUX_csrf_spp_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -10974,17 +10991,6 @@ module mkCore(CLK, assign MUX_commitStage_rg_instret$write_1__VAL_2 = commitStage_rg_instret + y__h716923 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, - fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = (k__h669941 == 1'd0 && fetchStage_pipelines_0_canDeq__2833_AND_NOT_fe_ETC___d13964) ? { fetchStage$pipelines_0_first[199:195], @@ -11009,6 +11015,17 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2835_BITS_194_ETC___d12961, + fetchStage_pipelines_0_first__2835_BIT_173_296_ETC___d13037, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11318,7 +11335,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; endcase end - assign MUX_csrf_ie_vec_1$write_1__VAL_2 = + assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == 6'd8 || @@ -11326,7 +11343,7 @@ module mkCore(CLK, 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; - assign MUX_csrf_ie_vec_3$write_1__VAL_2 = + assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == 6'd18) ? @@ -11337,7 +11354,7 @@ module mkCore(CLK, n__read__h713751 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = n__read__h713751 + { 62'd0, x__h717147 } ; - assign MUX_csrf_mpp_reg$write_1__VAL_2 = + assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == 6'd18) ? @@ -11346,14 +11363,14 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__VAL_1 = commitStage_commitTrap[4] ? 64'd0 : trap_val__h703302 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != 6'd8 && IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 != 6'd18 || @@ -11371,7 +11388,7 @@ module mkCore(CLK, (mmio_pRqQ_data_0[37:36] == 2'd2) ? mmio_pRqQ_data_0[0] : amoExec___d882[0] ; - assign MUX_csrf_spp_reg$write_1__VAL_2 = + assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4241_BIT_181_4470_T_ETC___d14544 == 6'd8 || @@ -11916,9 +11933,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd0 && @@ -11928,7 +11943,9 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd1 && @@ -11938,7 +11955,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd2 && @@ -11948,7 +11965,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd3 && @@ -11958,7 +11975,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd4 && @@ -11968,7 +11985,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd5 && @@ -11978,7 +11995,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd6 && @@ -11988,7 +12005,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7 && @@ -12705,25 +12722,25 @@ module mkCore(CLK, // register csrf_ie_vec_1 assign csrf_ie_vec_1$D_IN = - !MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_2 ; + MUX_csrf_ie_vec_1$write_1__SEL_1 && + MUX_csrf_ie_vec_1$write_1__VAL_1 ; assign csrf_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; // register csrf_ie_vec_3 assign csrf_ie_vec_3$D_IN = - !MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_2 ; + MUX_csrf_ie_vec_3$write_1__SEL_1 && + MUX_csrf_ie_vec_3$write_1__VAL_1 ; assign csrf_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; + NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 ? + MUX_csrf_ie_vec_3$write_1__SEL_2 ? cause_code__h702271 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = @@ -12736,7 +12753,7 @@ module mkCore(CLK, // register csrf_mcause_interrupt_reg assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 ? + MUX_csrf_ie_vec_3$write_1__SEL_2 ? commitStage_commitTrap[4] : csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = @@ -12802,7 +12819,7 @@ module mkCore(CLK, // register csrf_mepc_csr assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 ? + MUX_csrf_ie_vec_3$write_1__SEL_2 ? commitStage_commitTrap[132:69] : rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = @@ -12854,13 +12871,13 @@ module mkCore(CLK, // register csrf_mpp_reg assign csrf_mpp_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 ? - csrf_prv_reg : - MUX_csrf_mpp_reg$write_1__VAL_2 ; + MUX_csrf_mpp_reg$write_1__SEL_1 ? + MUX_csrf_mpp_reg$write_1__VAL_1 : + csrf_prv_reg ; assign csrf_mpp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; + NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ; @@ -12880,7 +12897,7 @@ module mkCore(CLK, // register csrf_mtval_csr assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 ? + MUX_csrf_ie_vec_3$write_1__SEL_2 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = @@ -12937,23 +12954,23 @@ module mkCore(CLK, // register csrf_prev_ie_vec_1 assign csrf_prev_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 ? - csrf_ie_vec_1 : - MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; + MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ? + MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : + csrf_ie_vec_1 ; assign csrf_prev_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; // register csrf_prev_ie_vec_3 assign csrf_prev_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 ? - csrf_ie_vec_3 : - MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; + MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ? + MUX_csrf_prev_ie_vec_3$write_1__VAL_1 : + csrf_ie_vec_3 ; assign csrf_prev_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; + NOT_csrf_prv_reg_read__2863_ULE_1_4382_4446_OR_ETC___d14450 ; // register csrf_prv_reg assign csrf_prv_reg$D_IN = @@ -12968,7 +12985,7 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 ? + MUX_csrf_ie_vec_1$write_1__SEL_2 ? cause_code__h702271 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = @@ -12981,7 +12998,7 @@ module mkCore(CLK, // register csrf_scause_interrupt_reg assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 ? + MUX_csrf_ie_vec_1$write_1__SEL_2 ? commitStage_commitTrap[4] : csrf_mscratch_csr$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = @@ -13018,7 +13035,7 @@ module mkCore(CLK, // register csrf_sepc_csr assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 ? + MUX_csrf_ie_vec_1$write_1__SEL_2 ? commitStage_commitTrap[132:69] : rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = @@ -13083,13 +13100,13 @@ module mkCore(CLK, // register csrf_spp_reg assign csrf_spp_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 ? - csrf_prv_reg[0] : - MUX_csrf_spp_reg$write_1__VAL_2 ; + MUX_csrf_spp_reg$write_1__SEL_1 ? + MUX_csrf_spp_reg$write_1__VAL_1 : + csrf_prv_reg[0] ; assign csrf_spp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + csrf_prv_reg_read__2863_ULE_1_4382_AND_IF_comm_ETC___d14422 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; @@ -13105,7 +13122,7 @@ module mkCore(CLK, // register csrf_stval_csr assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 ? + MUX_csrf_ie_vec_1$write_1__SEL_2 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = @@ -13765,9 +13782,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 || - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -18846,8 +18863,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; + CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10783 = (_theResult___fst_exp__h553938 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19368,8 +19385,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; + CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10768 = (_theResult___fst_exp__h544361 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -25499,7 +25516,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q208 : + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 ; assign _theResult___fst_exp__h524753 = (_theResult___fst_exp__h523970 == 11'd2047) ? @@ -25786,7 +25803,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q184 : + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 ; assign _theResult___fst_exp__h593971 = (_theResult___fst_exp__h593139 == 11'd2047) ? @@ -25817,7 +25834,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q182 : + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 ; assign _theResult___fst_exp__h602755 = (_theResult___fst_exp__h601972 == 11'd2047) ? @@ -25949,7 +25966,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q206 : + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 ; assign _theResult___fst_sfd__h506319 = (_theResult___fst_exp__h505560 == 11'd2047) ? @@ -27980,9 +27997,9 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2835_BITS_19_ETC___d13378 ; - assign fetchStage_RDY_pipelines_0_first__2832_AND_epo_ETC___d13285 = + assign fetchStage_RDY_pipelines_0_first__2832_AND_fet_ETC___d13285 = fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && rob$RDY_enqPort_0_enq && @@ -30149,23 +30166,23 @@ module mkCore(CLK, default: rVal1__h638559 = 64'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h440815 = 8'd255; + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h395127 = 8'd255; 3'd2: - _theResult___fst_exp__h440815 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___fst_exp__h395127 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h440815 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + _theResult___fst_exp__h395127 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h440815 = 8'd254; - default: _theResult___fst_exp__h440815 = 8'd0; + 3'd4: _theResult___fst_exp__h395127 = 8'd254; + default: _theResult___fst_exp__h395127 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or @@ -30206,25 +30223,6 @@ module mkCore(CLK, default: _theResult___fst_sfd__h349436 = 23'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h395127 = 8'd255; - 3'd2: - _theResult___fst_exp__h395127 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h395127 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h395127 = 8'd254; - default: _theResult___fst_exp__h395127 = 8'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -30244,6 +30242,25 @@ module mkCore(CLK, default: _theResult___fst_sfd__h395128 = 23'd0; endcase end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h440815 = 8'd255; + 3'd2: + _theResult___fst_exp__h440815 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h440815 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h440815 = 8'd254; + default: _theResult___fst_exp__h440815 = 8'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -30468,23 +30485,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[15:0]; - 2'd1: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[31:16]; - 2'd2: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[47:32]; - 2'd3: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[63:48]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -30513,6 +30513,23 @@ module mkCore(CLK, mmio_dataRespQ_data_0[63:56]; endcase end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[15:0]; + 2'd1: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[31:16]; + 2'd2: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[47:32]; + 2'd3: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[63:48]; + endcase + end always@(coreFix_memExe_dTlb$procResp) begin case (coreFix_memExe_dTlb$procResp[105:103]) @@ -30624,19 +30641,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h358172 or _theResult___fst_exp__h366220 or out_exp__h366665 or _theResult___exp__h366662) @@ -30997,28 +31001,80 @@ module mkCore(CLK, default: _theResult___fst_sfd__h375925 = 23'd0; endcase end + always@(guard__h375938 or + _theResult___snd__h383961 or + out_sfd__h384486 or _theResult___sfd__h384483) + begin + case (guard__h375938) + 2'b0, 2'b01: + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 = + _theResult___snd__h383961[56:34]; + 2'b10: + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 = + out_sfd__h384486; + 2'b11: + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 = + _theResult___sfd__h384483; + endcase + end + always@(guard__h375938 or + _theResult___snd__h383961 or _theResult___sfd__h384483) + begin + case (guard__h375938) + 2'b0: + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 = + _theResult___snd__h383961[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 = + _theResult___sfd__h384483; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46 or + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or + _theResult___snd__h383961) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h384561 = + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q46; + 3'd1: + _theResult___fst_sfd__h384561 = + CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47; + 3'd2: + _theResult___fst_sfd__h384561 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; + 3'd3: + _theResult___fst_sfd__h384561 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; + 3'd4: _theResult___fst_sfd__h384561 = _theResult___snd__h383961[56:34]; + default: _theResult___fst_sfd__h384561 = 23'd0; + endcase + end always@(guard__h349463 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h349463) 2'b0, 2'b01, 2'b10: - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46 = + CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46 = + CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = guard__h349463 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46 or + CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or guard__h349463) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46; + CASE_guard49463_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = (guard__h349463 == 2'b0) ? @@ -31035,58 +31091,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h375938 or - _theResult___snd__h383961 or - out_sfd__h384486 or _theResult___sfd__h384483) - begin - case (guard__h375938) - 2'b0, 2'b01: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 = - _theResult___snd__h383961[56:34]; - 2'b10: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 = - out_sfd__h384486; - 2'b11: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 = - _theResult___sfd__h384483; - endcase - end - always@(guard__h375938 or - _theResult___snd__h383961 or _theResult___sfd__h384483) - begin - case (guard__h375938) - 2'b0: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q48 = - _theResult___snd__h383961[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q48 = - _theResult___sfd__h384483; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47 or - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q48 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or - _theResult___snd__h383961) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h384561 = - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q47; - 3'd1: - _theResult___fst_sfd__h384561 = - CASE_guard75938_0b0_theResult___snd83961_BITS__ETC__q48; - 3'd2: - _theResult___fst_sfd__h384561 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; - 3'd3: - _theResult___fst_sfd__h384561 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; - 3'd4: _theResult___fst_sfd__h384561 = _theResult___snd__h383961[56:34]; - default: _theResult___fst_sfd__h384561 = 23'd0; - endcase - end always@(guard__h349463 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -31353,6 +31357,19 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -32108,22 +32125,6 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(fetchStage$pipelines_0_first) - begin - case (fetchStage$pipelines_0_first[67:64]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = - fetchStage$pipelines_0_first[67:64]; - 4'd11: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd10; - 4'd12: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd11; - 4'd13: - IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd12; - default: IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = - 4'd13; - endcase - end always@(guard__h449550 or _theResult___fst_exp__h457598 or out_exp__h458043 or _theResult___exp__h458040) @@ -33411,66 +33412,15 @@ module mkCore(CLK, _theResult___exp__h563451; endcase end - always@(guard__h593982 or - _theResult___fst_exp__h601972 or _theResult___exp__h602652) - begin - case (guard__h593982) - 2'b0: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q181 = - _theResult___fst_exp__h601972; - 2'b01, 2'b10, 2'b11: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q181 = - _theResult___exp__h602652; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h601972 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9900 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9898 or - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q181) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = - _theResult___fst_exp__h601972; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9900; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9898; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q181; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = - 11'd0; - endcase - end - always@(guard__h593982 or - _theResult___fst_exp__h601972 or - out_exp__h602655 or _theResult___exp__h602652) - begin - case (guard__h593982) - 2'b0, 2'b01: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q182 = - _theResult___fst_exp__h601972; - 2'b10: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q182 = - out_exp__h602655; - 2'b11: - CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q182 = - _theResult___exp__h602652; - endcase - end always@(guard__h584913 or _theResult___fst_exp__h593139 or _theResult___exp__h593868) begin case (guard__h584913) 2'b0: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q183 = + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181 = _theResult___fst_exp__h593139; 2'b01, 2'b10, 2'b11: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q183 = + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181 = _theResult___exp__h593868; endcase end @@ -33478,7 +33428,7 @@ module mkCore(CLK, _theResult___fst_exp__h593139 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9869 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9867 or - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q183) + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -33492,7 +33442,7 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9867; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 = - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q183; + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9873 = 11'd0; endcase @@ -33503,16 +33453,67 @@ module mkCore(CLK, begin case (guard__h584913) 2'b0, 2'b01: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q184 = + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 = _theResult___fst_exp__h593139; 2'b10: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q184 = + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 = out_exp__h593871; 2'b11: - CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q184 = + CASE_guard84913_0b0_theResult___fst_exp93139_0_ETC__q182 = _theResult___exp__h593868; endcase end + always@(guard__h593982 or + _theResult___fst_exp__h601972 or _theResult___exp__h602652) + begin + case (guard__h593982) + 2'b0: + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183 = + _theResult___fst_exp__h601972; + 2'b01, 2'b10, 2'b11: + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183 = + _theResult___exp__h602652; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h601972 or + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9900 or + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9898 or + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = + _theResult___fst_exp__h601972; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9900; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9898; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q183; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9904 = + 11'd0; + endcase + end + always@(guard__h593982 or + _theResult___fst_exp__h601972 or + out_exp__h602655 or _theResult___exp__h602652) + begin + case (guard__h593982) + 2'b0, 2'b01: + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 = + _theResult___fst_exp__h601972; + 2'b10: + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 = + out_exp__h602655; + 2'b11: + CASE_guard93982_0b0_theResult___fst_exp01972_0_ETC__q184 = + _theResult___exp__h602652; + endcase + end always@(guard__h536400 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h536400) @@ -33543,44 +33544,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h554781 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h554781) - 2'b0, 2'b01, 2'b10: - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h554781 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h554781) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h554781 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h554781 == 2'b01 || guard__h554781 == 2'b10 || - guard__h554781 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h545712 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h545712) 2'b0, 2'b01, 2'b10: - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard45712_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = guard__h545712 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase @@ -33589,15 +33560,45 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = (guard__h545712 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : (guard__h545712 == 2'b01 || guard__h545712 == 2'b10 || guard__h545712 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h554781 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h554781) + 2'b0, 2'b01, 2'b10: + CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard54781_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h554781 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h554781) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + (guard__h554781 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h554781 == 2'b01 || guard__h554781 == 2'b10 || + guard__h554781 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -33895,66 +33896,15 @@ module mkCore(CLK, _theResult___exp__h515866; endcase end - always@(guard__h497599 or - _theResult___snd__h505511 or _theResult___sfd__h506216) - begin - case (guard__h497599) - 2'b0: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q205 = - _theResult___snd__h505511[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q205 = - _theResult___sfd__h506216; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h505511 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9221 or - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9219 or - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q205) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = - _theResult___snd__h505511[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9221; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = - IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9219; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q205; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = - 52'd0; - endcase - end - always@(guard__h497599 or - _theResult___snd__h505511 or - out_sfd__h506219 or _theResult___sfd__h506216) - begin - case (guard__h497599) - 2'b0, 2'b01: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q206 = - _theResult___snd__h505511[56:5]; - 2'b10: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q206 = - out_sfd__h506219; - 2'b11: - CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q206 = - _theResult___sfd__h506216; - endcase - end always@(guard__h515980 or _theResult___fst_exp__h523970 or _theResult___exp__h524650) begin case (guard__h515980) 2'b0: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q207 = + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205 = _theResult___fst_exp__h523970; 2'b01, 2'b10, 2'b11: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q207 = + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205 = _theResult___exp__h524650; endcase end @@ -33962,7 +33912,7 @@ module mkCore(CLK, _theResult___fst_exp__h523970 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9195 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9193 or - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q207) + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -33976,7 +33926,7 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9193; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 = - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q207; + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9199 = 11'd0; endcase @@ -33987,16 +33937,67 @@ module mkCore(CLK, begin case (guard__h515980) 2'b0, 2'b01: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q208 = + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 = _theResult___fst_exp__h523970; 2'b10: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q208 = + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 = out_exp__h524653; 2'b11: - CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q208 = + CASE_guard15980_0b0_theResult___fst_exp23970_0_ETC__q206 = _theResult___exp__h524650; endcase end + always@(guard__h497599 or + _theResult___snd__h505511 or _theResult___sfd__h506216) + begin + case (guard__h497599) + 2'b0: + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207 = + _theResult___snd__h505511[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207 = + _theResult___sfd__h506216; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h505511 or + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9221 or + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9219 or + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = + _theResult___snd__h505511[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9221; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = + IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9219; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q207; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9225 = + 52'd0; + endcase + end + always@(guard__h497599 or + _theResult___snd__h505511 or + out_sfd__h506219 or _theResult___sfd__h506216) + begin + case (guard__h497599) + 2'b0, 2'b01: + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 = + _theResult___snd__h505511[56:5]; + 2'b10: + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 = + out_sfd__h506219; + 2'b11: + CASE_guard97599_0b0_theResult___snd05511_BITS__ETC__q208 = + _theResult___sfd__h506216; + endcase + end always@(guard__h506911 or sfdin__h515131 or _theResult___sfd__h515867) begin case (guard__h506911) @@ -34473,6 +34474,22 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first) + begin + case (fetchStage$pipelines_0_first[67:64]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = + fetchStage$pipelines_0_first[67:64]; + 4'd11: + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd10; + 4'd12: + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd11; + 4'd13: + IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = 4'd12; + default: IF_fetchStage_pipelines_0_first__2835_BIT_68_2_ETC___d13139 = + 4'd13; + endcase + end + always@(fetchStage$pipelines_0_first) begin case (fetchStage$pipelines_0_first[172:161]) 12'd1, @@ -35731,26 +35748,6 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) - 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq; - 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq; - 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) @@ -35777,6 +35774,26 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) + 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq; + 5'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq; + 5'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 = + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8538 or coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v index 23b4916..1727e7e 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v @@ -2009,17 +2009,16 @@ module mkCoreW(CLK, // rule RL_rl_cpu_hart0_reset_from_soc_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = + plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && proc$RDY_hart0_server_reset_request_put && - plic$RDY_server_reset_request_put && - fabric_2x3$RDY_reset && f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; // rule RL_rl_cpu_hart0_reset_complete assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - proc$RDY_start && proc$RDY_hart0_server_reset_response_get && - plic$RDY_server_reset_response_get && + plic$RDY_server_reset_response_get && proc$RDY_start && + proc$RDY_hart0_server_reset_response_get && f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; @@ -2039,16 +2038,15 @@ module mkCoreW(CLK, // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; assign f_reset_reqs$DEQ = + plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && proc$RDY_hart0_server_reset_request_put && - plic$RDY_server_reset_request_put && - fabric_2x3$RDY_reset && f_reset_reqs$EMPTY_N ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps assign f_reset_rsps$ENQ = - proc$RDY_start && proc$RDY_hart0_server_reset_response_get && - plic$RDY_server_reset_response_get && + plic$RDY_server_reset_response_get && proc$RDY_start && + proc$RDY_hart0_server_reset_response_get && f_reset_rsps$FULL_N ; assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; assign f_reset_rsps$CLR = 1'b0 ; diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v index a6a6e73..687d7b3 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v @@ -2711,9 +2711,9 @@ module mkFetchStage(CLK, SEL_ARR_IF_rg_pending_straddle_555_THEN_IF_SEL_ETC___d4385; reg [11 : 0] CASE_decode_217_BITS_72_TO_61_1_decode_217_BIT_ETC__q4, CASE_decode_805_BITS_72_TO_61_1_decode_805_BIT_ETC__q7, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q208; - reg [9 : 0] CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, + reg [9 : 0] CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q209; reg [4 : 0] CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, @@ -2725,7 +2725,7 @@ module mkFetchStage(CLK, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199, - CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, + CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q37, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q63, CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q66; @@ -2817,8 +2817,8 @@ module mkFetchStage(CLK, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q169, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171, + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26, @@ -4827,10 +4827,7 @@ module mkFetchStage(CLK, WILL_FIRE_RL_doFetch2 && !iTlb$to_proc_response_get[4] && mmio$getFetchTarget == 2'd0 ; assign MUX_rg_pending_straddle$write_1__SEL_1 = - WILL_FIRE_RL_doFetch3 && - SEL_ARR_f22f3_data_0_511_BIT_4_537_f22f3_data__ETC___d3543 && - rg_pending_straddle && - SEL_ARR_f22f3_data_0_511_BITS_266_TO_203_556_f_ETC___d3564 ; + WILL_FIRE_RL_doDecode && _dfoo523 ; assign MUX_iTlb$to_proc_request_put_1__VAL_2 = { x__h116593[63:2], 2'd0 } ; // inlined wires @@ -8662,13 +8659,13 @@ module mkFetchStage(CLK, SEL_ARR_f32d_data_0_719_BITS_3_TO_0_720_f32d_d_ETC___d5204) ; // register rg_pending_straddle - assign rg_pending_straddle$D_IN = !MUX_rg_pending_straddle$write_1__SEL_1 ; + assign rg_pending_straddle$D_IN = MUX_rg_pending_straddle$write_1__SEL_1 ; assign rg_pending_straddle$EN = + WILL_FIRE_RL_doDecode && _dfoo523 || WILL_FIRE_RL_doFetch3 && SEL_ARR_f22f3_data_0_511_BIT_4_537_f22f3_data__ETC___d3543 && rg_pending_straddle && - SEL_ARR_f22f3_data_0_511_BITS_266_TO_203_556_f_ETC___d3564 || - WILL_FIRE_RL_doDecode && _dfoo523 ; + SEL_ARR_f22f3_data_0_511_BITS_266_TO_203_556_f_ETC___d3564 ; // register started assign started$D_IN = !EN_stop ; @@ -12074,10 +12071,10 @@ module mkFetchStage(CLK, CAN_FIRE_RL_setTrainNAPByDec || !napTrainByDecQ_full_rl) ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d5583 = - { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, + { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206, - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 } ; + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d5640 = { CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q8, CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q9, @@ -12154,7 +12151,7 @@ module mkFetchStage(CLK, IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d6221, SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d6201 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d6309 = - { CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203, + { CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207, IF_SEL_ARR_out_fifo_internalFifos_0_first__552_ETC___d6228, NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d6308 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__552_BI_ETC___d6372 = @@ -15582,22 +15579,6 @@ module mkFetchStage(CLK, 4'd13; endcase end - always@(f22f3_data_3) - begin - case (f22f3_data_3[73:70]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = - f22f3_data_3[73:70]; - 4'd11: - IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = 4'd10; - 4'd12: - IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = 4'd11; - 4'd13: - IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = 4'd12; - default: IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = - 4'd13; - endcase - end always@(f22f3_data_2) begin case (f22f3_data_2[73:70]) @@ -15614,6 +15595,22 @@ module mkFetchStage(CLK, 4'd13; endcase end + always@(f22f3_data_3) + begin + case (f22f3_data_3[73:70]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = + f22f3_data_3[73:70]; + 4'd11: + IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = 4'd10; + 4'd12: + IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = 4'd11; + 4'd13: + IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = 4'd12; + default: IF_f22f3_data_3_520_BITS_73_TO_70_698_EQ_0_699_ETC___d3724 = + 4'd13; + endcase + end always@(f22f3_deqP or IF_f22f3_data_0_511_BITS_73_TO_70_614_EQ_0_615_ETC___d3640 or IF_f22f3_data_1_514_BITS_73_TO_70_642_EQ_0_643_ETC___d3668 or @@ -16089,6 +16086,17 @@ module mkFetchStage(CLK, instdata_data_1[65:64]; endcase end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + SEL_ARR_f32d_data_0_719_BIT_4_738_f32d_data_1__ETC___d4741 = + f32d_data_0[4]; + 1'd1: + SEL_ARR_f32d_data_0_719_BIT_4_738_f32d_data_1__ETC___d4741 = + f32d_data_1[4]; + endcase + end always@(n__read__h143420 or instdata_data_0 or instdata_data_1) begin case (n__read__h143420) @@ -16101,17 +16109,6 @@ module mkFetchStage(CLK, endcase end always@(f32d_deqP or f32d_data_0 or f32d_data_1) - begin - case (f32d_deqP) - 1'd0: - SEL_ARR_f32d_data_0_719_BIT_4_738_f32d_data_1__ETC___d4741 = - f32d_data_0[4]; - 1'd1: - SEL_ARR_f32d_data_0_719_BIT_4_738_f32d_data_1__ETC___d4741 = - f32d_data_1[4]; - endcase - end - always@(f32d_deqP or f32d_data_0 or f32d_data_1) begin case (f32d_deqP) 1'd0: @@ -16122,17 +16119,6 @@ module mkFetchStage(CLK, f32d_data_1[267]; endcase end - always@(n__read__h143420 or instdata_data_0 or instdata_data_1) - begin - case (n__read__h143420) - 1'd0: - SEL_ARR_instdata_data_0_727_BITS_63_TO_32_787__ETC___d4790 = - instdata_data_0[63:32]; - 1'd1: - SEL_ARR_instdata_data_0_727_BITS_63_TO_32_787__ETC___d4790 = - instdata_data_1[63:32]; - endcase - end always@(f32d_deqP or f32d_data_0 or f32d_data_1) begin case (f32d_deqP) @@ -16145,6 +16131,17 @@ module mkFetchStage(CLK, endcase end always@(n__read__h143420 or instdata_data_0 or instdata_data_1) + begin + case (n__read__h143420) + 1'd0: + SEL_ARR_instdata_data_0_727_BITS_63_TO_32_787__ETC___d4790 = + instdata_data_0[63:32]; + 1'd1: + SEL_ARR_instdata_data_0_727_BITS_63_TO_32_787__ETC___d4790 = + instdata_data_1[63:32]; + endcase + end + always@(n__read__h143420 or instdata_data_0 or instdata_data_1) begin case (n__read__h143420) 1'd0: @@ -19008,27 +19005,15 @@ module mkFetchStage(CLK, out_fifo_internalFifos_1$D_OUT[199:195]; endcase end - always@(x__h73310 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h73310) - 1'd0: - CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = - out_fifo_internalFifos_0$D_OUT[199:195]; - 1'd1: - CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = - out_fifo_internalFifos_1$D_OUT[199:195]; - endcase - end always@(x__h63248 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = out_fifo_internalFifos_0$D_OUT[255:244]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q203 = out_fifo_internalFifos_1$D_OUT[255:244]; endcase end @@ -19037,10 +19022,10 @@ module mkFetchStage(CLK, begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = out_fifo_internalFifos_0$D_OUT[243:234]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q204 = out_fifo_internalFifos_1$D_OUT[243:234]; endcase end @@ -19049,10 +19034,10 @@ module mkFetchStage(CLK, begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = out_fifo_internalFifos_0$D_OUT[233]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q205 = out_fifo_internalFifos_1$D_OUT[233]; endcase end @@ -19061,13 +19046,25 @@ module mkFetchStage(CLK, begin case (x__h63248) 1'd0: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = out_fifo_internalFifos_0$D_OUT[232]; 1'd1: - CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = + CASE_x3248_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q206 = out_fifo_internalFifos_1$D_OUT[232]; endcase end + always@(x__h73310 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h73310) + 1'd0: + CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = + out_fifo_internalFifos_0$D_OUT[199:195]; + 1'd1: + CASE_x3310_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q207 = + out_fifo_internalFifos_1$D_OUT[199:195]; + endcase + end always@(x__h73310 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMMIOInst.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMMIOInst.v index 90d593c..f5a9143 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMMIOInst.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMMIOInst.v @@ -337,6 +337,12 @@ module mkMMIOInst(CLK, respQ_enqReq_dummy2_2$EN, respQ_enqReq_dummy2_2$Q_OUT; + // ports of submodule soc_map + wire [63 : 0] soc_map$m_is_IO_addr_addr, + soc_map$m_is_mem_addr_addr, + soc_map$m_is_near_mem_IO_addr_addr; + wire soc_map$m_is_IO_addr; + // rule scheduling signals wire CAN_FIRE_RL_pendQ_canonicalize, CAN_FIRE_RL_pendQ_clearReq_canon, @@ -387,8 +393,7 @@ module mkMMIOInst(CLK, // value method getFetchTarget assign getFetchTarget = - (getFetchTarget_phyPc[63:3] >= 61'd512 && - getFetchTarget_phyPc[63:3] < 61'd1024) ? + soc_map$m_is_IO_addr ? 2'd1 : ((getFetchTarget_phyPc[63:3] >= 61'd268435456 && getFetchTarget_phyPc[63:3] < 61'd301989888 && @@ -584,6 +589,37 @@ module mkMMIOInst(CLK, .EN(respQ_enqReq_dummy2_2$EN), .Q_OUT(respQ_enqReq_dummy2_2$Q_OUT)); + // submodule soc_map + mkSoC_Map soc_map(.CLK(CLK), + .RST_N(RST_N), + .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), + .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), + .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), + .m_near_mem_io_addr_base(), + .m_near_mem_io_addr_size(), + .m_near_mem_io_addr_lim(), + .m_plic_addr_base(), + .m_plic_addr_size(), + .m_plic_addr_lim(), + .m_uart0_addr_base(), + .m_uart0_addr_size(), + .m_uart0_addr_lim(), + .m_boot_rom_addr_base(), + .m_boot_rom_addr_size(), + .m_boot_rom_addr_lim(), + .m_mem0_controller_addr_base(), + .m_mem0_controller_addr_size(), + .m_mem0_controller_addr_lim(), + .m_tcm_addr_base(), + .m_tcm_addr_size(), + .m_tcm_addr_lim(), + .m_is_mem_addr(), + .m_is_IO_addr(soc_map$m_is_IO_addr), + .m_is_near_mem_IO_addr(), + .m_pc_reset_value(), + .m_mtvec_reset_value(), + .m_nmivec_reset_value()); + // rule RL_reqQ_canonicalize assign CAN_FIRE_RL_reqQ_canonicalize = 1'd1 ; assign WILL_FIRE_RL_reqQ_canonicalize = 1'd1 ; @@ -842,6 +878,11 @@ module mkMMIOInst(CLK, assign respQ_enqReq_dummy2_2$D_IN = 1'd1 ; assign respQ_enqReq_dummy2_2$EN = 1'd1 ; + // submodule soc_map + assign soc_map$m_is_IO_addr_addr = getFetchTarget_phyPc ; + assign soc_map$m_is_mem_addr_addr = 64'h0 ; + assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + // remaining internal signals assign IF_reqQ_enqReq_lat_1_whas_THEN_reqQ_enqReq_lat_ETC___d13 = EN_bootRomReq ? reqQ_enqReq_lat_0$wget[65] : reqQ_enqReq_rl[65] ; diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v index 048be91..89c6984 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v @@ -673,10 +673,10 @@ module mkMemLoader(CLK_portalClk, IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41, IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11, IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114, - IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84, - IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260, IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230, IF_mmio_req_wrBE_BIT_7_38_THEN_mmio_req_wrData_ETC___d864, + x__h10090, + x__h3821, x__h6528; wire [7 : 0] IF_reqSel_69_EQ_0_76_THEN_hostWrDataQ_q_wDataO_ETC___d480, IF_reqSel_69_EQ_1_97_THEN_hostWrDataQ_q_wDataO_ETC___d499, @@ -1338,11 +1338,11 @@ module mkMemLoader(CLK_portalClk, hostWrDataQ_q_rRdPtr_rsCounter | x__h4511 : hostWrDataQ_q_rRdPtr_rsCounter & y__h4698 ; assign MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 = - (~hostWrDataQ_q_rWrPtr_rsCounter[IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84[0]]) ? + (~hostWrDataQ_q_rWrPtr_rsCounter[x__h3821[0]]) ? hostWrDataQ_q_rWrPtr_rsCounter | x__h3656 : hostWrDataQ_q_rWrPtr_rsCounter & y__h3843 ; assign MUX_hostWrDoneQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrDoneQ_q_rRdPtr_rsCounter[IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260[0]]) ? + (~hostWrDoneQ_q_rRdPtr_rsCounter[x__h10090[0]]) ? hostWrDoneQ_q_rRdPtr_rsCounter | x__h9925 : hostWrDoneQ_q_rRdPtr_rsCounter & y__h10112 ; assign MUX_hostWrDoneQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1783,14 +1783,6 @@ module mkMemLoader(CLK_portalClk, hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? 32'd1 : 32'd0 ; - assign IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 = - hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? - 32'd1 : - 32'd0 ; - assign IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 = - hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 ? - 32'd1 : - 32'd0 ; assign IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230 = hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27_XOR_ETC___d229 ? 32'd1 : @@ -2127,14 +2119,20 @@ module mkMemLoader(CLK_portalClk, (!respStQ_deqReq_dummy2_2$Q_OUT || !CAN_FIRE_RL_doStResp && !respStQ_deqReq_rl) && respStQ_full ; + assign x__h10090 = + hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 ? + 32'd1 : + 32'd0 ; assign x__h10885 = x_sReadBin__h10334 + 2'd1 ; assign x__h1801 = 2'd1 << IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 ; assign x__h2762 = x_sReadBin__h2210 + 2'd1 ; - assign x__h3656 = - 2'd1 << - IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 ; + assign x__h3656 = 2'd1 << x__h3821 ; + assign x__h3821 = + hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? + 32'd1 : + 32'd0 ; assign x__h4511 = 2'd1 << IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 ; @@ -2154,9 +2152,7 @@ module mkMemLoader(CLK_portalClk, assign x__h938 = 2'd1 << IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 ; - assign x__h9925 = - 2'd1 << - IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 ; + assign x__h9925 = 2'd1 << x__h10090 ; assign x_addr__h43806 = MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[639:576] : diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index a3cd8df..360ffc3 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -1667,51 +1667,51 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h4124; - reg [31 : 0] v__h4290; - reg [31 : 0] v__h4554; - reg [31 : 0] v__h6593; + reg [31 : 0] v__h4297; + reg [31 : 0] v__h4561; + reg [31 : 0] v__h6600; reg [31 : 0] v__h2400; - reg [31 : 0] v__h6894; - reg [31 : 0] v__h7387; - reg [31 : 0] v__h7550; - reg [31 : 0] v__h112132; - reg [31 : 0] v__h112299; - reg [31 : 0] v__h114402; - reg [31 : 0] v__h131748; - reg [31 : 0] v__h111513; - reg [31 : 0] v__h138443; - reg [31 : 0] v__h138951; + reg [31 : 0] v__h6901; + reg [31 : 0] v__h7394; + reg [31 : 0] v__h7557; + reg [31 : 0] v__h112139; + reg [31 : 0] v__h112306; + reg [31 : 0] v__h114409; + reg [31 : 0] v__h131755; + reg [31 : 0] v__h111520; + reg [31 : 0] v__h138450; + reg [31 : 0] v__h138958; reg [31 : 0] v__h2394; reg [31 : 0] v__h4118; - reg [31 : 0] v__h4284; - reg [31 : 0] v__h4548; - reg [31 : 0] v__h6587; - reg [31 : 0] v__h6888; - reg [31 : 0] v__h7381; - reg [31 : 0] v__h7544; - reg [31 : 0] v__h111507; - reg [31 : 0] v__h112126; - reg [31 : 0] v__h112293; - reg [31 : 0] v__h114396; - reg [31 : 0] v__h131742; - reg [31 : 0] v__h138437; - reg [31 : 0] v__h138945; + reg [31 : 0] v__h4291; + reg [31 : 0] v__h4555; + reg [31 : 0] v__h6594; + reg [31 : 0] v__h6895; + reg [31 : 0] v__h7388; + reg [31 : 0] v__h7551; + reg [31 : 0] v__h111514; + reg [31 : 0] v__h112133; + reg [31 : 0] v__h112300; + reg [31 : 0] v__h114403; + reg [31 : 0] v__h131749; + reg [31 : 0] v__h138444; + reg [31 : 0] v__h138952; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x7542_0_n__read_addr7720_1_n__read_addr77_ETC__q26, - CASE_x8657_0_n__read_addr8839_1_n__read_addr89_ETC__q15, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x7549_0_n__read_addr7727_1_n__read_addr78_ETC__q26, + CASE_x8664_0_n__read_addr8846_1_n__read_addr89_ETC__q15, IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775, IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788, IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827, @@ -1721,34 +1721,34 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885, IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d853, IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d855, - data64__h125572, - ld_data__h109233, - w1__h45638, - w1__h45643, - w2__h45639, - w2__h45645, - x__h45634; + data64__h125579, + ld_data__h109240, + w1__h45645, + w1__h45650, + w2__h45646, + w2__h45652, + x__h45641; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952; - reg [7 : 0] strb8__h125573; + reg [7 : 0] strb8__h125580; reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [2 : 0] x__h58971; - reg [1 : 0] CASE_x7542_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; + reg [2 : 0] x__h58978; + reg [1 : 0] CASE_x7549_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x7542_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x8657_0_propDstData_0_dummy2_1_read__061__ETC__q12, + CASE_x7549_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x8664_0_propDstData_0_dummy2_1_read__061__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__023_AND_IF_ETC___d1054, SEL_ARR_propDstIdx_1_0_dummy2_1_read__287_AND__ETC___d1328, - x__h58978, - x__h79958; + x__h58985, + x__h79965; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__232_THEN_enqDst_1_0__ETC___d1279; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__335__ETC___d1427; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__232_THEN_enqDst_1_0__ETC___d1278; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1270, SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1420, - new_cline__h112435; + new_cline__h112442; wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1403; wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1386; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1369; @@ -1768,82 +1768,82 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, IF_propDstData_1_0_lat_0_whas__159_THEN_propDs_ETC___d1164, IF_propDstData_1_1_lat_0_whas__197_THEN_propDs_ETC___d1202, - data__h29363, - failed_testnum__h140337, - mem_req_rd_addr_araddr__h111733, - mem_req_wr_addr_awaddr__h125657, - mmioPlatform_fromHostQ_data_0__h40209, - mmioPlatform_mtime__h34677, - mmioPlatform_reqData__h46230, - n__read_addr__h58839, - n__read_addr__h58924, - n__read_addr__h77720, - n__read_addr__h77799, - n__read_snd_addr__h92151, - newData__h29444, - newData__h32374, - op_result__h46246, - op_result__h46776, - op_result__h46781, - op_result__h46786, - op_result__h46791, - op_result__h46797, + data__h29370, + failed_testnum__h140344, + mem_req_rd_addr_araddr__h111740, + mem_req_wr_addr_awaddr__h125664, + mmioPlatform_fromHostQ_data_0__h40216, + mmioPlatform_mtime__h34684, + mmioPlatform_reqData__h46237, + n__read_addr__h58846, + n__read_addr__h58931, + n__read_addr__h77727, + n__read_addr__h77806, + n__read_snd_addr__h92158, + newData__h29451, + newData__h32381, + op_result__h46253, + op_result__h46783, + op_result__h46788, + op_result__h46793, + op_result__h46798, op_result__h46804, - op_result__h46810, - result__h45689, - result__h45813, - result__h45841, - result__h45869, - result__h45897, - result__h45925, - result__h45953, - result__h45981, - result__h46009, - result__h46054, - result__h46082, - result__h46110, - result__h46138, - result__h46179, - result__h46207, - result__h46333, - result__h46360, - result__h46387, - result__h46414, - result__h46441, - result__h46468, - result__h46495, - result__h46522, - result__h46566, - result__h46593, - result__h46620, - result__h46647, - result__h46687, - result__h46714, - result__h46831, - result__h46897, - result__h46963, - result__h47029, - result__h47095, - result__h47161, - result__h47227, - result__h47289, - result__h47334, - result__h47400, - result__h47466, - result__h47524, - result__h47569, - w1___1__h45748, - w2___1__h45749, - x1_avValue_data__h37881, - x1_avValue_data__h42567, - x__h29555, - x__h32465, - x__h34825, - x__h38399, - x__h38410, - x__h40492, - x__h40503, - x__h47746; + op_result__h46811, + op_result__h46817, + result__h45696, + result__h45820, + result__h45848, + result__h45876, + result__h45904, + result__h45932, + result__h45960, + result__h45988, + result__h46016, + result__h46061, + result__h46089, + result__h46117, + result__h46145, + result__h46186, + result__h46214, + result__h46340, + result__h46367, + result__h46394, + result__h46421, + result__h46448, + result__h46475, + result__h46502, + result__h46529, + result__h46573, + result__h46600, + result__h46627, + result__h46654, + result__h46694, + result__h46721, + result__h46838, + result__h46904, + result__h46970, + result__h47036, + result__h47102, + result__h47168, + result__h47234, + result__h47296, + result__h47341, + result__h47407, + result__h47473, + result__h47531, + result__h47576, + w1___1__h45755, + w2___1__h45756, + x1_avValue_data__h37888, + x1_avValue_data__h42574, + x__h29562, + x__h32472, + x__h34832, + x__h38406, + x__h38417, + x__h40499, + x__h40510, + x__h47753; wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d674; @@ -1854,16 +1854,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h29156, - v__h29193, - w15638_BITS_31_TO_0__q7, - w25639_BITS_31_TO_0__q8, - x_data__h27946; + v__h29163, + v__h29200, + w15645_BITS_31_TO_0__q7, + w25646_BITS_31_TO_0__q8, + x_data__h27953; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__061_TH_ETC___d1125; - wire [5 : 0] x__h111768, x__h125682; + wire [5 : 0] x__h111775, x__h125689; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__061_AND_I_ETC___d1124; - wire [3 : 0] b__h111440, b__h2294; - wire [2 : 0] n__read_id__h58843, n__read_id__h58928; + wire [3 : 0] b__h111447, b__h2294; + wire [2 : 0] n__read_id__h58850, n__read_id__h58935; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1255, IF_propDstData_0_dummy2_1_read__061_THEN_IF_pr_ETC___d1077, IF_propDstData_0_dummy2_1_read__061_THEN_IF_pr_ETC___d1087, @@ -1924,22 +1924,22 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27571, - mmioPlatform_reqBE_BIT_4___h27531, + mmioPlatform_reqBE_BIT_0___h27578, + mmioPlatform_reqBE_BIT_4___h27538, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h58844, - n__read_child__h58929, - n__read_child__h77723, - n__read_child__h77802, - n__read_snd_id__h92152, + n__read_child__h58851, + n__read_child__h58936, + n__read_child__h77730, + n__read_child__h77809, + n__read_snd_id__h92159, propDstData_0_dummy2_1_read__061_AND_IF_propDs_ETC___d1097, propDstData_1_dummy2_1_read__066_AND_IF_propDs_ETC___d1101, - x__h58657, - x__h72471, - x__h77542; + x__h58664, + x__h72478, + x__h77549; // action method hart0_server_reset_request_put assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -2738,16 +2738,16 @@ module mkProc(CLK, // rule RL_srcPropose assign CAN_FIRE_RL_srcPropose = - core_0$RDY_dCacheToParent_rqToP_deq && core_0$RDY_dCacheToParent_rqToP_first && + core_0$RDY_dCacheToParent_rqToP_deq && (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT || !propDstIdx_0_rl) ; assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ; // rule RL_srcPropose_1 assign CAN_FIRE_RL_srcPropose_1 = - core_0$RDY_iCacheToParent_rqToP_deq && core_0$RDY_iCacheToParent_rqToP_first && + core_0$RDY_iCacheToParent_rqToP_deq && (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT || !propDstIdx_1_rl) ; assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ; @@ -2764,8 +2764,8 @@ module mkProc(CLK, // rule RL_srcPropose_2 assign CAN_FIRE_RL_srcPropose_2 = - core_0$RDY_dCacheToParent_rsToP_deq && core_0$RDY_dCacheToParent_rsToP_first && + core_0$RDY_dCacheToParent_rsToP_deq && (!propDstIdx_1_0_dummy2_0$Q_OUT || !propDstIdx_1_0_dummy2_1$Q_OUT || !propDstIdx_1_0_rl) ; @@ -2773,8 +2773,8 @@ module mkProc(CLK, // rule RL_srcPropose_3 assign CAN_FIRE_RL_srcPropose_3 = - core_0$RDY_iCacheToParent_rsToP_deq && core_0$RDY_iCacheToParent_rsToP_first && + core_0$RDY_iCacheToParent_rsToP_deq && (!propDstIdx_1_1_dummy2_0$Q_OUT || !propDstIdx_1_1_dummy2_1$Q_OUT || !propDstIdx_1_1_rl) ; @@ -2792,7 +2792,7 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_deq && llc$RDY_to_child_toC_first && + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; @@ -2800,7 +2800,7 @@ module mkProc(CLK, // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_deq && llc$RDY_to_child_toC_first && + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; @@ -2808,7 +2808,7 @@ module mkProc(CLK, // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_deq && llc$RDY_to_child_toC_first && + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; @@ -2816,7 +2816,7 @@ module mkProc(CLK, // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_deq && llc$RDY_to_child_toC_first && + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; @@ -2824,8 +2824,8 @@ module mkProc(CLK, // rule RL_srcPropose_4 assign CAN_FIRE_RL_srcPropose_4 = - core_0$RDY_tlbToMem_memReq_deq && core_0$RDY_tlbToMem_memReq_first && + core_0$RDY_tlbToMem_memReq_deq && (!propDstIdx_0_dummy2_0_1$Q_OUT || !propDstIdx_0_dummy2_1_1$Q_OUT || !propDstIdx_0_rl_1) ; @@ -2848,28 +2848,28 @@ module mkProc(CLK, // rule RL_sendLdRespToMemLoader assign CAN_FIRE_RL_sendLdRespToMemLoader = - llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && !llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_sendLdRespToMemLoader = CAN_FIRE_RL_sendLdRespToMemLoader ; // rule RL_sendLdRespToTlb assign CAN_FIRE_RL_sendLdRespToTlb = - llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && core_0$RDY_tlbToMem_respLd_enq && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_sendLdRespToTlb = CAN_FIRE_RL_sendLdRespToTlb ; // rule RL_sendStRespToMemLoader assign CAN_FIRE_RL_sendStRespToMemLoader = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && !llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_sendStRespToMemLoader = CAN_FIRE_RL_sendStRespToMemLoader ; // rule RL_sendStRespToTlb assign CAN_FIRE_RL_sendStRespToTlb = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_sendStRespToTlb = CAN_FIRE_RL_sendStRespToTlb ; @@ -3037,8 +3037,8 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMTimeCmpDone assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone = - core_0$RDY_mmioToPlatform_pRs_enq && core_0$RDY_mmioToPlatform_cRs_deq && + core_0$RDY_mmioToPlatform_pRs_enq && mmioPlatform_curReq[66:64] == 3'd3 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone = @@ -3067,7 +3067,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40492 == 64'd0 || + x__h40499 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3244,13 +3244,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h111440 == 4'd0 ; + b__h111447 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h111440 != 4'd0 && + b__h111447 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3342,7 +3342,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h27946 } ; + x_data__h27953 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && @@ -3377,7 +3377,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d957 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29363 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29370 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3491,7 +3491,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45634 } ; + x__h45641 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, @@ -3500,53 +3500,53 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47746, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h47753, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40492 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40499 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40492 != 64'd0 ; + x__h40499 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38399 == 64'd0 ; + x__h38406 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__044_045_OR_NOT_enq_ETC___d1060 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__023_AND_ETC___d1130 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__044_045_OR_NOT_enq_ETC___d1060 && - x__h58657 ; + x__h58664 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8657_0_n__read_addr8839_1_n__read_addr89_ETC__q15, + CASE_x8664_0_n__read_addr8846_1_n__read_addr89_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__061_TH_ETC___d1125 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__318_319_OR_NOT_e_ETC___d1334 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__287_A_ETC___d1432 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__318_319_OR_NOT_e_ETC___d1334 && - x__h77542 ; + x__h77549 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7542_0_n__read_addr7720_1_n__read_addr77_ETC__q26, + CASE_x7549_0_n__read_addr7727_1_n__read_addr78_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__335__ETC___d1427 } ; assign enqDst_0_lat_0_1$wget = - { 1'd1, n__read_snd_addr__h92151, n__read_snd_id__h92152 } ; + { 1'd1, n__read_snd_addr__h92158, n__read_snd_id__h92159 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -3652,11 +3652,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h111440 - 4'd1 ; + b__h111447 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h111440 ; + b__h111447 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = CAN_FIRE_RL_rl_reset ? 4'd0 : @@ -3731,7 +3731,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h111733, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h111740, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -3742,13 +3742,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h125657, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h125664, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h125572, strb8__h125573, 1'd1 } ; + { 4'd0, data64__h125579, strb8__h125580, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -3760,7 +3760,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h112435 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h112442 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3897,7 +3897,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32374 : + newData__h32381 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -3906,7 +3906,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29444 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h29451 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4328,7 +4328,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h109233, llc$dma_respLd_first[3] } ; + { ld_data__h109240, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4438,11 +4438,11 @@ module mkProc(CLK, // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; + assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; + assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -4465,7 +4465,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1270, IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1276 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h112435, + { new_cline__h112442, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -4726,47 +4726,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27531 && - mmioPlatform_reqBE_BIT_0___h27571, + mmioPlatform_reqBE_BIT_4___h27538 && + mmioPlatform_reqBE_BIT_0___h27578, 2'd0 }), - .amoExec_current_data(x__h34825), - .amoExec_in_data(mmioPlatform_reqData__h46230), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27531 && - !mmioPlatform_reqBE_BIT_0___h27571), - .amoExec(x__h29555)); + .amoExec_current_data(x__h34832), + .amoExec_in_data(mmioPlatform_reqData__h46237), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27538 && + !mmioPlatform_reqBE_BIT_0___h27578), + .amoExec(x__h29562)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27531 && - mmioPlatform_reqBE_BIT_0___h27571, + mmioPlatform_reqBE_BIT_4___h27538 && + mmioPlatform_reqBE_BIT_0___h27578, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34677), - .amoExec_in_data(mmioPlatform_reqData__h46230), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27531 && - !mmioPlatform_reqBE_BIT_0___h27571), - .amoExec(x__h32465)); + .amoExec_current_data(mmioPlatform_mtime__h34684), + .amoExec_in_data(mmioPlatform_reqData__h46237), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27538 && + !mmioPlatform_reqBE_BIT_0___h27578), + .amoExec(x__h32472)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27531 && - mmioPlatform_reqBE_BIT_0___h27571, + mmioPlatform_reqBE_BIT_4___h27538 && + mmioPlatform_reqBE_BIT_0___h27578, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40209), - .amoExec_in_data(mmioPlatform_reqData__h46230), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27531 && - !mmioPlatform_reqBE_BIT_0___h27571), - .amoExec(x__h38410)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40216), + .amoExec_in_data(mmioPlatform_reqData__h46237), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27538 && + !mmioPlatform_reqBE_BIT_0___h27578), + .amoExec(x__h38417)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27531 && - mmioPlatform_reqBE_BIT_0___h27571, + mmioPlatform_reqBE_BIT_4___h27538 && + mmioPlatform_reqBE_BIT_0___h27578, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h46230), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27531 && - !mmioPlatform_reqBE_BIT_0___h27571), - .amoExec(x__h40503)); + .amoExec_in_data(mmioPlatform_reqData__h46237), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27538 && + !mmioPlatform_reqBE_BIT_0___h27578), + .amoExec(x__h40510)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37881 } } ; + x1_avValue_data__h37888 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && !mmioPlatform_mtip_0 || @@ -4782,7 +4782,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29444 <= mmioPlatform_mtime ; + newData__h29451 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__023_024_OR__ETC___d1058 = NOT_propDstIdx_0_dummy2_1_read__023_024_OR_IF__ETC___d1057 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -4851,7 +4851,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1270, - x__h72471 } ; + x__h72478 } ; assign IF_enqDst_1_0_lat_1_whas__232_THEN_enqDst_1_0__ETC___d1279 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -4996,23 +4996,23 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d687 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h40492 == 64'd0 : - x__h38399 == 64'd0, + x__h40499 == 64'd0 : + x__h38406 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42567 } ; + x1_avValue_data__h42574 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; assign IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 = mmioPlatform_waitLowerMSIPCRs ? - core_0$RDY_mmioToPlatform_cRs_deq && - core_0$RDY_mmioToPlatform_cRs_first : + core_0$RDY_mmioToPlatform_cRs_first && + core_0$RDY_mmioToPlatform_cRs_deq : (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_deq) && + core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_first) ; + core_0$RDY_mmioToPlatform_cRs_deq) ; assign IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d940 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < @@ -5184,8 +5184,8 @@ module mkProc(CLK, !mmioPlatform_mtip_0 && mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || !core_0$mmioToPlatform_cRq_notEmpty || - core_0$RDY_mmioToPlatform_cRq_deq && - core_0$RDY_mmioToPlatform_cRq_first ; + core_0$RDY_mmioToPlatform_cRq_first && + core_0$RDY_mmioToPlatform_cRq_deq ; assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || @@ -5239,34 +5239,34 @@ module mkProc(CLK, !propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__061_TH_ETC___d1125 = - { CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, + { CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__061_AND_I_ETC___d1124 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__335__ETC___d1427 = - { CASE_x7542_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x7542_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x7549_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x7549_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1420, - x__h79958 } ; + x__h79965 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1369 = - { CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1386 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1369, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1403 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1386, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1420 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__159_THE_ETC___d1403, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__061_AND_I_ETC___d1124 = - { CASE_x8657_0_propDstData_0_dummy2_1_read__061__ETC__q12, - x__h58971, - x__h58978 } ; - assign b__h111440 = + { CASE_x8664_0_propDstData_0_dummy2_1_read__061__ETC__q12, + x__h58978, + x__h58985 } ; + assign b__h111447 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -5274,20 +5274,20 @@ module mkProc(CLK, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29363 = + assign data__h29370 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29156, 32'd0 } ; - assign failed_testnum__h140337 = + { v__h29163, 32'd0 } ; + assign failed_testnum__h140344 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign mem_req_rd_addr_araddr__h111733 = - { llc$to_mem_toM_first[68:11], x__h111768 } ; - assign mem_req_wr_addr_awaddr__h125657 = - { llc$to_mem_toM_first[639:582], x__h125682 } ; + assign mem_req_rd_addr_araddr__h111740 = + { llc$to_mem_toM_first[68:11], x__h111775 } ; + assign mem_req_wr_addr_awaddr__h125664 = + { llc$to_mem_toM_first[639:582], x__h125689 } ; assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_35_ULT_mmioPlatform_r_ETC___d945 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40209 = + assign mmioPlatform_fromHostQ_data_0__h40216 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -5298,18 +5298,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34677 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h34684 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32374 ; + mmioPlatform_mtimecmp_0 <= newData__h32381 ; assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27571 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27531 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h46230 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h27578 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h27538 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h46237 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -5336,104 +5336,104 @@ module mkProc(CLK, !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h58839 = + assign n__read_addr__h58846 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h58924 = + assign n__read_addr__h58931 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h77720 = + assign n__read_addr__h77727 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__159_THEN_propDs_ETC___d1164 : 64'd0 ; - assign n__read_addr__h77799 = + assign n__read_addr__h77806 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__197_THEN_propDs_ETC___d1202 : 64'd0 ; - assign n__read_child__h58844 = + assign n__read_child__h58851 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h58929 = + assign n__read_child__h58936 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h77723 = + assign n__read_child__h77730 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__159_THEN_propDs_ETC___d1190 ; - assign n__read_child__h77802 = + assign n__read_child__h77809 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__197_THEN_propDs_ETC___d1228 ; - assign n__read_id__h58843 = + assign n__read_id__h58850 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h58928 = + assign n__read_id__h58935 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h92151 = + assign n__read_snd_addr__h92158 = propDstData_0_dummy2_1_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[64:1] : propDstData_0_rl_1[64:1]) : 64'd0 ; - assign n__read_snd_id__h92152 = + assign n__read_snd_id__h92159 = propDstData_0_dummy2_1_1$Q_OUT && (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[0] : propDstData_0_rl_1[0]) ; - assign newData__h29444 = + assign newData__h29451 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29555 : + x__h29562 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32374 = + assign newData__h32381 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32465 : + x__h32472 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h112435 = + assign new_cline__h112442 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h46246 = + assign op_result__h46253 = IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d853 + IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d855 ; - assign op_result__h46776 = w1__h45643 ^ w2__h45645 ; - assign op_result__h46781 = w1__h45643 & w2__h45645 ; - assign op_result__h46786 = w1__h45643 | w2__h45645 ; - assign op_result__h46791 = - (w1__h45643 < w2__h45645) ? w1__h45643 : w2__h45645 ; - assign op_result__h46797 = - (w1__h45643 <= w2__h45645) ? w2__h45645 : w1__h45643 ; + assign op_result__h46783 = w1__h45650 ^ w2__h45652 ; + assign op_result__h46788 = w1__h45650 & w2__h45652 ; + assign op_result__h46793 = w1__h45650 | w2__h45652 ; + assign op_result__h46798 = + (w1__h45650 < w2__h45652) ? w1__h45650 : w2__h45652 ; assign op_result__h46804 = + (w1__h45650 <= w2__h45652) ? w2__h45652 : w1__h45650 ; + assign op_result__h46811 = ((IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d853 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d855 ^ 64'h8000000000000000)) ? - w1__h45643 : - w2__h45645 ; - assign op_result__h46810 = + w1__h45650 : + w2__h45652 ; + assign op_result__h46817 = ((IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d853 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d855 ^ 64'h8000000000000000)) ? - w2__h45645 : - w1__h45643 ; + w2__h45652 : + w1__h45650 ; assign propDstData_0_dummy2_1_read__061_AND_IF_propDs_ETC___d1097 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -5444,126 +5444,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h45689 = + assign result__h45696 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0] } ; - assign result__h45813 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45841 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45869 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45897 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45925 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45953 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45981 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h46009 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h46054 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h46082 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h46110 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h46138 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h46179 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h46207 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46333 = + assign result__h45820 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h45848 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h45876 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h45904 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h45932 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h45960 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h45988 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h46016 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h46061 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h46089 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h46117 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h46145 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h46186 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h46214 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h46340 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46360 = + assign result__h46367 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46387 = + assign result__h46394 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46414 = + assign result__h46421 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46441 = + assign result__h46448 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46468 = + assign result__h46475 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46495 = + assign result__h46502 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46522 = + assign result__h46529 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46566 = + assign result__h46573 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46593 = + assign result__h46600 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46620 = + assign result__h46627 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46647 = + assign result__h46654 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46687 = + assign result__h46694 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46714 = + assign result__h46721 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46831 = + assign result__h46838 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46897 = + assign result__h46904 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46963 = + assign result__h46970 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h47029 = + assign result__h47036 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h47095 = + assign result__h47102 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h47161 = + assign result__h47168 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h47227 = + assign result__h47234 = { IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h47289 = + assign result__h47296 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[15:0] } ; - assign result__h47334 = + assign result__h47341 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47400 = + assign result__h47407 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47466 = + assign result__h47473 = { IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47524 = + assign result__h47531 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[31:0] } ; - assign result__h47569 = + assign result__h47576 = { IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29156 = mmioPlatform_waitUpperMSIPCRs ? v__h29193 : 32'd0 ; - assign v__h29193 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15638_BITS_31_TO_0__q7 = w1__h45638[31:0] ; - assign w1___1__h45748 = { 32'd0, w1__h45638[31:0] } ; - assign w25639_BITS_31_TO_0__q8 = w2__h45639[31:0] ; - assign w2___1__h45749 = { 32'd0, w2__h45639[31:0] } ; - assign x1_avValue_data__h37881 = + assign v__h29163 = mmioPlatform_waitUpperMSIPCRs ? v__h29200 : 32'd0 ; + assign v__h29200 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w15645_BITS_31_TO_0__q7 = w1__h45645[31:0] ; + assign w1___1__h45755 = { 32'd0, w1__h45645[31:0] } ; + assign w25646_BITS_31_TO_0__q8 = w2__h45646[31:0] ; + assign w2___1__h45756 = { 32'd0, w2__h45646[31:0] } ; + assign x1_avValue_data__h37888 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42567 = + assign x1_avValue_data__h42574 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h111768 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h125682 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34825 = mmioPlatform_mtimecmp_0 ; - assign x__h38399 = + assign x__h111775 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h125689 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h34832 = mmioPlatform_mtimecmp_0 ; + assign x__h38406 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38410 : + x__h38417 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d679 ; - assign x__h40492 = + assign x__h40499 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40503 : + x__h40510 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -5572,123 +5572,123 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47746 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h58657 = + assign x__h47753 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h58664 = SEL_ARR_propDstIdx_0_dummy2_1_read__023_AND_IF_ETC___d1054 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__023_024_OR_IF__ETC___d1057 ; - assign x__h72471 = + assign x__h72478 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__235_THEN_enqDst_1_0__ETC___d1276 ; - assign x__h77542 = + assign x__h77549 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__287_AND__ETC___d1328 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__287_288_OR_I_ETC___d1331 ; - assign x_data__h27946 = { 31'd0, mmioPlatform_reqData[0] } ; + assign x_data__h27953 = { 31'd0, mmioPlatform_reqData[0] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h109233 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h109233 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h109233 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h109233 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h109233 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h109233 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h109233 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h109233 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h109240 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h109240 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h109240 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h109240 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h109240 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h109240 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h109240 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h109240 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h125572 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h125572 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h125572 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h125572 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h125572 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h125572 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h125572 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h125572 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h125579 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h125579 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h125579 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h125579 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h125579 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h125579 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h125579 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h125579 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h125573 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h125573 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h125573 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h125573 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h125573 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h125573 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h125573 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h125573 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h125580 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h125580 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h125580 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h125580 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h125580 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h125580 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h125580 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h125580 = llc$to_mem_toM_first[575:568]; endcase end always@(mmioPlatform_curReq or - result__h46054 or - result__h46082 or result__h46110 or result__h46138) + result__h45820 or + result__h45848 or + result__h45876 or + result__h45904 or + result__h45932 or + result__h45960 or result__h45988 or result__h46016) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h45820; + 3'h1: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h45848; + 3'h2: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h45876; + 3'h3: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h45904; + 3'h4: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h45932; + 3'h5: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h45960; + 3'h6: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h45988; + 3'h7: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = + result__h46016; + endcase + end + always@(mmioPlatform_curReq or + result__h46061 or + result__h46089 or result__h46117 or result__h46145) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46054; + result__h46061; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46082; + result__h46089; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46110; + result__h46117; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = - result__h46138; + result__h46145; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h45813 or - result__h45841 or - result__h45869 or - result__h45897 or - result__h45925 or - result__h45953 or result__h45981 or result__h46009) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h45813; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h45841; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h45869; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h45897; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h45925; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h45953; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h45981; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 = - result__h46009; - endcase - end - always@(mmioPlatform_curReq or result__h46179 or result__h46207) + always@(mmioPlatform_curReq or result__h46186 or result__h46214) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h46179; + result__h46186; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h46207; + result__h46214; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -5700,102 +5700,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h45639 = + w2__h45646 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775; 2'b01: - w2__h45639 = + w2__h45646 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788; 2'b10: - w2__h45639 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h45646 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h45639 = + w2__h45646 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d795; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 or - w2___1__h45749 or + w2___1__h45756 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d795) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45645 = + w2__h45652 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775; 2'b01: - w2__h45645 = + w2__h45652 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788; - 2'b10: w2__h45645 = w2___1__h45749; + 2'b10: w2__h45652 = w2___1__h45756; 2'b11: - w2__h45645 = + w2__h45652 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d795; endcase end always@(mmioPlatform_curReq or - result__h46566 or - result__h46593 or result__h46620 or result__h46647) + result__h46573 or + result__h46600 or result__h46627 or result__h46654) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839 = - result__h46566; + result__h46573; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839 = - result__h46593; + result__h46600; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839 = - result__h46620; + result__h46627; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839 = - result__h46647; + result__h46654; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h46333 or - result__h46360 or - result__h46387 or - result__h46414 or - result__h46441 or - result__h46468 or result__h46495 or result__h46522) + result__h46340 or + result__h46367 or + result__h46394 or + result__h46421 or + result__h46448 or + result__h46475 or result__h46502 or result__h46529) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46333; + result__h46340; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46360; + result__h46367; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46387; + result__h46394; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46414; + result__h46421; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46441; + result__h46448; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46468; + result__h46475; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46495; + result__h46502; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 = - result__h46522; + result__h46529; endcase end - always@(mmioPlatform_curReq or result__h46687 or result__h46714) + always@(mmioPlatform_curReq or result__h46694 or result__h46721) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46687; + result__h46694; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46714; + result__h46721; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -5807,41 +5807,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h45638 = + w1__h45645 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827; 2'b01: - w1__h45638 = + w1__h45645 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839; 2'b10: - w1__h45638 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h45645 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h45638 = + w1__h45645 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d846; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839 or - w1___1__h45748 or + w1___1__h45755 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d846) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45643 = + w1__h45650 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827; 2'b01: - w1__h45643 = + w1__h45650 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839; - 2'b10: w1__h45643 = w1___1__h45748; + 2'b10: w1__h45650 = w1___1__h45755; 2'b11: - w1__h45643 = + w1__h45650 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d846; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d827 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839 or - w15638_BITS_31_TO_0__q7 or + w15645_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d846) begin case (mmioPlatform_reqSz) @@ -5853,7 +5853,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d839; 2'b10: IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d853 = - { {32{w15638_BITS_31_TO_0__q7[31]}}, w15638_BITS_31_TO_0__q7 }; + { {32{w15645_BITS_31_TO_0__q7[31]}}, w15645_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d853 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d846; @@ -5862,7 +5862,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d775 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788 or - w25639_BITS_31_TO_0__q8 or + w25646_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d795) begin case (mmioPlatform_reqSz) @@ -5874,115 +5874,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d788; 2'b10: IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d855 = - { {32{w25639_BITS_31_TO_0__q8[31]}}, w25639_BITS_31_TO_0__q8 }; + { {32{w25646_BITS_31_TO_0__q8[31]}}, w25646_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_45_EQ_0b10_52_THEN_SEXT__ETC___d855 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d795; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h46810 or - w2__h45645 or - op_result__h46246 or - op_result__h46776 or - op_result__h46781 or - op_result__h46786 or - op_result__h46804 or op_result__h46791 or op_result__h46797) + op_result__h46817 or + w2__h45652 or + op_result__h46253 or + op_result__h46783 or + op_result__h46788 or + op_result__h46793 or + op_result__h46811 or op_result__h46798 or op_result__h46804) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - w2__h45645; + w2__h45652; 4'd1: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46246; + op_result__h46253; 4'd2: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46776; + op_result__h46783; 4'd3: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46781; + op_result__h46788; 4'd4: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46786; + op_result__h46793; 4'd5: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46804; + op_result__h46811; 4'd7: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46791; + op_result__h46798; 4'd8: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46797; + op_result__h46804; default: IF_mmioPlatform_reqAmofunc_50_EQ_0_51_THEN_IF__ETC___d885 = - op_result__h46810; + op_result__h46817; endcase end always@(mmioPlatform_curReq or - result__h47289 or - result__h47334 or result__h47400 or result__h47466) + result__h47296 or + result__h47341 or result__h47407 or result__h47473) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d918 = - result__h47289; + result__h47296; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d918 = - result__h47334; + result__h47341; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d918 = - result__h47400; + result__h47407; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d918 = - result__h47466; + result__h47473; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d918 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h45689 or - result__h46831 or - result__h46897 or - result__h46963 or - result__h47029 or - result__h47095 or result__h47161 or result__h47227) + result__h45696 or + result__h46838 or + result__h46904 or + result__h46970 or + result__h47036 or + result__h47102 or result__h47168 or result__h47234) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h45689; + result__h45696; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h46831; + result__h46838; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h46897; + result__h46904; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h46963; + result__h46970; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h47029; + result__h47036; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h47095; + result__h47102; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h47161; + result__h47168; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909 = - result__h47227; + result__h47234; endcase end - always@(mmioPlatform_curReq or result__h47524 or result__h47569) + always@(mmioPlatform_curReq or result__h47531 or result__h47576) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47524; + result__h47531; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47569; + result__h47576; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -5994,15 +5994,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h45634 = + x__h45641 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d909; 2'b01: - x__h45634 = + x__h45641 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d918; 2'b10: - x__h45634 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h45641 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h45634 = + x__h45641 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_47_EQ_0x_ETC___d795; endcase end @@ -6086,278 +6086,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__151_THEN_propDst_ETC___d1154; endcase end - always@(x__h58657 or n__read_id__h58843 or n__read_id__h58928) + always@(x__h58664 or n__read_id__h58850 or n__read_id__h58935) begin - case (x__h58657) - 1'd0: x__h58971 = n__read_id__h58843; - 1'd1: x__h58971 = n__read_id__h58928; + case (x__h58664) + 1'd0: x__h58978 = n__read_id__h58850; + 1'd1: x__h58978 = n__read_id__h58935; endcase end - always@(x__h58657 or n__read_child__h58844 or n__read_child__h58929) + always@(x__h58664 or n__read_child__h58851 or n__read_child__h58936) begin - case (x__h58657) - 1'd0: x__h58978 = n__read_child__h58844; - 1'd1: x__h58978 = n__read_child__h58929; + case (x__h58664) + 1'd0: x__h58985 = n__read_child__h58851; + 1'd1: x__h58985 = n__read_child__h58936; endcase end - always@(x__h58657 or + always@(x__h58664 or propDstData_0_dummy2_1_read__061_AND_IF_propDs_ETC___d1097 or propDstData_1_dummy2_1_read__066_AND_IF_propDs_ETC___d1101) begin - case (x__h58657) + case (x__h58664) 1'd0: - CASE_x8657_0_propDstData_0_dummy2_1_read__061__ETC__q12 = + CASE_x8664_0_propDstData_0_dummy2_1_read__061__ETC__q12 = propDstData_0_dummy2_1_read__061_AND_IF_propDs_ETC___d1097; 1'd1: - CASE_x8657_0_propDstData_0_dummy2_1_read__061__ETC__q12 = + CASE_x8664_0_propDstData_0_dummy2_1_read__061__ETC__q12 = propDstData_1_dummy2_1_read__066_AND_IF_propDs_ETC___d1101; endcase end - always@(x__h58657 or + always@(x__h58664 or IF_propDstData_0_dummy2_1_read__061_THEN_IF_pr_ETC___d1077 or IF_propDstData_1_dummy2_1_read__066_THEN_IF_pr_ETC___d1081) begin - case (x__h58657) + case (x__h58664) 1'd0: - CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = IF_propDstData_0_dummy2_1_read__061_THEN_IF_pr_ETC___d1077; 1'd1: - CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = IF_propDstData_1_dummy2_1_read__066_THEN_IF_pr_ETC___d1081; endcase end - always@(x__h58657 or + always@(x__h58664 or IF_propDstData_0_dummy2_1_read__061_THEN_IF_pr_ETC___d1087 or IF_propDstData_1_dummy2_1_read__066_THEN_IF_pr_ETC___d1091) begin - case (x__h58657) + case (x__h58664) 1'd0: - CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = IF_propDstData_0_dummy2_1_read__061_THEN_IF_pr_ETC___d1087; 1'd1: - CASE_x8657_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + CASE_x8664_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = IF_propDstData_1_dummy2_1_read__066_THEN_IF_pr_ETC___d1091; endcase end - always@(x__h58657 or n__read_addr__h58839 or n__read_addr__h58924) + always@(x__h58664 or n__read_addr__h58846 or n__read_addr__h58931) begin - case (x__h58657) + case (x__h58664) 1'd0: - CASE_x8657_0_n__read_addr8839_1_n__read_addr89_ETC__q15 = - n__read_addr__h58839; + CASE_x8664_0_n__read_addr8846_1_n__read_addr89_ETC__q15 = + n__read_addr__h58846; 1'd1: - CASE_x8657_0_n__read_addr8839_1_n__read_addr89_ETC__q15 = - n__read_addr__h58924; + CASE_x8664_0_n__read_addr8846_1_n__read_addr89_ETC__q15 = + n__read_addr__h58931; endcase end - always@(x__h77542 or n__read_child__h77723 or n__read_child__h77802) + always@(x__h77549 or n__read_child__h77730 or n__read_child__h77809) begin - case (x__h77542) - 1'd0: x__h79958 = n__read_child__h77723; - 1'd1: x__h79958 = n__read_child__h77802; + case (x__h77549) + 1'd0: x__h79965 = n__read_child__h77730; + 1'd1: x__h79965 = n__read_child__h77809; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77542 or + always@(x__h77549 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7542_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7549_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77542 or + always@(x__h77549 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__159_THEN_propDs_ETC___d1169 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__197_THEN_propDs_ETC___d1207) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7549_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__159_THEN_propDs_ETC___d1169 : 2'd0; 1'd1: - CASE_x7542_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7549_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__197_THEN_propDs_ETC___d1207 : 2'd0; endcase end - always@(x__h77542 or + always@(x__h77549 or NOT_propDstData_1_0_dummy2_1_read__335_346_OR__ETC___d1347 or NOT_propDstData_1_1_dummy2_1_read__337_348_OR__ETC___d1349) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x7549_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__335_346_OR__ETC___d1347; 1'd1: - CASE_x7542_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x7549_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__337_348_OR__ETC___d1349; endcase end - always@(x__h77542 or n__read_addr__h77720 or n__read_addr__h77799) + always@(x__h77549 or n__read_addr__h77727 or n__read_addr__h77806) begin - case (x__h77542) + case (x__h77549) 1'd0: - CASE_x7542_0_n__read_addr7720_1_n__read_addr77_ETC__q26 = - n__read_addr__h77720; + CASE_x7549_0_n__read_addr7727_1_n__read_addr78_ETC__q26 = + n__read_addr__h77727; 1'd1: - CASE_x7542_0_n__read_addr7720_1_n__read_addr77_ETC__q26 = - n__read_addr__h77799; + CASE_x7549_0_n__read_addr7727_1_n__read_addr78_ETC__q26 = + n__read_addr__h77806; endcase end @@ -6772,17 +6772,17 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__044_045_OR_NOT_enq_ETC___d1060 && - x__h58657 && + x__h58664 && NOT_propDstIdx_1_dummy2_1_read__036_037_OR_IF__ETC___d1136) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__044_045_OR_NOT_enq_ETC___d1060 && - x__h58657 && + x__h58664 && NOT_propDstIdx_1_dummy2_1_read__036_037_OR_IF__ETC___d1136) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__044_045_OR_NOT_enq_ETC___d1060 && - x__h58657 && + x__h58664 && NOT_propDstIdx_1_dummy2_1_read__036_037_OR_IF__ETC___d1136) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) @@ -6802,17 +6802,17 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__318_319_OR_NOT_e_ETC___d1334 && - x__h77542 && + x__h77549 && NOT_propDstIdx_1_1_dummy2_1_read__305_306_OR_I_ETC___d1438) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__318_319_OR_NOT_e_ETC___d1334 && - x__h77542 && + x__h77549 && NOT_propDstIdx_1_1_dummy2_1_read__305_306_OR_I_ETC___d1438) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__318_319_OR_NOT_e_ETC___d1334 && - x__h77542 && + x__h77549 && NOT_propDstIdx_1_1_dummy2_1_read__305_306_OR_I_ETC___d1438) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) @@ -6851,7 +6851,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h140337); + $display("FAIL %0d", failed_testnum__h140344); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -6923,69 +6923,84 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4290 = $stime; + v__h4297 = $stime; #0; end - v__h4284 = v__h4290 / 32'd10; + v__h4291 = v__h4297 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h4284); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", + v__h4291); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 && mmio_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 && !mmio_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) @@ -7024,15 +7039,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4554 = $stime; + v__h4561 = $stime; #0; end - v__h4548 = v__h4554 / 32'd10; + v__h4555 = v__h4561 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4548); + v__h4555); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7201,14 +7216,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6593 = $stime; + v__h6600 = $stime; #0; end - v__h6587 = v__h6593 / 32'd10; + v__h6594 = v__h6600 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6587); + $display("%0d: ERROR: CreditCounter: overflow", v__h6594); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -7634,14 +7649,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6894 = $stime; + v__h6901 = $stime; #0; end - v__h6888 = v__h6894 / 32'd10; + v__h6895 = v__h6901 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6888); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6895); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7678,15 +7693,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7387 = $stime; + v__h7394 = $stime; #0; end - v__h7381 = v__h7387 / 32'd10; + v__h7388 = v__h7394 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7381); + v__h7388); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -7726,14 +7741,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7550 = $stime; + v__h7557 = $stime; #0; end - v__h7544 = v__h7550 / 32'd10; + v__h7551 = v__h7557 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7544); + v__h7551); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -7953,37 +7968,37 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h40492 != 64'd0) + x__h40499 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h40492 != 64'd0) + x__h40499 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 856, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h40492 != 64'd0) + x__h40499 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38399 != 64'd0) + x__h38406 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38399 != 64'd0) + x__h38406 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 848, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38399 != 64'd0) + x__h38406 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -8007,15 +8022,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) begin - v__h112132 = $stime; + v__h112139 = $stime; #0; end - v__h112126 = v__h112132 / 32'd10; + v__h112133 = v__h112139 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h112126, + v__h112133, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -8075,15 +8090,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h112299 = $stime; + v__h112306 = $stime; #0; end - v__h112293 = v__h112299 / 32'd10; + v__h112300 = v__h112306 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h112293); + v__h112300); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -8264,16 +8279,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h114402 = $stime; + v__h114409 = $stime; #0; end - v__h114396 = v__h114402 / 32'd10; + v__h114403 = v__h114409 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h114396); + v__h114403); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -9471,14 +9486,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h131748 = $stime; + v__h131755 = $stime; #0; end - v__h131742 = v__h131748 / 32'd10; + v__h131749 = v__h131755 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h131742); + $display("%0d: ERROR: CreditCounter: overflow", v__h131749); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -9502,7 +9517,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) - $write("'h%h", mem_req_wr_addr_awaddr__h125657); + $write("'h%h", mem_req_wr_addr_awaddr__h125664); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) @@ -9598,7 +9613,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) - $write("'h%h", data64__h125572); + $write("'h%h", data64__h125579); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) @@ -9606,7 +9621,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) - $write("'h%h", strb8__h125573); + $write("'h%h", strb8__h125580); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) @@ -9632,16 +9647,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h111513 = $stime; + v__h111520 = $stime; #0; end - v__h111507 = v__h111513 / 32'd10; + v__h111514 = v__h111520 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h111507, + v__h111514, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -9729,7 +9744,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) - $write("'h%h", mem_req_rd_addr_araddr__h111733); + $write("'h%h", mem_req_rd_addr_araddr__h111740); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) @@ -9810,15 +9825,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) begin - v__h138443 = $stime; + v__h138450 = $stime; #0; end - v__h138437 = v__h138443 / 32'd10; + v__h138444 = v__h138450 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__616_U_ETC___d1633) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h138437, + v__h138444, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -9856,15 +9871,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h138951 = $stime; + v__h138958 = $stime; #0; end - v__h138945 = v__h138951 / 32'd10; + v__h138952 = v__h138958 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h138945); + v__h138952); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Map.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Map.v index c88e21c..a6953b6 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Map.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Map.v @@ -267,13 +267,13 @@ module mkSoC_Map(CLK, // value method m_is_mem_addr assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || m_is_mem_addr_addr >= 64'h0000000080000000 && m_is_mem_addr_addr < 64'h0000000090000000 ; // value method m_is_IO_addr assign m_is_IO_addr = + m_is_IO_addr_addr >= 64'h0000000000001000 && + m_is_IO_addr_addr < 64'd8192 || m_is_IO_addr_addr >= 64'h0000000002000000 && m_is_IO_addr_addr < 64'd33603584 || m_is_IO_addr_addr >= 64'h000000000C000000 && diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v index 65bbb61..e633a5b 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v @@ -680,6 +680,9 @@ module mkSoC_Top(CLK, WILL_FIRE_to_raw_mem_request_get, WILL_FIRE_to_raw_mem_response_put; + // inputs to muxes for submodule ports + wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; + // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h8723; @@ -1351,22 +1354,26 @@ module mkSoC_Top(CLK, assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; // rule RL_rl_reset_start_2 - assign CAN_FIRE_RL_rl_reset_start_2 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - corew$RDY_cpu_reset_server_request_put && - fabric$RDY_reset && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start_2 = CAN_FIRE_RL_rl_reset_start_2 ; + assign CAN_FIRE_RL_rl_reset_start_2 = MUX_rg_state$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_reset_start_2 = MUX_rg_state$write_1__SEL_1 ; // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = + assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ; + assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ; + + // inputs to muxes for submodule ports + assign MUX_rg_state$write_1__SEL_1 = + mem0_controller$RDY_server_reset_request_put && + uart0$RDY_server_reset_request_put && + fabric$RDY_reset && + corew$RDY_cpu_reset_server_request_put && + rg_state == 2'd0 ; + assign MUX_rg_state$write_1__SEL_2 = + mem0_controller$RDY_set_addr_map && mem0_controller$RDY_server_reset_response_get && uart0$RDY_server_reset_response_get && - mem0_controller$RDY_set_addr_map && corew$RDY_cpu_reset_server_response_get && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = CAN_FIRE_RL_rl_reset_complete ; // register rg_state assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_2 ? 2'd1 : 2'd2 ; @@ -1405,7 +1412,7 @@ module mkSoC_Top(CLK, assign boot_rom$slave_wlast = fabric$v_to_slaves_0_wlast ; assign boot_rom$slave_wstrb = fabric$v_to_slaves_0_wstrb ; assign boot_rom$slave_wvalid = fabric$v_to_slaves_0_wvalid ; - assign boot_rom$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; // submodule corew assign corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = @@ -1470,10 +1477,9 @@ module mkSoC_Top(CLK, assign corew$EN_set_verbosity = EN_set_verbosity ; assign corew$EN_set_htif_addrs = EN_set_watch_tohost && set_watch_tohost_watch_tohost ; - assign corew$EN_cpu_reset_server_request_put = - CAN_FIRE_RL_rl_reset_start_2 ; + assign corew$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; assign corew$EN_cpu_reset_server_response_get = - CAN_FIRE_RL_rl_reset_complete ; + MUX_rg_state$write_1__SEL_2 ; // submodule fabric assign fabric$set_verbosity_verbosity = 4'h0 ; @@ -1568,7 +1574,7 @@ module mkSoC_Top(CLK, assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = CAN_FIRE_RL_rl_reset_start_2 ; + assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; assign fabric$EN_set_verbosity = 1'b0 ; // submodule mem0_controller @@ -1611,10 +1617,10 @@ module mkSoC_Top(CLK, assign mem0_controller$slave_wvalid = fabric$v_to_slaves_1_wvalid ; assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; assign mem0_controller$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start_2 ; + MUX_rg_state$write_1__SEL_1 ; assign mem0_controller$EN_server_reset_response_get = - CAN_FIRE_RL_rl_reset_complete ; - assign mem0_controller$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + MUX_rg_state$write_1__SEL_2 ; + assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; assign mem0_controller$EN_to_raw_mem_request_get = EN_to_raw_mem_request_get ; assign mem0_controller$EN_to_raw_mem_response_put = @@ -1659,9 +1665,9 @@ module mkSoC_Top(CLK, assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start_2 ; - assign uart0$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_complete ; - assign uart0$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; + assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; + assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; assign uart0$EN_get_to_console_get = EN_get_to_console_get ; assign uart0$EN_put_from_console_put = EN_put_from_console_put ; diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index c40fc94..7424031 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -478,7 +478,7 @@ module mkFetchStage(FetchStage); // Send ICache request mem_server.request.put(phys_pc); end - BootRom: begin + IODevice: begin // Send MMIO req. Luckily boot rom is also aligned with // cache line size, so all nbSup+1 insts can be fetched // from boot rom. It won't happen that insts fetched from diff --git a/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv b/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv index 7d26817..c4b4884 100644 --- a/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv @@ -30,6 +30,8 @@ import CCTypes::*; import CacheUtils::*; import MMIOAddrs::*; +import SoC_Map :: *; // Bluespec setup + interface MMIOInstToCore; interface FifoDeq#(Tuple2#(Addr, SupWaySel)) instReq; interface FifoEnq#(Vector#(SupSize, Maybe#(Instruction))) instResp; @@ -38,7 +40,7 @@ endinterface typedef enum { MainMem, - BootRom, + IODevice, // BootRom, Flash, ... (Bluespec setup) Fault } InstFetchTarget deriving(Bits, Eq, FShow); @@ -71,10 +73,12 @@ module mkMMIOInst(MMIOInst); // respQ, no affecting other MMIO accesses. Fifo#(1, void) pendQ <- mkCFFifo; + SoC_Map_IFC soc_map <- mkSoC_Map; // Bluespec setup + method InstFetchTarget getFetchTarget(Addr phyPc); let addr = getDataAlignedAddr(phyPc); - if(addr >= bootRomBaseAddr && addr < bootRomBoundAddr) begin - return BootRom; + if (soc_map.m_is_IO_addr (phyPc)) begin + return IODevice; end else if(addr >= mainMemBaseAddr && (addr < mainMemBoundAddr) && addr != toHostAddr && addr != fromHostAddr) begin diff --git a/src_Testbench/SoC/SoC_Map.bsv b/src_Testbench/SoC/SoC_Map.bsv index f254115..e4f1bd2 100644 --- a/src_Testbench/SoC/SoC_Map.bsv +++ b/src_Testbench/SoC/SoC_Map.bsv @@ -209,8 +209,7 @@ module mkSoC_Map (SoC_Map_IFC); // (Caches need this information to cache these addresses.) function Bool fn_is_mem_addr (Fabric_Addr addr); - return ( fn_is_boot_rom_addr (addr) - || fn_is_mem0_controller_addr (addr) + return ( fn_is_mem0_controller_addr (addr) || fn_is_tcm_addr (addr) ); endfunction @@ -221,7 +220,8 @@ module mkSoC_Map (SoC_Map_IFC); // (Caches need this information to avoid cacheing these addresses.) function Bool fn_is_IO_addr (Fabric_Addr addr); - return ( fn_is_near_mem_io_addr (addr) + return ( fn_is_boot_rom_addr (addr) + || fn_is_near_mem_io_addr (addr) || fn_is_plic_addr (addr) || fn_is_uart0_addr (addr) );