diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile index 6316758..11baa09 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile @@ -38,6 +38,7 @@ BSC_COMPILATION_FLAGS += \ -D CheriMasterIDWidth=1 \ -D CheriTransactionIDWidth=5 \ -D CAP128 -D BLUESIM \ + -D PERFORMANCE_MONITORING \ -D MEM64 \ -D RISCV \ -D RVFI_DII \ diff --git a/libs/BlueStuff b/libs/BlueStuff index b9c76d5..29332e8 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit b9c76d57ed363744f1ba3fc0596931c6dbaa04b0 +Subproject commit 29332e87fc3b2e4badf7edd727d29447d52f20ed diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 1c16a97..32ea1f1 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -59,6 +59,10 @@ import TlbTypes::*; import SynthParam::*; import VerificationPacket::*; import Performance::*; +`ifdef PERFORMANCE_MONITORING +import PerformanceMonitor::*; +import SpecialWires::*; +`endif import HasSpecBits::*; import Exec::*; import FetchStage::*; @@ -232,6 +236,13 @@ typedef enum { } Core_Run_State deriving (Bits, Eq, FShow); +`ifdef PERFORMANCE_MONITORING +instance BitVectorable #(EventsCore, SizeOf#(SupCnt), EventsCoreElements) provisos (Bits #(EventsCore, m)); + function Vector#(EventsCoreElements, SupCnt) to_vector(EventsCore e) = + reverse(unpack(pack(e))); +endinstance +`endif + (* synthesize *) module mkCore#(CoreId coreId)(Core); let verbose = False; @@ -258,6 +269,14 @@ module mkCore#(CoreId coreId)(Core); Vector #(SupSize, FIFOF #(Trace_Data2)) v_f_to_TV <- replicateM (mkFIFOF); `endif +`ifdef PERFORMANCE_MONITORING + Array #(Wire #(EventsCore)) aw_events <- mkDWireOR (5, unpack (0)); + Reg #(EventsCore) aw_events_reg <- mkConfigReg(unpack(0)); + rule update_aw_events_reg; + aw_events_reg <= aw_events[0]; + endrule +`endif + // ================================================================ // front end @@ -400,6 +419,11 @@ module mkCore#(CoreId coreId)(Core); `endif ); globalSpecUpdate.incorrectSpec(False, spec_tag, inst_tag); +`ifdef PERFORMANCE_MONITORING + EventsCore events = unpack (0); + events.evt_REDIRECT = 1; + aw_events[1] <= events; +`endif endmethod method correctSpec = globalSpecUpdate.correctSpec[finishAluCorrectSpecPort(i)].put; method doStats = doStatsReg._read; @@ -1075,6 +1099,31 @@ module mkCore#(CoreId coreId)(Core); endrule `endif +`ifdef PERFORMANCE_MONITORING + // ================================================================ + // Performance counters + + rule report_commit_events; + aw_events[2] <= commitStage.events; + endrule + + Vector #(1, Bit #(Report_Width)) null_evt = replicate (0); + Vector #(31, Bit #(Report_Width)) core_evts_vec = to_large_vector (aw_events_reg); + Vector #(16, Bit #(Report_Width)) imem_evts_vec = replicate (0);//to_large_vector (near_mem.imem.events); + Vector #(16, Bit #(Report_Width)) dmem_evts_vec = replicate (0);//to_large_vector (near_mem.dmem.events); + Vector #(32, Bit #(Report_Width)) external_evts_vec = replicate (0);//to_large_vector (w_external_evts); + + let events = append (null_evt, core_evts_vec); + events = append (events, imem_evts_vec); + events = append (events, dmem_evts_vec); + events = append (events, external_evts_vec); + + (* fire_when_enabled, no_implicit_conditions *) + rule rl_send_perf_evts; + csrf.send_performance_events (events); + endrule +`endif + `ifdef INCLUDE_GDB_CONTROL // ================================================================ // DEBUG MODULE INTERFACE diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index 9519ac2..49055a6 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -58,6 +58,10 @@ import ISA_Decls_CHERI::*; import Cur_Cycle :: *; +`ifdef PERFORMANCE_MONITORING +import PerformanceMonitor :: *; +`endif + // ================================================================ // Project imports from Toooba @@ -179,6 +183,10 @@ interface CsrFile; method Action dcsr_cause_write (Bit #(3) dcsr_cause); `endif +`ifdef PERFORMANCE_MONITORING + (* always_ready, always_enabled *) + method Action send_performance_events (Vector #(No_Of_Evts, Bit #(Report_Width)) evts); +`endif endinterface // Fancy Reg functions @@ -233,6 +241,38 @@ function Reg#(t) addWriteSideEffect(Reg#(t) r, Action a); endinterface); endfunction +`ifdef PERFORMANCE_MONITORING +interface PerfCountersVec; + interface Vector#(No_Of_Ctrs, Reg#(Data)) counter_vec; + interface Vector#(No_Of_Ctrs, Reg#(Data)) event_vec; + interface Reg#(Data) inhibit; + method Action send_performance_events (Vector #(No_Of_Evts, Bit#(Report_Width)) evts); +endinterface +(* synthesize *) +module mkPerfCountersToooba (PerfCountersVec); + PerfCounters_IFC #(No_Of_Ctrs, Counter_Width, Report_Width, No_Of_Evts) perf_counters <- mkPerfCounters; + Vector#(No_Of_Ctrs, Reg#(Data)) counters = ?; + for (Bit#(TLog#(No_Of_Ctrs)) i = 0; i < 29; i = i + 1) counters[i] = + interface Reg; + method Action _write(Data x) = perf_counters.write_counter(i,x); + method Data _read = perf_counters.read_counters[i]; + endinterface; + Vector#(No_Of_Ctrs, Reg#(Data)) events = ?; + for (Bit#(TLog#(No_Of_Ctrs)) i = 0; i < 29; i = i + 1) events[i] = + interface Reg; + method Action _write(Data x) = perf_counters.write_ctr_sel(i,truncate(x)); + method Data _read = zeroExtend(perf_counters.read_ctr_sels[i]); + endinterface; + interface counter_vec = counters; + interface event_vec = events; + interface inhibit = interface Reg; + method Action _write(Data x) = perf_counters.write_ctr_inhibit(truncate(x)); + method Data _read = zeroExtend(perf_counters.read_ctr_inhibit); + endinterface; + method send_performance_events = perf_counters.send_performance_events; +endmodule +`endif + function Bool has_csr_permission(CSR csr, Bit#(2) prv, Bool write); Bit#(12) csr_index = pack(csr); return ((prv >= csr_index[9:8]) && (!write || (csr_index[11:10] != 2'b11))); @@ -682,6 +722,16 @@ module mkCsrFile #(Data hartid)(CsrFile); Reg #(Data) rg_dscratch1 <- mkConfigRegU; `endif +`ifdef PERFORMANCE_MONITORING + PerfCountersVec perf_counters <- mkPerfCountersToooba; + + //Reg #(Bit #(2)) rg_ctr_inhib_lsb <- mkReg (0); + //Wire #(Bit #(2)) w_ctr_inhib_lsb <- mkWire; + //Bit #(3) ctr_inhibit_lsb = { rg_ctr_inhib_lsb [1], 0, rg_ctr_inhib_lsb [0] }; + //Word ctr_inhibit = zeroExtend ({ perf_counters.read_ctr_inhibit, ctr_inhibit_lsb }); + //CSR_Addr no_of_ctrs = fromInteger (valueOf (No_Of_Ctrs)); +`endif + `ifdef SECURITY // sanctum machine CSRs @@ -756,6 +806,14 @@ module mkCsrFile #(Data hartid)(CsrFile); // Function for getting a csr given an index function Reg#(Data) get_csr(CSR csr); + Reg#(Data) ret = readOnlyReg(64'b0); +`ifdef PERFORMANCE_MONITORING + let c = csr.addr; + if ((csrAddrMHPMCOUNTER3.addr <= c) && (c <= csrAddrMHPMCOUNTER31.addr)) + ret = perf_counters.counter_vec[c-csrAddrMHPMCOUNTER3.addr]; + if ((csrAddrMHPMEVENT3.addr <= c) && (c <= csrAddrMHPMEVENT31.addr)) + ret = perf_counters.event_vec[c - csrAddrMHPMEVENT3.addr]; +`endif return (case (csr) // User CSRs csrAddrFFLAGS: fflags_csr; @@ -797,6 +855,9 @@ module mkCsrFile #(Data hartid)(CsrFile); csrAddrMIMPID: mimpid_csr; csrAddrMHARTID: mhartid_csr; csrAddrMCCSR: csr_capcause(mccsr_reg); +`ifdef PERFORMANCE_MONITORING + csrAddrMCOUNTERINHIBIT: perf_counters.inhibit; +`endif `ifdef SECURITY csrAddrMEVBASE: mevbase_csr; csrAddrMEVMASK: mevmask_csr; @@ -810,20 +871,19 @@ module mkCsrFile #(Data hartid)(CsrFile); csrAddrMSPEC: mspec_csr; csrAddrTRNG: trng_csr; `endif - - csrAddrTSELECT: rg_tselect; - csrAddrTDATA1: rg_tdata1; - csrAddrTDATA2: rg_tdata2; - csrAddrTDATA3: rg_tdata3; + csrAddrTSELECT: rg_tselect; + csrAddrTDATA1: rg_tdata1; + csrAddrTDATA2: rg_tdata2; + csrAddrTDATA3: rg_tdata3; `ifdef INCLUDE_GDB_CONTROL - csrAddrDCSR: rg_dcsr; // TODO: take NMI into account (cf. Piccolo/Flute) - csrAddrDPC: scrToCsr(rg_dpc); - csrAddrDSCRATCH0: rg_dscratch0; - csrAddrDSCRATCH1: rg_dscratch1; + csrAddrDCSR: rg_dcsr; // TODO: take NMI into account (cf. Piccolo/Flute) + csrAddrDPC: scrToCsr(rg_dpc); + csrAddrDSCRATCH0: rg_dscratch0; + csrAddrDSCRATCH1: rg_dscratch1; `endif - default: readOnlyReg(64'b0); + default: ret; endcase); endfunction @@ -1341,4 +1401,7 @@ module mkCsrFile #(Data hartid)(CsrFile); `endif +`ifdef PERFORMANCE_MONITORING + method send_performance_events = perf_counters.send_performance_events; +`endif endmodule diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index f7b529e..3d003c3 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -43,6 +43,7 @@ import Vector::*; import GetPut::*; import Cntrs::*; import ConfigReg::*; +import DReg::*; import FIFO::*; import FIFOF::*; import Types::*; @@ -161,6 +162,9 @@ interface CommitStage; method Bool is_debug_halted; method Action debug_resume; `endif +`ifdef PERFORMANCE_MONITORING + method EventsCore events; +`endif `ifdef DEBUG_WEDGE (* always_enabled *) method Tuple2#(CapMem, Bit#(32)) debugLastInst; @@ -410,6 +414,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); Count#(Data) flushCacheCnt <- mkCount(0); `endif +`ifdef PERFORMANCE_MONITORING + Reg#(EventsCore) events_reg <- mkDReg(unpack(0)); +`endif + `ifdef RVFI // RVFI trace report. Not an input? FIFO#(Rvfi_Traces) rvfiQ <- mkFIFO; @@ -988,6 +996,13 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); end end `endif +`ifdef PERFORMANCE_MONITORING + EventsCore events = unpack(0); + case(x.iType) + Fence, FenceI, SFence: events.evt_FENCE = 1; + endcase + events_reg <= events; +`endif `ifdef CHECK_DEADLOCK commitInst.send; if(csrf.decodeInfo.prv == 0) begin @@ -1060,7 +1075,6 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); // incr committed inst cnt at the end of rule SupCnt comInstCnt = 0; SupCnt comUserInstCnt = 0; -`ifdef PERF_COUNT // incr some performance counter at the end of rule SupCnt brCnt = 0; SupCnt jmpCnt = 0; @@ -1070,7 +1084,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); SupCnt lrCnt = 0; SupCnt scCnt = 0; SupCnt amoCnt = 0; -`endif + SupCnt shiftCnt = 0; + SupCnt muldivCnt = 0; + SupCnt auipcCnt = 0; + SupCnt fenceCnt = 0; `ifdef RVFI Rvfi_Traces rvfis = replicate(tagged Invalid); @@ -1170,9 +1187,24 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); comUserInstCnt = comUserInstCnt + 1; // user space inst end -`ifdef PERF_COUNT - // performance counter + // performance counters + // Some fields of the original instruction to help with classification. + let inst = x.orig_inst; + Opcode opcode = unpackOpcode(inst[ 6 : 0 ]); + let funct3 = inst[ 14 : 12 ]; + let funct7 = inst[ 31 : 25 ]; + // For "F" and "D" ISA extensions + let funct5 = inst[ 31 : 27 ]; + let fmt = inst[ 26 : 25 ]; + let rs3 = inst[ 31 : 27 ]; + let funct2 = inst[ 26 : 25 ]; + // For "A" ISA extension + Bool aq = unpack(inst[ 26 ]); + Bool rl = unpack(inst[ 25 ]); + // For "xCHERI" ISA extension + let funct5rs2 = inst[ 24 : 20 ]; case(x.iType) + Auipc, Auipcc: auipcCnt = auipcCnt + 1; Br: brCnt = brCnt + 1; J : jmpCnt = jmpCnt + 1; Jr: jrCnt = jrCnt + 1; @@ -1181,8 +1213,14 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); Lr: lrCnt = lrCnt + 1; Sc: scCnt = scCnt + 1; Amo: amoCnt = amoCnt + 1; + Alu: begin + if (((opcode == opcOpImm) || (opcode == opcOpImm32) || (opcode == opcOp)) && ((funct3 == fnSLL) || (funct3 == fnSR))) + shiftCnt = shiftCnt + 1; + if ((opcode == opcOp || opcode == opcOp32) && funct7 == opMULDIV) + muldivCnt = muldivCnt + 1; + end endcase -`endif + if (opcode == opcMiscMem && funct3 == fnFENCE) fenceCnt = fenceCnt + 1; end end end @@ -1235,6 +1273,22 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); end end `endif +`ifdef PERFORMANCE_MONITORING + EventsCore events = unpack(0); + events.evt_BRANCH = brCnt; + events.evt_JAL = jmpCnt; + events.evt_JALR = jrCnt; + events.evt_AUIPC = auipcCnt; // XXX + events.evt_LOAD = ldCnt; + events.evt_STORE = stCnt; + events.evt_LR = lrCnt; + events.evt_SC = scCnt; + events.evt_AMO = amoCnt; + events.evt_SERIAL_SHIFT = shiftCnt; + events.evt_INT_MUL_DIV_REM = muldivCnt; + events.evt_FENCE = fenceCnt; + events_reg <= events; +`endif `ifdef RVFI rvfiQ.enq(rvfis); traceCnt <= traceCnt + zeroExtend(whichTrace); @@ -1309,6 +1363,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); endmethod `endif +`ifdef PERFORMANCE_MONITORING + method events = events_reg; +`endif + `ifdef DEBUG_WEDGE method Tuple2#(CapMem, Bit#(32)) debugLastInst; return tuple2(rg_last_pcc, rg_last_inst); diff --git a/src_Core/RISCY_OOO/procs/lib/CSRs.bsvi b/src_Core/RISCY_OOO/procs/lib/CSRs.bsvi index a7b029b..96970e3 100644 --- a/src_Core/RISCY_OOO/procs/lib/CSRs.bsvi +++ b/src_Core/RISCY_OOO/procs/lib/CSRs.bsvi @@ -37,6 +37,101 @@ `CSR(MIP, 12'h344) `CSR(MCYCLE, 12'hb00) `CSR(MINSTRET, 12'hb02) + +`ifdef PERFORMANCE_MONITORING +`CSR(HPMCOUNTER3, 12'hc03) +`CSR(HPMCOUNTER4, 12'hc04) +`CSR(HPMCOUNTER5, 12'hc05) +`CSR(HPMCOUNTER6, 12'hc06) +`CSR(HPMCOUNTER7, 12'hc07) +`CSR(HPMCOUNTER8, 12'hc08) +`CSR(HPMCOUNTER9, 12'hc09) +`CSR(HPMCOUNTER10, 12'hc0a) +`CSR(HPMCOUNTER11, 12'hc0b) +`CSR(HPMCOUNTER12, 12'hc0c) +`CSR(HPMCOUNTER13, 12'hc0d) +`CSR(HPMCOUNTER14, 12'hc0e) +`CSR(HPMCOUNTER15, 12'hc0f) +`CSR(HPMCOUNTER16, 12'hc10) +`CSR(HPMCOUNTER17, 12'hc11) +`CSR(HPMCOUNTER18, 12'hc12) +`CSR(HPMCOUNTER19, 12'hc13) +`CSR(HPMCOUNTER20, 12'hc14) +`CSR(HPMCOUNTER21, 12'hc15) +`CSR(HPMCOUNTER22, 12'hc16) +`CSR(HPMCOUNTER23, 12'hc17) +`CSR(HPMCOUNTER24, 12'hc18) +`CSR(HPMCOUNTER25, 12'hc19) +`CSR(HPMCOUNTER26, 12'hc1a) +`CSR(HPMCOUNTER27, 12'hc1b) +`CSR(HPMCOUNTER28, 12'hc1c) +`CSR(HPMCOUNTER29, 12'hc1d) +`CSR(HPMCOUNTER30, 12'hc1e) +`CSR(HPMCOUNTER31, 12'hc1f) + +`CSR(MHPMCOUNTER3, 12'hb03) +`CSR(MHPMCOUNTER4, 12'hb04) +`CSR(MHPMCOUNTER5, 12'hb05) +`CSR(MHPMCOUNTER6, 12'hb06) +`CSR(MHPMCOUNTER7, 12'hb07) +`CSR(MHPMCOUNTER8, 12'hb08) +`CSR(MHPMCOUNTER9, 12'hb09) +`CSR(MHPMCOUNTER10, 12'hb0a) +`CSR(MHPMCOUNTER11, 12'hb0b) +`CSR(MHPMCOUNTER12, 12'hb0c) +`CSR(MHPMCOUNTER13, 12'hb0d) +`CSR(MHPMCOUNTER14, 12'hb0e) +`CSR(MHPMCOUNTER15, 12'hb0f) +`CSR(MHPMCOUNTER16, 12'hb10) +`CSR(MHPMCOUNTER17, 12'hb11) +`CSR(MHPMCOUNTER18, 12'hb12) +`CSR(MHPMCOUNTER19, 12'hb13) +`CSR(MHPMCOUNTER20, 12'hb14) +`CSR(MHPMCOUNTER21, 12'hb15) +`CSR(MHPMCOUNTER22, 12'hb16) +`CSR(MHPMCOUNTER23, 12'hb17) +`CSR(MHPMCOUNTER24, 12'hb18) +`CSR(MHPMCOUNTER25, 12'hb19) +`CSR(MHPMCOUNTER26, 12'hb1a) +`CSR(MHPMCOUNTER27, 12'hb1b) +`CSR(MHPMCOUNTER28, 12'hb1c) +`CSR(MHPMCOUNTER29, 12'hb1d) +`CSR(MHPMCOUNTER30, 12'hb1e) +`CSR(MHPMCOUNTER31, 12'hb1f) + +`CSR(MCOUNTERINHIBIT, 12'h320) // Machine Counter-Inhibit + +`CSR(MHPMEVENT3, 12'h323) +`CSR(MHPMEVENT4, 12'h324) +`CSR(MHPMEVENT5, 12'h325) +`CSR(MHPMEVENT6, 12'h326) +`CSR(MHPMEVENT7, 12'h327) +`CSR(MHPMEVENT8, 12'h328) +`CSR(MHPMEVENT9, 12'h329) +`CSR(MHPMEVENT10, 12'h32a) +`CSR(MHPMEVENT11, 12'h32b) +`CSR(MHPMEVENT12, 12'h32c) +`CSR(MHPMEVENT13, 12'h32d) +`CSR(MHPMEVENT14, 12'h32e) +`CSR(MHPMEVENT15, 12'h32f) +`CSR(MHPMEVENT16, 12'h330) +`CSR(MHPMEVENT17, 12'h331) +`CSR(MHPMEVENT18, 12'h332) +`CSR(MHPMEVENT19, 12'h333) +`CSR(MHPMEVENT20, 12'h334) +`CSR(MHPMEVENT21, 12'h335) +`CSR(MHPMEVENT22, 12'h336) +`CSR(MHPMEVENT23, 12'h337) +`CSR(MHPMEVENT24, 12'h338) +`CSR(MHPMEVENT25, 12'h339) +`CSR(MHPMEVENT26, 12'h33a) +`CSR(MHPMEVENT27, 12'h33b) +`CSR(MHPMEVENT28, 12'h33c) +`CSR(MHPMEVENT29, 12'h33d) +`CSR(MHPMEVENT30, 12'h33e) +`CSR(MHPMEVENT31, 12'h33f) +`endif // PERFORMANCE_MONITORING + `CSR(MVENDORID, 12'hf11) `CSR(MARCHID, 12'hf12) `CSR(MIMPID, 12'hf13) diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv index 85c6235..afca918 100755 --- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv @@ -1040,3 +1040,43 @@ function Fmt showInst(Instruction inst); endfunction function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc)); + +`ifdef PERFORMANCE_MONITORING +typedef 96 No_Of_Evts; +typedef 8 Report_Width; +typedef 64 Counter_Width; +typedef 29 No_Of_Ctrs; + +typedef struct { + SupCnt evt_REDIRECT; + SupCnt evt_TLB_EXC; // TODO: Misleading name + SupCnt evt_BRANCH; + SupCnt evt_JAL; + SupCnt evt_JALR; + SupCnt evt_AUIPC; + SupCnt evt_LOAD; + SupCnt evt_STORE; + SupCnt evt_LR; + SupCnt evt_SC; + SupCnt evt_AMO; + SupCnt evt_SERIAL_SHIFT; + SupCnt evt_INT_MUL_DIV_REM; + SupCnt evt_FP; + SupCnt evt_SC_SUCCESS; + SupCnt evt_LOAD_WAIT; + SupCnt evt_STORE_WAIT; + SupCnt evt_FENCE; + SupCnt evt_F_BUSY_NO_CONSUME; + SupCnt evt_D_BUSY_NO_CONSUME; + SupCnt evt_1_BUSY_NO_CONSUME; + SupCnt evt_2_BUSY_NO_CONSUME; + SupCnt evt_3_BUSY_NO_CONSUME; + SupCnt evt_IMPRECISE_SETBOUND; + SupCnt evt_UNREPRESENTABLE_CAP; + SupCnt evt_MEM_CAP_LOAD; + SupCnt evt_MEM_CAP_STORE; + SupCnt evt_MEM_CAP_LOAD_TAG_SET; + SupCnt evt_MEM_CAP_STORE_TAG_SET; +} EventsCore deriving (Bits, FShow); +typedef TDiv#(SizeOf#(EventsCore),SizeOf#(SupCnt)) EventsCoreElements; +`endif