From 3953581b50a0102588f893df83d4eb2c5245b692 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Sat, 22 Apr 2023 10:00:15 +0100 Subject: [PATCH 1/3] Fix stride prefetcher mis-commit --- src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index b258b87..61153ec 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -1473,8 +1473,6 @@ provisos( Int#(16) strideToUse = signExtend(se.stride); if (abs(strideToUse) < cLineSize) begin strideToUse = (strideToUse < 0) ? -cLineSize : cLineSize; - strideToUse = (strideToUse < 0) ? -cLineSize : cLineSize; - strideToUse = (strideToUse < 0) ? -cLineSize : cLineSize; end Bit#(16) jumpDist = pack(strideToUse) * zeroExtend(cLinesPrefetched+1); let reqAddr = addr + signExtend(jumpDist); From 88fee870d09d9519aa82a6b3b55ec115654facf3 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Sat, 22 Apr 2023 10:00:50 +0100 Subject: [PATCH 2/3] Minor update to single-window-target --- .../RISCY_OOO/coherence/src/Prefetcher.bsv | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index 61153ec..9d7d652 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -739,17 +739,12 @@ module mkBRAMSingleWindowTargetPrefetcher(Prefetcher) provisos Reg#(LineAddr) nextToAsk <- mkReg(0); Reg#(LineAddr) lastChildRequest <- mkReg(0); - TargetTableBRAM#(1024, 128) targetTable <- mkTargetTableBRAM; - FIFOF#(LineAddr) targetTableReadResp <- mkBypassFIFOF; + TargetTableBRAM#(8192, 2048) targetTable <- mkTargetTableBRAM; + Fifo#(1, LineAddr) targetTableReadResp <- mkOverflowBypassFifo; - Reg#(Vector#(numLastRequests, Bit#(32))) lastTargetRequests <- mkReg(replicate(0)); + Reg#(Vector#(numLastRequests, Bit#(16))) lastTargetRequests <- mkReg(replicate(0)); rule sendReadReq; - if (!elem(hash(lastChildRequest), lastTargetRequests)) begin - targetTable.readReq(lastChildRequest); - $display("%t Prefetcher sending target read request for %h", $time, lastChildRequest); - lastTargetRequests <= shiftInAt0(lastTargetRequests, hash(lastChildRequest)); - end endrule rule getReadResp; @@ -782,6 +777,13 @@ module mkBRAMSingleWindowTargetPrefetcher(Prefetcher) provisos $display("%t Prefetcher add target entry from addr %h to addr %h", $time, Addr'{lastChildRequest, '0}, addr); targetTable.writeReq(lastChildRequest, cl); end + + // Send target request if not in last 16 hits. + if (!elem(hash(cl), lastTargetRequests)) begin + targetTable.readReq(cl); + $display("%t Prefetcher sending target read request for %h", $time, cl); + lastTargetRequests <= shiftInAt0(lastTargetRequests, hash(cl)); + end lastChildRequest <= cl; endmethod From 73e710d875bd00ad73a9f6c457b760647b15f3ce Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Sat, 22 Apr 2023 10:04:05 +0100 Subject: [PATCH 3/3] Config for L1I 1window-target-1 --- builds/Resources/Include_RISCY_Config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk index 888b825..2fe6d75 100644 --- a/builds/Resources/Include_RISCY_Config.mk +++ b/builds/Resources/Include_RISCY_Config.mk @@ -46,7 +46,7 @@ SIM_LLC_ARBITER_LAT ?= CHECK_DEADLOCK ?= true RENAME_DEBUG ?= false INSTR_PREFETCHER_LOCATION ?= L1 -INSTR_PREFETCHER_TYPE ?= MULTI_WINDOW_TARGET +INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW_TARGET DATA_PREFETCHER_LOCATION ?= NONE DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT_2