diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk
index d48b077..5d45fa8 100644
--- a/builds/Resources/Include_Common.mk
+++ b/builds/Resources/Include_Common.mk
@@ -55,7 +55,7 @@ TOPMODULE ?= mkTop_HW_Side
 
 BSC_COMPILATION_FLAGS += \
 	-keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \
-	-suppress-warnings G0020    \
+	-suppress-warnings G0020 -steps-max-intervals 10000000   \
 	+RTS -K128M -RTS  -show-range-conflict
 
 # ================================================================
@@ -63,6 +63,11 @@ BSC_COMPILATION_FLAGS += \
 
 EXAMPLE ?= PLEASE_DEFINE_EXAMPLE_PATH_TO_ELF
 
+# ================================================================
+# Rules to compile .bo files.  .depends.mk is the dependency graph extracted from an analysis of mkTop_HW_Side
+include $(REPO)/builds/Resources/.depends.mk
+
+
 .PHONY: run_example
 run_example:
 	make -C  $(TESTS_DIR)/elf_to_hex
@@ -95,7 +100,7 @@ isa_tests:
 
 .PHONY: clean
 clean:
-	rm -r -f  *~  Makefile_*  symbol_table.txt  build_dir  obj_dir
+	rm -r -f  *~  Makefile_*  symbol_table.txt  build_dir/*  obj_dir Verilog_RTL/*
 
 .PHONY: full_clean
 full_clean: clean
diff --git a/builds/Resources/Include_verilator.mk b/builds/Resources/Include_verilator.mk
index f26b780..4b41a22 100644
--- a/builds/Resources/Include_verilator.mk
+++ b/builds/Resources/Include_verilator.mk
@@ -15,10 +15,16 @@ build_dir:
 Verilog_RTL:
 	mkdir -p $@
 
+%.bo:
+	echo $@
+	bsc -verilog -elab -bdir build_dir -vdir Verilog_RTL $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
+
 .PHONY: compile
-compile:  build_dir  Verilog_RTL
+compile: Verilog_RTL/mkTop_HW_Side.v
+#Verilog_RTL/mkTop_HW_Side.v:  build_dir Verilog_RTL /tmp/src_dir $(VERILOG_SUB_MODULES)
+Verilog_RTL/mkTop_HW_Side.v: $(TOPFILE) build_dir/Top_HW_Side.bo build_dir Verilog_RTL
 	@echo  "INFO: Verilog RTL generation ..."
-	bsc -u -elab -verilog  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS)  -p $(BSC_PATH)  $(TOPFILE)
+	bsc -u -verilog  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
 	@echo  "INFO: Verilog RTL generation finished"
 
 # ================================================================
@@ -45,7 +51,7 @@ VTOP                = V$(TOPMODULE)_edited
 VERILATOR_RESOURCES = $(REPO)/builds/Resources/Verilator_resources
 
 .PHONY: simulator
-simulator:
+simulator: Verilog_RTL/mkTop_HW_Side.v
 	@echo "INFO: Verilating Verilog files (in newly created obj_dir)"
 	sed  -f $(VERILATOR_RESOURCES)/sed_script.txt  Verilog_RTL/$(TOPMODULE).v > tmp1.v
 	cat  $(VERILATOR_RESOURCES)/verilator_config.vlt \
diff --git a/builds/Resources/genDependencies.tcl b/builds/Resources/genDependencies.tcl
new file mode 100755
index 0000000..d59a5d7
--- /dev/null
+++ b/builds/Resources/genDependencies.tcl
@@ -0,0 +1,44 @@
+#! /usr/bin/env bluetcl
+
+namespace import ::Bluetcl::*
+
+flags set -p "../RV64ACDFIMSU_Toooba_verilator:../../libs/BlueStuff:../../libs/BlueStuff/AXI:../../libs/BlueStuff/BlueUtils:../../libs/BlueStuff/BlueBasics:../../src_Core/RISCY_OOO/procs/RV64G_OOO:../../src_Core/RISCY_OOO/procs/lib:../../src_Core/RISCY_OOO/coherence/src:../../src_Core/RISCY_OOO/fpgautils/lib:../../src_Core/RISCY_OOO/connectal/bsv:../../src_Core/RISCY_OOO/connectal/tests/spi:../../src_Core/RISCY_OOO/connectal/lib/bsv:../../src_Core/RISCY_OOO/../../src_Verifier:../../src_Core/RISCY_OOO/../../src_Verifier/BSV-RVFI-DII:../../src_Core/RISCY_OOO/../CHERI:../../src_Core/RISCY_OOO/../../libs/cheri-cap-lib:../../src_Core/CPU:../../src_Core/ISA:../../src_Core/Core:../../src_Core/PLIC:../../src_Core/Debug_Module:../../src_Core/BSV_Additional_Libs:../../src_Testbench/Top:../../src_Testbench/SoC:../../libs/TagController/TagController:../../libs/TagController/TagController/CacheCore:+"
+
+flags set -D RISCV
+flags set -D RV64
+flags set -D ISA_PRIV_M
+flags set -D ISA_PRIV_U
+flags set -D ISA_PRIV_S
+flags set -D SV39
+flags set -D ISA_I
+flags set -D ISA_M
+flags set -D ISA_A
+flags set -D ISA_F
+flags set -D ISA_D
+flags set -D ISA_FD_DIV
+flags set -D ISA_C
+flags set -D SHIFT_BARREL
+flags set -D MULT_SYNTH
+flags set -D Near_Mem_Caches
+flags set -D FABRIC64
+flags set -D CAP128
+flags set -D MEM64
+#flags set -D RVFI_DII
+#flags set -D RVFI
+flags set -D BSIM
+flags set -D CORE_SMALL
+flags set -D NUM_CORES=1
+flags set -D CACHE_SMALL
+flags set -D XILINX_FP_FMA_LATENCY=3
+flags set -D XILINX_INT_MUL_LATENCY=2
+flags set -D USE_BSV_BRAM_SYNC_FIFO
+
+flags set -bdir build_dir
+
+set topfile [lindex $argv 0]
+
+foreach i [depend make $topfile] {
+  set tgt [lindex $i 0]
+  set deps [join [lindex $i 1]]
+  puts [append tgt ": " $deps]
+}