From f800cdeb779466de3837b91a1575156f43b2df4a Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Sat, 30 Jan 2021 15:21:38 +0000 Subject: [PATCH] Prevent spurious warnings --- builds/Resources/Include_Common.mk | 1 + src_SSITH_P3/Makefile | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index f6f7b3d..769b293 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -56,6 +56,7 @@ TOPMODULE ?= mkTop_HW_Side BSC_COMPILATION_FLAGS += \ -keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \ -suppress-warnings G0020 -steps-max-intervals 10000000 \ + -steps-warn-interval 1000000 \ +RTS -K128M -RTS -show-range-conflict # ================================================================ diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile index f2be041..6c0f767 100644 --- a/src_SSITH_P3/Makefile +++ b/src_SSITH_P3/Makefile @@ -92,7 +92,8 @@ BSC_COMPILATION_FLAGS += \ -suppress-warnings G0020 \ +RTS -K128M -RTS -show-range-conflict \ -unspecified-to X -opt-undetermined-vals \ - -steps-max-intervals 10000000 + -steps-max-intervals 10000000 \ + -steps-warn-interval 1000000 # ================================================================ # Generate Verilog RTL from BSV sources (needs Bluespec 'bsc' compiler)