From f83d7b15544f8e148ef5dceeec0334e3452f9587 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Thu, 24 Jun 2021 08:35:21 +0100 Subject: [PATCH] Added missing ifdefs --- src_Core/CPU/Core.bsv | 7 +++++++ .../RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 9 +++------ src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 12 +++++++++++- 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 914d7dc..ced77b7 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -305,6 +305,8 @@ module mkCore#(CoreId coreId)(Core); EpochManager epochManager <- mkEpochManager; SpecTagManager specTagManager <- mkSpecTagManager; ReorderBufferSynth rob <- mkReorderBufferSynth; + +`ifdef PERFORMANCE_MONITORING Vector#(SupSize, Bag#(16, CapMem, CapMem)) bags; for(Integer i = 0; i < valueof(SupSize); i=i+1) begin bags[i] <- mkSmallBag; @@ -313,6 +315,7 @@ module mkCore#(CoreId coreId)(Core); for(Integer i = 0; i < valueof(SupSize); i=i+1) begin returnBags[i] <- mkSmallBag; end +`endif // We have two scoreboards: one conservative and other aggressive // - Aggressive sb is checked at rename stage, so inst after rename may be issued early @@ -433,6 +436,7 @@ module mkCore#(CoreId coreId)(Core); endmethod method correctSpec = globalSpecUpdate.correctSpec[finishAluCorrectSpecPort(i)].put; method doStats = doStatsReg._read; +`ifdef PERFORMANCE_MONITORING method Bool checkTarget(CapMem ppc); Bool ret = False; for(Integer j = 0; j < valueof(SupSize); j=j+1) begin @@ -447,6 +451,7 @@ module mkCore#(CoreId coreId)(Core); end return ret; endmethod +`endif endinterface); aluExe[i] <- mkAluExePipeline(aluExeInput); // truly call fetch method to train branch predictor @@ -699,6 +704,7 @@ module mkCore#(CoreId coreId)(Core); `endif endmethod +`ifdef PERFORMANCE_MONITORING method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets); for(Integer i = 0; i < valueof(SupSize); i=i+1) begin if(targets[i] matches tagged Valid .tar) begin @@ -714,6 +720,7 @@ module mkCore#(CoreId coreId)(Core); end end endmethod +`endif `ifdef INCLUDE_TANDEM_VERIF interface v_to_TV = map (toPut, v_f_to_TV); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index e164744..c9003d7 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -196,10 +196,12 @@ interface AluExeInput; // performance method Bool doStats; +`ifdef PERFORMANCE_MONITORING // check previous branch targets method Bool checkTarget(CapMem ppc); // check (previous) return targets method Bool checkReturnTarget(CapMem ppc); +`endif endinterface interface AluExePipeline; @@ -296,9 +298,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); let ppc = inIfc.rob_getPredPC(x.tag); let orig_inst = inIfc.rob_getOrig_Inst (x.tag); - // TODO: split into Br, jumps, and rets `ifdef PERFORMANCE_MONITORING - let ppc_addr = getAddr(ppc); let pc_addr = getAddr(pc); EventsTransExe events = unpack(0); @@ -323,10 +323,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); events.evt_WILD_JUMP = 1; events_reg <= events; end - end - - - + end `endif // go to next stage diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index aebd55c..138695f 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -132,10 +132,12 @@ interface CommitInput; // deadlock check method Bool checkDeadlock; +`ifdef PERFORMANCE_MONITORING // update branch targets method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets); // update return targets method Action updateReturnTargets(Vector#(SupSize, Maybe#(CapMem)) returnTargets); +`endif `ifdef INCLUDE_TANDEM_VERIF interface Vector #(SupSize, Put #(Trace_Data2)) v_to_TV; @@ -1093,14 +1095,18 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); Data po_mstatus = ?; `endif +`ifdef PERFORMANCE_MONITORING // update targets vector Vector#(SupSize, Maybe#(CapMem)) targets; // update return targets vector Vector#(SupSize, Maybe#(CapMem)) returnTargets; +`endif // compute what actions to take for(Integer i = 0; i < valueof(SupSize); i = i+1) begin +`ifdef PERFORMANCE_MONITORING Maybe#(CapMem) tar = tagged Invalid; Maybe#(CapMem) retTar = tagged Invalid; +`endif if(!stop && rob.deqPort[i].canDeq) begin let x = rob.deqPort[i].deq_data; let inst_tag = rob.deqPort[i].getDeqInstTag; @@ -1144,6 +1150,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); // inst can be committed, deq it rob.deqPort[i].deq; +`ifdef PERFORMANCE_MONITORING // return address stack link reg is x1 or x5 function Bool linkedR(Maybe#(ArchRIndx) register); Bool res = False; @@ -1172,6 +1179,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); tar = tagged Valid x.ppc_vaddr_csrData.PPC; $display("BRANCH target added: pc = ", fshow(x.pc), " ppc = ", fshow(tar)); end*/ +`endif // every inst here should have been renamed, commit renaming regRenamingTable.commit[i].commit; @@ -1248,8 +1256,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); if (opcode == opcMiscMem && funct3 == fnFENCE) fenceCnt = fenceCnt + 1; end end +`ifdef PERFORMANCE_MONITORING targets[i] = tar; returnTargets[i] = retTar; +`endif end rg_serial_num <= rg_serial_num + instret; @@ -1312,10 +1322,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); events.evt_FP = fpuCnt; events.evt_FENCE = fenceCnt; events_reg <= events; -`endif inIfc.updateTargets(targets); inIfc.updateReturnTargets(returnTargets); +`endif `ifdef RVFI rvfiQ.enq(rvfis);