From f86ea0203d9e1f96e787efdabe661aac61568c24 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 4 Apr 2024 14:09:16 +0100 Subject: [PATCH] Potential workaround for issue with vcu118 memory bus error. Just use the same ID for all outstanding requests such that all requests are in-order. Previously we were working fine with requests serialised; requests are now fully pipelined and out-of-order. This change should roll back to in-order, but still pipelined. This only affects the top-level used in the GFE (vcu118). This design is working on the DE10 setup, so the issue is not believed fundamental with CoreW. --- src_SSITH_P3/src_BSV/P3_Core.bsv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index dc029bf..5517aae 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -340,9 +340,13 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ `endif + // Work around issue that is not understood with multiple outstanding + // requests in VCU118 GFE system. + let master0_inOrder <- mkAXI4SingleIDMaster(master_0_delay.master); + // ================================================================ // INTERFACE - let master0_sig <- toAXI4_Master_Sig (master_0_delay.master); + let master0_sig <- toAXI4_Master_Sig (master0_inOrder); let master1_sig <- toAXI4_Master_Sig (master_1_delay.master); // ---------------------------------------------------------------- // Core CPU interfaces