Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below)
PLIC: updated to latest version from Piccolo/Flute.
MMIO_AXI4_Adapter: added workaround for Xilinx IP problem on 64-bit
AXI4 fabrics. Writes that specify 8-byte size, but only write in
upper or lower word using strobes, are converted into 4-byte size.
Core.bsv: added a notification to the Debug Module re. CPU halt.
This commit is contained in:
rsnikhil
@@ -1216,7 +1216,8 @@ module mkCore#(CoreId coreId)(Core);
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&& (f_run_halt_reqs.first == False));
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f_run_halt_reqs.deq;
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// Ignore this.
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// Notify debugger that we're halted, but otherwise ignore the request
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f_run_halt_rsps.enq (False);
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_halt_req_already_halted", cur_cycle);
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@@ -125,6 +125,21 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
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wlast: True,
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wuser: fabric_default_user};
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`ifdef FABRIC64
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// Work-around for a misbehavior on Xilinx UART and its
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// Xilinx AXI4 adapter. On 64-bit fabrics, for a write where
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// axsize says '8 bytes' but wstrb is for <= 4 bytes, the
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// adapter converts it two 32-bit writes, one of which has
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// wstrb=4'b0000. The Xilinx UART, in turn ignores wstrb and
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// therefore performs a spurious write. This workaround
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// changes axsize for such writes to '4 bytes', avoiding this
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// problem.
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if (strb [7:4] == 0 || strb [3:0] == 0) begin
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mem_req_wr_addr.awsize = axsize_4;
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end
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`endif
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master_xactor.i_wr_addr.enq (mem_req_wr_addr);
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master_xactor.i_wr_data.enq (mem_req_wr_data);
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@@ -1,4 +1,4 @@
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// Copyright (c) 2019 Bluespec, Inc. All Rights Reserved
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// Copyright (c) 2019-2020 Bluespec, Inc. All Rights Reserved
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package PLIC;
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@@ -102,6 +102,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
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Add #(_any_1, TLog #(t_n_targets), T_wd_target_id),
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Log #(TAdd #(t_max_priority, 1), t_wd_priority));
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// 0 = quiet; 1 = show PLIC transactions; 2 = also show AXI4 transactions
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0);
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// Source_Ids and Priorities are read and written over the memory interface
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@@ -551,12 +552,12 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
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return interface PLIC_Source_IFC;
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method Action m_interrupt_req (Bool set_not_clear);
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action
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if (! vrg_source_busy [source_id]) begin
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vrg_source_ip [source_id] <= set_not_clear;
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if (! vrg_source_busy [source_id + 1]) begin
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vrg_source_ip [source_id + 1] <= set_not_clear;
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if ((cfg_verbosity > 0) && (vrg_source_ip [source_id] != set_not_clear))
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$display ("%0d: Changing vrg_source_ip [%0d] to %0d",
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cur_cycle, source_id, pack (set_not_clear));
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if ((cfg_verbosity > 0) && (vrg_source_ip [source_id + 1] != set_not_clear))
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$display ("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
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cur_cycle, source_id + 1, pack (set_not_clear));
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end
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endaction
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endmethod
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@@ -1,4 +1,29 @@
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The (relative) Memory map for this PLIC follows the one given in:
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// Copyright (c) 2019-2020 Bluespec, Inc. All Rights Reserved
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>================================================================
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Our BSV PLIC here follows the example of the SiFive PLIC spec
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described below ("Background"), in order to be able to use the same
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Linux driver.
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>================================================================
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Background on PLIC ("Platform Level Interrupt Controller")
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As of this writing (2019-04-29), there is not yet any official PLIC
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spec for RISC-V.
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In an earlier version (v1.10) of the RISC-V Privilege Architecture
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spec, Chapter 7 was a PLIC spec, but it was taken out of the Priv Arch
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spec to be considered separately in the future as part of a platform
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spec rather than as part of the ISA spec. That chapter spec was
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partial in that, while it described the required functionality, it did
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not specify any specific address map for the functional components.
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SiFive has implemented that PLIC spec for their cores, taking
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particular decisions for memory mappings, etc., and they have
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implemented a Linux driver for it.
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Below is a summary of their (relative) Memory map for the PLIC the
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following SiFive chip:
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SiFive U54-MC Core Complex Manual, v1p0, Oct 4 2017
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Chapter 8 Platform Level Interrupt Controller, pp.32-38.
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@@ -27,7 +52,7 @@ IP (Interrupt Pending) array: 32 sources per 32b word
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>----------------
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Reserved
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0x1018 ... 0x1FFF
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0x1040 ... 0x1FFF
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>----------------
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IE (interrupt enables) array for Hart0 M mode (1 bit per source)
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@@ -105,30 +130,32 @@ Reserved
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>----------------
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Threshold (of priority) and Claim/Complete registers
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0x0C20 0000 Hart 0 M-mode
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0x0C20 0004 Hart 0 M-mode claim/complete
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0x0020 0000 Hart 0 M-mode
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0x0020 0004 Hart 0 M-mode claim/complete
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>----------------
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0x0C20 1000 Hart 1 M-mode
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0x0C20 1004 Hart 1 M-mode claim/complete
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0x0020 1000 Hart 1 M-mode
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0x0020 1004 Hart 1 M-mode claim/complete
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>----------------
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0x0C20 2000 Hart 1 S-mode
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0x0C20 2004 Hart 1 S-mode claim/complete
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0x0020 2000 Hart 1 S-mode
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0x0020 2004 Hart 1 S-mode claim/complete
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>----------------
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0x0C20 3000 Hart 2 M-mode
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0x0C20 3004 Hart 2 M-mode claim/complete
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0x0020 3000 Hart 2 M-mode
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0x0020 3004 Hart 2 M-mode claim/complete
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>----------------
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0x0C20 4000 Hart 2 S-mode
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0x0C20 4004 Hart 2 S-mode claim/complete
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0x0020 4000 Hart 2 S-mode
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0x0020 4004 Hart 2 S-mode claim/complete
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>----------------
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0x0C20 5000 Hart 3 M-mode
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0x0C20 5004 Hart 3 M-mode claim/complete
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0x0020 5000 Hart 3 M-mode
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0x0020 5004 Hart 3 M-mode claim/complete
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>----------------
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0x0C20 6000 Hart 3 S-mode
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0x0C20 6004 Hart 3 S-mode claim/complete
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0x0020 6000 Hart 3 S-mode
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0x0020 6004 Hart 3 S-mode claim/complete
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>----------------
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0x0C20 7000 Hart 4 M-mode
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0x0C20 7004 Hart 4 M-mode claim/complete
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0x0020 7000 Hart 4 M-mode
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0x0020 7004 Hart 4 M-mode claim/complete
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>----------------
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0x0C20 8000 Hart 4 S-mode
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0x0C20 8004 Hart 4 S-mode claim/complete
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0x0020 8000 Hart 4 S-mode
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0x0020 8004 Hart 4 S-mode claim/complete
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>----------------
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>================================================================
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