diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv
index b391a79..e57e1e3 100644
--- a/src_Core/CPU/Proc.bsv
+++ b/src_Core/CPU/Proc.bsv
@@ -296,11 +296,13 @@ module mkProc (Proc_IFC);
    // External interrupts
 
    method Action  m_external_interrupt_req (x);
-      core[0].setMEIP (pack (x));
+      for(Integer i = 0; i < valueof(CoreNum); i = i+1)
+         core[i].setMEIP (pack (x[i]));
    endmethod
 
    method Action  s_external_interrupt_req (x);
-      core[0].setSEIP (pack (x));
+      for(Integer i = 0; i < valueof(CoreNum); i = i+1)
+         core[i].setSEIP (pack (x[i]));
    endmethod
 
    // ----------------
diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv
index 1af5afb..38091a2 100644
--- a/src_Core/CPU/Proc_IFC.bsv
+++ b/src_Core/CPU/Proc_IFC.bsv
@@ -27,6 +27,8 @@ import ClientServer :: *;
 // ================================================================
 // Project imports
 
+import ProcTypes :: *;
+
 import ISA_Decls  :: *;
 
 import AXI4  :: *;
@@ -75,10 +77,10 @@ interface Proc_IFC;
    // External interrupts
 
    (* always_ready, always_enabled *)
-   method Action  m_external_interrupt_req (Bool set_not_clear);
+   method Action  m_external_interrupt_req (Vector #(CoreNum, Bool) set_not_clear);
 
    (* always_ready, always_enabled *)
-   method Action  s_external_interrupt_req (Bool set_not_clear);
+   method Action  s_external_interrupt_req (Vector #(CoreNum, Bool) set_not_clear);
 
    // ----------------
    // Non-maskable interrupt
diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index 7e75669..7ad8f92 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -37,7 +37,7 @@ package CoreW;
 //
 // mkCoreW instantiates:
 //     - mkProc (the RISC-V CPU, a version of MIT's RISCY-OOO)
-//     - mkPLIC_16_2_7
+//     - mkPLIC_16_CoreNumX2_7
 //     - mkTV_Encode          (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)
 //     - mkDebug_Module       (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)
 // and connects them all up.
@@ -81,11 +81,12 @@ import Debug_Module  :: *;
 `endif
 
 import CoreW_IFC    :: *;
-import PLIC         :: *;
-import PLIC_16_2_7  :: *;
 import Proc_IFC     :: *;
 import Proc         :: *;
 
+import PLIC                :: *;
+import PLIC_16_CoreNumX2_7 :: *;
+
 `ifdef INCLUDE_TANDEM_VERIF
 import TV_Info                   :: *;
 import Trace_Data2               :: *;
@@ -190,7 +191,7 @@ module mkCoreW #(Reset dm_power_on_reset)
 `endif
 
    // PLIC (Platform-Level Interrupt Controller)
-   PLIC_IFC_16_2_7  plic <- mkPLIC_16_2_7;
+   PLIC_IFC_16_CoreNumX2_7  plic <- mkPLIC_16_CoreNumX2_7;
 
 `ifdef INCLUDE_GDB_CONTROL
    // Debug Module
@@ -402,13 +403,16 @@ module mkCoreW #(Reset dm_power_on_reset)
    // Connect external interrupt lines from PLIC to CPU
 
    rule rl_relay_external_interrupts;    // from PLIC
-      Bool meip = plic.v_targets [0].m_eip;
-      proc.m_external_interrupt_req (meip);
+      Vector #(CoreNum, Bool) meips;
+      Vector #(CoreNum, Bool) seips;
 
-      Bool seip = plic.v_targets [1].m_eip;
-      proc.s_external_interrupt_req (seip);
+      for (Integer i = 0; i < valueof(CoreNum); i = i + 1) begin
+	 meips [i] = plic.v_targets [2 * i].m_eip;
+	 seips [i] = plic.v_targets [2 * i + 1].m_eip;
+      end
 
-      // $display ("%0d: Core.rl_relay_external_interrupts: relaying: %d", cur_cycle, pack (x));
+      proc.m_external_interrupt_req (meips);
+      proc.s_external_interrupt_req (seips);
    endrule
 
    // ================================================================
diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv
index 731fedf..2bb5a6e 100644
--- a/src_Core/Core/CoreW_IFC.bsv
+++ b/src_Core/Core/CoreW_IFC.bsv
@@ -25,7 +25,7 @@ package CoreW_IFC;
 //                  interface and its module is called 'CoreW', to disambiguate.
 //     - mkFabric_2x3
 //     - mkNear_Mem_IO_AXI4
-//     - mkPLIC_16_2_7
+//     - mkPLIC_16_CoreNumX2_7
 //     - mkTV_Encode          (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)
 //     - mkDebug_Module       (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)
 
diff --git a/src_Core/PLIC/PLIC_16_2_7.bsv b/src_Core/PLIC/PLIC_16_CoreNumX2_7.bsv
similarity index 81%
rename from src_Core/PLIC/PLIC_16_2_7.bsv
rename to src_Core/PLIC/PLIC_16_CoreNumX2_7.bsv
index b62d1d4..2e318c5 100644
--- a/src_Core/PLIC/PLIC_16_2_7.bsv
+++ b/src_Core/PLIC/PLIC_16_CoreNumX2_7.bsv
@@ -13,7 +13,7 @@
 //     This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
 //-
 
-package PLIC_16_2_7;
+package PLIC_16_CoreNumX2_7;
 
 // ================================================================
 // Instantiation of parameterized PLIC to specific parameter values.
@@ -31,21 +31,23 @@ package PLIC_16_2_7;
 // ================================================================
 // Project imports
 
+import ProcTypes :: *;  // For CoreNum
+
 import SoC_Map :: *;    // For N_External_Interrupt_Sources
 import PLIC    :: *;    // For PLIC_IFC, mkPLIC
 
 // ================================================================
 // PLIC for this core
 
-typedef  2  PLIC_N_Targets;
-typedef  7  PLIC_Max_Priority;
+typedef  TMul #(CoreNum, 2)  PLIC_N_Targets;
+typedef  7                   PLIC_Max_Priority;
 
 typedef  PLIC_IFC #(N_External_Interrupt_Sources,
-                    PLIC_N_Targets,
-                    PLIC_Max_Priority)             PLIC_IFC_16_2_7;
+		    PLIC_N_Targets,
+		    PLIC_Max_Priority)             PLIC_IFC_16_CoreNumX2_7;
 
 (* synthesize *)
-module mkPLIC_16_2_7 (PLIC_IFC_16_2_7);
+module mkPLIC_16_CoreNumX2_7 (PLIC_IFC_16_CoreNumX2_7);
    let m <- mkPLIC;
    return m;
 endmodule
diff --git a/src_Core/PLIC/Test_PLIC.bsv b/src_Core/PLIC/Test_PLIC.bsv
index e4dd2c7..0583bbf 100644
--- a/src_Core/PLIC/Test_PLIC.bsv
+++ b/src_Core/PLIC/Test_PLIC.bsv
@@ -44,8 +44,9 @@ import AXI4_Types   :: *;
 import AXI4_Fabric  :: *;
 import Fabric_Defs  :: *;    // for Wd_Id, Wd_Addr, Wd_Data, Wd_User
 import SoC_Map      :: *;
-import PLIC         :: *;
-import PLIC_16_2_7  :: *;
+
+import PLIC                :: *;
+import PLIC_16_CoreNumX2_7 :: *;
 
 // ================================================================
 
@@ -70,7 +71,7 @@ module mkTest_PLIC (Empty);
    SoC_Map_IFC  soc_map  <- mkSoC_Map;
 
    // PLIC (Platform-Level Interrupt Controller)
-   PLIC_IFC_16_2_7  plic <- mkPLIC_16_2_7;
+   PLIC_IFC_16_CoreNumX2_7  plic <- mkPLIC_16_CoreNumX2_7;
 
    // Master transactor through which to read/write PLIC regs
    AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor;
diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml
index e7b7301..30c22e6 100644
--- a/src_SSITH_P3/xilinx_ip/component.xml
+++ b/src_SSITH_P3/xilinx_ip/component.xml
@@ -2532,7 +2532,7 @@
         <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/mkPLIC_16_2_7.v</spirit:name>
+        <spirit:name>hdl/mkPLIC_16_CoreNumX2_7.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
       </spirit:file>
@@ -3159,7 +3159,7 @@
         <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/mkPLIC_16_2_7.v</spirit:name>
+        <spirit:name>hdl/mkPLIC_16_CoreNumX2_7.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
       </spirit:file>