From b4fe3ee93ca698a353969adca47efb6a118d88a1 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Thu, 30 Sep 2021 13:33:26 +0100 Subject: [PATCH 1/3] adjusted SSITH_P3 Makefile to new version of HPM Events --- src_SSITH_P3/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile index a095efb..974a37e 100644 --- a/src_SSITH_P3/Makefile +++ b/src_SSITH_P3/Makefile @@ -119,7 +119,7 @@ src_BSV/TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py generate_hpm_vector: GenerateHPMVector.bsv GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py @echo "INFO: Re-generating GenerateHPMVector bluespec file" - $^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -b $@ + $^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -b $@ @echo "INFO: Re-generated GenerateHPMVector bluespec file" @@ -127,7 +127,7 @@ GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py stat_counters: StatCounters.bsv StatCounters.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py @echo "INFO: Re-generating HPM events struct bluepsec file" - $^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -s $@ + $^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -s $@ @echo "INFO: Re-generated HPM events struct bluespec file" compile_sim: tagsparams stat_counters generate_hpm_vector compile_synth: tagsparams stat_counters generate_hpm_vector From df74a71d610a6424bae1e436b7c0005e39e17ea6 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Thu, 30 Sep 2021 15:02:47 +0100 Subject: [PATCH 2/3] changed _Synth to _Sig following the new convention in BlueStuff --- src_SSITH_P3/src_BSV/Giraffe_IFC.bsv | 16 ++++++++-------- src_SSITH_P3/src_BSV/P3_Core.bsv | 12 ++++++------ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv b/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv index d3bf344..2eafcff 100644 --- a/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv +++ b/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv @@ -118,10 +118,10 @@ instance Connectable#(DMI_IFC, DMI_Master_IFC); endinstance interface Core_IFC; - interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master0; - interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master1; - interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master2; - interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master3; + interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master0; + interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master1; + interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master2; + interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master3; (* always_ready, always_enabled *) (* prefix = "", result = "unused0" *) @@ -145,10 +145,10 @@ interface Core_IFC; endinterface interface Platform_IFC; - interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave0; - interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave1; - interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave2; - interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave3; + interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave0; + interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave1; + interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave2; + interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave3; (* always_ready, always_enabled *) method Bit#(1) interrupt0; diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 5c4b81a..ef5be3e 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -70,10 +70,10 @@ interface P3_Core_IFC; // Core CPU interfaces // CPU IMem to Fabric master interface - interface AXI4_Master_Synth#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, + interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) master0; - interface AXI4_Master_Synth#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, + interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) master1; // External interrupt sources @@ -293,16 +293,16 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ // INTERFACE - let master0_synth <- toAXI4_Master_Synth(corew.cpu_imem_master); - let master1_synth <- toAXI4_Master_Synth(corew.cpu_dmem_master); + let master0_sig <- toAXI4_Master_Sig(corew.cpu_imem_master); + let master1_sig <- toAXI4_Master_Sig(corew.cpu_dmem_master); // ---------------------------------------------------------------- // Core CPU interfaces // CPU IMem to Fabric master interface - interface AXI4_Master_Synth master0 = master0_synth; + interface AXI4_Master_Sig master0 = master0_sig; // CPU DMem to Fabric master interface - interface AXI4_Master_Synth master1 = master1_synth; + interface AXI4_Master_Sig master1 = master1_sig; // External interrupts method Action interrupt_reqs (Bit #(N_External_Interrupt_Sources) reqs); From db54d27368726423074423c083ac44bbf2c38404 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Fri, 1 Oct 2021 16:54:17 +0100 Subject: [PATCH 3/3] Move import DReg::* into ifdefs --- src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 2 +- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 25eedd8..8b59771 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -44,7 +44,6 @@ import BuildVector::*; import Cntrs::*; import Types::*; import ProcTypes::*; -import DReg::*; import SynthParam::*; import Exec::*; import Performance::*; @@ -62,6 +61,7 @@ import ISA_Decls_CHERI::*; `ifdef PERFORMANCE_MONITORING import BlueUtils::*; import StatCounters::*; +import DReg::*; `endif diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 24312ab..51346ee 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -45,7 +45,6 @@ import Fifos::*; import FIFO::*; import Types::*; import ProcTypes::*; -import DReg::*; import CCTypes::*; import SynthParam::*; import Performance::*; @@ -69,6 +68,7 @@ import CHERICC_Fat::*; import ISA_Decls_CHERI::*; `ifdef PERFORMANCE_MONITORING import StatCounters::*; +import DReg::*; `endif import Cur_Cycle :: *;