From fec16f64c834b6ee3975cca2447299ea57b2be09 Mon Sep 17 00:00:00 2001
From: Franz Fuchs <franz.fuchs@cl.cam.ac.uk>
Date: Fri, 25 Jun 2021 15:44:29 +0100
Subject: [PATCH] Added first attempts for counting wild exceptions

---
 src_Core/CPU/Core.bsv                         |  3 +++
 .../procs/RV64G_OOO/AluExePipeline.bsv        | 27 ++++++++++++++++---
 src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv    |  1 +
 3 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index ced77b7..a80ea43 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -1171,12 +1171,15 @@ module mkCore#(CoreId coreId)(Core);
 
      EventsTransExe transExe = renameStage.events;
      SupCnt wildJumps = 0;
+     SupCnt wildExceptions = 0;
      for(Integer i = 0; i < valueof(AluExeNum); i = i+1) begin
           let alu_events = coreFix.aluExeIfc[i].events;
           wildJumps = wildJumps + alu_events.evt_WILD_JUMP;
+          wildExceptions = wildExceptions + alu_events.evt_WILD_EXCEPTION;
      end
 
      transExe.evt_WILD_JUMP = wildJumps;
+     transExe.evt_WILD_EXCEPTION = wildExceptions;
      Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (transExe);
 
      let events = append (null_evt, core_evts_vec);
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
index c9003d7..2017af7 100755
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
@@ -59,6 +59,10 @@ import Bypass::*;
 import CHERICap::*;
 import CHERICC_Fat::*;
 import ISA_Decls_CHERI::*;
+`ifdef PERFORMANCE_MONITORING
+import BlueUtils::*;
+`endif
+
 
 import Cur_Cycle :: *;
 
@@ -233,7 +237,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
     Integer finishSendBypassPort = 1;
 
 `ifdef PERFORMANCE_MONITORING
-    Reg#(EventsTransExe) events_reg <- mkDReg(unpack(0));
+    Array#(Reg#(EventsTransExe)) events_reg <- mkDRegOR(2, unpack(0));
 `endif
 
 `ifdef PERF_COUNT
@@ -308,7 +312,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
             if((val != ppc_addr) && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin
                 $display("Wild direct jump: pc = ", fshow(pc), " ppc = ", fshow(ppc), " imm = ", fshow(imm));
                 events.evt_WILD_JUMP = 1;
-                events_reg <= events;
+                events_reg[1] <= events;
             end
         end
 
@@ -321,7 +325,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
             if(!res_targets && !res_ret_targets && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin
                 $display("Wild indirect jump: pc = ", fshow(pc), " ppc = ", fshow(ppc));
                 events.evt_WILD_JUMP = 1;
-                events_reg <= events;
+                events_reg[1] <= events;
             end
         end  
 `endif
@@ -439,6 +443,21 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
 `endif
         );
 
+`ifdef PERFORMANCE_MONITORING
+        // get PC and PPC
+        let pc = getAddr(x.controlFlow.pc);
+        let ppc = getAddr(x.controlFlow.nextPc);
+        let validPc = x.isCompressed ? (pc + 2) : (pc + 4);
+        $display("spec_excps: pc = ", fshow(pc), ", ppc = ", fshow(ppc), ", validPc = ", fshow(validPc));
+        $display("capException = ", fshow(x.capException));
+        if(x.capException matches tagged Valid .exc &&& (ppc != validPc)) begin
+            $display("Wild exception");
+            EventsTransExe events = unpack(0);
+            events.evt_WILD_EXCEPTION = 1;
+            events_reg[0] <= events;
+        end
+`endif
+
         // handle spec tags for branch predictions
         // TODO what happens here if we trap?
         (* split *)
@@ -513,7 +532,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
     endmethod
 
 `ifdef PERFORMANCE_MONITORING
-    method events = events_reg;
+    method events = events_reg[0];
 `endif
 
 endmodule
diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
index 0162789..957af46 100755
--- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
@@ -1124,6 +1124,7 @@ typedef TDiv#(SizeOf#(EventsCoreMem),Report_Width) EventsCoreMemElements;
 typedef struct {
    SupCnt evt_RENAMED_INST;
    SupCnt evt_WILD_JUMP;
+   SupCnt evt_WILD_EXCEPTION;
 } EventsTransExe deriving (Bits, FShow);
 typedef TDiv#(SizeOf#(EventsTransExe),SizeOf#(SupCnt)) EventsTransExeElements;
 `endif