Commit Graph

5 Commits

Author SHA1 Message Date
rsnikhil
96a0897bf5 In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately.
Previously, the request went out into the fabric, and we were relying
on the fabric returning an error response.  Some fabrics don't do this
reliably, so this removes that reliance on the fabric.
2020-02-28 14:07:45 -05:00
rsnikhil
83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
2020-02-04 16:02:53 -05:00
rsnikhil
3d4960edc5 Bug fixes; now passing rv64mi-p-access ISA test
Modified
  src_Core/CPU/MMIO_AXI4_Adapter.bsv
    Instead of aborting on axi4 mem read error, pass the error on to the core
  src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv
    Added mainMemBoundAddr
  src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv
    Update isMMIOAddr check to also check mainMemBoundAddr
  src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
    Update getFetchTarget to also check mainMemBoundAddr
    (still TODO: allow other IO addrs other than bootRom)
2019-04-10 12:42:23 -04:00
rsnikhil
9f94c9176e Added verbosity guards around $displays to dial down log verbosity
To get the instruction trace back, set verbosity to 1 in CommitStage.bsv.
Regressions: RV64ADFIMSU_Tooba_verilator: 199/227 PASS (1 test hangs)
2019-04-01 20:35:52 -04:00
rsnikhil
ee24a93944 Initial load of files 2019-03-26 14:49:40 -04:00