Commit Graph

9 Commits

Author SHA1 Message Date
Peter Rugg
f71f650023 Allow dynamic latency config 2023-07-15 22:37:45 +01:00
Peter Rugg
47c94b5a34 Map more RAM in SSITH build 2021-02-19 09:25:41 +00:00
Peter Rugg
6a317d1a00 Prevent instruction fetch to unexpected devices 2020-07-10 17:35:06 +01:00
Peter Rugg
962ade1092 Fixes for synthesis 2020-06-05 17:40:28 +01:00
Niraj Sharma
ce327a1615 Updated SoC_Map in src_SSITH_P3 (synth version)
Regenerated synth RTL
2020-01-30 14:04:29 -05:00
rsnikhil
d84ec657d7 Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL 2020-01-28 21:33:56 -05:00
rsnikhil
e7fbf32b38 Bugfix in MMIOPlatform.bsv for instruction-fetch from IO addrs
Detail: an "instruction-fetch" response from mmioplatform to core
should be an "InstFetch". This was true for successful fabric reads,
but on error responses it was wrongly returned as a "DataAccess"
response.  This was causing a deadlock.
2019-04-17 15:29:10 -04:00
rsnikhil
4e305ac98d Updated so SoC addrs are taken from SoC_Map.bsv 2019-04-01 14:34:49 -04:00
rsnikhil
113f888d37 Added support for 'debug_external_interrupt_req'
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00