Jessica Clarke
72f49a1109
Regenerate verilog
2020-07-16 19:35:51 +01:00
Jessica Clarke
682ff10d72
Regenerate verilog
2020-07-15 03:16:24 +01:00
Jessica Clarke
e8c1de7793
Regenerate verilog
2020-07-14 19:01:47 +01:00
Jessica Clarke
e89f7a8130
Regenerate verilog
2020-07-13 18:54:53 +01:00
Jessica Clarke
ece8423119
Regenerate verilog
2020-07-11 17:26:00 +01:00
Jessica Clarke
40f8109263
Regenerate verilog
2020-07-06 19:32:56 +01:00
Jessica Clarke
9c12b97a09
Regenerate verilog
2020-07-06 01:55:30 +01:00
Jessica Clarke
cd8e2a15ef
Regenerate verilog
2020-07-02 03:00:55 +01:00
Peter Rugg
f8972768a2
Regenerate verilog
2020-06-30 00:00:29 +01:00
Peter Rugg
a5578a715a
Regenerate verilog
2020-06-24 21:16:57 +01:00
Peter Rugg
7d866f85e7
Regenerate verilog
2020-06-17 13:02:20 +01:00
Peter Rugg
3117fcc9d5
Regenerate verilog
2020-06-07 16:52:34 +01:00
rsnikhil
ddcb784297
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
Niraj Sharma
e35c48efff
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
Niraj Sharma
ce327a1615
Updated SoC_Map in src_SSITH_P3 (synth version)
...
Regenerated synth RTL
2020-01-30 14:04:29 -05:00
rsnikhil
d84ec657d7
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
Niraj N Sharma
64178e0bd7
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
Darius Rad
d337f1b8cf
Update compiled output.
2019-10-25 00:13:58 -04:00
Darius Rad
afb5e0d13c
Update compiled output.
2019-04-22 13:55:36 -04:00
rsnikhil
113f888d37
Added support for 'debug_external_interrupt_req'
...
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14]. The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either. Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.
Builds in standalone mode, runs ISA tests.
Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00
