6 Commits

Author	SHA1	Message	Date
Peter Rugg	a5578a715a	Regenerate verilog	2020-06-24 21:16:57 +01:00
Peter Rugg	7d866f85e7	Regenerate verilog	2020-06-17 13:02:20 +01:00
Peter Rugg	3117fcc9d5	Regenerate verilog	2020-06-07 16:52:34 +01:00
rsnikhil	976494a8ff	Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. ... When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also changes MSTATUS.FS and, by implication, MSTATUS.SD because the floating point state has become "dirty". Tandem Verification trace-generation was not reporting this update.	2020-03-08 21:29:30 -04:00
rsnikhil	ddcb784297	Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.	2020-02-12 10:44:30 -05:00
Niraj Sharma	e35c48efff	Merged src_SSITH_P3 and src_SSITH_P3_sim	2020-02-07 21:00:50 +05:30