If DRAM latency is too high and the cache is performing frequent writes,
it would be possible to overflow this counter, which means we don't rate
limit, the cache could erroneously believe it's safe to do I/O
accesses/cache refills/page table walks, and the cache would block due
to the guard on decr when it finally gets enough write responses back.
We should block the incr method to automatically stall the cache until
it receives a new write response.
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14]. The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either. Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.
Builds in standalone mode, runs ISA tests.
Builds in src_SSITH_P3, generating RTL.
