def compute_percent_diff(regular, modified):
    percent_diff = {}
    for key in regular:
        if key in modified and regular[key] != 0:
            percent_diff[key] = ((regular[key] - modified[key]) / regular[key]) * 100
    return percent_diff

def compute_percent_diff_mod_vs_pte(modified, after_pte):
    percent_diff = {}
    for key in ["CPU_cycles", "L1_DTLB_access"]:
        if key in modified and key in after_pte and modified[key] != 0:
            percent_diff[key] = ((modified[key] - after_pte[key]) / modified[key]) * 100
    return percent_diff


performance_data = {
    "Mem": {
        "regular": {
            "CPU_cycles": 33940,
            "L1_DTLB_access": 13202,
            "L1_DTLB_miss": 36,
            "L2_DTLB_miss": 10,
        },
        "modified": {
            "CPU_cycles": 2457,
            "L1_DTLB_access": 151,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
        "after_PTE_setup": {
            "CPU_cycles": 531,
            "L1_DTLB_access": 25,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
    },

    "Test_C": {
        "regular": {
            "CPU_cycles": 34040,
            "L1_DTLB_access": 13284,
            "L1_DTLB_miss": 36,
            "L2_DTLB_miss": 10,
        },
        "modified": {
            "CPU_cycles": 2789,
            "L1_DTLB_access": 396,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
        "after_PTE_setup": {
            "CPU_cycles": 631,
            "L1_DTLB_access": 107,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
    },

    "Glibc": {
        "regular": {
            "CPU_cycles": 36053,
            "L1_DTLB_access": 14027,
            "L1_DTLB_miss": 36,
            "L2_DTLB_miss": 10,
        },
        "modified": {
            "CPU_cycles": 4219,
            "L1_DTLB_access": 783,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
        "after_PTE_setup": {
            "CPU_cycles": 2644,
            "L1_DTLB_access": 850,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
    },

    "Setup": {
        "regular": {
            "CPU_cycles": 33409,
            "L1_DTLB_access": 13177,
            "L1_DTLB_miss": 36,
            "L2_DTLB_miss": 10,
        }
    },

    "Richards": {
        "regular": {
            "CPU_cycles": 37808,
            "L1_DTLB_access": 14363,
            "L1_DTLB_miss": 10,
            "L2_DTLB_miss": 6,
        },
        "modified": {
            "CPU_cycles": 4433,
            "L1_DTLB_access": 874,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
        "after_PTE_setup": {
            "CPU_cycles": 4399,
            "L1_DTLB_access": 1186,
        },
    },

    "Matrix_mul": {
        "regular": {
            "CPU_cycles": 42383,
            "L1_DTLB_access": 17020,
            "L1_DTLB_miss": 14,
            "L2_DTLB_miss": 10,
        },
        "modified": {
            "CPU_cycles": 12149,
            "L1_DTLB_access": 4411,
            "L1_DTLB_miss": 0,
            "L2_DTLB_miss": 0,
        },
        "after_PTE_setup": {
            "CPU_cycles": 8974,
            "L1_DTLB_access": 3843,
        },
    }
}

# Add percentage differences
for test, data in performance_data.items():
    if "regular" in data and "modified" in data:
        data["percent_diff"] = compute_percent_diff(
            data["regular"], data["modified"]
        )


# Add modified vs after_PTE_setup percentage differences
for test, data in performance_data.items():
    if "modified" in data and "after_PTE_setup" in data:
        data["mod_vs_pte_percent_diff"] = compute_percent_diff_mod_vs_pte(
            data["modified"], data["after_PTE_setup"]
        )

# Example usage:
print(performance_data["Mem"]["percent_diff"])
print(performance_data["Mem"]["mod_vs_pte_percent_diff"])