ssith user ssith_processor 1.0 master0 AWID master0_awid AWADDR master0_awaddr AWLEN master0_awlen AWSIZE master0_awsize AWBURST master0_awburst AWLOCK master0_awlock AWCACHE master0_awcache AWPROT master0_awprot AWREGION master0_awregion AWQOS master0_awqos AWVALID master0_awvalid AWREADY master0_awready WDATA master0_wdata WSTRB master0_wstrb WLAST master0_wlast WVALID master0_wvalid WREADY master0_wready BID master0_bid BRESP master0_bresp BVALID master0_bvalid BREADY master0_bready ARID master0_arid ARADDR master0_araddr ARLEN master0_arlen ARSIZE master0_arsize ARBURST master0_arburst ARLOCK master0_arlock ARCACHE master0_arcache ARPROT master0_arprot ARREGION master0_arregion ARQOS master0_arqos ARVALID master0_arvalid ARREADY master0_arready RID master0_rid RDATA master0_rdata RRESP master0_rresp RLAST master0_rlast RVALID master0_rvalid RREADY master0_rready master1 AWID master1_awid AWADDR master1_awaddr AWLEN master1_awlen AWSIZE master1_awsize AWBURST master1_awburst AWLOCK master1_awlock AWCACHE master1_awcache AWPROT master1_awprot AWREGION master1_awregion AWQOS master1_awqos AWVALID master1_awvalid AWREADY master1_awready WDATA master1_wdata WSTRB master1_wstrb WLAST master1_wlast WVALID master1_wvalid WREADY master1_wready BID master1_bid BRESP master1_bresp BVALID master1_bvalid BREADY master1_bready ARID master1_arid ARADDR master1_araddr ARLEN master1_arlen ARSIZE master1_arsize ARBURST master1_arburst ARLOCK master1_arlock ARCACHE master1_arcache ARPROT master1_arprot ARREGION master1_arregion ARQOS master1_arqos ARVALID master1_arvalid ARREADY master1_arready RID master1_rid RDATA master1_rdata RRESP master1_rresp RLAST master1_rlast RVALID master1_rvalid RREADY master1_rready RST_N RST RST_N POLARITY ACTIVE_LOW CLK CLK CLK ASSOCIATED_BUSIF master0:master1 master0 16777216T 64 master1 16777216T 64 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog mkP3_Core xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_div_gen_5_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_floating_point_7_1__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum c8a99f02 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 CLK in std_logic xilinx_anylanguagesynthesis RST_N in std_logic xilinx_anylanguagesynthesis master0_awvalid out wire xilinx_anylanguagesynthesis master0_awid out 6 0 wire xilinx_anylanguagesynthesis master0_awaddr out 63 0 wire xilinx_anylanguagesynthesis master0_awlen out 7 0 wire xilinx_anylanguagesynthesis master0_awsize out 2 0 wire xilinx_anylanguagesynthesis master0_awburst out 1 0 wire xilinx_anylanguagesynthesis master0_awlock out wire xilinx_anylanguagesynthesis master0_awcache out 3 0 wire xilinx_anylanguagesynthesis master0_awprot out 2 0 wire xilinx_anylanguagesynthesis master0_awqos out 3 0 wire xilinx_anylanguagesynthesis master0_awregion out 3 0 wire xilinx_anylanguagesynthesis master0_awready in std_logic xilinx_anylanguagesynthesis 0 master0_wvalid out wire xilinx_anylanguagesynthesis master0_wdata out 63 0 wire xilinx_anylanguagesynthesis master0_wstrb out 7 0 wire xilinx_anylanguagesynthesis master0_wlast out wire xilinx_anylanguagesynthesis master0_wready in std_logic xilinx_anylanguagesynthesis 0 master0_bvalid in std_logic xilinx_anylanguagesynthesis 0 master0_bid in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 master0_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 master0_bready out wire xilinx_anylanguagesynthesis master0_arvalid out wire xilinx_anylanguagesynthesis master0_arid out 6 0 wire xilinx_anylanguagesynthesis master0_araddr out 63 0 wire xilinx_anylanguagesynthesis master0_arlen out 7 0 wire xilinx_anylanguagesynthesis master0_arsize out 2 0 wire xilinx_anylanguagesynthesis master0_arburst out 1 0 wire xilinx_anylanguagesynthesis master0_arlock out wire xilinx_anylanguagesynthesis master0_arcache out 3 0 wire xilinx_anylanguagesynthesis master0_arprot out 2 0 wire xilinx_anylanguagesynthesis master0_arqos out 3 0 wire xilinx_anylanguagesynthesis master0_arregion out 3 0 wire xilinx_anylanguagesynthesis master0_arready in std_logic xilinx_anylanguagesynthesis 0 master0_rvalid in std_logic xilinx_anylanguagesynthesis 0 master0_rid in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 master0_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis 0 master0_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 master0_rlast in std_logic xilinx_anylanguagesynthesis 0 master0_rready out wire xilinx_anylanguagesynthesis master1_awvalid out wire xilinx_anylanguagesynthesis master1_awid out 6 0 wire xilinx_anylanguagesynthesis master1_awaddr out 63 0 wire xilinx_anylanguagesynthesis master1_awlen out 7 0 wire xilinx_anylanguagesynthesis master1_awsize out 2 0 wire xilinx_anylanguagesynthesis master1_awburst out 1 0 wire xilinx_anylanguagesynthesis master1_awlock out wire xilinx_anylanguagesynthesis master1_awcache out 3 0 wire xilinx_anylanguagesynthesis master1_awprot out 2 0 wire xilinx_anylanguagesynthesis master1_awqos out 3 0 wire xilinx_anylanguagesynthesis master1_awregion out 3 0 wire xilinx_anylanguagesynthesis master1_awready in std_logic xilinx_anylanguagesynthesis 0 master1_wvalid out wire xilinx_anylanguagesynthesis master1_wdata out 63 0 wire xilinx_anylanguagesynthesis master1_wstrb out 7 0 wire xilinx_anylanguagesynthesis master1_wlast out wire xilinx_anylanguagesynthesis master1_wready in std_logic xilinx_anylanguagesynthesis 0 master1_bvalid in std_logic xilinx_anylanguagesynthesis 0 master1_bid in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 master1_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 master1_bready out wire xilinx_anylanguagesynthesis master1_arvalid out wire xilinx_anylanguagesynthesis master1_arid out 6 0 wire xilinx_anylanguagesynthesis master1_araddr out 63 0 wire xilinx_anylanguagesynthesis master1_arlen out 7 0 wire xilinx_anylanguagesynthesis master1_arsize out 2 0 wire xilinx_anylanguagesynthesis master1_arburst out 1 0 wire xilinx_anylanguagesynthesis master1_arlock out wire xilinx_anylanguagesynthesis master1_arcache out 3 0 wire xilinx_anylanguagesynthesis master1_arprot out 2 0 wire xilinx_anylanguagesynthesis master1_arqos out 3 0 wire xilinx_anylanguagesynthesis master1_arregion out 3 0 wire xilinx_anylanguagesynthesis master1_arready in std_logic xilinx_anylanguagesynthesis 0 master1_rvalid in std_logic xilinx_anylanguagesynthesis 0 master1_rid in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 master1_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis 0 master1_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 master1_rlast in std_logic xilinx_anylanguagesynthesis 0 master1_rready out wire xilinx_anylanguagesynthesis cpu_external_interrupt_req in 15 0 std_logic_vector xilinx_anylanguagesynthesis debug_external_interrupt_req_set_not_clear in std_logic xilinx_anylanguagesynthesis jtag_tdi in std_logic xilinx_anylanguagesynthesis jtag_tms in std_logic xilinx_anylanguagesynthesis jtag_tclk in std_logic xilinx_anylanguagesynthesis jtag_tdo out wire xilinx_anylanguagesynthesis CLK_jtag_tclk_out out wire xilinx_anylanguagesynthesis CLK_GATE_jtag_tclk_out out wire xilinx_anylanguagesynthesis choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset src/p3_constraints.xdc xdc USED_IN_implementation USED_IN_synthesis hdl/ASSIGN1.v verilogSource IMPORTED_FILE hdl/RegUNInit.v verilogSource IMPORTED_FILE hdl/BRAM2.v verilogSource IMPORTED_FILE hdl/FIFO1.v verilogSource IMPORTED_FILE hdl/FIFO10.v verilogSource IMPORTED_FILE hdl/FIFO2.v verilogSource IMPORTED_FILE hdl/FIFO20.v verilogSource IMPORTED_FILE hdl/RevertReg.v verilogSource IMPORTED_FILE hdl/MakeClock.v verilogSource IMPORTED_FILE hdl/MakeReset0.v verilogSource IMPORTED_FILE hdl/RegFile.v verilogSource IMPORTED_FILE hdl/Counter.v verilogSource IMPORTED_FILE hdl/RevertReg.v verilogSource IMPORTED_FILE hdl/SizedFIFO.v verilogSource IMPORTED_FILE hdl/SizedFIFO0.v verilogSource IMPORTED_FILE hdl/SyncFIFOLevel.v verilogSource IMPORTED_FILE hdl/SyncHandshake.v verilogSource IMPORTED_FILE hdl/SyncResetA.v verilogSource IMPORTED_FILE hdl/SyncReset0.v verilogSource IMPORTED_FILE hdl/SyncWire.v verilogSource IMPORTED_FILE hdl/reset_guard.v verilogSource IMPORTED_FILE hdl/MakeResetA.v verilogSource hdl/ResetEither.v verilogSource hdl/FIFOL1.v verilogSource CHECKSUM_bfe3b3df ../Verilog_RTL/mkPowerOnReset.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkAluDispToRegFifo.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkAluExeToFinFifo.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkAluRegToExeFifo.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkCore.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkTagController.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDCRqMshrWrapper.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDM_Abstract_Commands.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDM_Run_Control.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDM_System_Bus.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDPRqMshrWrapper.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDPipeline.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDTlbSynth.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDebug_Module.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDirPredictor.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDivExecQ.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDoubleDiv.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDoubleFMA.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDoubleSqrt.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkEpochManager.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkFetchStage.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkBtb.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkFmaExecQ.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkFpuMulDivDispToRegFifo.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkFpuMulDivRegToExeFifo.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkIBankWrapper.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkICRqMshrWrapper.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkICoCache.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkIPRqMshrWrapper.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkIPipeline.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkITlb.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkJtagTap.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkL2Tlb.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkLLCache.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkLLPipeline.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkLSQIssueLdQ.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkLastLvCRqMshr.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkMMIOInst.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkMemDispToRegFifo.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkMemRegToExeFifo.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkMinimumExecQ.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkMulExecQ.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkPLIC_16_CoreNumX2_7.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkProc.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkPerfCountersToooba.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkRFileSynth.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkRas.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkRegRenamingTable.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkReorderBufferSynth.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkReservationStationAlu.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkReservationStationFpuMulDiv.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkReservationStationMem.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkRobRowSynth.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkScoreboardAggr.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkScoreboardCons.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkSimpleRespQ.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkSoC_Map.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkSpecTagManager.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkSplitLSQ.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkSplitTransCache.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkStoreBufferEhr.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkDummyStoreBuffer.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkTourGHistReg.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkTourPred.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkXilinxFpDiv.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkXilinxFpDivIP.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkXilinxFpFma.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkXilinxFpFmaIP.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkXilinxFpSqrt.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkXilinxFpSqrtIP.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_alu.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_aluBr.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_amoExec.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_basicExec.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_brAddrCalc.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_checkForException.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_capChecksExec.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_capChecksMem.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_decode.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_decodeBrPred.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_execFpuSimple.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_capInspect.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_capModify.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_prepareBoundsCheck.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_setBoundsALU.v verilogSource IMPORTED_FILE ../Verilog_RTL/module_specialRWALU.v verilogSource IMPORTED_FILE ../Verilog_RTL/mkP3_Core.v verilogSource CHECKSUM_a15c10a8 IMPORTED_FILE src/int_mul_unsigned/int_mul_unsigned.xci xci IMPORTED_FILE src/int_mul_signed_unsigned/int_mul_signed_unsigned.xci xci IMPORTED_FILE src/int_mul_signed/int_mul_signed.xci xci IMPORTED_FILE src/int_div_unsigned/int_div_unsigned.xci xci IMPORTED_FILE src/fp_sqrt/fp_sqrt.xci xci IMPORTED_FILE src/fp_fma/fp_fma.xci xci IMPORTED_FILE src/fp_div/fp_div.xci xci IMPORTED_FILE xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_div_gen_5_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_floating_point_7_1__ref_view_fileset xilinx_xpgui_view_fileset xgui/ssith_processor_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 mkP3_Core_v1_0 Component_Name mkP3_Core_v1_0 virtexuplus /UserIP mkP3_Core_v1_0 package_project 2 user.org:user:mkP3_Core:1.0 2020-02-20T15:03:34Z /home/charlie/ssith_processor /home/charlie/ssith_processor /home/charlie/ssith_processor /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip 2019.1