// // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // // On Thu Jul 16 18:39:38 BST 2020 // // // Ports: // Name I/O size props // RDY_set_verbosity O 1 const // RDY_start O 1 // cpu_imem_master_awid O 6 // cpu_imem_master_awaddr O 64 // cpu_imem_master_awlen O 8 // cpu_imem_master_awsize O 3 // cpu_imem_master_awburst O 2 // cpu_imem_master_awlock O 1 // cpu_imem_master_awcache O 4 // cpu_imem_master_awprot O 3 // cpu_imem_master_awqos O 4 // cpu_imem_master_awregion O 4 // cpu_imem_master_awvalid O 1 // cpu_imem_master_wdata O 64 // cpu_imem_master_wstrb O 8 // cpu_imem_master_wlast O 1 // cpu_imem_master_wvalid O 1 // cpu_imem_master_bready O 1 // cpu_imem_master_arid O 6 // cpu_imem_master_araddr O 64 // cpu_imem_master_arlen O 8 // cpu_imem_master_arsize O 3 // cpu_imem_master_arburst O 2 // cpu_imem_master_arlock O 1 // cpu_imem_master_arcache O 4 // cpu_imem_master_arprot O 3 // cpu_imem_master_arqos O 4 // cpu_imem_master_arregion O 4 // cpu_imem_master_arvalid O 1 // cpu_imem_master_rready O 1 // cpu_dmem_master_awid O 6 // cpu_dmem_master_awaddr O 64 // cpu_dmem_master_awlen O 8 // cpu_dmem_master_awsize O 3 // cpu_dmem_master_awburst O 2 // cpu_dmem_master_awlock O 1 // cpu_dmem_master_awcache O 4 // cpu_dmem_master_awprot O 3 // cpu_dmem_master_awqos O 4 // cpu_dmem_master_awregion O 4 // cpu_dmem_master_awvalid O 1 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg // cpu_dmem_master_wvalid O 1 reg // cpu_dmem_master_bready O 1 reg // cpu_dmem_master_arid O 6 // cpu_dmem_master_araddr O 64 // cpu_dmem_master_arlen O 8 // cpu_dmem_master_arsize O 3 // cpu_dmem_master_arburst O 2 // cpu_dmem_master_arlock O 1 // cpu_dmem_master_arcache O 4 // cpu_dmem_master_arprot O 3 // cpu_dmem_master_arqos O 4 // cpu_dmem_master_arregion O 4 // cpu_dmem_master_arvalid O 1 reg // cpu_dmem_master_rready O 1 reg // RDY_dmi_read_addr O 1 // dmi_read_data O 32 // RDY_dmi_read_data O 1 // RDY_dmi_write O 1 // ndm_reset_client_request_get O 1 reg // RDY_ndm_reset_client_request_get O 1 reg // RDY_ndm_reset_client_response_put O 1 reg // RST_N_dm_power_on_reset I 1 reset // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused // start_is_running I 1 // start_tohost_addr I 64 // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 // cpu_imem_master_bid I 6 // cpu_imem_master_bresp I 2 // cpu_imem_master_arready I 1 // cpu_imem_master_rvalid I 1 // cpu_imem_master_rid I 6 // cpu_imem_master_rdata I 64 // cpu_imem_master_rresp I 2 // cpu_imem_master_rlast I 1 // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 // cpu_dmem_master_bvalid I 1 // cpu_dmem_master_bid I 6 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 // cpu_dmem_master_rvalid I 1 // cpu_dmem_master_rid I 6 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg // cpu_dmem_master_rlast I 1 reg // core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 // nmi_req_set_not_clear I 1 unused // dmi_read_addr_dm_addr I 7 reg // dmi_write_dm_addr I 7 // dmi_write_dm_word I 32 // ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 // EN_start I 1 // EN_dmi_read_addr I 1 // EN_dmi_write I 1 // EN_ndm_reset_client_response_put I 1 // EN_dmi_read_data I 1 // EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: // EN_dmi_read_data -> dmi_read_data // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkCoreW(RST_N_dm_power_on_reset, CLK, RST_N, set_verbosity_verbosity, set_verbosity_logdelay, EN_set_verbosity, RDY_set_verbosity, start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, RDY_start, cpu_imem_master_awid, cpu_imem_master_awaddr, cpu_imem_master_awlen, cpu_imem_master_awsize, cpu_imem_master_awburst, cpu_imem_master_awlock, cpu_imem_master_awcache, cpu_imem_master_awprot, cpu_imem_master_awqos, cpu_imem_master_awregion, cpu_imem_master_awvalid, cpu_imem_master_awready, cpu_imem_master_wdata, cpu_imem_master_wstrb, cpu_imem_master_wlast, cpu_imem_master_wvalid, cpu_imem_master_wready, cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, cpu_imem_master_bready, cpu_imem_master_arid, cpu_imem_master_araddr, cpu_imem_master_arlen, cpu_imem_master_arsize, cpu_imem_master_arburst, cpu_imem_master_arlock, cpu_imem_master_arcache, cpu_imem_master_arprot, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_arvalid, cpu_imem_master_arready, cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, cpu_imem_master_rready, cpu_dmem_master_awid, cpu_dmem_master_awaddr, cpu_dmem_master_awlen, cpu_dmem_master_awsize, cpu_dmem_master_awburst, cpu_dmem_master_awlock, cpu_dmem_master_awcache, cpu_dmem_master_awprot, cpu_dmem_master_awqos, cpu_dmem_master_awregion, cpu_dmem_master_awvalid, cpu_dmem_master_awready, cpu_dmem_master_wdata, cpu_dmem_master_wstrb, cpu_dmem_master_wlast, cpu_dmem_master_wvalid, cpu_dmem_master_wready, cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, cpu_dmem_master_bready, cpu_dmem_master_arid, cpu_dmem_master_araddr, cpu_dmem_master_arlen, cpu_dmem_master_arsize, cpu_dmem_master_arburst, cpu_dmem_master_arlock, cpu_dmem_master_arcache, cpu_dmem_master_arprot, cpu_dmem_master_arqos, cpu_dmem_master_arregion, cpu_dmem_master_arvalid, cpu_dmem_master_arready, cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, cpu_dmem_master_rready, core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, nmi_req_set_not_clear, dmi_read_addr_dm_addr, EN_dmi_read_addr, RDY_dmi_read_addr, EN_dmi_read_data, dmi_read_data, RDY_dmi_read_data, dmi_write_dm_addr, dmi_write_dm_word, EN_dmi_write, RDY_dmi_write, EN_ndm_reset_client_request_get, ndm_reset_client_request_get, RDY_ndm_reset_client_request_get, ndm_reset_client_response_put, EN_ndm_reset_client_response_put, RDY_ndm_reset_client_response_put); input RST_N_dm_power_on_reset; input CLK; input RST_N; // action method set_verbosity input [3 : 0] set_verbosity_verbosity; input [63 : 0] set_verbosity_logdelay; input EN_set_verbosity; output RDY_set_verbosity; // action method start input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; output RDY_start; // value method cpu_imem_master_aw_awid output [5 : 0] cpu_imem_master_awid; // value method cpu_imem_master_aw_awaddr output [63 : 0] cpu_imem_master_awaddr; // value method cpu_imem_master_aw_awlen output [7 : 0] cpu_imem_master_awlen; // value method cpu_imem_master_aw_awsize output [2 : 0] cpu_imem_master_awsize; // value method cpu_imem_master_aw_awburst output [1 : 0] cpu_imem_master_awburst; // value method cpu_imem_master_aw_awlock output cpu_imem_master_awlock; // value method cpu_imem_master_aw_awcache output [3 : 0] cpu_imem_master_awcache; // value method cpu_imem_master_aw_awprot output [2 : 0] cpu_imem_master_awprot; // value method cpu_imem_master_aw_awqos output [3 : 0] cpu_imem_master_awqos; // value method cpu_imem_master_aw_awregion output [3 : 0] cpu_imem_master_awregion; // value method cpu_imem_master_aw_awuser // value method cpu_imem_master_aw_awvalid output cpu_imem_master_awvalid; // action method cpu_imem_master_aw_awready input cpu_imem_master_awready; // value method cpu_imem_master_w_wdata output [63 : 0] cpu_imem_master_wdata; // value method cpu_imem_master_w_wstrb output [7 : 0] cpu_imem_master_wstrb; // value method cpu_imem_master_w_wlast output cpu_imem_master_wlast; // value method cpu_imem_master_w_wuser // value method cpu_imem_master_w_wvalid output cpu_imem_master_wvalid; // action method cpu_imem_master_w_wready input cpu_imem_master_wready; // action method cpu_imem_master_b_bflit input cpu_imem_master_bvalid; input [5 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; // value method cpu_imem_master_b_bready output cpu_imem_master_bready; // value method cpu_imem_master_ar_arid output [5 : 0] cpu_imem_master_arid; // value method cpu_imem_master_ar_araddr output [63 : 0] cpu_imem_master_araddr; // value method cpu_imem_master_ar_arlen output [7 : 0] cpu_imem_master_arlen; // value method cpu_imem_master_ar_arsize output [2 : 0] cpu_imem_master_arsize; // value method cpu_imem_master_ar_arburst output [1 : 0] cpu_imem_master_arburst; // value method cpu_imem_master_ar_arlock output cpu_imem_master_arlock; // value method cpu_imem_master_ar_arcache output [3 : 0] cpu_imem_master_arcache; // value method cpu_imem_master_ar_arprot output [2 : 0] cpu_imem_master_arprot; // value method cpu_imem_master_ar_arqos output [3 : 0] cpu_imem_master_arqos; // value method cpu_imem_master_ar_arregion output [3 : 0] cpu_imem_master_arregion; // value method cpu_imem_master_ar_aruser // value method cpu_imem_master_ar_arvalid output cpu_imem_master_arvalid; // action method cpu_imem_master_ar_arready input cpu_imem_master_arready; // action method cpu_imem_master_r_rflit input cpu_imem_master_rvalid; input [5 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; // value method cpu_imem_master_r_rready output cpu_imem_master_rready; // value method cpu_dmem_master_aw_awid output [5 : 0] cpu_dmem_master_awid; // value method cpu_dmem_master_aw_awaddr output [63 : 0] cpu_dmem_master_awaddr; // value method cpu_dmem_master_aw_awlen output [7 : 0] cpu_dmem_master_awlen; // value method cpu_dmem_master_aw_awsize output [2 : 0] cpu_dmem_master_awsize; // value method cpu_dmem_master_aw_awburst output [1 : 0] cpu_dmem_master_awburst; // value method cpu_dmem_master_aw_awlock output cpu_dmem_master_awlock; // value method cpu_dmem_master_aw_awcache output [3 : 0] cpu_dmem_master_awcache; // value method cpu_dmem_master_aw_awprot output [2 : 0] cpu_dmem_master_awprot; // value method cpu_dmem_master_aw_awqos output [3 : 0] cpu_dmem_master_awqos; // value method cpu_dmem_master_aw_awregion output [3 : 0] cpu_dmem_master_awregion; // value method cpu_dmem_master_aw_awuser // value method cpu_dmem_master_aw_awvalid output cpu_dmem_master_awvalid; // action method cpu_dmem_master_aw_awready input cpu_dmem_master_awready; // value method cpu_dmem_master_w_wdata output [63 : 0] cpu_dmem_master_wdata; // value method cpu_dmem_master_w_wstrb output [7 : 0] cpu_dmem_master_wstrb; // value method cpu_dmem_master_w_wlast output cpu_dmem_master_wlast; // value method cpu_dmem_master_w_wuser // value method cpu_dmem_master_w_wvalid output cpu_dmem_master_wvalid; // action method cpu_dmem_master_w_wready input cpu_dmem_master_wready; // action method cpu_dmem_master_b_bflit input cpu_dmem_master_bvalid; input [5 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; // value method cpu_dmem_master_b_bready output cpu_dmem_master_bready; // value method cpu_dmem_master_ar_arid output [5 : 0] cpu_dmem_master_arid; // value method cpu_dmem_master_ar_araddr output [63 : 0] cpu_dmem_master_araddr; // value method cpu_dmem_master_ar_arlen output [7 : 0] cpu_dmem_master_arlen; // value method cpu_dmem_master_ar_arsize output [2 : 0] cpu_dmem_master_arsize; // value method cpu_dmem_master_ar_arburst output [1 : 0] cpu_dmem_master_arburst; // value method cpu_dmem_master_ar_arlock output cpu_dmem_master_arlock; // value method cpu_dmem_master_ar_arcache output [3 : 0] cpu_dmem_master_arcache; // value method cpu_dmem_master_ar_arprot output [2 : 0] cpu_dmem_master_arprot; // value method cpu_dmem_master_ar_arqos output [3 : 0] cpu_dmem_master_arqos; // value method cpu_dmem_master_ar_arregion output [3 : 0] cpu_dmem_master_arregion; // value method cpu_dmem_master_ar_aruser // value method cpu_dmem_master_ar_arvalid output cpu_dmem_master_arvalid; // action method cpu_dmem_master_ar_arready input cpu_dmem_master_arready; // action method cpu_dmem_master_r_rflit input cpu_dmem_master_rvalid; input [5 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; // value method cpu_dmem_master_r_rready output cpu_dmem_master_rready; // action method core_external_interrupt_sources_0_m_interrupt_req input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_1_m_interrupt_req input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_2_m_interrupt_req input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_3_m_interrupt_req input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_4_m_interrupt_req input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_5_m_interrupt_req input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_6_m_interrupt_req input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_7_m_interrupt_req input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_8_m_interrupt_req input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_9_m_interrupt_req input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_10_m_interrupt_req input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_11_m_interrupt_req input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_12_m_interrupt_req input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_13_m_interrupt_req input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_14_m_interrupt_req input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; // action method nmi_req input nmi_req_set_not_clear; // action method dmi_read_addr input [6 : 0] dmi_read_addr_dm_addr; input EN_dmi_read_addr; output RDY_dmi_read_addr; // actionvalue method dmi_read_data input EN_dmi_read_data; output [31 : 0] dmi_read_data; output RDY_dmi_read_data; // action method dmi_write input [6 : 0] dmi_write_dm_addr; input [31 : 0] dmi_write_dm_word; input EN_dmi_write; output RDY_dmi_write; // actionvalue method ndm_reset_client_request_get input EN_ndm_reset_client_request_get; output ndm_reset_client_request_get; output RDY_ndm_reset_client_request_get; // action method ndm_reset_client_response_put input ndm_reset_client_response_put; input EN_ndm_reset_client_response_put; output RDY_ndm_reset_client_response_put; // signals for module outputs wire [63 : 0] cpu_dmem_master_araddr, cpu_dmem_master_awaddr, cpu_dmem_master_wdata, cpu_imem_master_araddr, cpu_imem_master_awaddr, cpu_imem_master_wdata; wire [31 : 0] dmi_read_data; wire [7 : 0] cpu_dmem_master_arlen, cpu_dmem_master_awlen, cpu_dmem_master_wstrb, cpu_imem_master_arlen, cpu_imem_master_awlen, cpu_imem_master_wstrb; wire [5 : 0] cpu_dmem_master_arid, cpu_dmem_master_awid, cpu_imem_master_arid, cpu_imem_master_awid; wire [3 : 0] cpu_dmem_master_arcache, cpu_dmem_master_arqos, cpu_dmem_master_arregion, cpu_dmem_master_awcache, cpu_dmem_master_awqos, cpu_dmem_master_awregion, cpu_imem_master_arcache, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_awcache, cpu_imem_master_awqos, cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, cpu_dmem_master_arsize, cpu_dmem_master_awprot, cpu_dmem_master_awsize, cpu_imem_master_arprot, cpu_imem_master_arsize, cpu_imem_master_awprot, cpu_imem_master_awsize; wire [1 : 0] cpu_dmem_master_arburst, cpu_dmem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst; wire RDY_dmi_read_addr, RDY_dmi_read_data, RDY_dmi_write, RDY_ndm_reset_client_request_get, RDY_ndm_reset_client_response_put, RDY_set_verbosity, RDY_start, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, cpu_dmem_master_awlock, cpu_dmem_master_awvalid, cpu_dmem_master_bready, cpu_dmem_master_rready, cpu_dmem_master_wlast, cpu_dmem_master_wvalid, cpu_imem_master_arlock, cpu_imem_master_arvalid, cpu_imem_master_awlock, cpu_imem_master_awvalid, cpu_imem_master_bready, cpu_imem_master_rready, cpu_imem_master_wlast, cpu_imem_master_wvalid, ndm_reset_client_request_get; // inlined wires wire [172 : 0] split_0_doPut$wget, split_1_doPut$wget, split_2_doPut$wget; wire [171 : 0] merged_0_outflit$wget, merged_1_outflit$wget; wire [99 : 0] tagController_tmp_shimMaster_arff_rv$port0__write_1, tagController_tmp_shimMaster_arff_rv$port1__read, tagController_tmp_shimMaster_arff_rv$port1__write_1, tagController_tmp_shimMaster_arff_rv$port2__read, tagController_tmp_shimMaster_arff_rv$port3__read, tagController_tmp_shimMaster_awff_rv$port0__write_1, tagController_tmp_shimMaster_awff_rv$port1__read, tagController_tmp_shimMaster_awff_rv$port2__read, tagController_tmp_shimMaster_awff_rv$port3__read; wire [98 : 0] tagController_tmp_shimSlave_arff_rv$port0__write_1, tagController_tmp_shimSlave_arff_rv$port1__read, tagController_tmp_shimSlave_arff_rv$port1__write_1, tagController_tmp_shimSlave_arff_rv$port2__read, tagController_tmp_shimSlave_arff_rv$port3__read, tagController_tmp_shimSlave_awff_rv$port0__write_1, tagController_tmp_shimSlave_awff_rv$port1__read, tagController_tmp_shimSlave_awff_rv$port2__read, tagController_tmp_shimSlave_awff_rv$port3__read, uncached_mem_master_arSynth_src_peekWire$wget, uncached_mem_master_awSynth_src_peekWire$wget; wire [97 : 0] slave_vector_0_arSynth_snk_putWire$wget, slave_vector_0_awSynth_snk_putWire$wget, ssNoSynth_0_arNoSynth_buffer_enqw$wget, ssNoSynth_1_arNoSynth_buffer_enqw$wget, ssNoSynth_1_arNoSynth_src_peekWire$wget, ssNoSynth_1_awNoSynth_src_peekWire$wget, ssNoSynth_2_arNoSynth_buffer_enqw$wget, ssNoSynth_2_arNoSynth_src_peekWire$wget, ssNoSynth_2_awNoSynth_src_peekWire$wget, tagController_tmp_ug_slave_u_ar_putWire$wget, tagController_tmp_ug_slave_u_aw_putWire$wget, tmp2_arNoSynth_buffer_enqw$wget, tmp2_awNoSynth_buffer_enqw$wget; wire [96 : 0] ifcs_0_1_noRoute_currentReq$port1__read, ifcs_0_noRoute_inner_currentReq$port1__read, ifcs_1_1_noRoute_currentReq$port1__read, ifcs_1_noRoute_inner_currentReq$port1__read, msNoSynth_1_arNoSynth_buffer_enqw$wget, msNoSynth_1_awNoSynth_buffer_enqw$wget; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, tagController_tmp_shimSlave_wff_rv$port1__read, tagController_tmp_shimSlave_wff_rv$port1__write_1, tagController_tmp_shimSlave_wff_rv$port2__read, tagController_tmp_shimSlave_wff_rv$port3__read; wire [73 : 0] msNoSynth_1_wNoSynth_buffer_enqw$wget, proc_uncached_wSynth_src_peekWire$wget, slave_vector_0_wSynth_snk_putWire$wget, ssNoSynth_1_wNoSynth_src_peekWire$wget, ssNoSynth_2_wNoSynth_src_peekWire$wget, tagController_tmp_shimMaster_rff_rv$port0__write_1, tagController_tmp_shimMaster_rff_rv$port1__read, tagController_tmp_shimMaster_rff_rv$port1__write_1, tagController_tmp_shimMaster_rff_rv$port2__read, tagController_tmp_shimMaster_rff_rv$port3__read, tagController_tmp_shimMaster_wff_rv$port0__write_1, tagController_tmp_shimMaster_wff_rv$port1__read, tagController_tmp_shimMaster_wff_rv$port2__read, tagController_tmp_shimMaster_wff_rv$port3__read, tagController_tmp_shimSlave_rff_rv$port0__write_1, tagController_tmp_shimSlave_rff_rv$port1__read, tagController_tmp_shimSlave_rff_rv$port2__read, tagController_tmp_shimSlave_rff_rv$port3__read, tagController_tmp_ug_slave_u_w_putWire$wget, tmp2_wNoSynth_buffer_enqw$wget; wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_enqw$wget, ssNoSynth_2_rNoSynth_buffer_enqw$wget, tagController_tmp_ug_master_u_r_putWire$wget, tmp2_rNoSynth_src_peekWire$wget, uncached_mem_master_rSynth_snk_putWire$wget; wire [71 : 0] msNoSynth_0_rNoSynth_buffer_enqw$wget, msNoSynth_1_rNoSynth_buffer_enqw$wget, msNoSynth_1_rNoSynth_src_peekWire$wget, proc_uncached_rSynth_snk_putWire$wget; wire [8 : 0] ifcs_0_1_noRoute_flitCount$port0__write_1, ifcs_0_1_noRoute_flitCount$port1__write_1, ifcs_0_1_noRoute_flitCount$port2__read, ifcs_1_1_noRoute_flitCount$port0__write_1, ifcs_1_1_noRoute_flitCount$port1__write_1, ifcs_1_1_noRoute_flitCount$port2__read, tagController_tmp_shimMaster_bff_rv$port0__write_1, tagController_tmp_shimMaster_bff_rv$port1__read, tagController_tmp_shimMaster_bff_rv$port1__write_1, tagController_tmp_shimMaster_bff_rv$port2__read, tagController_tmp_shimMaster_bff_rv$port3__read; wire [7 : 0] tagController_tmp_shimSlave_bff_rv$port0__write_1, tagController_tmp_shimSlave_bff_rv$port1__read, tagController_tmp_shimSlave_bff_rv$port1__write_1, tagController_tmp_shimSlave_bff_rv$port2__read, tagController_tmp_shimSlave_bff_rv$port3__read, tagController_tmp_ug_master_u_b_putWire$wget, uncached_mem_master_bSynth_snk_putWire$wget; wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_enqw$wget, ssNoSynth_2_bNoSynth_buffer_enqw$wget, tmp2_bNoSynth_src_peekWire$wget; wire [5 : 0] msNoSynth_0_bNoSynth_buffer_enqw$wget, msNoSynth_1_bNoSynth_buffer_enqw$wget, msNoSynth_1_bNoSynth_src_peekWire$wget, proc_uncached_bSynth_snk_putWire$wget; wire cached_mem_master_arSynth_src_dropWire$whas, cached_mem_master_awSynth_src_dropWire$whas, cached_mem_master_wSynth_src_dropWire$whas, flitToSink_0$whas, flitToSink_1$whas, flitToSink_1_0$whas, flitToSink_1_0_1$whas, flitToSink_1_1$whas, flitToSink_1_1_0$whas, flitToSink_1_1_1$whas, flitToSink_1_1_1_1$whas, flitToSink_1_2$whas, flitToSink_2$whas, ifcs_0_1_snk_putWire$whas, ifcs_0_noRoute_inner_currentReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$port1__read, ifcs_0_noRoute_inner_pendingReq$port2__read, ifcs_0_snk_putWire$whas, ifcs_1_1_snk_putWire$whas, ifcs_1_noRoute_inner_currentReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$port1__read, ifcs_1_noRoute_inner_pendingReq$port2__read, ifcs_1_snk_putWire$whas, merged_0_doDrop$whas, merged_1_doDrop$whas, msNoSynth_0_arNoSynth_buffer_dequeueing$whas, msNoSynth_1_arNoSynth_buffer_dequeueing$whas, reqWires_0$wget, reqWires_1$wget, reqWires_1_0$wget, reqWires_1_0_1$wget, reqWires_1_1$wget, reqWires_1_1_0$wget, reqWires_1_1_1$wget, reqWires_1_1_1_1$wget, reqWires_1_1_2$wget, reqWires_1_2$wget, sourceSelect_1_0$whas, sourceSelect_1_0_1$whas, sourceSelect_1_1$whas, sourceSelect_1_1_1$whas, sourceSelect_1_2$whas, ssNoSynth_0_bNoSynth_buffer_dequeueing$whas, ssNoSynth_0_rNoSynth_buffer_dequeueing$whas, ssNoSynth_0_wNoSynth_buffer_enqw$whas, ssNoSynth_1_bNoSynth_buffer_dequeueing$whas, ssNoSynth_1_rNoSynth_buffer_dequeueing$whas, ssNoSynth_1_wNoSynth_buffer_enqw$whas, ssNoSynth_2_bNoSynth_buffer_dequeueing$whas, ssNoSynth_2_rNoSynth_buffer_dequeueing$whas, ssNoSynth_2_wNoSynth_buffer_enqw$whas, tagController_tmp_shimMaster_arff_rv$EN_port0__write, tagController_tmp_shimMaster_awff_rv$EN_port0__write, tagController_tmp_shimMaster_wff_rv$EN_port0__write, tagController_tmp_shimSlave_bff_rv$EN_port0__write, tagController_tmp_shimSlave_rff_rv$EN_port0__write, uncached_mem_master_arSynth_src_dropWire$whas, uncached_mem_master_awSynth_src_dropWire$whas, uncached_mem_master_bSynth_snk_putWire$whas, uncached_mem_master_rSynth_snk_putWire$whas, uncached_mem_master_wSynth_src_dropWire$whas; // register activeSource_0 reg activeSource_0; wire activeSource_0$D_IN, activeSource_0$EN; // register activeSource_1 reg activeSource_1; wire activeSource_1$D_IN, activeSource_1$EN; // register activeSource_1_0 reg activeSource_1_0; wire activeSource_1_0$D_IN, activeSource_1_0$EN; // register activeSource_1_0_1 reg activeSource_1_0_1; wire activeSource_1_0_1$D_IN, activeSource_1_0_1$EN; // register activeSource_1_1 reg activeSource_1_1; wire activeSource_1_1$D_IN, activeSource_1_1$EN; // register activeSource_1_1_0 reg activeSource_1_1_0; reg activeSource_1_1_0$D_IN; wire activeSource_1_1_0$EN; // register activeSource_1_1_1 reg activeSource_1_1_1; wire activeSource_1_1_1$D_IN, activeSource_1_1_1$EN; // register activeSource_1_1_1_1 reg activeSource_1_1_1_1; reg activeSource_1_1_1_1$D_IN; wire activeSource_1_1_1_1$EN; // register activeSource_1_1_2 reg activeSource_1_1_2; reg activeSource_1_1_2$D_IN; wire activeSource_1_1_2$EN; // register activeSource_1_2 reg activeSource_1_2; wire activeSource_1_2$D_IN, activeSource_1_2$EN; // register arbiter_1_1_firstHot reg arbiter_1_1_firstHot; wire arbiter_1_1_firstHot$D_IN, arbiter_1_1_firstHot$EN; // register arbiter_1_1_lastSelect reg arbiter_1_1_lastSelect; wire arbiter_1_1_lastSelect$D_IN, arbiter_1_1_lastSelect$EN; // register arbiter_1_1_lastSelect_1 reg arbiter_1_1_lastSelect_1; wire arbiter_1_1_lastSelect_1$D_IN, arbiter_1_1_lastSelect_1$EN; // register arbiter_1_firstHot reg arbiter_1_firstHot; wire arbiter_1_firstHot$D_IN, arbiter_1_firstHot$EN; // register arbiter_1_firstHot_1 reg arbiter_1_firstHot_1; wire arbiter_1_firstHot_1$D_IN, arbiter_1_firstHot_1$EN; // register arbiter_1_lastSelect reg arbiter_1_lastSelect; wire arbiter_1_lastSelect$D_IN, arbiter_1_lastSelect$EN; // register arbiter_1_lastSelect_1 reg arbiter_1_lastSelect_1; wire arbiter_1_lastSelect_1$D_IN, arbiter_1_lastSelect_1$EN; // register arbiter_1_lastSelect_2 reg arbiter_1_lastSelect_2; wire arbiter_1_lastSelect_2$D_IN, arbiter_1_lastSelect_2$EN; // register arbiter_firstHot reg arbiter_firstHot; wire arbiter_firstHot$D_IN, arbiter_firstHot$EN; // register arbiter_lastSelect reg arbiter_lastSelect; wire arbiter_lastSelect$D_IN, arbiter_lastSelect$EN; // register ifcs_0_1_noRoute_currentReq reg [96 : 0] ifcs_0_1_noRoute_currentReq; wire [96 : 0] ifcs_0_1_noRoute_currentReq$D_IN; wire ifcs_0_1_noRoute_currentReq$EN; // register ifcs_0_1_noRoute_flitCount reg [8 : 0] ifcs_0_1_noRoute_flitCount; wire [8 : 0] ifcs_0_1_noRoute_flitCount$D_IN; wire ifcs_0_1_noRoute_flitCount$EN; // register ifcs_0_1_state reg [1 : 0] ifcs_0_1_state; wire [1 : 0] ifcs_0_1_state$D_IN; wire ifcs_0_1_state$EN; // register ifcs_0_1_state_1 reg ifcs_0_1_state_1; wire ifcs_0_1_state_1$D_IN, ifcs_0_1_state_1$EN; // register ifcs_0_noRoute_inner_currentReq reg [96 : 0] ifcs_0_noRoute_inner_currentReq; wire [96 : 0] ifcs_0_noRoute_inner_currentReq$D_IN; wire ifcs_0_noRoute_inner_currentReq$EN; // register ifcs_0_noRoute_inner_pendingReq reg ifcs_0_noRoute_inner_pendingReq; wire ifcs_0_noRoute_inner_pendingReq$D_IN, ifcs_0_noRoute_inner_pendingReq$EN; // register ifcs_0_state reg [1 : 0] ifcs_0_state; reg [1 : 0] ifcs_0_state$D_IN; wire ifcs_0_state$EN; // register ifcs_0_state_1 reg ifcs_0_state_1; wire ifcs_0_state_1$D_IN, ifcs_0_state_1$EN; // register ifcs_1_1_noRoute_currentReq reg [96 : 0] ifcs_1_1_noRoute_currentReq; wire [96 : 0] ifcs_1_1_noRoute_currentReq$D_IN; wire ifcs_1_1_noRoute_currentReq$EN; // register ifcs_1_1_noRoute_flitCount reg [8 : 0] ifcs_1_1_noRoute_flitCount; wire [8 : 0] ifcs_1_1_noRoute_flitCount$D_IN; wire ifcs_1_1_noRoute_flitCount$EN; // register ifcs_1_1_state reg [1 : 0] ifcs_1_1_state; wire [1 : 0] ifcs_1_1_state$D_IN; wire ifcs_1_1_state$EN; // register ifcs_1_1_state_1 reg ifcs_1_1_state_1; wire ifcs_1_1_state_1$D_IN, ifcs_1_1_state_1$EN; // register ifcs_1_noRoute_inner_currentReq reg [96 : 0] ifcs_1_noRoute_inner_currentReq; wire [96 : 0] ifcs_1_noRoute_inner_currentReq$D_IN; wire ifcs_1_noRoute_inner_currentReq$EN; // register ifcs_1_noRoute_inner_pendingReq reg ifcs_1_noRoute_inner_pendingReq; wire ifcs_1_noRoute_inner_pendingReq$D_IN, ifcs_1_noRoute_inner_pendingReq$EN; // register ifcs_1_state reg [1 : 0] ifcs_1_state; reg [1 : 0] ifcs_1_state$D_IN; wire ifcs_1_state$EN; // register ifcs_1_state_1 reg ifcs_1_state_1; wire ifcs_1_state_1$D_IN, ifcs_1_state_1$EN; // register ifcs_2_1_state reg ifcs_2_1_state; wire ifcs_2_1_state$D_IN, ifcs_2_1_state$EN; // register ifcs_2_state reg ifcs_2_state; wire ifcs_2_state$D_IN, ifcs_2_state$EN; // register merged_0_flitLeft reg [7 : 0] merged_0_flitLeft; wire [7 : 0] merged_0_flitLeft$D_IN; wire merged_0_flitLeft$EN; // register merged_1_flitLeft reg [7 : 0] merged_1_flitLeft; wire [7 : 0] merged_1_flitLeft$D_IN; wire merged_1_flitLeft$EN; // register rg_fromhost_addr reg [63 : 0] rg_fromhost_addr; wire [63 : 0] rg_fromhost_addr$D_IN; wire rg_fromhost_addr$EN; // register rg_hart0_reset_delay reg [7 : 0] rg_hart0_reset_delay; wire [7 : 0] rg_hart0_reset_delay$D_IN; wire rg_hart0_reset_delay$EN; // register rg_tohost_addr reg [63 : 0] rg_tohost_addr; wire [63 : 0] rg_tohost_addr$D_IN; wire rg_tohost_addr$EN; // register split_0_flitLeft reg [7 : 0] split_0_flitLeft; wire [7 : 0] split_0_flitLeft$D_IN; wire split_0_flitLeft$EN; // register split_1_flitLeft reg [7 : 0] split_1_flitLeft; wire [7 : 0] split_1_flitLeft$D_IN; wire split_1_flitLeft$EN; // register split_2_flitLeft reg [7 : 0] split_2_flitLeft; wire [7 : 0] split_2_flitLeft$D_IN; wire split_2_flitLeft$EN; // register state reg state; wire state$D_IN, state$EN; // register state_1 reg state_1; wire state_1$D_IN, state_1$EN; // register state_1_1 reg state_1_1; wire state_1_1$D_IN, state_1_1$EN; // register state_1_1_1 reg state_1_1_1; wire state_1_1_1$D_IN, state_1_1_1$EN; // register tagController_tmp_addrOffset reg [63 : 0] tagController_tmp_addrOffset; wire [63 : 0] tagController_tmp_addrOffset$D_IN; wire tagController_tmp_addrOffset$EN; // register tagController_tmp_doneSendingAW reg tagController_tmp_doneSendingAW; wire tagController_tmp_doneSendingAW$D_IN, tagController_tmp_doneSendingAW$EN; // register tagController_tmp_reset_done reg tagController_tmp_reset_done; wire tagController_tmp_reset_done$D_IN, tagController_tmp_reset_done$EN; // register tagController_tmp_shimMaster_arff_rv reg [99 : 0] tagController_tmp_shimMaster_arff_rv; wire [99 : 0] tagController_tmp_shimMaster_arff_rv$D_IN; wire tagController_tmp_shimMaster_arff_rv$EN; // register tagController_tmp_shimMaster_awff_rv reg [99 : 0] tagController_tmp_shimMaster_awff_rv; wire [99 : 0] tagController_tmp_shimMaster_awff_rv$D_IN; wire tagController_tmp_shimMaster_awff_rv$EN; // register tagController_tmp_shimMaster_bff_rv reg [8 : 0] tagController_tmp_shimMaster_bff_rv; wire [8 : 0] tagController_tmp_shimMaster_bff_rv$D_IN; wire tagController_tmp_shimMaster_bff_rv$EN; // register tagController_tmp_shimMaster_rff_rv reg [73 : 0] tagController_tmp_shimMaster_rff_rv; wire [73 : 0] tagController_tmp_shimMaster_rff_rv$D_IN; wire tagController_tmp_shimMaster_rff_rv$EN; // register tagController_tmp_shimMaster_wff_rv reg [73 : 0] tagController_tmp_shimMaster_wff_rv; wire [73 : 0] tagController_tmp_shimMaster_wff_rv$D_IN; wire tagController_tmp_shimMaster_wff_rv$EN; // register tagController_tmp_shimSlave_arff_rv reg [98 : 0] tagController_tmp_shimSlave_arff_rv; wire [98 : 0] tagController_tmp_shimSlave_arff_rv$D_IN; wire tagController_tmp_shimSlave_arff_rv$EN; // register tagController_tmp_shimSlave_awff_rv reg [98 : 0] tagController_tmp_shimSlave_awff_rv; wire [98 : 0] tagController_tmp_shimSlave_awff_rv$D_IN; wire tagController_tmp_shimSlave_awff_rv$EN; // register tagController_tmp_shimSlave_bff_rv reg [7 : 0] tagController_tmp_shimSlave_bff_rv; wire [7 : 0] tagController_tmp_shimSlave_bff_rv$D_IN; wire tagController_tmp_shimSlave_bff_rv$EN; // register tagController_tmp_shimSlave_rff_rv reg [73 : 0] tagController_tmp_shimSlave_rff_rv; wire [73 : 0] tagController_tmp_shimSlave_rff_rv$D_IN; wire tagController_tmp_shimSlave_rff_rv$EN; // register tagController_tmp_shimSlave_wff_rv reg [74 : 0] tagController_tmp_shimSlave_wff_rv; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$D_IN; wire tagController_tmp_shimSlave_wff_rv$EN; // ports of submodule debug_module wire [76 : 0] debug_module$hart0_csr_mem_client_request_get; wire [69 : 0] debug_module$hart0_gpr_mem_client_request_get; wire [64 : 0] debug_module$hart0_csr_mem_client_response_put, debug_module$hart0_fpr_mem_client_response_put, debug_module$hart0_gpr_mem_client_response_put; wire [63 : 0] debug_module$master_araddr, debug_module$master_awaddr, debug_module$master_rdata, debug_module$master_wdata; wire [31 : 0] debug_module$dmi_read_data, debug_module$dmi_write_dm_word; wire [7 : 0] debug_module$master_arlen, debug_module$master_awlen, debug_module$master_wstrb; wire [6 : 0] debug_module$dmi_read_addr_dm_addr, debug_module$dmi_write_dm_addr; wire [3 : 0] debug_module$hart0_get_other_req_get, debug_module$master_arcache, debug_module$master_arid, debug_module$master_arqos, debug_module$master_arregion, debug_module$master_awcache, debug_module$master_awid, debug_module$master_awqos, debug_module$master_awregion, debug_module$master_bid, debug_module$master_rid; wire [2 : 0] debug_module$master_arprot, debug_module$master_arsize, debug_module$master_awprot, debug_module$master_awsize; wire [1 : 0] debug_module$master_arburst, debug_module$master_awburst, debug_module$master_bresp, debug_module$master_rresp; wire debug_module$EN_dmi_read_addr, debug_module$EN_dmi_read_data, debug_module$EN_dmi_write, debug_module$EN_hart0_client_run_halt_request_get, debug_module$EN_hart0_client_run_halt_response_put, debug_module$EN_hart0_csr_mem_client_request_get, debug_module$EN_hart0_csr_mem_client_response_put, debug_module$EN_hart0_fpr_mem_client_request_get, debug_module$EN_hart0_fpr_mem_client_response_put, debug_module$EN_hart0_get_other_req_get, debug_module$EN_hart0_gpr_mem_client_request_get, debug_module$EN_hart0_gpr_mem_client_response_put, debug_module$EN_hart0_reset_client_request_get, debug_module$EN_hart0_reset_client_response_put, debug_module$EN_ndm_reset_client_request_get, debug_module$EN_ndm_reset_client_response_put, debug_module$RDY_dmi_read_addr, debug_module$RDY_dmi_read_data, debug_module$RDY_dmi_write, debug_module$RDY_hart0_client_run_halt_request_get, debug_module$RDY_hart0_client_run_halt_response_put, debug_module$RDY_hart0_csr_mem_client_request_get, debug_module$RDY_hart0_csr_mem_client_response_put, debug_module$RDY_hart0_get_other_req_get, debug_module$RDY_hart0_gpr_mem_client_request_get, debug_module$RDY_hart0_gpr_mem_client_response_put, debug_module$RDY_hart0_reset_client_request_get, debug_module$RDY_hart0_reset_client_response_put, debug_module$RDY_ndm_reset_client_request_get, debug_module$RDY_ndm_reset_client_response_put, debug_module$hart0_client_run_halt_request_get, debug_module$hart0_client_run_halt_response_put, debug_module$hart0_reset_client_response_put, debug_module$master_arlock, debug_module$master_arready, debug_module$master_arvalid, debug_module$master_awlock, debug_module$master_awready, debug_module$master_awvalid, debug_module$master_bready, debug_module$master_bvalid, debug_module$master_rlast, debug_module$master_rready, debug_module$master_ruser, debug_module$master_rvalid, debug_module$master_wlast, debug_module$master_wready, debug_module$master_wuser, debug_module$master_wvalid, debug_module$ndm_reset_client_request_get, debug_module$ndm_reset_client_response_put; // ports of submodule dm_hart0_reset_controller wire dm_hart0_reset_controller$ASSERT_IN, dm_hart0_reset_controller$OUT_RST; // ports of submodule hart0_reset wire hart0_reset$RST_OUT; // ports of submodule ifcs_0_1_innerReq wire [97 : 0] ifcs_0_1_innerReq$D_IN, ifcs_0_1_innerReq$D_OUT; wire ifcs_0_1_innerReq$CLR, ifcs_0_1_innerReq$DEQ, ifcs_0_1_innerReq$EMPTY_N, ifcs_0_1_innerReq$ENQ, ifcs_0_1_innerReq$FULL_N; // ports of submodule ifcs_0_1_innerRoute wire [2 : 0] ifcs_0_1_innerRoute$D_IN, ifcs_0_1_innerRoute$D_OUT; wire ifcs_0_1_innerRoute$CLR, ifcs_0_1_innerRoute$DEQ, ifcs_0_1_innerRoute$EMPTY_N, ifcs_0_1_innerRoute$ENQ, ifcs_0_1_innerRoute$FULL_N; // ports of submodule ifcs_0_1_noRouteRsp wire [71 : 0] ifcs_0_1_noRouteRsp$D_IN, ifcs_0_1_noRouteRsp$D_OUT; wire ifcs_0_1_noRouteRsp$CLR, ifcs_0_1_noRouteRsp$DEQ, ifcs_0_1_noRouteRsp$EMPTY_N, ifcs_0_1_noRouteRsp$ENQ, ifcs_0_1_noRouteRsp$FULL_N; // ports of submodule ifcs_0_1_routeBack wire [1 : 0] ifcs_0_1_routeBack$D_IN, ifcs_0_1_routeBack$D_OUT; wire ifcs_0_1_routeBack$CLR, ifcs_0_1_routeBack$DEQ, ifcs_0_1_routeBack$EMPTY_N, ifcs_0_1_routeBack$ENQ, ifcs_0_1_routeBack$FULL_N; // ports of submodule ifcs_0_1_rspBack wire [71 : 0] ifcs_0_1_rspBack$D_IN, ifcs_0_1_rspBack$D_OUT; wire ifcs_0_1_rspBack$CLR, ifcs_0_1_rspBack$DEQ, ifcs_0_1_rspBack$EMPTY_N, ifcs_0_1_rspBack$ENQ, ifcs_0_1_rspBack$FULL_N; // ports of submodule ifcs_0_innerReq wire [172 : 0] ifcs_0_innerReq$D_IN, ifcs_0_innerReq$D_OUT; wire ifcs_0_innerReq$CLR, ifcs_0_innerReq$DEQ, ifcs_0_innerReq$EMPTY_N, ifcs_0_innerReq$ENQ, ifcs_0_innerReq$FULL_N; // ports of submodule ifcs_0_innerRoute wire [2 : 0] ifcs_0_innerRoute$D_IN, ifcs_0_innerRoute$D_OUT; wire ifcs_0_innerRoute$CLR, ifcs_0_innerRoute$DEQ, ifcs_0_innerRoute$EMPTY_N, ifcs_0_innerRoute$ENQ, ifcs_0_innerRoute$FULL_N; // ports of submodule ifcs_0_noRouteRsp wire [5 : 0] ifcs_0_noRouteRsp$D_IN, ifcs_0_noRouteRsp$D_OUT; wire ifcs_0_noRouteRsp$CLR, ifcs_0_noRouteRsp$DEQ, ifcs_0_noRouteRsp$EMPTY_N, ifcs_0_noRouteRsp$ENQ, ifcs_0_noRouteRsp$FULL_N; // ports of submodule ifcs_0_routeBack wire [1 : 0] ifcs_0_routeBack$D_IN, ifcs_0_routeBack$D_OUT; wire ifcs_0_routeBack$CLR, ifcs_0_routeBack$DEQ, ifcs_0_routeBack$EMPTY_N, ifcs_0_routeBack$ENQ, ifcs_0_routeBack$FULL_N; // ports of submodule ifcs_0_rspBack wire [5 : 0] ifcs_0_rspBack$D_IN, ifcs_0_rspBack$D_OUT; wire ifcs_0_rspBack$CLR, ifcs_0_rspBack$DEQ, ifcs_0_rspBack$EMPTY_N, ifcs_0_rspBack$ENQ, ifcs_0_rspBack$FULL_N; // ports of submodule ifcs_1_1_innerReq wire [97 : 0] ifcs_1_1_innerReq$D_IN, ifcs_1_1_innerReq$D_OUT; wire ifcs_1_1_innerReq$CLR, ifcs_1_1_innerReq$DEQ, ifcs_1_1_innerReq$EMPTY_N, ifcs_1_1_innerReq$ENQ, ifcs_1_1_innerReq$FULL_N; // ports of submodule ifcs_1_1_innerRoute wire [2 : 0] ifcs_1_1_innerRoute$D_IN, ifcs_1_1_innerRoute$D_OUT; wire ifcs_1_1_innerRoute$CLR, ifcs_1_1_innerRoute$DEQ, ifcs_1_1_innerRoute$EMPTY_N, ifcs_1_1_innerRoute$ENQ, ifcs_1_1_innerRoute$FULL_N; // ports of submodule ifcs_1_1_noRouteRsp wire [71 : 0] ifcs_1_1_noRouteRsp$D_IN, ifcs_1_1_noRouteRsp$D_OUT; wire ifcs_1_1_noRouteRsp$CLR, ifcs_1_1_noRouteRsp$DEQ, ifcs_1_1_noRouteRsp$EMPTY_N, ifcs_1_1_noRouteRsp$ENQ, ifcs_1_1_noRouteRsp$FULL_N; // ports of submodule ifcs_1_1_routeBack wire [1 : 0] ifcs_1_1_routeBack$D_IN, ifcs_1_1_routeBack$D_OUT; wire ifcs_1_1_routeBack$CLR, ifcs_1_1_routeBack$DEQ, ifcs_1_1_routeBack$EMPTY_N, ifcs_1_1_routeBack$ENQ, ifcs_1_1_routeBack$FULL_N; // ports of submodule ifcs_1_1_rspBack wire [71 : 0] ifcs_1_1_rspBack$D_IN, ifcs_1_1_rspBack$D_OUT; wire ifcs_1_1_rspBack$CLR, ifcs_1_1_rspBack$DEQ, ifcs_1_1_rspBack$EMPTY_N, ifcs_1_1_rspBack$ENQ, ifcs_1_1_rspBack$FULL_N; // ports of submodule ifcs_1_innerReq wire [172 : 0] ifcs_1_innerReq$D_IN, ifcs_1_innerReq$D_OUT; wire ifcs_1_innerReq$CLR, ifcs_1_innerReq$DEQ, ifcs_1_innerReq$EMPTY_N, ifcs_1_innerReq$ENQ, ifcs_1_innerReq$FULL_N; // ports of submodule ifcs_1_innerRoute wire [2 : 0] ifcs_1_innerRoute$D_IN, ifcs_1_innerRoute$D_OUT; wire ifcs_1_innerRoute$CLR, ifcs_1_innerRoute$DEQ, ifcs_1_innerRoute$EMPTY_N, ifcs_1_innerRoute$ENQ, ifcs_1_innerRoute$FULL_N; // ports of submodule ifcs_1_noRouteRsp wire [5 : 0] ifcs_1_noRouteRsp$D_IN, ifcs_1_noRouteRsp$D_OUT; wire ifcs_1_noRouteRsp$CLR, ifcs_1_noRouteRsp$DEQ, ifcs_1_noRouteRsp$EMPTY_N, ifcs_1_noRouteRsp$ENQ, ifcs_1_noRouteRsp$FULL_N; // ports of submodule ifcs_1_routeBack wire [1 : 0] ifcs_1_routeBack$D_IN, ifcs_1_routeBack$D_OUT; wire ifcs_1_routeBack$CLR, ifcs_1_routeBack$DEQ, ifcs_1_routeBack$EMPTY_N, ifcs_1_routeBack$ENQ, ifcs_1_routeBack$FULL_N; // ports of submodule ifcs_1_rspBack wire [5 : 0] ifcs_1_rspBack$D_IN, ifcs_1_rspBack$D_OUT; wire ifcs_1_rspBack$CLR, ifcs_1_rspBack$DEQ, ifcs_1_rspBack$EMPTY_N, ifcs_1_rspBack$ENQ, ifcs_1_rspBack$FULL_N; // ports of submodule ifcs_2_1_routeBack wire [1 : 0] ifcs_2_1_routeBack$D_IN, ifcs_2_1_routeBack$D_OUT; wire ifcs_2_1_routeBack$CLR, ifcs_2_1_routeBack$DEQ, ifcs_2_1_routeBack$EMPTY_N, ifcs_2_1_routeBack$ENQ, ifcs_2_1_routeBack$FULL_N; // ports of submodule ifcs_2_1_rspBack wire [71 : 0] ifcs_2_1_rspBack$D_IN, ifcs_2_1_rspBack$D_OUT; wire ifcs_2_1_rspBack$CLR, ifcs_2_1_rspBack$DEQ, ifcs_2_1_rspBack$EMPTY_N, ifcs_2_1_rspBack$ENQ, ifcs_2_1_rspBack$FULL_N; // ports of submodule ifcs_2_routeBack wire [1 : 0] ifcs_2_routeBack$D_IN, ifcs_2_routeBack$D_OUT; wire ifcs_2_routeBack$CLR, ifcs_2_routeBack$DEQ, ifcs_2_routeBack$EMPTY_N, ifcs_2_routeBack$ENQ, ifcs_2_routeBack$FULL_N; // ports of submodule ifcs_2_rspBack wire [5 : 0] ifcs_2_rspBack$D_IN, ifcs_2_rspBack$D_OUT; wire ifcs_2_rspBack$CLR, ifcs_2_rspBack$DEQ, ifcs_2_rspBack$EMPTY_N, ifcs_2_rspBack$ENQ, ifcs_2_rspBack$FULL_N; // ports of submodule merged_0_awff wire [96 : 0] merged_0_awff$D_IN, merged_0_awff$D_OUT; wire merged_0_awff$CLR, merged_0_awff$DEQ, merged_0_awff$EMPTY_N, merged_0_awff$ENQ, merged_0_awff$FULL_N; // ports of submodule merged_0_wff wire [73 : 0] merged_0_wff$D_IN, merged_0_wff$D_OUT; wire merged_0_wff$CLR, merged_0_wff$DEQ, merged_0_wff$EMPTY_N, merged_0_wff$ENQ, merged_0_wff$FULL_N; // ports of submodule merged_1_awff wire [96 : 0] merged_1_awff$D_IN, merged_1_awff$D_OUT; wire merged_1_awff$CLR, merged_1_awff$DEQ, merged_1_awff$EMPTY_N, merged_1_awff$ENQ, merged_1_awff$FULL_N; // ports of submodule merged_1_wff wire [73 : 0] merged_1_wff$D_IN, merged_1_wff$D_OUT; wire merged_1_wff$CLR, merged_1_wff$DEQ, merged_1_wff$EMPTY_N, merged_1_wff$ENQ, merged_1_wff$FULL_N; // ports of submodule msNoSynth_0_arNoSynth_buffer_ff wire [96 : 0] msNoSynth_0_arNoSynth_buffer_ff$D_IN, msNoSynth_0_arNoSynth_buffer_ff$D_OUT; wire msNoSynth_0_arNoSynth_buffer_ff$CLR, msNoSynth_0_arNoSynth_buffer_ff$DEQ, msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, msNoSynth_0_arNoSynth_buffer_ff$ENQ, msNoSynth_0_arNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_0_arNoSynth_buffer_firstValid wire msNoSynth_0_arNoSynth_buffer_firstValid$D_IN, msNoSynth_0_arNoSynth_buffer_firstValid$EN, msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_0_awNoSynth_buffer_ff wire [96 : 0] msNoSynth_0_awNoSynth_buffer_ff$D_IN, msNoSynth_0_awNoSynth_buffer_ff$D_OUT; wire msNoSynth_0_awNoSynth_buffer_ff$CLR, msNoSynth_0_awNoSynth_buffer_ff$DEQ, msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, msNoSynth_0_awNoSynth_buffer_ff$ENQ, msNoSynth_0_awNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_0_awNoSynth_buffer_firstValid wire msNoSynth_0_awNoSynth_buffer_firstValid$D_IN, msNoSynth_0_awNoSynth_buffer_firstValid$EN, msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_0_bNoSynth_buffer_ff wire [5 : 0] msNoSynth_0_bNoSynth_buffer_ff$D_IN, msNoSynth_0_bNoSynth_buffer_ff$D_OUT; wire msNoSynth_0_bNoSynth_buffer_ff$CLR, msNoSynth_0_bNoSynth_buffer_ff$DEQ, msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, msNoSynth_0_bNoSynth_buffer_ff$ENQ, msNoSynth_0_bNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_0_bNoSynth_buffer_firstValid wire msNoSynth_0_bNoSynth_buffer_firstValid$D_IN, msNoSynth_0_bNoSynth_buffer_firstValid$EN, msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_0_rNoSynth_buffer_ff wire [71 : 0] msNoSynth_0_rNoSynth_buffer_ff$D_IN, msNoSynth_0_rNoSynth_buffer_ff$D_OUT; wire msNoSynth_0_rNoSynth_buffer_ff$CLR, msNoSynth_0_rNoSynth_buffer_ff$DEQ, msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, msNoSynth_0_rNoSynth_buffer_ff$ENQ, msNoSynth_0_rNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_0_rNoSynth_buffer_firstValid wire msNoSynth_0_rNoSynth_buffer_firstValid$D_IN, msNoSynth_0_rNoSynth_buffer_firstValid$EN, msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_0_wNoSynth_buffer_ff wire [73 : 0] msNoSynth_0_wNoSynth_buffer_ff$D_IN, msNoSynth_0_wNoSynth_buffer_ff$D_OUT; wire msNoSynth_0_wNoSynth_buffer_ff$CLR, msNoSynth_0_wNoSynth_buffer_ff$DEQ, msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, msNoSynth_0_wNoSynth_buffer_ff$ENQ, msNoSynth_0_wNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_0_wNoSynth_buffer_firstValid wire msNoSynth_0_wNoSynth_buffer_firstValid$D_IN, msNoSynth_0_wNoSynth_buffer_firstValid$EN, msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_1_arNoSynth_buffer_ff wire [96 : 0] msNoSynth_1_arNoSynth_buffer_ff$D_IN, msNoSynth_1_arNoSynth_buffer_ff$D_OUT; wire msNoSynth_1_arNoSynth_buffer_ff$CLR, msNoSynth_1_arNoSynth_buffer_ff$DEQ, msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, msNoSynth_1_arNoSynth_buffer_ff$ENQ, msNoSynth_1_arNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_1_arNoSynth_buffer_firstValid wire msNoSynth_1_arNoSynth_buffer_firstValid$D_IN, msNoSynth_1_arNoSynth_buffer_firstValid$EN, msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_1_awNoSynth_buffer_ff wire [96 : 0] msNoSynth_1_awNoSynth_buffer_ff$D_IN, msNoSynth_1_awNoSynth_buffer_ff$D_OUT; wire msNoSynth_1_awNoSynth_buffer_ff$CLR, msNoSynth_1_awNoSynth_buffer_ff$DEQ, msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, msNoSynth_1_awNoSynth_buffer_ff$ENQ, msNoSynth_1_awNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_1_awNoSynth_buffer_firstValid wire msNoSynth_1_awNoSynth_buffer_firstValid$D_IN, msNoSynth_1_awNoSynth_buffer_firstValid$EN, msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_1_bNoSynth_buffer_ff wire [5 : 0] msNoSynth_1_bNoSynth_buffer_ff$D_IN, msNoSynth_1_bNoSynth_buffer_ff$D_OUT; wire msNoSynth_1_bNoSynth_buffer_ff$CLR, msNoSynth_1_bNoSynth_buffer_ff$DEQ, msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, msNoSynth_1_bNoSynth_buffer_ff$ENQ, msNoSynth_1_bNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_1_bNoSynth_buffer_firstValid wire msNoSynth_1_bNoSynth_buffer_firstValid$D_IN, msNoSynth_1_bNoSynth_buffer_firstValid$EN, msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_1_rNoSynth_buffer_ff wire [71 : 0] msNoSynth_1_rNoSynth_buffer_ff$D_IN, msNoSynth_1_rNoSynth_buffer_ff$D_OUT; wire msNoSynth_1_rNoSynth_buffer_ff$CLR, msNoSynth_1_rNoSynth_buffer_ff$DEQ, msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, msNoSynth_1_rNoSynth_buffer_ff$ENQ, msNoSynth_1_rNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_1_rNoSynth_buffer_firstValid wire msNoSynth_1_rNoSynth_buffer_firstValid$D_IN, msNoSynth_1_rNoSynth_buffer_firstValid$EN, msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; // ports of submodule msNoSynth_1_wNoSynth_buffer_ff wire [73 : 0] msNoSynth_1_wNoSynth_buffer_ff$D_IN, msNoSynth_1_wNoSynth_buffer_ff$D_OUT; wire msNoSynth_1_wNoSynth_buffer_ff$CLR, msNoSynth_1_wNoSynth_buffer_ff$DEQ, msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, msNoSynth_1_wNoSynth_buffer_ff$ENQ, msNoSynth_1_wNoSynth_buffer_ff$FULL_N; // ports of submodule msNoSynth_1_wNoSynth_buffer_firstValid wire msNoSynth_1_wNoSynth_buffer_firstValid$D_IN, msNoSynth_1_wNoSynth_buffer_firstValid$EN, msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, plic$axi4_slave_awaddr, plic$axi4_slave_rdata, plic$axi4_slave_wdata, plic$set_addr_map_addr_base, plic$set_addr_map_addr_lim; wire [7 : 0] plic$axi4_slave_arlen, plic$axi4_slave_awlen, plic$axi4_slave_wstrb; wire [4 : 0] plic$axi4_slave_arid, plic$axi4_slave_awid, plic$axi4_slave_bid, plic$axi4_slave_rid; wire [3 : 0] plic$axi4_slave_arcache, plic$axi4_slave_arqos, plic$axi4_slave_arregion, plic$axi4_slave_awcache, plic$axi4_slave_awqos, plic$axi4_slave_awregion, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, plic$axi4_slave_awprot, plic$axi4_slave_awsize; wire [1 : 0] plic$axi4_slave_arburst, plic$axi4_slave_awburst, plic$axi4_slave_bresp, plic$axi4_slave_rresp; wire plic$EN_server_reset_request_put, plic$EN_server_reset_response_get, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, plic$axi4_slave_awlock, plic$axi4_slave_awready, plic$axi4_slave_awvalid, plic$axi4_slave_bready, plic$axi4_slave_bvalid, plic$axi4_slave_rlast, plic$axi4_slave_rready, plic$axi4_slave_ruser, plic$axi4_slave_rvalid, plic$axi4_slave_wlast, plic$axi4_slave_wready, plic$axi4_slave_wuser, plic$axi4_slave_wvalid, plic$v_sources_0_m_interrupt_req_set_not_clear, plic$v_sources_10_m_interrupt_req_set_not_clear, plic$v_sources_11_m_interrupt_req_set_not_clear, plic$v_sources_12_m_interrupt_req_set_not_clear, plic$v_sources_13_m_interrupt_req_set_not_clear, plic$v_sources_14_m_interrupt_req_set_not_clear, plic$v_sources_15_m_interrupt_req_set_not_clear, plic$v_sources_1_m_interrupt_req_set_not_clear, plic$v_sources_2_m_interrupt_req_set_not_clear, plic$v_sources_3_m_interrupt_req_set_not_clear, plic$v_sources_4_m_interrupt_req_set_not_clear, plic$v_sources_5_m_interrupt_req_set_not_clear, plic$v_sources_6_m_interrupt_req_set_not_clear, plic$v_sources_7_m_interrupt_req_set_not_clear, plic$v_sources_8_m_interrupt_req_set_not_clear, plic$v_sources_9_m_interrupt_req_set_not_clear, plic$v_targets_0_m_eip, plic$v_targets_1_m_eip; // ports of submodule proc wire [96 : 0] proc$master1_ar_peek, proc$master1_aw_peek; wire [76 : 0] proc$hart0_csr_mem_server_request_put; wire [73 : 0] proc$master1_w_peek; wire [71 : 0] proc$master1_r_put_val; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; wire [64 : 0] proc$hart0_csr_mem_server_response_get, proc$hart0_gpr_mem_server_response_get; wire [63 : 0] proc$debug_module_mem_server_araddr, proc$debug_module_mem_server_awaddr, proc$debug_module_mem_server_rdata, proc$debug_module_mem_server_wdata, proc$master0_araddr, proc$master0_awaddr, proc$master0_rdata, proc$master0_wdata, proc$start_fromhostAddr, proc$start_startpc, proc$start_tohostAddr; wire [7 : 0] proc$debug_module_mem_server_arlen, proc$debug_module_mem_server_awlen, proc$debug_module_mem_server_wstrb, proc$master0_arlen, proc$master0_awlen, proc$master0_wstrb; wire [5 : 0] proc$master1_b_put_val; wire [4 : 0] proc$debug_module_mem_server_arid, proc$debug_module_mem_server_awid, proc$debug_module_mem_server_bid, proc$debug_module_mem_server_rid, proc$master0_arid, proc$master0_awid, proc$master0_bid, proc$master0_rid; wire [3 : 0] proc$debug_module_mem_server_arcache, proc$debug_module_mem_server_arqos, proc$debug_module_mem_server_arregion, proc$debug_module_mem_server_awcache, proc$debug_module_mem_server_awqos, proc$debug_module_mem_server_awregion, proc$hart0_put_other_req_put, proc$master0_arcache, proc$master0_arqos, proc$master0_arregion, proc$master0_awcache, proc$master0_awqos, proc$master0_awregion, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, proc$debug_module_mem_server_awprot, proc$debug_module_mem_server_awsize, proc$master0_arprot, proc$master0_arsize, proc$master0_awprot, proc$master0_awsize; wire [1 : 0] proc$debug_module_mem_server_arburst, proc$debug_module_mem_server_awburst, proc$debug_module_mem_server_bresp, proc$debug_module_mem_server_rresp, proc$master0_arburst, proc$master0_awburst, proc$master0_bresp, proc$master0_rresp; wire proc$EN_hart0_csr_mem_server_request_put, proc$EN_hart0_csr_mem_server_response_get, proc$EN_hart0_fpr_mem_server_request_put, proc$EN_hart0_fpr_mem_server_response_get, proc$EN_hart0_gpr_mem_server_request_put, proc$EN_hart0_gpr_mem_server_response_get, proc$EN_hart0_put_other_req_put, proc$EN_hart0_run_halt_server_request_put, proc$EN_hart0_run_halt_server_response_get, proc$EN_master1_ar_drop, proc$EN_master1_aw_drop, proc$EN_master1_b_put, proc$EN_master1_r_put, proc$EN_master1_w_drop, proc$EN_set_verbosity, proc$EN_start, proc$RDY_hart0_csr_mem_server_request_put, proc$RDY_hart0_csr_mem_server_response_get, proc$RDY_hart0_gpr_mem_server_request_put, proc$RDY_hart0_gpr_mem_server_response_get, proc$RDY_hart0_run_halt_server_request_put, proc$RDY_hart0_run_halt_server_response_get, proc$RDY_master1_ar_drop, proc$RDY_master1_ar_peek, proc$RDY_master1_aw_drop, proc$RDY_master1_aw_peek, proc$RDY_master1_b_put, proc$RDY_master1_r_put, proc$RDY_master1_w_drop, proc$RDY_master1_w_peek, proc$RDY_start, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, proc$debug_module_mem_server_arvalid, proc$debug_module_mem_server_awlock, proc$debug_module_mem_server_awready, proc$debug_module_mem_server_awvalid, proc$debug_module_mem_server_bready, proc$debug_module_mem_server_bvalid, proc$debug_module_mem_server_rlast, proc$debug_module_mem_server_rready, proc$debug_module_mem_server_ruser, proc$debug_module_mem_server_rvalid, proc$debug_module_mem_server_wlast, proc$debug_module_mem_server_wready, proc$debug_module_mem_server_wuser, proc$debug_module_mem_server_wvalid, proc$hart0_run_halt_server_request_put, proc$hart0_run_halt_server_response_get, proc$m_external_interrupt_req_set_not_clear, proc$master0_arlock, proc$master0_arready, proc$master0_arvalid, proc$master0_awlock, proc$master0_awready, proc$master0_awvalid, proc$master0_bready, proc$master0_bvalid, proc$master0_rlast, proc$master0_rready, proc$master0_ruser, proc$master0_rvalid, proc$master0_wlast, proc$master0_wready, proc$master0_wuser, proc$master0_wvalid, proc$master1_ar_canPeek, proc$master1_aw_canPeek, proc$master1_b_canPut, proc$master1_r_canPut, proc$master1_w_canPeek, proc$non_maskable_interrupt_req_set_not_clear, proc$s_external_interrupt_req_set_not_clear, proc$start_running; // ports of submodule soc_map wire [127 : 0] soc_map$m_mem0_controller_addr_range, soc_map$m_plic_addr_range; wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr; wire soc_map$m_is_IO_addr_imem_not_dmem; // ports of submodule ssNoSynth_0_arNoSynth_buffer_ff wire [97 : 0] ssNoSynth_0_arNoSynth_buffer_ff$D_IN, ssNoSynth_0_arNoSynth_buffer_ff$D_OUT; wire ssNoSynth_0_arNoSynth_buffer_ff$CLR, ssNoSynth_0_arNoSynth_buffer_ff$DEQ, ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, ssNoSynth_0_arNoSynth_buffer_ff$ENQ, ssNoSynth_0_arNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_0_arNoSynth_buffer_firstValid wire ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN, ssNoSynth_0_arNoSynth_buffer_firstValid$EN, ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_0_awNoSynth_buffer_ff wire [97 : 0] ssNoSynth_0_awNoSynth_buffer_ff$D_IN, ssNoSynth_0_awNoSynth_buffer_ff$D_OUT; wire ssNoSynth_0_awNoSynth_buffer_ff$CLR, ssNoSynth_0_awNoSynth_buffer_ff$DEQ, ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, ssNoSynth_0_awNoSynth_buffer_ff$ENQ, ssNoSynth_0_awNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_0_awNoSynth_buffer_firstValid wire ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN, ssNoSynth_0_awNoSynth_buffer_firstValid$EN, ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_0_bNoSynth_buffer_ff wire [6 : 0] ssNoSynth_0_bNoSynth_buffer_ff$D_IN, ssNoSynth_0_bNoSynth_buffer_ff$D_OUT; wire ssNoSynth_0_bNoSynth_buffer_ff$CLR, ssNoSynth_0_bNoSynth_buffer_ff$DEQ, ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, ssNoSynth_0_bNoSynth_buffer_ff$ENQ, ssNoSynth_0_bNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_0_bNoSynth_buffer_firstValid wire ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN, ssNoSynth_0_bNoSynth_buffer_firstValid$EN, ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_0_rNoSynth_buffer_ff wire [72 : 0] ssNoSynth_0_rNoSynth_buffer_ff$D_IN, ssNoSynth_0_rNoSynth_buffer_ff$D_OUT; wire ssNoSynth_0_rNoSynth_buffer_ff$CLR, ssNoSynth_0_rNoSynth_buffer_ff$DEQ, ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, ssNoSynth_0_rNoSynth_buffer_ff$ENQ, ssNoSynth_0_rNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_0_rNoSynth_buffer_firstValid wire ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN, ssNoSynth_0_rNoSynth_buffer_firstValid$EN, ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_0_wNoSynth_buffer_ff wire [73 : 0] ssNoSynth_0_wNoSynth_buffer_ff$D_IN, ssNoSynth_0_wNoSynth_buffer_ff$D_OUT; wire ssNoSynth_0_wNoSynth_buffer_ff$CLR, ssNoSynth_0_wNoSynth_buffer_ff$DEQ, ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, ssNoSynth_0_wNoSynth_buffer_ff$ENQ, ssNoSynth_0_wNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_0_wNoSynth_buffer_firstValid wire ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN, ssNoSynth_0_wNoSynth_buffer_firstValid$EN, ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_1_arNoSynth_buffer_ff wire [97 : 0] ssNoSynth_1_arNoSynth_buffer_ff$D_IN, ssNoSynth_1_arNoSynth_buffer_ff$D_OUT; wire ssNoSynth_1_arNoSynth_buffer_ff$CLR, ssNoSynth_1_arNoSynth_buffer_ff$DEQ, ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, ssNoSynth_1_arNoSynth_buffer_ff$ENQ, ssNoSynth_1_arNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_1_arNoSynth_buffer_firstValid wire ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN, ssNoSynth_1_arNoSynth_buffer_firstValid$EN, ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_1_awNoSynth_buffer_ff wire [97 : 0] ssNoSynth_1_awNoSynth_buffer_ff$D_IN, ssNoSynth_1_awNoSynth_buffer_ff$D_OUT; wire ssNoSynth_1_awNoSynth_buffer_ff$CLR, ssNoSynth_1_awNoSynth_buffer_ff$DEQ, ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, ssNoSynth_1_awNoSynth_buffer_ff$ENQ, ssNoSynth_1_awNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_1_awNoSynth_buffer_firstValid wire ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN, ssNoSynth_1_awNoSynth_buffer_firstValid$EN, ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_1_bNoSynth_buffer_ff wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_ff$D_IN, ssNoSynth_1_bNoSynth_buffer_ff$D_OUT; wire ssNoSynth_1_bNoSynth_buffer_ff$CLR, ssNoSynth_1_bNoSynth_buffer_ff$DEQ, ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, ssNoSynth_1_bNoSynth_buffer_ff$ENQ, ssNoSynth_1_bNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_1_bNoSynth_buffer_firstValid wire ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN, ssNoSynth_1_bNoSynth_buffer_firstValid$EN, ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_1_rNoSynth_buffer_ff wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_ff$D_IN, ssNoSynth_1_rNoSynth_buffer_ff$D_OUT; wire ssNoSynth_1_rNoSynth_buffer_ff$CLR, ssNoSynth_1_rNoSynth_buffer_ff$DEQ, ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, ssNoSynth_1_rNoSynth_buffer_ff$ENQ, ssNoSynth_1_rNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_1_rNoSynth_buffer_firstValid wire ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN, ssNoSynth_1_rNoSynth_buffer_firstValid$EN, ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_1_wNoSynth_buffer_ff wire [73 : 0] ssNoSynth_1_wNoSynth_buffer_ff$D_IN, ssNoSynth_1_wNoSynth_buffer_ff$D_OUT; wire ssNoSynth_1_wNoSynth_buffer_ff$CLR, ssNoSynth_1_wNoSynth_buffer_ff$DEQ, ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, ssNoSynth_1_wNoSynth_buffer_ff$ENQ, ssNoSynth_1_wNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_1_wNoSynth_buffer_firstValid wire ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN, ssNoSynth_1_wNoSynth_buffer_firstValid$EN, ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_2_arNoSynth_buffer_ff wire [97 : 0] ssNoSynth_2_arNoSynth_buffer_ff$D_IN, ssNoSynth_2_arNoSynth_buffer_ff$D_OUT; wire ssNoSynth_2_arNoSynth_buffer_ff$CLR, ssNoSynth_2_arNoSynth_buffer_ff$DEQ, ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N, ssNoSynth_2_arNoSynth_buffer_ff$ENQ, ssNoSynth_2_arNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_2_arNoSynth_buffer_firstValid wire ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN, ssNoSynth_2_arNoSynth_buffer_firstValid$EN, ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_2_awNoSynth_buffer_ff wire [97 : 0] ssNoSynth_2_awNoSynth_buffer_ff$D_IN, ssNoSynth_2_awNoSynth_buffer_ff$D_OUT; wire ssNoSynth_2_awNoSynth_buffer_ff$CLR, ssNoSynth_2_awNoSynth_buffer_ff$DEQ, ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N, ssNoSynth_2_awNoSynth_buffer_ff$ENQ, ssNoSynth_2_awNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_2_awNoSynth_buffer_firstValid wire ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN, ssNoSynth_2_awNoSynth_buffer_firstValid$EN, ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_2_bNoSynth_buffer_ff wire [6 : 0] ssNoSynth_2_bNoSynth_buffer_ff$D_IN, ssNoSynth_2_bNoSynth_buffer_ff$D_OUT; wire ssNoSynth_2_bNoSynth_buffer_ff$CLR, ssNoSynth_2_bNoSynth_buffer_ff$DEQ, ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N, ssNoSynth_2_bNoSynth_buffer_ff$ENQ, ssNoSynth_2_bNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_2_bNoSynth_buffer_firstValid wire ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN, ssNoSynth_2_bNoSynth_buffer_firstValid$EN, ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_2_rNoSynth_buffer_ff wire [72 : 0] ssNoSynth_2_rNoSynth_buffer_ff$D_IN, ssNoSynth_2_rNoSynth_buffer_ff$D_OUT; wire ssNoSynth_2_rNoSynth_buffer_ff$CLR, ssNoSynth_2_rNoSynth_buffer_ff$DEQ, ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N, ssNoSynth_2_rNoSynth_buffer_ff$ENQ, ssNoSynth_2_rNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_2_rNoSynth_buffer_firstValid wire ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN, ssNoSynth_2_rNoSynth_buffer_firstValid$EN, ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT; // ports of submodule ssNoSynth_2_wNoSynth_buffer_ff wire [73 : 0] ssNoSynth_2_wNoSynth_buffer_ff$D_IN, ssNoSynth_2_wNoSynth_buffer_ff$D_OUT; wire ssNoSynth_2_wNoSynth_buffer_ff$CLR, ssNoSynth_2_wNoSynth_buffer_ff$DEQ, ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N, ssNoSynth_2_wNoSynth_buffer_ff$ENQ, ssNoSynth_2_wNoSynth_buffer_ff$FULL_N; // ports of submodule ssNoSynth_2_wNoSynth_buffer_firstValid wire ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN, ssNoSynth_2_wNoSynth_buffer_firstValid$EN, ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tagController_tmp_awreqff wire [97 : 0] tagController_tmp_awreqff$D_IN, tagController_tmp_awreqff$D_OUT; wire tagController_tmp_awreqff$CLR, tagController_tmp_awreqff$DEQ, tagController_tmp_awreqff$EMPTY_N, tagController_tmp_awreqff$ENQ, tagController_tmp_awreqff$FULL_N; // ports of submodule tagController_tmp_newRst wire tagController_tmp_newRst$ASSERT_IN, tagController_tmp_newRst$OUT_RST; // ports of submodule tagController_tmp_tagCon wire [140 : 0] tagController_tmp_tagCon$cache_request_put_val, tagController_tmp_tagCon$memory_request_get; wire [76 : 0] tagController_tmp_tagCon$cache_response_get, tagController_tmp_tagCon$memory_response_put_val; wire tagController_tmp_tagCon$EN_cache_request_put, tagController_tmp_tagCon$EN_cache_response_get, tagController_tmp_tagCon$EN_memory_request_get, tagController_tmp_tagCon$EN_memory_response_put, tagController_tmp_tagCon$RDY_cache_request_put, tagController_tmp_tagCon$RDY_cache_response_get, tagController_tmp_tagCon$RDY_memory_request_get, tagController_tmp_tagCon$RDY_memory_response_put; // ports of submodule tmp2_arNoSynth_buffer_ff wire [97 : 0] tmp2_arNoSynth_buffer_ff$D_IN, tmp2_arNoSynth_buffer_ff$D_OUT; wire tmp2_arNoSynth_buffer_ff$CLR, tmp2_arNoSynth_buffer_ff$DEQ, tmp2_arNoSynth_buffer_ff$EMPTY_N, tmp2_arNoSynth_buffer_ff$ENQ, tmp2_arNoSynth_buffer_ff$FULL_N; // ports of submodule tmp2_arNoSynth_buffer_firstValid wire tmp2_arNoSynth_buffer_firstValid$D_IN, tmp2_arNoSynth_buffer_firstValid$EN, tmp2_arNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tmp2_awNoSynth_buffer_ff wire [97 : 0] tmp2_awNoSynth_buffer_ff$D_IN, tmp2_awNoSynth_buffer_ff$D_OUT; wire tmp2_awNoSynth_buffer_ff$CLR, tmp2_awNoSynth_buffer_ff$DEQ, tmp2_awNoSynth_buffer_ff$EMPTY_N, tmp2_awNoSynth_buffer_ff$ENQ, tmp2_awNoSynth_buffer_ff$FULL_N; // ports of submodule tmp2_awNoSynth_buffer_firstValid wire tmp2_awNoSynth_buffer_firstValid$D_IN, tmp2_awNoSynth_buffer_firstValid$EN, tmp2_awNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tmp2_bNoSynth_buffer_ff wire [6 : 0] tmp2_bNoSynth_buffer_ff$D_IN, tmp2_bNoSynth_buffer_ff$D_OUT; wire tmp2_bNoSynth_buffer_ff$CLR, tmp2_bNoSynth_buffer_ff$DEQ, tmp2_bNoSynth_buffer_ff$EMPTY_N, tmp2_bNoSynth_buffer_ff$ENQ, tmp2_bNoSynth_buffer_ff$FULL_N; // ports of submodule tmp2_bNoSynth_buffer_firstValid wire tmp2_bNoSynth_buffer_firstValid$D_IN, tmp2_bNoSynth_buffer_firstValid$EN, tmp2_bNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tmp2_rNoSynth_buffer_ff wire [72 : 0] tmp2_rNoSynth_buffer_ff$D_IN, tmp2_rNoSynth_buffer_ff$D_OUT; wire tmp2_rNoSynth_buffer_ff$CLR, tmp2_rNoSynth_buffer_ff$DEQ, tmp2_rNoSynth_buffer_ff$EMPTY_N, tmp2_rNoSynth_buffer_ff$ENQ, tmp2_rNoSynth_buffer_ff$FULL_N; // ports of submodule tmp2_rNoSynth_buffer_firstValid wire tmp2_rNoSynth_buffer_firstValid$D_IN, tmp2_rNoSynth_buffer_firstValid$EN, tmp2_rNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tmp2_wNoSynth_buffer_ff wire [73 : 0] tmp2_wNoSynth_buffer_ff$D_IN, tmp2_wNoSynth_buffer_ff$D_OUT; wire tmp2_wNoSynth_buffer_ff$CLR, tmp2_wNoSynth_buffer_ff$DEQ, tmp2_wNoSynth_buffer_ff$EMPTY_N, tmp2_wNoSynth_buffer_ff$ENQ, tmp2_wNoSynth_buffer_ff$FULL_N; // ports of submodule tmp2_wNoSynth_buffer_firstValid wire tmp2_wNoSynth_buffer_firstValid$D_IN, tmp2_wNoSynth_buffer_firstValid$EN, tmp2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule uncached_mem_shim_arff wire [97 : 0] uncached_mem_shim_arff$D_IN, uncached_mem_shim_arff$D_OUT; wire uncached_mem_shim_arff$CLR, uncached_mem_shim_arff$DEQ, uncached_mem_shim_arff$EMPTY_N, uncached_mem_shim_arff$ENQ, uncached_mem_shim_arff$FULL_N; // ports of submodule uncached_mem_shim_awff wire [97 : 0] uncached_mem_shim_awff$D_IN, uncached_mem_shim_awff$D_OUT; wire uncached_mem_shim_awff$CLR, uncached_mem_shim_awff$DEQ, uncached_mem_shim_awff$EMPTY_N, uncached_mem_shim_awff$ENQ, uncached_mem_shim_awff$FULL_N; // ports of submodule uncached_mem_shim_bff wire [6 : 0] uncached_mem_shim_bff$D_IN, uncached_mem_shim_bff$D_OUT; wire uncached_mem_shim_bff$CLR, uncached_mem_shim_bff$DEQ, uncached_mem_shim_bff$EMPTY_N, uncached_mem_shim_bff$ENQ, uncached_mem_shim_bff$FULL_N; // ports of submodule uncached_mem_shim_rff wire [72 : 0] uncached_mem_shim_rff$D_IN, uncached_mem_shim_rff$D_OUT; wire uncached_mem_shim_rff$CLR, uncached_mem_shim_rff$DEQ, uncached_mem_shim_rff$EMPTY_N, uncached_mem_shim_rff$ENQ, uncached_mem_shim_rff$FULL_N; // ports of submodule uncached_mem_shim_wff wire [73 : 0] uncached_mem_shim_wff$D_IN, uncached_mem_shim_wff$D_OUT; wire uncached_mem_shim_wff$CLR, uncached_mem_shim_wff$DEQ, uncached_mem_shim_wff$EMPTY_N, uncached_mem_shim_wff$ENQ, uncached_mem_shim_wff$FULL_N; // rule scheduling signals wire CAN_FIRE_RL_ClientServerRequest, CAN_FIRE_RL_ClientServerRequest_1, CAN_FIRE_RL_ClientServerRequest_2, CAN_FIRE_RL_ClientServerResponse, CAN_FIRE_RL_ClientServerResponse_1, CAN_FIRE_RL_ClientServerResponse_2, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, CAN_FIRE_RL_arbitrate, CAN_FIRE_RL_arbitrate_1, CAN_FIRE_RL_arbitrate_2, CAN_FIRE_RL_arbitrate_3, CAN_FIRE_RL_burst, CAN_FIRE_RL_burst_1, CAN_FIRE_RL_burst_2, CAN_FIRE_RL_burst_3, CAN_FIRE_RL_burst_4, CAN_FIRE_RL_burst_5, CAN_FIRE_RL_burst_6, CAN_FIRE_RL_burst_7, CAN_FIRE_RL_burst_8, CAN_FIRE_RL_burst_9, CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop, CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek, CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop, CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek, CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut, CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut, CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop, CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek, CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_checkSinkReady, CAN_FIRE_RL_checkSinkReady_1, CAN_FIRE_RL_checkSinkReady_2, CAN_FIRE_RL_checkSinkReady_3, CAN_FIRE_RL_checkSinkReady_4, CAN_FIRE_RL_checkSinkReady_5, CAN_FIRE_RL_checkSinkReady_6, CAN_FIRE_RL_checkSinkReady_7, CAN_FIRE_RL_checkSinkReady_8, CAN_FIRE_RL_checkSinkReady_9, CAN_FIRE_RL_craftReq, CAN_FIRE_RL_craftReq_1, CAN_FIRE_RL_craftReq_2, CAN_FIRE_RL_craftReq_3, CAN_FIRE_RL_craftReq_4, CAN_FIRE_RL_craftReq_5, CAN_FIRE_RL_craftReq_6, CAN_FIRE_RL_craftReq_7, CAN_FIRE_RL_craftReq_8, CAN_FIRE_RL_craftReq_9, CAN_FIRE_RL_ifcs_0_1_drainFlits, CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_0_1_firstFlit, CAN_FIRE_RL_ifcs_0_1_firstFlit_1, CAN_FIRE_RL_ifcs_0_1_followFlits, CAN_FIRE_RL_ifcs_0_1_followFlits_1, CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, CAN_FIRE_RL_ifcs_0_1_snk_doPut, CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_0_drainFlits, CAN_FIRE_RL_ifcs_0_drainNoRouteResponse, CAN_FIRE_RL_ifcs_0_firstFlit, CAN_FIRE_RL_ifcs_0_firstFlit_1, CAN_FIRE_RL_ifcs_0_followFlits, CAN_FIRE_RL_ifcs_0_followFlits_1, CAN_FIRE_RL_ifcs_0_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp, CAN_FIRE_RL_ifcs_0_snk_doPut, CAN_FIRE_RL_ifcs_0_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_1_drainFlits, CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_1_firstFlit, CAN_FIRE_RL_ifcs_1_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_1_followFlits, CAN_FIRE_RL_ifcs_1_1_followFlits_1, CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, CAN_FIRE_RL_ifcs_1_1_snk_doPut, CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_drainFlits, CAN_FIRE_RL_ifcs_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_firstFlit, CAN_FIRE_RL_ifcs_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_followFlits, CAN_FIRE_RL_ifcs_1_followFlits_1, CAN_FIRE_RL_ifcs_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp, CAN_FIRE_RL_ifcs_1_snk_doPut, CAN_FIRE_RL_ifcs_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_2_1_firstFlit, CAN_FIRE_RL_ifcs_2_1_followFlits, CAN_FIRE_RL_ifcs_2_firstFlit, CAN_FIRE_RL_ifcs_2_followFlits, CAN_FIRE_RL_merged_0_awFlit, CAN_FIRE_RL_merged_0_genFirst, CAN_FIRE_RL_merged_0_genOther, CAN_FIRE_RL_merged_0_passFlit, CAN_FIRE_RL_merged_0_wFlit, CAN_FIRE_RL_merged_1_awFlit, CAN_FIRE_RL_merged_1_genFirst, CAN_FIRE_RL_merged_1_genOther, CAN_FIRE_RL_merged_1_passFlit, CAN_FIRE_RL_merged_1_wFlit, CAN_FIRE_RL_mkConnectionGetPut, CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop, CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek, CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop, CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek, CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut, CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut, CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop, CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek, CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, CAN_FIRE_RL_rl_dm_hart0_reset, CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_relay_external_interrupts, CAN_FIRE_RL_sink_selected, CAN_FIRE_RL_sink_selected_1, CAN_FIRE_RL_sink_selected_2, CAN_FIRE_RL_sink_selected_3, CAN_FIRE_RL_sink_selected_4, CAN_FIRE_RL_sink_selected_5, CAN_FIRE_RL_sink_selected_6, CAN_FIRE_RL_sink_selected_7, CAN_FIRE_RL_sink_selected_8, CAN_FIRE_RL_sink_selected_9, CAN_FIRE_RL_sinks_0_doPut, CAN_FIRE_RL_sinks_0_warnDoPut, CAN_FIRE_RL_sinks_1_0_doPut, CAN_FIRE_RL_sinks_1_0_doPut_1, CAN_FIRE_RL_sinks_1_0_warnDoPut, CAN_FIRE_RL_sinks_1_0_warnDoPut_1, CAN_FIRE_RL_sinks_1_1_0_doPut, CAN_FIRE_RL_sinks_1_1_0_warnDoPut, CAN_FIRE_RL_sinks_1_1_1_doPut, CAN_FIRE_RL_sinks_1_1_1_warnDoPut, CAN_FIRE_RL_sinks_1_1_doPut, CAN_FIRE_RL_sinks_1_1_doPut_1, CAN_FIRE_RL_sinks_1_1_warnDoPut, CAN_FIRE_RL_sinks_1_1_warnDoPut_1, CAN_FIRE_RL_sinks_1_2_doPut, CAN_FIRE_RL_sinks_1_2_warnDoPut, CAN_FIRE_RL_sinks_1_doPut, CAN_FIRE_RL_sinks_1_warnDoPut, CAN_FIRE_RL_sinks_2_doPut, CAN_FIRE_RL_sinks_2_warnDoPut, CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut, CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut, CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop, CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek, CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop, CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek, CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut, CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, CAN_FIRE_RL_source_selected, CAN_FIRE_RL_source_selected_1, CAN_FIRE_RL_source_selected_2, CAN_FIRE_RL_source_selected_3, CAN_FIRE_RL_source_selected_4, CAN_FIRE_RL_source_selected_5, CAN_FIRE_RL_source_selected_6, CAN_FIRE_RL_source_selected_7, CAN_FIRE_RL_source_selected_8, CAN_FIRE_RL_source_selected_9, CAN_FIRE_RL_split_0_putFirst, CAN_FIRE_RL_split_0_putOther, CAN_FIRE_RL_split_1_putFirst, CAN_FIRE_RL_split_1_putOther, CAN_FIRE_RL_split_2_putFirst, CAN_FIRE_RL_split_2_putOther, CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, CAN_FIRE_RL_tagController_tmp_getCacheAW, CAN_FIRE_RL_tagController_tmp_passCacheRead, CAN_FIRE_RL_tagController_tmp_passCacheResponse, CAN_FIRE_RL_tagController_tmp_passCacheWrite, CAN_FIRE_RL_tagController_tmp_passMemoryRequest, CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead, CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite, CAN_FIRE_RL_tagController_tmp_propagateReset, CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop, CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek, CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop, CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek, CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut, CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut, CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut, CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut, CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop, CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek, CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek, CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek, CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit, CAN_FIRE_RL_tmp2_arNoSynth_forwardReady, CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut, CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit, CAN_FIRE_RL_tmp2_awNoSynth_forwardReady, CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut, CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, CAN_FIRE_RL_tmp2_bNoSynth_dropFlit, CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit, CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop, CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek, CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, CAN_FIRE_RL_tmp2_rNoSynth_dropFlit, CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit, CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop, CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek, CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit, CAN_FIRE_RL_tmp2_wNoSynth_forwardReady, CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut, CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, CAN_FIRE___me_check_323, CAN_FIRE___me_check_324, CAN_FIRE___me_check_325, CAN_FIRE___me_check_327, CAN_FIRE___me_check_331, CAN_FIRE___me_check_332, CAN_FIRE___me_check_333, CAN_FIRE___me_check_335, CAN_FIRE___me_check_337, CAN_FIRE___me_check_339, CAN_FIRE___me_check_341, CAN_FIRE___me_check_355, CAN_FIRE___me_check_357, CAN_FIRE___me_check_359, CAN_FIRE___me_check_372, CAN_FIRE___me_check_374, CAN_FIRE___me_check_376, CAN_FIRE___me_check_378, CAN_FIRE___me_check_382, CAN_FIRE___me_check_383, CAN_FIRE___me_check_384, CAN_FIRE___me_check_386, CAN_FIRE___me_check_390, CAN_FIRE___me_check_391, CAN_FIRE___me_check_392, CAN_FIRE___me_check_394, CAN_FIRE___me_check_396, CAN_FIRE___me_check_398, CAN_FIRE___me_check_400, CAN_FIRE___me_check_414, CAN_FIRE___me_check_416, CAN_FIRE___me_check_418, CAN_FIRE___me_check_431, CAN_FIRE___me_check_433, CAN_FIRE___me_check_435, CAN_FIRE___me_check_437, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, CAN_FIRE_cpu_dmem_master_ar_arready, CAN_FIRE_cpu_dmem_master_aw_awready, CAN_FIRE_cpu_dmem_master_b_bflit, CAN_FIRE_cpu_dmem_master_r_rflit, CAN_FIRE_cpu_dmem_master_w_wready, CAN_FIRE_cpu_imem_master_ar_arready, CAN_FIRE_cpu_imem_master_aw_awready, CAN_FIRE_cpu_imem_master_b_bflit, CAN_FIRE_cpu_imem_master_r_rflit, CAN_FIRE_cpu_imem_master_w_wready, CAN_FIRE_dmi_read_addr, CAN_FIRE_dmi_read_data, CAN_FIRE_dmi_write, CAN_FIRE_ndm_reset_client_request_get, CAN_FIRE_ndm_reset_client_response_put, CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, CAN_FIRE_start, WILL_FIRE_RL_ClientServerRequest, WILL_FIRE_RL_ClientServerRequest_1, WILL_FIRE_RL_ClientServerRequest_2, WILL_FIRE_RL_ClientServerResponse, WILL_FIRE_RL_ClientServerResponse_1, WILL_FIRE_RL_ClientServerResponse_2, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, WILL_FIRE_RL_arbitrate, WILL_FIRE_RL_arbitrate_1, WILL_FIRE_RL_arbitrate_2, WILL_FIRE_RL_arbitrate_3, WILL_FIRE_RL_burst, WILL_FIRE_RL_burst_1, WILL_FIRE_RL_burst_2, WILL_FIRE_RL_burst_3, WILL_FIRE_RL_burst_4, WILL_FIRE_RL_burst_5, WILL_FIRE_RL_burst_6, WILL_FIRE_RL_burst_7, WILL_FIRE_RL_burst_8, WILL_FIRE_RL_burst_9, WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop, WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek, WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop, WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek, WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut, WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut, WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop, WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek, WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_checkSinkReady, WILL_FIRE_RL_checkSinkReady_1, WILL_FIRE_RL_checkSinkReady_2, WILL_FIRE_RL_checkSinkReady_3, WILL_FIRE_RL_checkSinkReady_4, WILL_FIRE_RL_checkSinkReady_5, WILL_FIRE_RL_checkSinkReady_6, WILL_FIRE_RL_checkSinkReady_7, WILL_FIRE_RL_checkSinkReady_8, WILL_FIRE_RL_checkSinkReady_9, WILL_FIRE_RL_craftReq, WILL_FIRE_RL_craftReq_1, WILL_FIRE_RL_craftReq_2, WILL_FIRE_RL_craftReq_3, WILL_FIRE_RL_craftReq_4, WILL_FIRE_RL_craftReq_5, WILL_FIRE_RL_craftReq_6, WILL_FIRE_RL_craftReq_7, WILL_FIRE_RL_craftReq_8, WILL_FIRE_RL_craftReq_9, WILL_FIRE_RL_ifcs_0_1_drainFlits, WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_0_1_firstFlit, WILL_FIRE_RL_ifcs_0_1_firstFlit_1, WILL_FIRE_RL_ifcs_0_1_followFlits, WILL_FIRE_RL_ifcs_0_1_followFlits_1, WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, WILL_FIRE_RL_ifcs_0_1_snk_doPut, WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_0_drainFlits, WILL_FIRE_RL_ifcs_0_drainNoRouteResponse, WILL_FIRE_RL_ifcs_0_firstFlit, WILL_FIRE_RL_ifcs_0_firstFlit_1, WILL_FIRE_RL_ifcs_0_followFlits, WILL_FIRE_RL_ifcs_0_followFlits_1, WILL_FIRE_RL_ifcs_0_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp, WILL_FIRE_RL_ifcs_0_snk_doPut, WILL_FIRE_RL_ifcs_0_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_1_drainFlits, WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_1_firstFlit, WILL_FIRE_RL_ifcs_1_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_1_followFlits, WILL_FIRE_RL_ifcs_1_1_followFlits_1, WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, WILL_FIRE_RL_ifcs_1_1_snk_doPut, WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_drainFlits, WILL_FIRE_RL_ifcs_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_firstFlit, WILL_FIRE_RL_ifcs_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_followFlits, WILL_FIRE_RL_ifcs_1_followFlits_1, WILL_FIRE_RL_ifcs_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp, WILL_FIRE_RL_ifcs_1_snk_doPut, WILL_FIRE_RL_ifcs_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_2_1_firstFlit, WILL_FIRE_RL_ifcs_2_1_followFlits, WILL_FIRE_RL_ifcs_2_firstFlit, WILL_FIRE_RL_ifcs_2_followFlits, WILL_FIRE_RL_merged_0_awFlit, WILL_FIRE_RL_merged_0_genFirst, WILL_FIRE_RL_merged_0_genOther, WILL_FIRE_RL_merged_0_passFlit, WILL_FIRE_RL_merged_0_wFlit, WILL_FIRE_RL_merged_1_awFlit, WILL_FIRE_RL_merged_1_genFirst, WILL_FIRE_RL_merged_1_genOther, WILL_FIRE_RL_merged_1_passFlit, WILL_FIRE_RL_merged_1_wFlit, WILL_FIRE_RL_mkConnectionGetPut, WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop, WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek, WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop, WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek, WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut, WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut, WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop, WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek, WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, WILL_FIRE_RL_rl_dm_hart0_reset, WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_relay_external_interrupts, WILL_FIRE_RL_sink_selected, WILL_FIRE_RL_sink_selected_1, WILL_FIRE_RL_sink_selected_2, WILL_FIRE_RL_sink_selected_3, WILL_FIRE_RL_sink_selected_4, WILL_FIRE_RL_sink_selected_5, WILL_FIRE_RL_sink_selected_6, WILL_FIRE_RL_sink_selected_7, WILL_FIRE_RL_sink_selected_8, WILL_FIRE_RL_sink_selected_9, WILL_FIRE_RL_sinks_0_doPut, WILL_FIRE_RL_sinks_0_warnDoPut, WILL_FIRE_RL_sinks_1_0_doPut, WILL_FIRE_RL_sinks_1_0_doPut_1, WILL_FIRE_RL_sinks_1_0_warnDoPut, WILL_FIRE_RL_sinks_1_0_warnDoPut_1, WILL_FIRE_RL_sinks_1_1_0_doPut, WILL_FIRE_RL_sinks_1_1_0_warnDoPut, WILL_FIRE_RL_sinks_1_1_1_doPut, WILL_FIRE_RL_sinks_1_1_1_warnDoPut, WILL_FIRE_RL_sinks_1_1_doPut, WILL_FIRE_RL_sinks_1_1_doPut_1, WILL_FIRE_RL_sinks_1_1_warnDoPut, WILL_FIRE_RL_sinks_1_1_warnDoPut_1, WILL_FIRE_RL_sinks_1_2_doPut, WILL_FIRE_RL_sinks_1_2_warnDoPut, WILL_FIRE_RL_sinks_1_doPut, WILL_FIRE_RL_sinks_1_warnDoPut, WILL_FIRE_RL_sinks_2_doPut, WILL_FIRE_RL_sinks_2_warnDoPut, WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut, WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut, WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop, WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek, WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop, WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek, WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut, WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, WILL_FIRE_RL_source_selected, WILL_FIRE_RL_source_selected_1, WILL_FIRE_RL_source_selected_2, WILL_FIRE_RL_source_selected_3, WILL_FIRE_RL_source_selected_4, WILL_FIRE_RL_source_selected_5, WILL_FIRE_RL_source_selected_6, WILL_FIRE_RL_source_selected_7, WILL_FIRE_RL_source_selected_8, WILL_FIRE_RL_source_selected_9, WILL_FIRE_RL_split_0_putFirst, WILL_FIRE_RL_split_0_putOther, WILL_FIRE_RL_split_1_putFirst, WILL_FIRE_RL_split_1_putOther, WILL_FIRE_RL_split_2_putFirst, WILL_FIRE_RL_split_2_putOther, WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, WILL_FIRE_RL_tagController_tmp_getCacheAW, WILL_FIRE_RL_tagController_tmp_passCacheRead, WILL_FIRE_RL_tagController_tmp_passCacheResponse, WILL_FIRE_RL_tagController_tmp_passCacheWrite, WILL_FIRE_RL_tagController_tmp_passMemoryRequest, WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead, WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite, WILL_FIRE_RL_tagController_tmp_propagateReset, WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop, WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek, WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop, WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek, WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut, WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut, WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut, WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut, WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop, WILL_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek, WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek, WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek, WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit, WILL_FIRE_RL_tmp2_arNoSynth_forwardReady, WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut, WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit, WILL_FIRE_RL_tmp2_awNoSynth_forwardReady, WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut, WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, WILL_FIRE_RL_tmp2_bNoSynth_dropFlit, WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit, WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop, WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek, WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, WILL_FIRE_RL_tmp2_rNoSynth_dropFlit, WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit, WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop, WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek, WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit, WILL_FIRE_RL_tmp2_wNoSynth_forwardReady, WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut, WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, WILL_FIRE___me_check_323, WILL_FIRE___me_check_324, WILL_FIRE___me_check_325, WILL_FIRE___me_check_327, WILL_FIRE___me_check_331, WILL_FIRE___me_check_332, WILL_FIRE___me_check_333, WILL_FIRE___me_check_335, WILL_FIRE___me_check_337, WILL_FIRE___me_check_339, WILL_FIRE___me_check_341, WILL_FIRE___me_check_355, WILL_FIRE___me_check_357, WILL_FIRE___me_check_359, WILL_FIRE___me_check_372, WILL_FIRE___me_check_374, WILL_FIRE___me_check_376, WILL_FIRE___me_check_378, WILL_FIRE___me_check_382, WILL_FIRE___me_check_383, WILL_FIRE___me_check_384, WILL_FIRE___me_check_386, WILL_FIRE___me_check_390, WILL_FIRE___me_check_391, WILL_FIRE___me_check_392, WILL_FIRE___me_check_394, WILL_FIRE___me_check_396, WILL_FIRE___me_check_398, WILL_FIRE___me_check_400, WILL_FIRE___me_check_414, WILL_FIRE___me_check_416, WILL_FIRE___me_check_418, WILL_FIRE___me_check_431, WILL_FIRE___me_check_433, WILL_FIRE___me_check_435, WILL_FIRE___me_check_437, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, WILL_FIRE_cpu_dmem_master_ar_arready, WILL_FIRE_cpu_dmem_master_aw_awready, WILL_FIRE_cpu_dmem_master_b_bflit, WILL_FIRE_cpu_dmem_master_r_rflit, WILL_FIRE_cpu_dmem_master_w_wready, WILL_FIRE_cpu_imem_master_ar_arready, WILL_FIRE_cpu_imem_master_aw_awready, WILL_FIRE_cpu_imem_master_b_bflit, WILL_FIRE_cpu_imem_master_r_rflit, WILL_FIRE_cpu_imem_master_w_wready, WILL_FIRE_dmi_read_addr, WILL_FIRE_dmi_read_data, WILL_FIRE_dmi_write, WILL_FIRE_ndm_reset_client_request_get, WILL_FIRE_ndm_reset_client_response_put, WILL_FIRE_nmi_req, WILL_FIRE_set_verbosity, WILL_FIRE_start; // inputs to muxes for submodule ports reg [71 : 0] MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1, MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1; reg [5 : 0] MUX_ifcs_0_snk_putWire$wset_1__VAL_1, MUX_ifcs_1_snk_putWire$wset_1__VAL_1; wire [140 : 0] MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1, MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2; wire [76 : 0] MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1, MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2; wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_2, MUX_merged_1_flitLeft$write_1__VAL_2, MUX_rg_hart0_reset_delay$write_1__VAL_1, MUX_split_0_flitLeft$write_1__VAL_1, MUX_split_1_flitLeft$write_1__VAL_1, MUX_split_2_flitLeft$write_1__VAL_1; wire MUX_activeSource_0$write_1__SEL_1, MUX_activeSource_0$write_1__VAL_1, MUX_activeSource_1$write_1__VAL_1, MUX_activeSource_1_1_0$write_1__SEL_1, MUX_activeSource_1_1_0$write_1__SEL_2, MUX_activeSource_1_1_0$write_1__SEL_3, MUX_activeSource_1_1_0$write_1__VAL_1, MUX_activeSource_1_1_1_1$write_1__VAL_1, MUX_activeSource_1_1_2$write_1__VAL_1, MUX_flitToSink_0$wset_1__SEL_1, MUX_flitToSink_0$wset_1__SEL_3, MUX_flitToSink_1$wset_1__SEL_1, MUX_flitToSink_1$wset_1__SEL_3, MUX_flitToSink_1_0$wset_1__SEL_1, MUX_flitToSink_1_0$wset_1__SEL_2, MUX_flitToSink_1_0$wset_1__SEL_3, MUX_flitToSink_1_0$wset_1__SEL_4, MUX_flitToSink_1_0$wset_1__SEL_5, MUX_flitToSink_1_0$wset_1__SEL_6, MUX_flitToSink_1_0_1$wset_1__SEL_1, MUX_flitToSink_1_0_1$wset_1__SEL_3, MUX_flitToSink_1_1$wset_1__SEL_1, MUX_flitToSink_1_1$wset_1__SEL_2, MUX_flitToSink_1_1$wset_1__SEL_3, MUX_flitToSink_1_1$wset_1__SEL_4, MUX_flitToSink_1_1$wset_1__SEL_5, MUX_flitToSink_1_1$wset_1__SEL_6, MUX_flitToSink_1_1_0$wset_1__SEL_1, MUX_flitToSink_1_1_0$wset_1__SEL_2, MUX_flitToSink_1_1_0$wset_1__SEL_3, MUX_flitToSink_1_1_0$wset_1__SEL_4, MUX_flitToSink_1_1_0$wset_1__SEL_5, MUX_flitToSink_1_1_0$wset_1__SEL_6, MUX_flitToSink_1_1_1$wset_1__SEL_1, MUX_flitToSink_1_1_1$wset_1__SEL_3, MUX_flitToSink_1_1_1_1$wset_1__SEL_1, MUX_flitToSink_1_1_1_1$wset_1__SEL_2, MUX_flitToSink_1_1_1_1$wset_1__SEL_3, MUX_flitToSink_1_1_1_1$wset_1__SEL_4, MUX_flitToSink_1_1_1_1$wset_1__SEL_5, MUX_flitToSink_1_1_1_1$wset_1__SEL_6, MUX_flitToSink_1_2$wset_1__SEL_1, MUX_flitToSink_1_2$wset_1__SEL_3, MUX_flitToSink_2$wset_1__SEL_1, MUX_flitToSink_2$wset_1__SEL_3, MUX_ifcs_0_1_state_1$write_1__SEL_1, MUX_ifcs_0_state$write_1__PSEL_3, MUX_ifcs_0_state$write_1__SEL_1, MUX_ifcs_0_state$write_1__SEL_2, MUX_ifcs_0_state$write_1__SEL_3, MUX_ifcs_1_1_state_1$write_1__SEL_1, MUX_ifcs_1_state$write_1__PSEL_1, MUX_ifcs_1_state$write_1__SEL_1, MUX_ifcs_1_state$write_1__SEL_2, MUX_ifcs_1_state$write_1__SEL_3, MUX_ifcs_2_1_state$write_1__SEL_1, MUX_proc$start_1__SEL_1, MUX_split_0_flitLeft$write_1__SEL_1, MUX_split_0_flitLeft$write_1__SEL_2, MUX_split_1_flitLeft$write_1__SEL_1, MUX_split_1_flitLeft$write_1__SEL_2, MUX_split_2_flitLeft$write_1__SEL_1, MUX_split_2_flitLeft$write_1__SEL_2, MUX_state$write_1__SEL_1, MUX_state$write_1__SEL_2, MUX_state_1_1_1$write_1__SEL_1, MUX_state_1_1_1$write_1__SEL_2, MUX_state_1_1_1$write_1__SEL_3; // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h27379; reg [31 : 0] v__h27522; reg [63 : 0] v__h71933; reg [63 : 0] v__h71322; reg [63 : 0] v__h75942; reg [63 : 0] v__h75331; reg [63 : 0] v__h87108; reg [63 : 0] v__h86727; reg [63 : 0] v__h89178; reg [63 : 0] v__h88797; reg [63 : 0] v__h91077; reg [63 : 0] v__h90696; reg [63 : 0] v__h107706; reg [63 : 0] v__h107095; reg [63 : 0] v__h110599; reg [63 : 0] v__h109988; reg [63 : 0] v__h120386; reg [63 : 0] v__h120005; reg [63 : 0] v__h122877; reg [63 : 0] v__h122496; reg [63 : 0] v__h125187; reg [63 : 0] v__h124806; reg [31 : 0] v__h128915; reg [31 : 0] v__h27373; reg [31 : 0] v__h27516; reg [31 : 0] v__h128909; // synopsys translate_on // remaining internal signals wire [171 : 0] IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551, IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645; wire [98 : 0] tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4, tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2; wire [72 : 0] tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3, uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1; wire [63 : 0] addr__h93766, addr__h96383, aw_awaddr__h10619, tmp__h10402, tmp__h8177, v_araddr__h15368, x__h56240, x__h56275, x__h59752, x__h59777, x__h8018, x__h93842, x__h93867, x__h96459, x__h96484; wire [39 : 0] x__h10651; wire [8 : 0] x__h95031, x__h97630; wire [7 : 0] arlen__h15352, v_arlen__h15369, x__h94928, x__h97527; wire [5 : 0] v_arid__h15367; wire [4 : 0] fatReq_arid__h94350, fatReq_arid__h96952, x__h100333, x__h62633, x__h63524, x__h64415, x__h98423, x__h99378; wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224, arcache__h15356, x__h10694, x__h12428, x__h12440, x__h12452, x__h12464, x__h12476, x__h12488, x__h12500, x__h14024, x__h15432, y__h12429, y__h12441, y__h12453, y__h12465, y__h12477, y__h12489, y__h12501; wire [2 : 0] aw_awsize_val__h12358, v_arsize_val__h15414; wire [1 : 0] IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531, IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535, IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540, IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625, IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629, IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634, IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227, IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231, IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236, IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322, IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326, IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331, SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22, SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12, SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17, SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7, SEXT_arbiter_1_1_firstHot__q19, SEXT_arbiter_1_1_lastSelect_1__q21, SEXT_arbiter_1_1_lastSelect__q20, SEXT_arbiter_1_firstHot_1__q15, SEXT_arbiter_1_firstHot__q9, SEXT_arbiter_1_lastSelect_1__q11, SEXT_arbiter_1_lastSelect_2__q16, SEXT_arbiter_1_lastSelect__q10, SEXT_arbiter_firstHot__q5, SEXT_arbiter_lastSelect__q6, SEXT_x0458__q8, SEXT_x06231__q18, SEXT_x18683__q23, SEXT_x18717__q24, SEXT_x5409__q13, SEXT_x5443__q14; wire IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513, IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812, IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529, IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828, IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769, IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775, IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781, IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078, IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084, IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090, IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565, IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569, IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864, IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868, IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498, IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516, IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524, IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556, IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561, IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598, IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614, IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619, IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650, IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655, IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216, IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221, IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311, IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316, IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764, IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773, IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782, SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750, SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744, SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738, SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059, SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553, SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047, SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053, SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549, SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852, SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848, reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030, reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721, split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409, split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438, split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467, state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122, state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155, state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189, state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819, state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855, state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891, state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608, state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648, state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913, state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957, x__h105704, x__h105807, x__h106172, x__h106231, x__h106313, x__h117862, x__h117864, x__h118013, x__h118015, x__h118149, x__h118151, x__h118621, x__h118623, x__h118683, x__h118717, x__h118809, x__h118811, x__h118990, x__h118992, x__h69931, x__h70034, x__h70399, x__h70458, x__h70540, x__h84588, x__h84590, x__h84739, x__h84741, x__h84875, x__h84877, x__h85347, x__h85349, x__h85409, x__h85443, x__h85535, x__h85537, x__h85716, x__h85718, y__h105705, y__h105808, y__h106173, y__h106314, y__h117863, y__h117865, y__h118014, y__h118016, y__h118150, y__h118152, y__h118622, y__h118624, y__h118810, y__h118812, y__h118991, y__h118993, y__h69932, y__h70035, y__h70400, y__h70541, y__h84589, y__h84591, y__h84740, y__h84742, y__h84876, y__h84878, y__h85348, y__h85350, y__h85536, y__h85538, y__h85717, y__h85719; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; // action method start assign RDY_start = proc$RDY_start ; assign CAN_FIRE_start = proc$RDY_start ; assign WILL_FIRE_start = EN_start ; // value method cpu_imem_master_aw_awid assign cpu_imem_master_awid = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[98:93] ; // value method cpu_imem_master_aw_awaddr assign cpu_imem_master_awaddr = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[92:29] ; // value method cpu_imem_master_aw_awlen assign cpu_imem_master_awlen = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[28:21] ; // value method cpu_imem_master_aw_awsize assign cpu_imem_master_awsize = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[20:18] ; // value method cpu_imem_master_aw_awburst assign cpu_imem_master_awburst = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[17:16] ; // value method cpu_imem_master_aw_awlock assign cpu_imem_master_awlock = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[15] ; // value method cpu_imem_master_aw_awcache assign cpu_imem_master_awcache = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[14:11] ; // value method cpu_imem_master_aw_awprot assign cpu_imem_master_awprot = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[10:8] ; // value method cpu_imem_master_aw_awqos assign cpu_imem_master_awqos = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[7:4] ; // value method cpu_imem_master_aw_awregion assign cpu_imem_master_awregion = tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2[3:0] ; // value method cpu_imem_master_aw_awvalid assign cpu_imem_master_awvalid = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek ; // action method cpu_imem_master_aw_awready assign CAN_FIRE_cpu_imem_master_aw_awready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_aw_awready = 1'd1 ; // value method cpu_imem_master_w_wdata assign cpu_imem_master_wdata = tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3[72:9] ; // value method cpu_imem_master_w_wstrb assign cpu_imem_master_wstrb = tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3[8:1] ; // value method cpu_imem_master_w_wlast assign cpu_imem_master_wlast = tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3[0] ; // value method cpu_imem_master_w_wvalid assign cpu_imem_master_wvalid = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek ; // action method cpu_imem_master_w_wready assign CAN_FIRE_cpu_imem_master_w_wready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_w_wready = 1'd1 ; // action method cpu_imem_master_b_bflit assign CAN_FIRE_cpu_imem_master_b_bflit = 1'd1 ; assign WILL_FIRE_cpu_imem_master_b_bflit = 1'd1 ; // value method cpu_imem_master_b_bready assign cpu_imem_master_bready = !tagController_tmp_shimMaster_bff_rv[8] ; // value method cpu_imem_master_ar_arid assign cpu_imem_master_arid = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[98:93] ; // value method cpu_imem_master_ar_araddr assign cpu_imem_master_araddr = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[92:29] ; // value method cpu_imem_master_ar_arlen assign cpu_imem_master_arlen = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[28:21] ; // value method cpu_imem_master_ar_arsize assign cpu_imem_master_arsize = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[20:18] ; // value method cpu_imem_master_ar_arburst assign cpu_imem_master_arburst = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[17:16] ; // value method cpu_imem_master_ar_arlock assign cpu_imem_master_arlock = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[15] ; // value method cpu_imem_master_ar_arcache assign cpu_imem_master_arcache = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[14:11] ; // value method cpu_imem_master_ar_arprot assign cpu_imem_master_arprot = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[10:8] ; // value method cpu_imem_master_ar_arqos assign cpu_imem_master_arqos = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[7:4] ; // value method cpu_imem_master_ar_arregion assign cpu_imem_master_arregion = tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4[3:0] ; // value method cpu_imem_master_ar_arvalid assign cpu_imem_master_arvalid = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek ; // action method cpu_imem_master_ar_arready assign CAN_FIRE_cpu_imem_master_ar_arready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_ar_arready = 1'd1 ; // action method cpu_imem_master_r_rflit assign CAN_FIRE_cpu_imem_master_r_rflit = 1'd1 ; assign WILL_FIRE_cpu_imem_master_r_rflit = 1'd1 ; // value method cpu_imem_master_r_rready assign cpu_imem_master_rready = !tagController_tmp_shimMaster_rff_rv[73] ; // value method cpu_dmem_master_aw_awid assign cpu_dmem_master_awid = uncached_mem_master_awSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_aw_awaddr assign cpu_dmem_master_awaddr = uncached_mem_master_awSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_aw_awlen assign cpu_dmem_master_awlen = uncached_mem_master_awSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_aw_awsize assign cpu_dmem_master_awsize = uncached_mem_master_awSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_aw_awburst assign cpu_dmem_master_awburst = uncached_mem_master_awSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_aw_awlock assign cpu_dmem_master_awlock = uncached_mem_master_awSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_aw_awcache assign cpu_dmem_master_awcache = uncached_mem_master_awSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_aw_awprot assign cpu_dmem_master_awprot = uncached_mem_master_awSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_aw_awqos assign cpu_dmem_master_awqos = uncached_mem_master_awSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_aw_awregion assign cpu_dmem_master_awregion = uncached_mem_master_awSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_aw_awvalid assign cpu_dmem_master_awvalid = uncached_mem_shim_awff$EMPTY_N ; // action method cpu_dmem_master_aw_awready assign CAN_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; // value method cpu_dmem_master_w_wdata assign cpu_dmem_master_wdata = uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1[72:9] ; // value method cpu_dmem_master_w_wstrb assign cpu_dmem_master_wstrb = uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1[8:1] ; // value method cpu_dmem_master_w_wlast assign cpu_dmem_master_wlast = uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1[0] ; // value method cpu_dmem_master_w_wvalid assign cpu_dmem_master_wvalid = uncached_mem_shim_wff$EMPTY_N ; // action method cpu_dmem_master_w_wready assign CAN_FIRE_cpu_dmem_master_w_wready = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_w_wready = 1'd1 ; // action method cpu_dmem_master_b_bflit assign CAN_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; // value method cpu_dmem_master_b_bready assign cpu_dmem_master_bready = uncached_mem_shim_bff$FULL_N ; // value method cpu_dmem_master_ar_arid assign cpu_dmem_master_arid = uncached_mem_master_arSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_ar_araddr assign cpu_dmem_master_araddr = uncached_mem_master_arSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_ar_arlen assign cpu_dmem_master_arlen = uncached_mem_master_arSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_ar_arsize assign cpu_dmem_master_arsize = uncached_mem_master_arSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_ar_arburst assign cpu_dmem_master_arburst = uncached_mem_master_arSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_ar_arlock assign cpu_dmem_master_arlock = uncached_mem_master_arSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_ar_arcache assign cpu_dmem_master_arcache = uncached_mem_master_arSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_ar_arprot assign cpu_dmem_master_arprot = uncached_mem_master_arSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_ar_arqos assign cpu_dmem_master_arqos = uncached_mem_master_arSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_ar_arregion assign cpu_dmem_master_arregion = uncached_mem_master_arSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_ar_arvalid assign cpu_dmem_master_arvalid = uncached_mem_shim_arff$EMPTY_N ; // action method cpu_dmem_master_ar_arready assign CAN_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; // action method cpu_dmem_master_r_rflit assign CAN_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; // value method cpu_dmem_master_r_rready assign cpu_dmem_master_rready = uncached_mem_shim_rff$FULL_N ; // action method core_external_interrupt_sources_0_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_1_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_2_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_3_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_4_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_5_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_6_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_7_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_8_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_9_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_10_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_11_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_12_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_13_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_14_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_15_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; // action method nmi_req assign CAN_FIRE_nmi_req = 1'd1 ; assign WILL_FIRE_nmi_req = 1'd1 ; // action method dmi_read_addr assign RDY_dmi_read_addr = debug_module$RDY_dmi_read_addr ; assign CAN_FIRE_dmi_read_addr = debug_module$RDY_dmi_read_addr ; assign WILL_FIRE_dmi_read_addr = EN_dmi_read_addr ; // actionvalue method dmi_read_data assign dmi_read_data = debug_module$dmi_read_data ; assign RDY_dmi_read_data = debug_module$RDY_dmi_read_data ; assign CAN_FIRE_dmi_read_data = debug_module$RDY_dmi_read_data ; assign WILL_FIRE_dmi_read_data = EN_dmi_read_data ; // action method dmi_write assign RDY_dmi_write = debug_module$RDY_dmi_write ; assign CAN_FIRE_dmi_write = debug_module$RDY_dmi_write ; assign WILL_FIRE_dmi_write = EN_dmi_write ; // actionvalue method ndm_reset_client_request_get assign ndm_reset_client_request_get = debug_module$ndm_reset_client_request_get ; assign RDY_ndm_reset_client_request_get = debug_module$RDY_ndm_reset_client_request_get ; assign CAN_FIRE_ndm_reset_client_request_get = debug_module$RDY_ndm_reset_client_request_get ; assign WILL_FIRE_ndm_reset_client_request_get = EN_ndm_reset_client_request_get ; // action method ndm_reset_client_response_put assign RDY_ndm_reset_client_response_put = debug_module$RDY_ndm_reset_client_response_put ; assign CAN_FIRE_ndm_reset_client_response_put = debug_module$RDY_ndm_reset_client_response_put ; assign WILL_FIRE_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; // submodule debug_module mkDebug_Module debug_module(.CLK(CLK), .RST_N(RST_N_dm_power_on_reset), .dmi_read_addr_dm_addr(debug_module$dmi_read_addr_dm_addr), .dmi_write_dm_addr(debug_module$dmi_write_dm_addr), .dmi_write_dm_word(debug_module$dmi_write_dm_word), .hart0_client_run_halt_response_put(debug_module$hart0_client_run_halt_response_put), .hart0_csr_mem_client_response_put(debug_module$hart0_csr_mem_client_response_put), .hart0_fpr_mem_client_response_put(debug_module$hart0_fpr_mem_client_response_put), .hart0_gpr_mem_client_response_put(debug_module$hart0_gpr_mem_client_response_put), .hart0_reset_client_response_put(debug_module$hart0_reset_client_response_put), .master_arready(debug_module$master_arready), .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), .master_bresp(debug_module$master_bresp), .master_bvalid(debug_module$master_bvalid), .master_rdata(debug_module$master_rdata), .master_rid(debug_module$master_rid), .master_rlast(debug_module$master_rlast), .master_rresp(debug_module$master_rresp), .master_ruser(debug_module$master_ruser), .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), .EN_dmi_read_data(debug_module$EN_dmi_read_data), .EN_dmi_write(debug_module$EN_dmi_write), .EN_hart0_reset_client_request_get(debug_module$EN_hart0_reset_client_request_get), .EN_hart0_reset_client_response_put(debug_module$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(debug_module$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(debug_module$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(debug_module$EN_hart0_get_other_req_get), .EN_hart0_gpr_mem_client_request_get(debug_module$EN_hart0_gpr_mem_client_request_get), .EN_hart0_gpr_mem_client_response_put(debug_module$EN_hart0_gpr_mem_client_response_put), .EN_hart0_fpr_mem_client_request_get(debug_module$EN_hart0_fpr_mem_client_request_get), .EN_hart0_fpr_mem_client_response_put(debug_module$EN_hart0_fpr_mem_client_response_put), .EN_hart0_csr_mem_client_request_get(debug_module$EN_hart0_csr_mem_client_request_get), .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), .RDY_dmi_write(debug_module$RDY_dmi_write), .hart0_reset_client_request_get(), .RDY_hart0_reset_client_request_get(debug_module$RDY_hart0_reset_client_request_get), .RDY_hart0_reset_client_response_put(debug_module$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(debug_module$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(debug_module$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(debug_module$RDY_hart0_client_run_halt_response_put), .hart0_get_other_req_get(debug_module$hart0_get_other_req_get), .RDY_hart0_get_other_req_get(debug_module$RDY_hart0_get_other_req_get), .hart0_gpr_mem_client_request_get(debug_module$hart0_gpr_mem_client_request_get), .RDY_hart0_gpr_mem_client_request_get(debug_module$RDY_hart0_gpr_mem_client_request_get), .RDY_hart0_gpr_mem_client_response_put(debug_module$RDY_hart0_gpr_mem_client_response_put), .hart0_fpr_mem_client_request_get(), .RDY_hart0_fpr_mem_client_request_get(), .RDY_hart0_fpr_mem_client_response_put(), .hart0_csr_mem_client_request_get(debug_module$hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_request_get(debug_module$RDY_hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_response_put(debug_module$RDY_hart0_csr_mem_client_response_put), .ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put), .master_awid(debug_module$master_awid), .master_awaddr(debug_module$master_awaddr), .master_awlen(debug_module$master_awlen), .master_awsize(debug_module$master_awsize), .master_awburst(debug_module$master_awburst), .master_awlock(debug_module$master_awlock), .master_awcache(debug_module$master_awcache), .master_awprot(debug_module$master_awprot), .master_awqos(debug_module$master_awqos), .master_awregion(debug_module$master_awregion), .master_awvalid(debug_module$master_awvalid), .master_wdata(debug_module$master_wdata), .master_wstrb(debug_module$master_wstrb), .master_wlast(debug_module$master_wlast), .master_wuser(debug_module$master_wuser), .master_wvalid(debug_module$master_wvalid), .master_bready(debug_module$master_bready), .master_arid(debug_module$master_arid), .master_araddr(debug_module$master_araddr), .master_arlen(debug_module$master_arlen), .master_arsize(debug_module$master_arsize), .master_arburst(debug_module$master_arburst), .master_arlock(debug_module$master_arlock), .master_arcache(debug_module$master_arcache), .master_arprot(debug_module$master_arprot), .master_arqos(debug_module$master_arqos), .master_arregion(debug_module$master_arregion), .master_arvalid(debug_module$master_arvalid), .master_rready(debug_module$master_rready)); // submodule dm_hart0_reset_controller MakeResetA #(.RSTDELAY(32'd10), .init(1'd1)) dm_hart0_reset_controller(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(dm_hart0_reset_controller$ASSERT_IN), .ASSERT_OUT(), .OUT_RST(dm_hart0_reset_controller$OUT_RST)); // submodule hart0_reset ResetEither hart0_reset(.A_RST(RST_N), .B_RST(dm_hart0_reset_controller$OUT_RST), .RST_OUT(hart0_reset$RST_OUT)); // submodule ifcs_0_1_innerReq FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_0_1_innerReq(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_1_innerReq$D_IN), .ENQ(ifcs_0_1_innerReq$ENQ), .DEQ(ifcs_0_1_innerReq$DEQ), .CLR(ifcs_0_1_innerReq$CLR), .D_OUT(ifcs_0_1_innerReq$D_OUT), .FULL_N(ifcs_0_1_innerReq$FULL_N), .EMPTY_N(ifcs_0_1_innerReq$EMPTY_N)); // submodule ifcs_0_1_innerRoute FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_1_innerRoute(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_1_innerRoute$D_IN), .ENQ(ifcs_0_1_innerRoute$ENQ), .DEQ(ifcs_0_1_innerRoute$DEQ), .CLR(ifcs_0_1_innerRoute$CLR), .D_OUT(ifcs_0_1_innerRoute$D_OUT), .FULL_N(ifcs_0_1_innerRoute$FULL_N), .EMPTY_N(ifcs_0_1_innerRoute$EMPTY_N)); // submodule ifcs_0_1_noRouteRsp FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_0_1_noRouteRsp(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_1_noRouteRsp$D_IN), .ENQ(ifcs_0_1_noRouteRsp$ENQ), .DEQ(ifcs_0_1_noRouteRsp$DEQ), .CLR(ifcs_0_1_noRouteRsp$CLR), .D_OUT(ifcs_0_1_noRouteRsp$D_OUT), .FULL_N(ifcs_0_1_noRouteRsp$FULL_N), .EMPTY_N(ifcs_0_1_noRouteRsp$EMPTY_N)); // submodule ifcs_0_1_routeBack FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_1_routeBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_1_routeBack$D_IN), .ENQ(ifcs_0_1_routeBack$ENQ), .DEQ(ifcs_0_1_routeBack$DEQ), .CLR(ifcs_0_1_routeBack$CLR), .D_OUT(ifcs_0_1_routeBack$D_OUT), .FULL_N(ifcs_0_1_routeBack$FULL_N), .EMPTY_N(ifcs_0_1_routeBack$EMPTY_N)); // submodule ifcs_0_1_rspBack FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_0_1_rspBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_1_rspBack$D_IN), .ENQ(ifcs_0_1_rspBack$ENQ), .DEQ(ifcs_0_1_rspBack$DEQ), .CLR(ifcs_0_1_rspBack$CLR), .D_OUT(ifcs_0_1_rspBack$D_OUT), .FULL_N(ifcs_0_1_rspBack$FULL_N), .EMPTY_N(ifcs_0_1_rspBack$EMPTY_N)); // submodule ifcs_0_innerReq FIFO2 #(.width(32'd173), .guarded(32'd1)) ifcs_0_innerReq(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_innerReq$D_IN), .ENQ(ifcs_0_innerReq$ENQ), .DEQ(ifcs_0_innerReq$DEQ), .CLR(ifcs_0_innerReq$CLR), .D_OUT(ifcs_0_innerReq$D_OUT), .FULL_N(ifcs_0_innerReq$FULL_N), .EMPTY_N(ifcs_0_innerReq$EMPTY_N)); // submodule ifcs_0_innerRoute FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_innerRoute(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_innerRoute$D_IN), .ENQ(ifcs_0_innerRoute$ENQ), .DEQ(ifcs_0_innerRoute$DEQ), .CLR(ifcs_0_innerRoute$CLR), .D_OUT(ifcs_0_innerRoute$D_OUT), .FULL_N(ifcs_0_innerRoute$FULL_N), .EMPTY_N(ifcs_0_innerRoute$EMPTY_N)); // submodule ifcs_0_noRouteRsp FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_noRouteRsp(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_noRouteRsp$D_IN), .ENQ(ifcs_0_noRouteRsp$ENQ), .DEQ(ifcs_0_noRouteRsp$DEQ), .CLR(ifcs_0_noRouteRsp$CLR), .D_OUT(ifcs_0_noRouteRsp$D_OUT), .FULL_N(ifcs_0_noRouteRsp$FULL_N), .EMPTY_N(ifcs_0_noRouteRsp$EMPTY_N)); // submodule ifcs_0_routeBack FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_routeBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_routeBack$D_IN), .ENQ(ifcs_0_routeBack$ENQ), .DEQ(ifcs_0_routeBack$DEQ), .CLR(ifcs_0_routeBack$CLR), .D_OUT(ifcs_0_routeBack$D_OUT), .FULL_N(ifcs_0_routeBack$FULL_N), .EMPTY_N(ifcs_0_routeBack$EMPTY_N)); // submodule ifcs_0_rspBack FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_rspBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_0_rspBack$D_IN), .ENQ(ifcs_0_rspBack$ENQ), .DEQ(ifcs_0_rspBack$DEQ), .CLR(ifcs_0_rspBack$CLR), .D_OUT(ifcs_0_rspBack$D_OUT), .FULL_N(ifcs_0_rspBack$FULL_N), .EMPTY_N(ifcs_0_rspBack$EMPTY_N)); // submodule ifcs_1_1_innerReq FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_1_1_innerReq(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_1_innerReq$D_IN), .ENQ(ifcs_1_1_innerReq$ENQ), .DEQ(ifcs_1_1_innerReq$DEQ), .CLR(ifcs_1_1_innerReq$CLR), .D_OUT(ifcs_1_1_innerReq$D_OUT), .FULL_N(ifcs_1_1_innerReq$FULL_N), .EMPTY_N(ifcs_1_1_innerReq$EMPTY_N)); // submodule ifcs_1_1_innerRoute FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_1_innerRoute(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_1_innerRoute$D_IN), .ENQ(ifcs_1_1_innerRoute$ENQ), .DEQ(ifcs_1_1_innerRoute$DEQ), .CLR(ifcs_1_1_innerRoute$CLR), .D_OUT(ifcs_1_1_innerRoute$D_OUT), .FULL_N(ifcs_1_1_innerRoute$FULL_N), .EMPTY_N(ifcs_1_1_innerRoute$EMPTY_N)); // submodule ifcs_1_1_noRouteRsp FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_1_1_noRouteRsp(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_1_noRouteRsp$D_IN), .ENQ(ifcs_1_1_noRouteRsp$ENQ), .DEQ(ifcs_1_1_noRouteRsp$DEQ), .CLR(ifcs_1_1_noRouteRsp$CLR), .D_OUT(ifcs_1_1_noRouteRsp$D_OUT), .FULL_N(ifcs_1_1_noRouteRsp$FULL_N), .EMPTY_N(ifcs_1_1_noRouteRsp$EMPTY_N)); // submodule ifcs_1_1_routeBack FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_1_routeBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_1_routeBack$D_IN), .ENQ(ifcs_1_1_routeBack$ENQ), .DEQ(ifcs_1_1_routeBack$DEQ), .CLR(ifcs_1_1_routeBack$CLR), .D_OUT(ifcs_1_1_routeBack$D_OUT), .FULL_N(ifcs_1_1_routeBack$FULL_N), .EMPTY_N(ifcs_1_1_routeBack$EMPTY_N)); // submodule ifcs_1_1_rspBack FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_1_1_rspBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_1_rspBack$D_IN), .ENQ(ifcs_1_1_rspBack$ENQ), .DEQ(ifcs_1_1_rspBack$DEQ), .CLR(ifcs_1_1_rspBack$CLR), .D_OUT(ifcs_1_1_rspBack$D_OUT), .FULL_N(ifcs_1_1_rspBack$FULL_N), .EMPTY_N(ifcs_1_1_rspBack$EMPTY_N)); // submodule ifcs_1_innerReq FIFO2 #(.width(32'd173), .guarded(32'd1)) ifcs_1_innerReq(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_innerReq$D_IN), .ENQ(ifcs_1_innerReq$ENQ), .DEQ(ifcs_1_innerReq$DEQ), .CLR(ifcs_1_innerReq$CLR), .D_OUT(ifcs_1_innerReq$D_OUT), .FULL_N(ifcs_1_innerReq$FULL_N), .EMPTY_N(ifcs_1_innerReq$EMPTY_N)); // submodule ifcs_1_innerRoute FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_innerRoute(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_innerRoute$D_IN), .ENQ(ifcs_1_innerRoute$ENQ), .DEQ(ifcs_1_innerRoute$DEQ), .CLR(ifcs_1_innerRoute$CLR), .D_OUT(ifcs_1_innerRoute$D_OUT), .FULL_N(ifcs_1_innerRoute$FULL_N), .EMPTY_N(ifcs_1_innerRoute$EMPTY_N)); // submodule ifcs_1_noRouteRsp FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_noRouteRsp(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_noRouteRsp$D_IN), .ENQ(ifcs_1_noRouteRsp$ENQ), .DEQ(ifcs_1_noRouteRsp$DEQ), .CLR(ifcs_1_noRouteRsp$CLR), .D_OUT(ifcs_1_noRouteRsp$D_OUT), .FULL_N(ifcs_1_noRouteRsp$FULL_N), .EMPTY_N(ifcs_1_noRouteRsp$EMPTY_N)); // submodule ifcs_1_routeBack FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_routeBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_routeBack$D_IN), .ENQ(ifcs_1_routeBack$ENQ), .DEQ(ifcs_1_routeBack$DEQ), .CLR(ifcs_1_routeBack$CLR), .D_OUT(ifcs_1_routeBack$D_OUT), .FULL_N(ifcs_1_routeBack$FULL_N), .EMPTY_N(ifcs_1_routeBack$EMPTY_N)); // submodule ifcs_1_rspBack FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_rspBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_1_rspBack$D_IN), .ENQ(ifcs_1_rspBack$ENQ), .DEQ(ifcs_1_rspBack$DEQ), .CLR(ifcs_1_rspBack$CLR), .D_OUT(ifcs_1_rspBack$D_OUT), .FULL_N(ifcs_1_rspBack$FULL_N), .EMPTY_N(ifcs_1_rspBack$EMPTY_N)); // submodule ifcs_2_1_routeBack FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_1_routeBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_2_1_routeBack$D_IN), .ENQ(ifcs_2_1_routeBack$ENQ), .DEQ(ifcs_2_1_routeBack$DEQ), .CLR(ifcs_2_1_routeBack$CLR), .D_OUT(ifcs_2_1_routeBack$D_OUT), .FULL_N(ifcs_2_1_routeBack$FULL_N), .EMPTY_N(ifcs_2_1_routeBack$EMPTY_N)); // submodule ifcs_2_1_rspBack FIFO2 #(.width(32'd72), .guarded(32'd1)) ifcs_2_1_rspBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_2_1_rspBack$D_IN), .ENQ(ifcs_2_1_rspBack$ENQ), .DEQ(ifcs_2_1_rspBack$DEQ), .CLR(ifcs_2_1_rspBack$CLR), .D_OUT(ifcs_2_1_rspBack$D_OUT), .FULL_N(ifcs_2_1_rspBack$FULL_N), .EMPTY_N(ifcs_2_1_rspBack$EMPTY_N)); // submodule ifcs_2_routeBack FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_routeBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_2_routeBack$D_IN), .ENQ(ifcs_2_routeBack$ENQ), .DEQ(ifcs_2_routeBack$DEQ), .CLR(ifcs_2_routeBack$CLR), .D_OUT(ifcs_2_routeBack$D_OUT), .FULL_N(ifcs_2_routeBack$FULL_N), .EMPTY_N(ifcs_2_routeBack$EMPTY_N)); // submodule ifcs_2_rspBack FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_2_rspBack(.RST(RST_N), .CLK(CLK), .D_IN(ifcs_2_rspBack$D_IN), .ENQ(ifcs_2_rspBack$ENQ), .DEQ(ifcs_2_rspBack$DEQ), .CLR(ifcs_2_rspBack$CLR), .D_OUT(ifcs_2_rspBack$D_OUT), .FULL_N(ifcs_2_rspBack$FULL_N), .EMPTY_N(ifcs_2_rspBack$EMPTY_N)); // submodule merged_0_awff FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_0_awff(.RST(RST_N), .CLK(CLK), .D_IN(merged_0_awff$D_IN), .ENQ(merged_0_awff$ENQ), .DEQ(merged_0_awff$DEQ), .CLR(merged_0_awff$CLR), .D_OUT(merged_0_awff$D_OUT), .FULL_N(merged_0_awff$FULL_N), .EMPTY_N(merged_0_awff$EMPTY_N)); // submodule merged_0_wff FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_0_wff(.RST(RST_N), .CLK(CLK), .D_IN(merged_0_wff$D_IN), .ENQ(merged_0_wff$ENQ), .DEQ(merged_0_wff$DEQ), .CLR(merged_0_wff$CLR), .D_OUT(merged_0_wff$D_OUT), .FULL_N(merged_0_wff$FULL_N), .EMPTY_N(merged_0_wff$EMPTY_N)); // submodule merged_1_awff FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_1_awff(.RST(RST_N), .CLK(CLK), .D_IN(merged_1_awff$D_IN), .ENQ(merged_1_awff$ENQ), .DEQ(merged_1_awff$DEQ), .CLR(merged_1_awff$CLR), .D_OUT(merged_1_awff$D_OUT), .FULL_N(merged_1_awff$FULL_N), .EMPTY_N(merged_1_awff$EMPTY_N)); // submodule merged_1_wff FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_1_wff(.RST(RST_N), .CLK(CLK), .D_IN(merged_1_wff$D_IN), .ENQ(merged_1_wff$ENQ), .DEQ(merged_1_wff$DEQ), .CLR(merged_1_wff$CLR), .D_OUT(merged_1_wff$D_OUT), .FULL_N(merged_1_wff$FULL_N), .EMPTY_N(merged_1_wff$EMPTY_N)); // submodule msNoSynth_0_arNoSynth_buffer_ff FIFO1 #(.width(32'd97), .guarded(32'd0)) msNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_0_arNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_0_arNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_0_arNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_0_arNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_0_arNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_0_arNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_0_arNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_0_arNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_0_awNoSynth_buffer_ff FIFO1 #(.width(32'd97), .guarded(32'd0)) msNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_0_awNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_0_awNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_0_awNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_0_awNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_0_awNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_0_awNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_0_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_0_awNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_0_awNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_0_bNoSynth_buffer_ff FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_0_bNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_0_bNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_0_bNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_0_bNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_0_bNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_0_bNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_0_bNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_0_bNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_0_bNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_0_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), .guarded(32'd0)) msNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_0_rNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_0_rNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_0_rNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_0_rNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_0_rNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_0_rNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_0_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_0_rNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_0_rNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_0_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), .guarded(32'd0)) msNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_0_wNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_0_wNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_0_wNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_0_wNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_0_wNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_0_wNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_0_wNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_0_wNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_1_arNoSynth_buffer_ff FIFO1 #(.width(32'd97), .guarded(32'd0)) msNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_1_arNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_1_arNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_1_arNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_1_arNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_1_arNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_1_arNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_1_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_1_arNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_1_arNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_1_awNoSynth_buffer_ff FIFO1 #(.width(32'd97), .guarded(32'd0)) msNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_1_awNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_1_awNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_1_awNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_1_awNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_1_awNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_1_awNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_1_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_1_awNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_1_awNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_1_bNoSynth_buffer_ff FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_1_bNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_1_bNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_1_bNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_1_bNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_1_bNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_1_bNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_1_bNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_1_bNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_1_bNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_1_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), .guarded(32'd0)) msNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_1_rNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_1_rNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_1_rNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_1_rNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_1_rNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_1_rNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_1_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_1_rNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_1_rNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); // submodule msNoSynth_1_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), .guarded(32'd0)) msNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(msNoSynth_1_wNoSynth_buffer_ff$D_IN), .ENQ(msNoSynth_1_wNoSynth_buffer_ff$ENQ), .DEQ(msNoSynth_1_wNoSynth_buffer_ff$DEQ), .CLR(msNoSynth_1_wNoSynth_buffer_ff$CLR), .D_OUT(msNoSynth_1_wNoSynth_buffer_ff$D_OUT), .FULL_N(msNoSynth_1_wNoSynth_buffer_ff$FULL_N), .EMPTY_N(msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); // submodule msNoSynth_1_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) msNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(msNoSynth_1_wNoSynth_buffer_firstValid$D_IN), .EN(msNoSynth_1_wNoSynth_buffer_firstValid$EN), .Q_OUT(msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), .RST_N(RST_N), .axi4_slave_araddr(plic$axi4_slave_araddr), .axi4_slave_arburst(plic$axi4_slave_arburst), .axi4_slave_arcache(plic$axi4_slave_arcache), .axi4_slave_arid(plic$axi4_slave_arid), .axi4_slave_arlen(plic$axi4_slave_arlen), .axi4_slave_arlock(plic$axi4_slave_arlock), .axi4_slave_arprot(plic$axi4_slave_arprot), .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), .axi4_slave_awid(plic$axi4_slave_awid), .axi4_slave_awlen(plic$axi4_slave_awlen), .axi4_slave_awlock(plic$axi4_slave_awlock), .axi4_slave_awprot(plic$axi4_slave_awprot), .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wuser(plic$axi4_slave_wuser), .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), .EN_set_verbosity(plic$EN_set_verbosity), .EN_show_PLIC_state(plic$EN_show_PLIC_state), .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(), .RDY_server_reset_response_get(), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), .axi4_slave_bid(plic$axi4_slave_bid), .axi4_slave_bresp(plic$axi4_slave_bresp), .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_arready(plic$axi4_slave_arready), .axi4_slave_rid(plic$axi4_slave_rid), .axi4_slave_rdata(plic$axi4_slave_rdata), .axi4_slave_rresp(plic$axi4_slave_rresp), .axi4_slave_rlast(plic$axi4_slave_rlast), .axi4_slave_ruser(plic$axi4_slave_ruser), .axi4_slave_rvalid(plic$axi4_slave_rvalid), .v_targets_0_m_eip(plic$v_targets_0_m_eip), .v_targets_1_m_eip(plic$v_targets_1_m_eip)); // submodule proc mkProc proc(.CLK(CLK), .RST_N(hart0_reset$RST_OUT), .debug_module_mem_server_araddr(proc$debug_module_mem_server_araddr), .debug_module_mem_server_arburst(proc$debug_module_mem_server_arburst), .debug_module_mem_server_arcache(proc$debug_module_mem_server_arcache), .debug_module_mem_server_arid(proc$debug_module_mem_server_arid), .debug_module_mem_server_arlen(proc$debug_module_mem_server_arlen), .debug_module_mem_server_arlock(proc$debug_module_mem_server_arlock), .debug_module_mem_server_arprot(proc$debug_module_mem_server_arprot), .debug_module_mem_server_arqos(proc$debug_module_mem_server_arqos), .debug_module_mem_server_arregion(proc$debug_module_mem_server_arregion), .debug_module_mem_server_arsize(proc$debug_module_mem_server_arsize), .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), .debug_module_mem_server_awaddr(proc$debug_module_mem_server_awaddr), .debug_module_mem_server_awburst(proc$debug_module_mem_server_awburst), .debug_module_mem_server_awcache(proc$debug_module_mem_server_awcache), .debug_module_mem_server_awid(proc$debug_module_mem_server_awid), .debug_module_mem_server_awlen(proc$debug_module_mem_server_awlen), .debug_module_mem_server_awlock(proc$debug_module_mem_server_awlock), .debug_module_mem_server_awprot(proc$debug_module_mem_server_awprot), .debug_module_mem_server_awqos(proc$debug_module_mem_server_awqos), .debug_module_mem_server_awregion(proc$debug_module_mem_server_awregion), .debug_module_mem_server_awsize(proc$debug_module_mem_server_awsize), .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wuser(proc$debug_module_mem_server_wuser), .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), .hart0_csr_mem_server_request_put(proc$hart0_csr_mem_server_request_put), .hart0_fpr_mem_server_request_put(proc$hart0_fpr_mem_server_request_put), .hart0_gpr_mem_server_request_put(proc$hart0_gpr_mem_server_request_put), .hart0_put_other_req_put(proc$hart0_put_other_req_put), .hart0_run_halt_server_request_put(proc$hart0_run_halt_server_request_put), .m_external_interrupt_req_set_not_clear(proc$m_external_interrupt_req_set_not_clear), .master0_arready(proc$master0_arready), .master0_awready(proc$master0_awready), .master0_bid(proc$master0_bid), .master0_bresp(proc$master0_bresp), .master0_bvalid(proc$master0_bvalid), .master0_rdata(proc$master0_rdata), .master0_rid(proc$master0_rid), .master0_rlast(proc$master0_rlast), .master0_rresp(proc$master0_rresp), .master0_ruser(proc$master0_ruser), .master0_rvalid(proc$master0_rvalid), .master0_wready(proc$master0_wready), .master1_b_put_val(proc$master1_b_put_val), .master1_r_put_val(proc$master1_r_put_val), .non_maskable_interrupt_req_set_not_clear(proc$non_maskable_interrupt_req_set_not_clear), .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), .EN_master1_aw_drop(proc$EN_master1_aw_drop), .EN_master1_w_drop(proc$EN_master1_w_drop), .EN_master1_b_put(proc$EN_master1_b_put), .EN_master1_ar_drop(proc$EN_master1_ar_drop), .EN_master1_r_put(proc$EN_master1_r_put), .EN_set_verbosity(proc$EN_set_verbosity), .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), .EN_hart0_run_halt_server_response_get(proc$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(proc$EN_hart0_gpr_mem_server_request_put), .EN_hart0_gpr_mem_server_response_get(proc$EN_hart0_gpr_mem_server_response_get), .EN_hart0_fpr_mem_server_request_put(proc$EN_hart0_fpr_mem_server_request_put), .EN_hart0_fpr_mem_server_response_get(proc$EN_hart0_fpr_mem_server_response_get), .EN_hart0_csr_mem_server_request_put(proc$EN_hart0_csr_mem_server_request_put), .EN_hart0_csr_mem_server_response_get(proc$EN_hart0_csr_mem_server_response_get), .EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put), .RDY_start(proc$RDY_start), .master0_awid(proc$master0_awid), .master0_awaddr(proc$master0_awaddr), .master0_awlen(proc$master0_awlen), .master0_awsize(proc$master0_awsize), .master0_awburst(proc$master0_awburst), .master0_awlock(proc$master0_awlock), .master0_awcache(proc$master0_awcache), .master0_awprot(proc$master0_awprot), .master0_awqos(proc$master0_awqos), .master0_awregion(proc$master0_awregion), .master0_awvalid(proc$master0_awvalid), .master0_wdata(proc$master0_wdata), .master0_wstrb(proc$master0_wstrb), .master0_wlast(proc$master0_wlast), .master0_wuser(proc$master0_wuser), .master0_wvalid(proc$master0_wvalid), .master0_bready(proc$master0_bready), .master0_arid(proc$master0_arid), .master0_araddr(proc$master0_araddr), .master0_arlen(proc$master0_arlen), .master0_arsize(proc$master0_arsize), .master0_arburst(proc$master0_arburst), .master0_arlock(proc$master0_arlock), .master0_arcache(proc$master0_arcache), .master0_arprot(proc$master0_arprot), .master0_arqos(proc$master0_arqos), .master0_arregion(proc$master0_arregion), .master0_arvalid(proc$master0_arvalid), .master0_rready(proc$master0_rready), .master1_aw_canPeek(proc$master1_aw_canPeek), .master1_aw_peek(proc$master1_aw_peek), .RDY_master1_aw_peek(proc$RDY_master1_aw_peek), .RDY_master1_aw_drop(proc$RDY_master1_aw_drop), .master1_w_canPeek(proc$master1_w_canPeek), .master1_w_peek(proc$master1_w_peek), .RDY_master1_w_peek(proc$RDY_master1_w_peek), .RDY_master1_w_drop(proc$RDY_master1_w_drop), .master1_b_canPut(proc$master1_b_canPut), .RDY_master1_b_put(proc$RDY_master1_b_put), .master1_ar_canPeek(proc$master1_ar_canPeek), .master1_ar_peek(proc$master1_ar_peek), .RDY_master1_ar_peek(proc$RDY_master1_ar_peek), .RDY_master1_ar_drop(proc$RDY_master1_ar_drop), .master1_r_canPut(proc$master1_r_canPut), .RDY_master1_r_put(proc$RDY_master1_r_put), .RDY_set_verbosity(), .debug_module_mem_server_awready(proc$debug_module_mem_server_awready), .debug_module_mem_server_wready(proc$debug_module_mem_server_wready), .debug_module_mem_server_bid(proc$debug_module_mem_server_bid), .debug_module_mem_server_bresp(proc$debug_module_mem_server_bresp), .debug_module_mem_server_bvalid(proc$debug_module_mem_server_bvalid), .debug_module_mem_server_arready(proc$debug_module_mem_server_arready), .debug_module_mem_server_rid(proc$debug_module_mem_server_rid), .debug_module_mem_server_rdata(proc$debug_module_mem_server_rdata), .debug_module_mem_server_rresp(proc$debug_module_mem_server_rresp), .debug_module_mem_server_rlast(proc$debug_module_mem_server_rlast), .debug_module_mem_server_ruser(proc$debug_module_mem_server_ruser), .debug_module_mem_server_rvalid(proc$debug_module_mem_server_rvalid), .RDY_hart0_run_halt_server_request_put(proc$RDY_hart0_run_halt_server_request_put), .hart0_run_halt_server_response_get(proc$hart0_run_halt_server_response_get), .RDY_hart0_run_halt_server_response_get(proc$RDY_hart0_run_halt_server_response_get), .RDY_hart0_gpr_mem_server_request_put(proc$RDY_hart0_gpr_mem_server_request_put), .hart0_gpr_mem_server_response_get(proc$hart0_gpr_mem_server_response_get), .RDY_hart0_gpr_mem_server_response_get(proc$RDY_hart0_gpr_mem_server_response_get), .RDY_hart0_fpr_mem_server_request_put(), .hart0_fpr_mem_server_response_get(), .RDY_hart0_fpr_mem_server_response_get(), .RDY_hart0_csr_mem_server_request_put(proc$RDY_hart0_csr_mem_server_request_put), .hart0_csr_mem_server_response_get(proc$hart0_csr_mem_server_response_get), .RDY_hart0_csr_mem_server_response_get(proc$RDY_hart0_csr_mem_server_response_get), .RDY_hart0_put_other_req_put()); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_IO_addr_imem_not_dmem(soc_map$m_is_IO_addr_imem_not_dmem), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), .m_plic_addr_range(soc_map$m_plic_addr_range), .m_near_mem_io_addr_range(), .m_flash_mem_addr_range(), .m_ethernet_0_addr_range(), .m_dma_0_addr_range(), .m_uart16550_0_addr_range(), .m_gpio_0_addr_range(), .m_boot_rom_addr_range(), .m_ddr4_0_uncached_addr_range(), .m_ddr4_0_cached_addr_range(), .m_mem0_controller_addr_range(soc_map$m_mem0_controller_addr_range), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), .m_pc_reset_value(), .m_mtvec_reset_value(), .m_nmivec_reset_value()); // submodule ssNoSynth_0_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) ssNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_0_arNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_0_arNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_0_arNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_0_arNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_0_arNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_0_arNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_0_arNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_0_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) ssNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_0_awNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_0_awNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_0_awNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_0_awNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_0_awNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_0_awNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_0_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_0_awNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_0_bNoSynth_buffer_ff FIFO1 #(.width(32'd7), .guarded(32'd0)) ssNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_0_bNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_0_bNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_0_bNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_0_bNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_0_bNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_0_bNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_0_bNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_0_bNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_0_rNoSynth_buffer_ff FIFO1 #(.width(32'd73), .guarded(32'd0)) ssNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_0_rNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_0_rNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_0_rNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_0_rNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_0_rNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_0_rNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_0_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_0_rNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_0_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), .guarded(32'd0)) ssNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_0_wNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_0_wNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_0_wNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_0_wNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_0_wNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_0_wNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_0_wNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_1_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) ssNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_1_arNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_1_arNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_1_arNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_1_arNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_1_arNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_1_arNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_1_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_1_arNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_1_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) ssNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_1_awNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_1_awNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_1_awNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_1_awNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_1_awNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_1_awNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_1_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_1_awNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_1_bNoSynth_buffer_ff FIFO1 #(.width(32'd7), .guarded(32'd0)) ssNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_1_bNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_1_bNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_1_bNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_1_bNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_1_bNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_1_bNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_1_bNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_1_bNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_1_rNoSynth_buffer_ff FIFO1 #(.width(32'd73), .guarded(32'd0)) ssNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_1_rNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_1_rNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_1_rNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_1_rNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_1_rNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_1_rNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_1_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_1_rNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_1_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), .guarded(32'd0)) ssNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_1_wNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_1_wNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_1_wNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_1_wNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_1_wNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_1_wNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_1_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_1_wNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_2_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) ssNoSynth_2_arNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_2_arNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_2_arNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_2_arNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_2_arNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_2_arNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_2_arNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_2_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_2_arNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_2_arNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_2_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) ssNoSynth_2_awNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_2_awNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_2_awNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_2_awNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_2_awNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_2_awNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_2_awNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_2_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_2_awNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_2_awNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_2_bNoSynth_buffer_ff FIFO1 #(.width(32'd7), .guarded(32'd0)) ssNoSynth_2_bNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_2_bNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_2_bNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_2_bNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_2_bNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_2_bNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_2_bNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_2_bNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_2_bNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_2_bNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_2_rNoSynth_buffer_ff FIFO1 #(.width(32'd73), .guarded(32'd0)) ssNoSynth_2_rNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_2_rNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_2_rNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_2_rNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_2_rNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_2_rNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_2_rNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_2_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_2_rNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_2_rNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT)); // submodule ssNoSynth_2_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), .guarded(32'd0)) ssNoSynth_2_wNoSynth_buffer_ff(.RST(RST_N), .CLK(CLK), .D_IN(ssNoSynth_2_wNoSynth_buffer_ff$D_IN), .ENQ(ssNoSynth_2_wNoSynth_buffer_ff$ENQ), .DEQ(ssNoSynth_2_wNoSynth_buffer_ff$DEQ), .CLR(ssNoSynth_2_wNoSynth_buffer_ff$CLR), .D_OUT(ssNoSynth_2_wNoSynth_buffer_ff$D_OUT), .FULL_N(ssNoSynth_2_wNoSynth_buffer_ff$FULL_N), .EMPTY_N(ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N)); // submodule ssNoSynth_2_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) ssNoSynth_2_wNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN), .EN(ssNoSynth_2_wNoSynth_buffer_firstValid$EN), .Q_OUT(ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule tagController_tmp_awreqff FIFO2 #(.width(32'd98), .guarded(32'd1)) tagController_tmp_awreqff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(tagController_tmp_awreqff$D_IN), .ENQ(tagController_tmp_awreqff$ENQ), .DEQ(tagController_tmp_awreqff$DEQ), .CLR(tagController_tmp_awreqff$CLR), .D_OUT(tagController_tmp_awreqff$D_OUT), .FULL_N(tagController_tmp_awreqff$FULL_N), .EMPTY_N(tagController_tmp_awreqff$EMPTY_N)); // submodule tagController_tmp_newRst MakeReset0 #(.init(1'd0)) tagController_tmp_newRst(.CLK(CLK), .RST(hart0_reset$RST_OUT), .ASSERT_IN(tagController_tmp_newRst$ASSERT_IN), .ASSERT_OUT(), .OUT_RST(tagController_tmp_newRst$OUT_RST)); // submodule tagController_tmp_tagCon mkTagController tagController_tmp_tagCon(.CLK(CLK), .RST_N(tagController_tmp_newRst$OUT_RST), .cache_request_put_val(tagController_tmp_tagCon$cache_request_put_val), .memory_response_put_val(tagController_tmp_tagCon$memory_response_put_val), .EN_cache_request_put(tagController_tmp_tagCon$EN_cache_request_put), .EN_cache_response_get(tagController_tmp_tagCon$EN_cache_response_get), .EN_memory_request_get(tagController_tmp_tagCon$EN_memory_request_get), .EN_memory_response_put(tagController_tmp_tagCon$EN_memory_response_put), .cache_request_canPut(), .RDY_cache_request_put(tagController_tmp_tagCon$RDY_cache_request_put), .cache_response_canGet(), .cache_response_peek(), .RDY_cache_response_peek(), .cache_response_get(tagController_tmp_tagCon$cache_response_get), .RDY_cache_response_get(tagController_tmp_tagCon$RDY_cache_response_get), .memory_request_canGet(), .memory_request_peek(), .RDY_memory_request_peek(), .memory_request_get(tagController_tmp_tagCon$memory_request_get), .RDY_memory_request_get(tagController_tmp_tagCon$RDY_memory_request_get), .memory_response_canPut(), .RDY_memory_response_put(tagController_tmp_tagCon$RDY_memory_response_put)); // submodule tmp2_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) tmp2_arNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(tmp2_arNoSynth_buffer_ff$D_IN), .ENQ(tmp2_arNoSynth_buffer_ff$ENQ), .DEQ(tmp2_arNoSynth_buffer_ff$DEQ), .CLR(tmp2_arNoSynth_buffer_ff$CLR), .D_OUT(tmp2_arNoSynth_buffer_ff$D_OUT), .FULL_N(tmp2_arNoSynth_buffer_ff$FULL_N), .EMPTY_N(tmp2_arNoSynth_buffer_ff$EMPTY_N)); // submodule tmp2_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) tmp2_arNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(tmp2_arNoSynth_buffer_firstValid$D_IN), .EN(tmp2_arNoSynth_buffer_firstValid$EN), .Q_OUT(tmp2_arNoSynth_buffer_firstValid$Q_OUT)); // submodule tmp2_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), .guarded(32'd0)) tmp2_awNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(tmp2_awNoSynth_buffer_ff$D_IN), .ENQ(tmp2_awNoSynth_buffer_ff$ENQ), .DEQ(tmp2_awNoSynth_buffer_ff$DEQ), .CLR(tmp2_awNoSynth_buffer_ff$CLR), .D_OUT(tmp2_awNoSynth_buffer_ff$D_OUT), .FULL_N(tmp2_awNoSynth_buffer_ff$FULL_N), .EMPTY_N(tmp2_awNoSynth_buffer_ff$EMPTY_N)); // submodule tmp2_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) tmp2_awNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(tmp2_awNoSynth_buffer_firstValid$D_IN), .EN(tmp2_awNoSynth_buffer_firstValid$EN), .Q_OUT(tmp2_awNoSynth_buffer_firstValid$Q_OUT)); // submodule tmp2_bNoSynth_buffer_ff FIFO1 #(.width(32'd7), .guarded(32'd0)) tmp2_bNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(tmp2_bNoSynth_buffer_ff$D_IN), .ENQ(tmp2_bNoSynth_buffer_ff$ENQ), .DEQ(tmp2_bNoSynth_buffer_ff$DEQ), .CLR(tmp2_bNoSynth_buffer_ff$CLR), .D_OUT(tmp2_bNoSynth_buffer_ff$D_OUT), .FULL_N(tmp2_bNoSynth_buffer_ff$FULL_N), .EMPTY_N(tmp2_bNoSynth_buffer_ff$EMPTY_N)); // submodule tmp2_bNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) tmp2_bNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(tmp2_bNoSynth_buffer_firstValid$D_IN), .EN(tmp2_bNoSynth_buffer_firstValid$EN), .Q_OUT(tmp2_bNoSynth_buffer_firstValid$Q_OUT)); // submodule tmp2_rNoSynth_buffer_ff FIFO1 #(.width(32'd73), .guarded(32'd0)) tmp2_rNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(tmp2_rNoSynth_buffer_ff$D_IN), .ENQ(tmp2_rNoSynth_buffer_ff$ENQ), .DEQ(tmp2_rNoSynth_buffer_ff$DEQ), .CLR(tmp2_rNoSynth_buffer_ff$CLR), .D_OUT(tmp2_rNoSynth_buffer_ff$D_OUT), .FULL_N(tmp2_rNoSynth_buffer_ff$FULL_N), .EMPTY_N(tmp2_rNoSynth_buffer_ff$EMPTY_N)); // submodule tmp2_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) tmp2_rNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(tmp2_rNoSynth_buffer_firstValid$D_IN), .EN(tmp2_rNoSynth_buffer_firstValid$EN), .Q_OUT(tmp2_rNoSynth_buffer_firstValid$Q_OUT)); // submodule tmp2_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), .guarded(32'd0)) tmp2_wNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(tmp2_wNoSynth_buffer_ff$D_IN), .ENQ(tmp2_wNoSynth_buffer_ff$ENQ), .DEQ(tmp2_wNoSynth_buffer_ff$DEQ), .CLR(tmp2_wNoSynth_buffer_ff$CLR), .D_OUT(tmp2_wNoSynth_buffer_ff$D_OUT), .FULL_N(tmp2_wNoSynth_buffer_ff$FULL_N), .EMPTY_N(tmp2_wNoSynth_buffer_ff$EMPTY_N)); // submodule tmp2_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), .init(1'd1)) tmp2_wNoSynth_buffer_firstValid(.CLK(CLK), .D_IN(tmp2_wNoSynth_buffer_firstValid$D_IN), .EN(tmp2_wNoSynth_buffer_firstValid$EN), .Q_OUT(tmp2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule uncached_mem_shim_arff FIFO2 #(.width(32'd98), .guarded(32'd1)) uncached_mem_shim_arff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(uncached_mem_shim_arff$D_IN), .ENQ(uncached_mem_shim_arff$ENQ), .DEQ(uncached_mem_shim_arff$DEQ), .CLR(uncached_mem_shim_arff$CLR), .D_OUT(uncached_mem_shim_arff$D_OUT), .FULL_N(uncached_mem_shim_arff$FULL_N), .EMPTY_N(uncached_mem_shim_arff$EMPTY_N)); // submodule uncached_mem_shim_awff FIFO2 #(.width(32'd98), .guarded(32'd1)) uncached_mem_shim_awff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(uncached_mem_shim_awff$D_IN), .ENQ(uncached_mem_shim_awff$ENQ), .DEQ(uncached_mem_shim_awff$DEQ), .CLR(uncached_mem_shim_awff$CLR), .D_OUT(uncached_mem_shim_awff$D_OUT), .FULL_N(uncached_mem_shim_awff$FULL_N), .EMPTY_N(uncached_mem_shim_awff$EMPTY_N)); // submodule uncached_mem_shim_bff FIFO2 #(.width(32'd7), .guarded(32'd1)) uncached_mem_shim_bff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(uncached_mem_shim_bff$D_IN), .ENQ(uncached_mem_shim_bff$ENQ), .DEQ(uncached_mem_shim_bff$DEQ), .CLR(uncached_mem_shim_bff$CLR), .D_OUT(uncached_mem_shim_bff$D_OUT), .FULL_N(uncached_mem_shim_bff$FULL_N), .EMPTY_N(uncached_mem_shim_bff$EMPTY_N)); // submodule uncached_mem_shim_rff FIFO2 #(.width(32'd73), .guarded(32'd1)) uncached_mem_shim_rff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(uncached_mem_shim_rff$D_IN), .ENQ(uncached_mem_shim_rff$ENQ), .DEQ(uncached_mem_shim_rff$DEQ), .CLR(uncached_mem_shim_rff$CLR), .D_OUT(uncached_mem_shim_rff$D_OUT), .FULL_N(uncached_mem_shim_rff$FULL_N), .EMPTY_N(uncached_mem_shim_rff$EMPTY_N)); // submodule uncached_mem_shim_wff FIFO2 #(.width(32'd74), .guarded(32'd1)) uncached_mem_shim_wff(.RST(hart0_reset$RST_OUT), .CLK(CLK), .D_IN(uncached_mem_shim_wff$D_IN), .ENQ(uncached_mem_shim_wff$ENQ), .DEQ(uncached_mem_shim_wff$DEQ), .CLR(uncached_mem_shim_wff$CLR), .D_OUT(uncached_mem_shim_wff$D_OUT), .FULL_N(uncached_mem_shim_wff$FULL_N), .EMPTY_N(uncached_mem_shim_wff$EMPTY_N)); // rule RL_rl_dm_hart0_reset assign CAN_FIRE_RL_rl_dm_hart0_reset = debug_module$RDY_hart0_reset_client_request_get && rg_hart0_reset_delay == 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset = CAN_FIRE_RL_rl_dm_hart0_reset ; // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || debug_module$RDY_hart0_reset_client_response_put && proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = debug_module$RDY_hart0_client_run_halt_request_get && proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = debug_module$RDY_hart0_client_run_halt_response_put && proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = debug_module$RDY_hart0_get_other_req_get ; assign WILL_FIRE_RL_mkConnectionGetPut = debug_module$RDY_hart0_get_other_req_get ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = debug_module$RDY_hart0_gpr_mem_client_response_put && proc$RDY_hart0_gpr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = debug_module$RDY_hart0_csr_mem_client_response_put && proc$RDY_hart0_csr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; // rule RL_checkSinkReady assign CAN_FIRE_RL_checkSinkReady = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady = 1'd1 ; // rule RL_checkSinkReady_1 assign CAN_FIRE_RL_checkSinkReady_1 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_1 = 1'd1 ; // rule RL_checkSinkReady_2 assign CAN_FIRE_RL_checkSinkReady_2 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_2 = 1'd1 ; // rule RL_craftReq assign CAN_FIRE_RL_craftReq = ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerReq$EMPTY_N ; assign WILL_FIRE_RL_craftReq = CAN_FIRE_RL_craftReq ; // rule RL_craftReq_1 assign CAN_FIRE_RL_craftReq_1 = ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerReq$EMPTY_N ; assign WILL_FIRE_RL_craftReq_1 = CAN_FIRE_RL_craftReq_1 ; // rule RL_arbitrate assign CAN_FIRE_RL_arbitrate = (CAN_FIRE_RL_craftReq && reqWires_0$wget || CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) && !state ; assign WILL_FIRE_RL_arbitrate = CAN_FIRE_RL_arbitrate ; // rule RL_source_selected assign CAN_FIRE_RL_source_selected = (!ifcs_0_innerRoute$EMPTY_N || ifcs_0_innerReq$EMPTY_N) && !state && MUX_activeSource_0$write_1__VAL_1 ; assign WILL_FIRE_RL_source_selected = CAN_FIRE_RL_source_selected ; // rule RL_burst assign CAN_FIRE_RL_burst = ifcs_0_innerReq$EMPTY_N && ifcs_0_innerRoute$EMPTY_N && state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 ; assign WILL_FIRE_RL_burst = CAN_FIRE_RL_burst ; // rule RL_source_selected_1 assign CAN_FIRE_RL_source_selected_1 = (!ifcs_1_innerRoute$EMPTY_N || ifcs_1_innerReq$EMPTY_N) && !state && MUX_activeSource_1$write_1__VAL_1 ; assign WILL_FIRE_RL_source_selected_1 = CAN_FIRE_RL_source_selected_1 ; // rule RL_burst_1 assign CAN_FIRE_RL_burst_1 = ifcs_1_innerReq$EMPTY_N && ifcs_1_innerRoute$EMPTY_N && state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 ; assign WILL_FIRE_RL_burst_1 = CAN_FIRE_RL_burst_1 ; // rule __me_check_355 assign CAN_FIRE___me_check_355 = 1'b1 ; assign WILL_FIRE___me_check_355 = 1'b1 ; // rule __me_check_357 assign CAN_FIRE___me_check_357 = 1'b1 ; assign WILL_FIRE___me_check_357 = 1'b1 ; // rule RL_sink_selected assign CAN_FIRE_RL_sink_selected = flitToSink_0$whas && IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 ; assign WILL_FIRE_RL_sink_selected = CAN_FIRE_RL_sink_selected ; // rule RL_sink_selected_1 assign CAN_FIRE_RL_sink_selected_1 = flitToSink_1$whas && IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 ; assign WILL_FIRE_RL_sink_selected_1 = CAN_FIRE_RL_sink_selected_1 ; // rule RL_sink_selected_2 assign CAN_FIRE_RL_sink_selected_2 = flitToSink_2$whas && IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 ; assign WILL_FIRE_RL_sink_selected_2 = CAN_FIRE_RL_sink_selected_2 ; // rule __me_check_359 assign CAN_FIRE___me_check_359 = 1'b1 ; assign WILL_FIRE___me_check_359 = 1'b1 ; // rule RL_checkSinkReady_3 assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; // rule RL_checkSinkReady_4 assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; // rule RL_craftReq_2 assign CAN_FIRE_RL_craftReq_2 = ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; // rule RL_craftReq_3 assign CAN_FIRE_RL_craftReq_3 = ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; // rule RL_craftReq_4 assign CAN_FIRE_RL_craftReq_4 = ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; // rule RL_arbitrate_1 assign CAN_FIRE_RL_arbitrate_1 = reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 && !state_1 ; assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; // rule RL_source_selected_2 assign CAN_FIRE_RL_source_selected_2 = (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && !state_1 && sourceSelect_1_0$whas ; assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; // rule RL_burst_2 assign CAN_FIRE_RL_burst_2 = ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 ; assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; // rule RL_source_selected_3 assign CAN_FIRE_RL_source_selected_3 = (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && !state_1 && sourceSelect_1_1$whas ; assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; // rule RL_burst_3 assign CAN_FIRE_RL_burst_3 = ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 ; assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; // rule __me_check_374 assign CAN_FIRE___me_check_374 = 1'b1 ; assign WILL_FIRE___me_check_374 = 1'b1 ; // rule RL_source_selected_4 assign CAN_FIRE_RL_source_selected_4 = (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && !state_1 && sourceSelect_1_2$whas ; assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; // rule RL_burst_4 assign CAN_FIRE_RL_burst_4 = ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 ; assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; // rule __me_check_372 assign CAN_FIRE___me_check_372 = 1'b1 ; assign WILL_FIRE___me_check_372 = 1'b1 ; // rule __me_check_376 assign CAN_FIRE___me_check_376 = 1'b1 ; assign WILL_FIRE___me_check_376 = 1'b1 ; // rule RL_sink_selected_3 assign CAN_FIRE_RL_sink_selected_3 = flitToSink_1_0$whas && msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; // rule RL_sink_selected_4 assign CAN_FIRE_RL_sink_selected_4 = flitToSink_1_1$whas && msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; // rule __me_check_378 assign CAN_FIRE___me_check_378 = 1'b1 ; assign WILL_FIRE___me_check_378 = 1'b1 ; // rule RL_checkSinkReady_5 assign CAN_FIRE_RL_checkSinkReady_5 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_5 = 1'd1 ; // rule RL_checkSinkReady_6 assign CAN_FIRE_RL_checkSinkReady_6 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_6 = 1'd1 ; // rule RL_checkSinkReady_7 assign CAN_FIRE_RL_checkSinkReady_7 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_7 = 1'd1 ; // rule RL_craftReq_5 assign CAN_FIRE_RL_craftReq_5 = ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerReq$EMPTY_N ; assign WILL_FIRE_RL_craftReq_5 = CAN_FIRE_RL_craftReq_5 ; // rule RL_craftReq_6 assign CAN_FIRE_RL_craftReq_6 = ifcs_1_1_innerRoute$EMPTY_N && ifcs_1_1_innerReq$EMPTY_N ; assign WILL_FIRE_RL_craftReq_6 = CAN_FIRE_RL_craftReq_6 ; // rule RL_arbitrate_2 assign CAN_FIRE_RL_arbitrate_2 = (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget || CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) && !state_1_1 ; assign WILL_FIRE_RL_arbitrate_2 = CAN_FIRE_RL_arbitrate_2 ; // rule RL_source_selected_5 assign CAN_FIRE_RL_source_selected_5 = (!ifcs_0_1_innerRoute$EMPTY_N || ifcs_0_1_innerReq$EMPTY_N) && !state_1_1 && sourceSelect_1_0_1$whas ; assign WILL_FIRE_RL_source_selected_5 = CAN_FIRE_RL_source_selected_5 ; // rule RL_burst_5 assign CAN_FIRE_RL_burst_5 = ifcs_0_1_innerReq$EMPTY_N && ifcs_0_1_innerRoute$EMPTY_N && state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 ; assign WILL_FIRE_RL_burst_5 = CAN_FIRE_RL_burst_5 ; // rule RL_source_selected_6 assign CAN_FIRE_RL_source_selected_6 = (!ifcs_1_1_innerRoute$EMPTY_N || ifcs_1_1_innerReq$EMPTY_N) && !state_1_1 && sourceSelect_1_1_1$whas ; assign WILL_FIRE_RL_source_selected_6 = CAN_FIRE_RL_source_selected_6 ; // rule RL_burst_6 assign CAN_FIRE_RL_burst_6 = ifcs_1_1_innerReq$EMPTY_N && ifcs_1_1_innerRoute$EMPTY_N && state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 ; assign WILL_FIRE_RL_burst_6 = CAN_FIRE_RL_burst_6 ; // rule __me_check_414 assign CAN_FIRE___me_check_414 = 1'b1 ; assign WILL_FIRE___me_check_414 = 1'b1 ; // rule __me_check_416 assign CAN_FIRE___me_check_416 = 1'b1 ; assign WILL_FIRE___me_check_416 = 1'b1 ; // rule RL_sink_selected_5 assign CAN_FIRE_RL_sink_selected_5 = flitToSink_1_0_1$whas && ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_5 = CAN_FIRE_RL_sink_selected_5 ; // rule RL_sink_selected_6 assign CAN_FIRE_RL_sink_selected_6 = flitToSink_1_1_1$whas && ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_6 = CAN_FIRE_RL_sink_selected_6 ; // rule RL_sink_selected_7 assign CAN_FIRE_RL_sink_selected_7 = flitToSink_1_2$whas && ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_7 = CAN_FIRE_RL_sink_selected_7 ; // rule __me_check_418 assign CAN_FIRE___me_check_418 = 1'b1 ; assign WILL_FIRE___me_check_418 = 1'b1 ; // rule RL_checkSinkReady_8 assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; // rule RL_checkSinkReady_9 assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; // rule RL_craftReq_7 assign CAN_FIRE_RL_craftReq_7 = ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; // rule RL_craftReq_8 assign CAN_FIRE_RL_craftReq_8 = ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; // rule RL_craftReq_9 assign CAN_FIRE_RL_craftReq_9 = ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; // rule RL_arbitrate_3 assign CAN_FIRE_RL_arbitrate_3 = reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 && !state_1_1_1 ; assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; // rule RL_source_selected_7 assign CAN_FIRE_RL_source_selected_7 = (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && !state_1_1_1 && MUX_activeSource_1_1_0$write_1__VAL_1 ; assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; // rule RL_burst_7 assign CAN_FIRE_RL_burst_7 = ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 ; assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; // rule RL_source_selected_8 assign CAN_FIRE_RL_source_selected_8 = (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && !state_1_1_1 && MUX_activeSource_1_1_1_1$write_1__VAL_1 ; assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; // rule RL_burst_8 assign CAN_FIRE_RL_burst_8 = ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 ; assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; // rule __me_check_433 assign CAN_FIRE___me_check_433 = 1'b1 ; assign WILL_FIRE___me_check_433 = 1'b1 ; // rule RL_source_selected_9 assign CAN_FIRE_RL_source_selected_9 = (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && !state_1_1_1 && MUX_activeSource_1_1_2$write_1__VAL_1 ; assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; // rule RL_burst_9 assign CAN_FIRE_RL_burst_9 = ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 ; assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; // rule __me_check_431 assign CAN_FIRE___me_check_431 = 1'b1 ; assign WILL_FIRE___me_check_431 = 1'b1 ; // rule __me_check_435 assign CAN_FIRE___me_check_435 = 1'b1 ; assign WILL_FIRE___me_check_435 = 1'b1 ; // rule RL_sink_selected_8 assign CAN_FIRE_RL_sink_selected_8 = flitToSink_1_1_0$whas && msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; // rule RL_sink_selected_9 assign CAN_FIRE_RL_sink_selected_9 = flitToSink_1_1_1_1$whas && msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; // rule __me_check_437 assign CAN_FIRE___me_check_437 = 1'b1 ; assign WILL_FIRE___me_check_437 = 1'b1 ; // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; // rule RL_proc_uncached_awSynth_src_setPeek assign CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek = proc$RDY_master1_aw_peek ; assign WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek = proc$RDY_master1_aw_peek ; // rule RL_proc_uncached_wSynth_src_setPeek assign CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek = proc$RDY_master1_w_peek ; assign WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek = proc$RDY_master1_w_peek ; // rule RL_proc_uncached_arSynth_src_setPeek assign CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek = proc$RDY_master1_ar_peek ; assign WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek = proc$RDY_master1_ar_peek ; // rule RL_uncached_mem_master_awSynth_src_setPeek assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; // rule RL_uncached_mem_master_awSynth_src_warnDoDrop assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = uncached_mem_master_awSynth_src_dropWire$whas && !uncached_mem_shim_awff$EMPTY_N ; assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop ; // rule RL_uncached_mem_master_wSynth_src_setPeek assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; // rule RL_uncached_mem_master_wSynth_src_warnDoDrop assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = uncached_mem_master_wSynth_src_dropWire$whas && !uncached_mem_shim_wff$EMPTY_N ; assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop ; // rule RL_uncached_mem_master_bSynth_snk_warnDoPut assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = uncached_mem_master_bSynth_snk_putWire$whas && !uncached_mem_shim_bff$FULL_N ; assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut ; // rule RL_uncached_mem_master_arSynth_src_setPeek assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; // rule RL_uncached_mem_master_arSynth_src_warnDoDrop assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = uncached_mem_master_arSynth_src_dropWire$whas && !uncached_mem_shim_arff$EMPTY_N ; assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop ; // rule RL_uncached_mem_master_rSynth_snk_warnDoPut assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = uncached_mem_master_rSynth_snk_putWire$whas && !uncached_mem_shim_rff$FULL_N ; assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut ; // rule RL_tagController_tmp_passCacheResponse assign CAN_FIRE_RL_tagController_tmp_passCacheResponse = tagController_tmp_tagCon$RDY_cache_response_get && !tagController_tmp_shimSlave_bff_rv[7] && !tagController_tmp_shimSlave_rff_rv[73] ; assign WILL_FIRE_RL_tagController_tmp_passCacheResponse = CAN_FIRE_RL_tagController_tmp_passCacheResponse ; // rule RL_tagController_tmp_passMemoryRequest assign CAN_FIRE_RL_tagController_tmp_passMemoryRequest = tagController_tmp_tagCon$RDY_memory_request_get && !tagController_tmp_shimMaster_wff_rv[73] && (tagController_tmp_doneSendingAW || !tagController_tmp_shimMaster_awff_rv[99]) && !tagController_tmp_shimMaster_arff_rv[99] ; assign WILL_FIRE_RL_tagController_tmp_passMemoryRequest = CAN_FIRE_RL_tagController_tmp_passMemoryRequest ; // rule RL_tagController_tmp_ug_slave_u_b_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek = tagController_tmp_shimSlave_bff_rv$port1__read[7] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_setPeek ; // rule RL_tagController_tmp_ug_slave_u_r_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek = tagController_tmp_shimSlave_rff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_setPeek ; // rule RL_tagController_tmp_ug_master_u_aw_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek = tagController_tmp_shimMaster_awff_rv$port1__read[99] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek ; // rule RL_tagController_tmp_ug_master_u_w_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = tagController_tmp_shimMaster_wff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek ; // rule RL_tagController_tmp_ug_master_u_ar_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = tagController_tmp_shimMaster_arff_rv$port1__read[99] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek ; // rule RL_tmp2_awNoSynth_forwardFlit assign CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit = proc$master0_awvalid && tmp2_awNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit = CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; // rule RL_tmp2_awNoSynth_forwardReady assign CAN_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; // rule RL_tmp2_awNoSynth_snk_warnDoPut assign CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit && !tmp2_awNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut ; // rule RL_tmp2_awNoSynth_snk_doPut assign CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut = tmp2_awNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; assign WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut = CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut ; // rule RL_tmp2_wNoSynth_forwardFlit assign CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit = proc$master0_wvalid && tmp2_wNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit = CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; // rule RL_tmp2_wNoSynth_forwardReady assign CAN_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; // rule RL_tmp2_wNoSynth_snk_warnDoPut assign CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit && !tmp2_wNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut ; // rule RL_tmp2_wNoSynth_snk_doPut assign CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut = tmp2_wNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; assign WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut = CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut ; // rule RL_tmp2_bNoSynth_dropFlit assign CAN_FIRE_RL_tmp2_bNoSynth_dropFlit = tmp2_bNoSynth_buffer_ff$EMPTY_N && proc$master0_bready ; assign WILL_FIRE_RL_tmp2_bNoSynth_dropFlit = CAN_FIRE_RL_tmp2_bNoSynth_dropFlit ; // rule RL_tmp2_bNoSynth_src_warnDoDrop assign CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && !tmp2_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop ; // rule RL_tmp2_arNoSynth_forwardFlit assign CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit = proc$master0_arvalid && tmp2_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit = CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; // rule RL_tmp2_arNoSynth_forwardReady assign CAN_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; // rule RL_tmp2_arNoSynth_snk_warnDoPut assign CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit && !tmp2_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut ; // rule RL_tmp2_arNoSynth_snk_doPut assign CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut = tmp2_arNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; assign WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut = CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut ; // rule RL_tmp2_rNoSynth_dropFlit assign CAN_FIRE_RL_tmp2_rNoSynth_dropFlit = tmp2_rNoSynth_buffer_ff$EMPTY_N && proc$master0_rready ; assign WILL_FIRE_RL_tmp2_rNoSynth_dropFlit = CAN_FIRE_RL_tmp2_rNoSynth_dropFlit ; // rule RL_tmp2_rNoSynth_src_warnDoDrop assign CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && !tmp2_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop ; // rule RL_Prelude_inst_changeSpecialWires_ug_src_setPeek assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = tmp2_awNoSynth_buffer_firstValid$Q_OUT && (tmp2_awNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut) ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek ; // rule RL_Prelude_inst_changeSpecialWires_connect assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; // rule RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && !tmp2_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop ; // rule RL_Prelude_inst_changeSpecialWires_ug_src_doDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && tmp2_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; // rule RL_tmp2_awNoSynth_buffer_enqueue assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut && (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop || tmp2_awNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; // rule RL_tmp2_awNoSynth_buffer_dequeue assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop && tmp2_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; // rule RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && tagController_tmp_shimSlave_awff_rv[98] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut ; // rule RL_Prelude_inst_changeSpecialWires_ug_snk_doPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = tmp2_awNoSynth_buffer_ff$EMPTY_N && !tagController_tmp_shimSlave_awff_rv[98] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_aw_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && tagController_tmp_shimSlave_awff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut ; // rule RL_tagController_tmp_ug_slave_u_aw_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = !tagController_tmp_shimSlave_awff_rv[98] && CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut ; // rule RL_tagController_tmp_getCacheAW assign CAN_FIRE_RL_tagController_tmp_getCacheAW = tagController_tmp_shimSlave_awff_rv$port1__read[98] && tagController_tmp_awreqff$FULL_N ; assign WILL_FIRE_RL_tagController_tmp_getCacheAW = CAN_FIRE_RL_tagController_tmp_getCacheAW ; // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = tmp2_wNoSynth_buffer_firstValid$Q_OUT && (tmp2_wNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut) ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek ; // rule RL_Prelude_inst_changeSpecialWires_1_connect assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && !tmp2_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop ; // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && tmp2_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; // rule RL_tmp2_wNoSynth_buffer_enqueue assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut && (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop || tmp2_wNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; // rule RL_tmp2_wNoSynth_buffer_dequeue assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop && tmp2_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && tagController_tmp_shimSlave_wff_rv[74] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut ; // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = tmp2_wNoSynth_buffer_ff$EMPTY_N && !tagController_tmp_shimSlave_wff_rv[74] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_w_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && tagController_tmp_shimSlave_wff_rv[74] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut ; // rule RL_tagController_tmp_ug_slave_u_w_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = !tagController_tmp_shimSlave_wff_rv[74] && CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut ; // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = 1'd1 ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = 1'd1 ; // rule RL_Prelude_inst_changeSpecialWires_2_connect assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = tagController_tmp_shimSlave_bff_rv$port1__read[7] && tmp2_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop ; // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && tagController_tmp_shimSlave_bff_rv$port1__read[7] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_b_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop && !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop ; // rule RL_tagController_tmp_ug_slave_u_b_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = tagController_tmp_shimSlave_bff_rv$port1__read[7] && CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop ; // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && !tmp2_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut ; // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = tmp2_bNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut ; // rule RL_tmp2_bNoSynth_src_setPeek assign CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek = tmp2_bNoSynth_buffer_firstValid$Q_OUT && (tmp2_bNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut) ; assign WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek = CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek ; // rule RL_tmp2_bNoSynth_forwardFlit assign CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; // rule RL_tmp2_bNoSynth_src_doDrop assign CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop = CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && tmp2_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop = CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; // rule RL_tmp2_bNoSynth_buffer_enqueue assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut && (!CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop || tmp2_bNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; // rule RL_tmp2_bNoSynth_buffer_dequeue assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop && tmp2_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = tmp2_arNoSynth_buffer_firstValid$Q_OUT && (tmp2_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut) ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek ; // rule RL_Prelude_inst_changeSpecialWires_3_connect assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && !tmp2_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop ; // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && tmp2_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; // rule RL_tmp2_arNoSynth_buffer_enqueue assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut && (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop || tmp2_arNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; // rule RL_tmp2_arNoSynth_buffer_dequeue assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop && tmp2_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && tagController_tmp_shimSlave_arff_rv[98] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut ; // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = tmp2_arNoSynth_buffer_ff$EMPTY_N && !tagController_tmp_shimSlave_arff_rv[98] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_ar_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && tagController_tmp_shimSlave_arff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut ; // rule RL_tagController_tmp_ug_slave_u_ar_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = !tagController_tmp_shimSlave_arff_rv[98] && CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut ; // rule RL_tagController_tmp_passCacheWrite assign CAN_FIRE_RL_tagController_tmp_passCacheWrite = tagController_tmp_shimSlave_wff_rv$port1__read[74] && tagController_tmp_tagCon$RDY_cache_request_put && tagController_tmp_awreqff$EMPTY_N ; assign WILL_FIRE_RL_tagController_tmp_passCacheWrite = CAN_FIRE_RL_tagController_tmp_passCacheWrite && !WILL_FIRE_RL_tagController_tmp_passCacheRead ; // rule RL_tagController_tmp_passCacheRead assign CAN_FIRE_RL_tagController_tmp_passCacheRead = tagController_tmp_shimSlave_arff_rv$port1__read[98] && tagController_tmp_tagCon$RDY_cache_request_put ; assign WILL_FIRE_RL_tagController_tmp_passCacheRead = CAN_FIRE_RL_tagController_tmp_passCacheRead ; // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = 1'd1 ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = 1'd1 ; // rule RL_Prelude_inst_changeSpecialWires_4_connect assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = tagController_tmp_shimSlave_rff_rv$port1__read[73] && tmp2_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop ; // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && tagController_tmp_shimSlave_rff_rv$port1__read[73] ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_r_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop && !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop ; // rule RL_tagController_tmp_ug_slave_u_r_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = tagController_tmp_shimSlave_rff_rv$port1__read[73] && CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop ; // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && !tmp2_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut ; // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = tmp2_rNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut ; // rule RL_tmp2_rNoSynth_src_setPeek assign CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek = tmp2_rNoSynth_buffer_firstValid$Q_OUT && (tmp2_rNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut) ; assign WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek = CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek ; // rule RL_tmp2_rNoSynth_forwardFlit assign CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; // rule RL_tmp2_rNoSynth_src_doDrop assign CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop = CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && tmp2_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop = CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; // rule RL_tmp2_rNoSynth_buffer_enqueue assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut && (!CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop || tmp2_rNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; // rule RL_tmp2_rNoSynth_buffer_dequeue assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop && tmp2_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; // rule RL_slave_vector_0_bSynth_src_setPeek assign CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek = uncached_mem_shim_bff$EMPTY_N ; assign WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek = uncached_mem_shim_bff$EMPTY_N ; // rule RL_slave_vector_0_rSynth_src_setPeek assign CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek = uncached_mem_shim_rff$EMPTY_N ; assign WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek = uncached_mem_shim_rff$EMPTY_N ; // rule RL_msNoSynth_0_awNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = proc$master1_aw_canPeek && msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; // rule RL_msNoSynth_0_awNoSynth_forwardReady assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; // rule RL_proc_uncached_awSynth_src_warnDoDrop assign CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && !proc$master1_aw_canPeek ; assign WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop ; // rule RL_proc_uncached_awSynth_src_doDrop assign CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop = proc$RDY_master1_aw_drop && CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && proc$master1_aw_canPeek ; assign WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop = CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; // rule RL_msNoSynth_0_awNoSynth_snk_warnDoPut assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && !msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut ; // rule RL_msNoSynth_0_awNoSynth_snk_doPut assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = msNoSynth_0_awNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut ; // rule RL_msNoSynth_0_wNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = proc$master1_w_canPeek && msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; // rule RL_msNoSynth_0_wNoSynth_forwardReady assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; // rule RL_proc_uncached_wSynth_src_warnDoDrop assign CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && !proc$master1_w_canPeek ; assign WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop ; // rule RL_proc_uncached_wSynth_src_doDrop assign CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop = proc$RDY_master1_w_drop && CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && proc$master1_w_canPeek ; assign WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop = CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; // rule RL_msNoSynth_0_wNoSynth_snk_warnDoPut assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && !msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut ; // rule RL_msNoSynth_0_wNoSynth_snk_doPut assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = msNoSynth_0_wNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut ; // rule RL_msNoSynth_0_bNoSynth_dropFlit assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && proc$master1_b_canPut ; assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; // rule RL_msNoSynth_0_bNoSynth_src_warnDoDrop assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && !msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop ; // rule RL_msNoSynth_0_arNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = proc$master1_ar_canPeek && msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; // rule RL_msNoSynth_0_arNoSynth_forwardReady assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; // rule RL_proc_uncached_arSynth_src_warnDoDrop assign CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && !proc$master1_ar_canPeek ; assign WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop ; // rule RL_proc_uncached_arSynth_src_doDrop assign CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop = proc$RDY_master1_ar_drop && CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && proc$master1_ar_canPeek ; assign WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop = CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; // rule RL_msNoSynth_0_arNoSynth_snk_warnDoPut assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && !msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut ; // rule RL_msNoSynth_0_arNoSynth_snk_doPut assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = msNoSynth_0_arNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut ; // rule RL_msNoSynth_0_rNoSynth_dropFlit assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && proc$master1_r_canPut ; assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; // rule RL_msNoSynth_0_rNoSynth_src_warnDoDrop assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && !msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop ; // rule RL_msNoSynth_1_bNoSynth_dropFlit assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && debug_module$master_bready ; assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit ; // rule RL_msNoSynth_1_bNoSynth_src_warnDoDrop assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && !msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop ; // rule RL_msNoSynth_1_rNoSynth_dropFlit assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && debug_module$master_rready ; assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit ; // rule RL_msNoSynth_1_rNoSynth_src_warnDoDrop assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && !msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_0_awNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_awff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; // rule RL_ssNoSynth_0_awNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && !ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_0_wNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_wff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; // rule RL_ssNoSynth_0_wNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && !ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_0_bNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = uncached_mem_shim_bff$EMPTY_N && ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; // rule RL_ssNoSynth_0_bNoSynth_forwardReady assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; // rule RL_slave_vector_0_bSynth_src_warnDoDrop assign CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && !uncached_mem_shim_bff$EMPTY_N ; assign WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop ; // rule RL_slave_vector_0_bSynth_src_doDrop assign CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop = uncached_mem_shim_bff$EMPTY_N && CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; assign WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop = CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; // rule RL_uncached_mem_master_bSynth_snk_doPut assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = uncached_mem_shim_bff$FULL_N && uncached_mem_master_bSynth_snk_putWire$whas ; assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; // rule RL_ssNoSynth_0_bNoSynth_snk_warnDoPut assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && !ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut ; // rule RL_ssNoSynth_0_bNoSynth_snk_doPut assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = ssNoSynth_0_bNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut ; // rule RL_ssNoSynth_0_arNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_arff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; // rule RL_ssNoSynth_0_arNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && !ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_0_rNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = uncached_mem_shim_rff$EMPTY_N && ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; // rule RL_ssNoSynth_0_rNoSynth_forwardReady assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; // rule RL_slave_vector_0_rSynth_src_warnDoDrop assign CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && !uncached_mem_shim_rff$EMPTY_N ; assign WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop ; // rule RL_slave_vector_0_rSynth_src_doDrop assign CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop = uncached_mem_shim_rff$EMPTY_N && CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; assign WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop = CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; // rule RL_uncached_mem_master_rSynth_snk_doPut assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = uncached_mem_shim_rff$FULL_N && uncached_mem_master_rSynth_snk_putWire$whas ; assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; // rule RL_ssNoSynth_0_rNoSynth_snk_warnDoPut assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && !ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut ; // rule RL_ssNoSynth_0_rNoSynth_snk_doPut assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = ssNoSynth_0_rNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut ; // rule RL_ssNoSynth_1_awNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_awready ; assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit ; // rule RL_ssNoSynth_1_awNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && !ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_1_wNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_wready ; assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit ; // rule RL_ssNoSynth_1_wNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && !ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_1_bNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = plic$axi4_slave_bvalid && ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; // rule RL_ssNoSynth_1_bNoSynth_forwardReady assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; // rule RL_ssNoSynth_1_bNoSynth_snk_warnDoPut assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit && !ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut ; // rule RL_ssNoSynth_1_bNoSynth_snk_doPut assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = ssNoSynth_1_bNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut ; // rule RL_ssNoSynth_1_arNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_arready ; assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit ; // rule RL_ssNoSynth_1_arNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && !ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_1_rNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = plic$axi4_slave_rvalid && ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; // rule RL_ssNoSynth_1_rNoSynth_forwardReady assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; // rule RL_ssNoSynth_1_rNoSynth_snk_warnDoPut assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit && !ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut ; // rule RL_ssNoSynth_1_rNoSynth_snk_doPut assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = ssNoSynth_1_rNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut ; // rule RL_ssNoSynth_2_awNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_awready ; assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit ; // rule RL_ssNoSynth_2_awNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && !ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_2_wNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_wready ; assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit ; // rule RL_ssNoSynth_2_wNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && !ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop ; // rule RL_ssNoSynth_2_arNoSynth_dropFlit assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_arready ; assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit ; // rule RL_ssNoSynth_2_arNoSynth_src_warnDoDrop assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && !ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop ; // rule RL_merged_0_passFlit assign CAN_FIRE_RL_merged_0_passFlit = merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && merged_0_flitLeft == 8'd0 ; assign WILL_FIRE_RL_merged_0_passFlit = CAN_FIRE_RL_merged_0_passFlit ; // rule RL_merged_1_passFlit assign CAN_FIRE_RL_merged_1_passFlit = merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && merged_1_flitLeft == 8'd0 ; assign WILL_FIRE_RL_merged_1_passFlit = CAN_FIRE_RL_merged_1_passFlit ; // rule RL_ifcs_0_firstFlit assign CAN_FIRE_RL_ifcs_0_firstFlit = IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && ifcs_0_innerRoute$FULL_N && (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd0 && IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit = CAN_FIRE_RL_ifcs_0_firstFlit ; // rule RL_ifcs_0_followFlits assign CAN_FIRE_RL_ifcs_0_followFlits = IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_followFlits = CAN_FIRE_RL_ifcs_0_followFlits ; // rule RL_ifcs_0_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_nonRoutableFlit = IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && (!CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171] || !ifcs_0_noRoute_inner_pendingReq) && ifcs_0_state == 2'd0 && IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_nonRoutableFlit ; // rule RL_ifcs_0_drainFlits assign CAN_FIRE_RL_ifcs_0_drainFlits = IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_drainFlits = CAN_FIRE_RL_ifcs_0_drainFlits ; // rule __me_check_325 assign CAN_FIRE___me_check_325 = 1'b1 ; assign WILL_FIRE___me_check_325 = 1'b1 ; // rule RL_ifcs_1_firstFlit assign CAN_FIRE_RL_ifcs_1_firstFlit = IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && ifcs_1_innerReq$FULL_N && ifcs_1_innerRoute$FULL_N && (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && ifcs_1_state == 2'd0 && IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 == 2'd1 ; assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; // rule RL_ifcs_1_followFlits assign CAN_FIRE_RL_ifcs_1_followFlits = IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && ifcs_1_innerReq$FULL_N && (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && ifcs_1_state == 2'd1 ; assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; // rule RL_ifcs_1_nonRoutableFlit assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && (!CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171] || !ifcs_1_noRoute_inner_pendingReq) && ifcs_1_state == 2'd0 && IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 != 2'd1 ; assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; // rule RL_ifcs_1_drainFlits assign CAN_FIRE_RL_ifcs_1_drainFlits = IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && ifcs_1_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; // rule __me_check_333 assign CAN_FIRE___me_check_333 = 1'b1 ; assign WILL_FIRE___me_check_333 = 1'b1 ; // rule RL_ifcs_0_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_firstFlit_1 = ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && ifcs_0_rspBack$FULL_N && ifcs_0_routeBack$FULL_N && !ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit_1 = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; // rule RL_ifcs_0_followFlits_1 assign CAN_FIRE_RL_ifcs_0_followFlits_1 = ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && ifcs_0_rspBack$FULL_N && ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_followFlits_1 = CAN_FIRE_RL_ifcs_0_followFlits_1 ; // rule __me_check_337 assign CAN_FIRE___me_check_337 = 1'b1 ; assign WILL_FIRE___me_check_337 = 1'b1 ; // rule RL_ssNoSynth_0_bNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut && (!ssNoSynth_0_bNoSynth_buffer_dequeueing$whas || ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_0_bNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = ssNoSynth_0_bNoSynth_buffer_dequeueing$whas && ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; // rule RL_ifcs_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_firstFlit_1 = ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && ifcs_1_rspBack$FULL_N && ifcs_1_routeBack$FULL_N && !ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; // rule RL_ifcs_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_followFlits_1 = ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && ifcs_1_rspBack$FULL_N && ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_followFlits_1 ; // rule __me_check_339 assign CAN_FIRE___me_check_339 = 1'b1 ; assign WILL_FIRE___me_check_339 = 1'b1 ; // rule RL_ssNoSynth_1_bNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut && (!ssNoSynth_1_bNoSynth_buffer_dequeueing$whas || ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_1_bNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = ssNoSynth_1_bNoSynth_buffer_dequeueing$whas && ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; // rule RL_sinks_0_warnDoPut assign CAN_FIRE_RL_sinks_0_warnDoPut = CAN_FIRE_RL_sink_selected && ((split_0_flitLeft == 8'd0) ? !ssNoSynth_0_awNoSynth_buffer_ff$FULL_N || !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; assign WILL_FIRE_RL_sinks_0_warnDoPut = CAN_FIRE_RL_sinks_0_warnDoPut ; // rule RL_sinks_0_doPut assign CAN_FIRE_RL_sinks_0_doPut = IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 && CAN_FIRE_RL_sink_selected ; assign WILL_FIRE_RL_sinks_0_doPut = CAN_FIRE_RL_sinks_0_doPut ; // rule RL_split_0_putFirst assign CAN_FIRE_RL_split_0_putFirst = split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 && split_0_flitLeft == 8'd0 ; assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; // rule RL_ssNoSynth_0_awNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || MUX_split_0_flitLeft$write_1__SEL_2) ; assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek ; // rule RL_ssNoSynth_0_awNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; // rule RL_slave_vector_0_awSynth_snk_warnDoPut assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && !uncached_mem_shim_awff$FULL_N ; assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut ; // rule RL_uncached_mem_master_awSynth_src_doDrop assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = uncached_mem_shim_awff$EMPTY_N && uncached_mem_master_awSynth_src_dropWire$whas ; assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; // rule RL_slave_vector_0_awSynth_snk_doPut assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut = uncached_mem_shim_awff$FULL_N && CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut = CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; // rule RL_ssNoSynth_0_awNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; // rule RL_ssNoSynth_0_awNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = MUX_split_0_flitLeft$write_1__SEL_2 && (!CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop || ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_0_awNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop && ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; // rule RL_split_0_putOther assign CAN_FIRE_RL_split_0_putOther = CAN_FIRE_RL_sinks_0_doPut && (!split_0_doPut$wget[172] || ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) && split_0_flitLeft != 8'd0 ; assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; // rule RL_ssNoSynth_0_wNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || ssNoSynth_0_wNoSynth_buffer_enqw$whas) ; assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek ; // rule RL_ssNoSynth_0_wNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; // rule RL_slave_vector_0_wSynth_snk_warnDoPut assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && !uncached_mem_shim_wff$FULL_N ; assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut ; // rule RL_uncached_mem_master_wSynth_src_doDrop assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = uncached_mem_shim_wff$EMPTY_N && uncached_mem_master_wSynth_src_dropWire$whas ; assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; // rule RL_slave_vector_0_wSynth_snk_doPut assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut = uncached_mem_shim_wff$FULL_N && CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut = CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; // rule RL_ssNoSynth_0_wNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; // rule RL_ssNoSynth_0_wNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = ssNoSynth_0_wNoSynth_buffer_enqw$whas && (!CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop || ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_0_wNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop && ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; // rule RL_sinks_1_warnDoPut assign CAN_FIRE_RL_sinks_1_warnDoPut = CAN_FIRE_RL_sink_selected_1 && ((split_1_flitLeft == 8'd0) ? !ssNoSynth_1_awNoSynth_buffer_ff$FULL_N || !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; assign WILL_FIRE_RL_sinks_1_warnDoPut = CAN_FIRE_RL_sinks_1_warnDoPut ; // rule RL_sinks_1_doPut assign CAN_FIRE_RL_sinks_1_doPut = IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 && CAN_FIRE_RL_sink_selected_1 ; assign WILL_FIRE_RL_sinks_1_doPut = CAN_FIRE_RL_sinks_1_doPut ; // rule RL_split_1_putFirst assign CAN_FIRE_RL_split_1_putFirst = split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 && split_1_flitLeft == 8'd0 ; assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; // rule RL_ssNoSynth_1_awNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || MUX_split_1_flitLeft$write_1__SEL_2) ; assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek ; // rule RL_ssNoSynth_1_awNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; // rule RL_ssNoSynth_1_awNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; // rule RL_ssNoSynth_1_awNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = MUX_split_1_flitLeft$write_1__SEL_2 && (!CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop || ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_1_awNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop && ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; // rule RL_split_1_putOther assign CAN_FIRE_RL_split_1_putOther = CAN_FIRE_RL_sinks_1_doPut && (!split_1_doPut$wget[172] || ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) && split_1_flitLeft != 8'd0 ; assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; // rule RL_ssNoSynth_1_wNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || ssNoSynth_1_wNoSynth_buffer_enqw$whas) ; assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek ; // rule RL_ssNoSynth_1_wNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; // rule RL_ssNoSynth_1_wNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; // rule RL_ssNoSynth_1_wNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = ssNoSynth_1_wNoSynth_buffer_enqw$whas && (!CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop || ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_1_wNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop && ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; // rule RL_sinks_2_warnDoPut assign CAN_FIRE_RL_sinks_2_warnDoPut = CAN_FIRE_RL_sink_selected_2 && ((split_2_flitLeft == 8'd0) ? !ssNoSynth_2_awNoSynth_buffer_ff$FULL_N || !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; assign WILL_FIRE_RL_sinks_2_warnDoPut = CAN_FIRE_RL_sinks_2_warnDoPut ; // rule RL_sinks_2_doPut assign CAN_FIRE_RL_sinks_2_doPut = IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 && CAN_FIRE_RL_sink_selected_2 ; assign WILL_FIRE_RL_sinks_2_doPut = CAN_FIRE_RL_sinks_2_doPut ; // rule RL_split_2_putFirst assign CAN_FIRE_RL_split_2_putFirst = split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 && split_2_flitLeft == 8'd0 ; assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; // rule RL_ssNoSynth_2_awNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N || MUX_split_2_flitLeft$write_1__SEL_2) ; assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek ; // rule RL_ssNoSynth_2_awNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; // rule RL_ssNoSynth_2_awNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; // rule RL_ssNoSynth_2_awNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = MUX_split_2_flitLeft$write_1__SEL_2 && (!CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop || ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_2_awNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop && ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; // rule RL_split_2_putOther assign CAN_FIRE_RL_split_2_putOther = CAN_FIRE_RL_sinks_2_doPut && (!split_2_doPut$wget[172] || ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) && split_2_flitLeft != 8'd0 ; assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; // rule RL_ssNoSynth_2_wNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N || ssNoSynth_2_wNoSynth_buffer_enqw$whas) ; assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek ; // rule RL_ssNoSynth_2_wNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; // rule RL_ssNoSynth_2_wNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; // rule RL_ssNoSynth_2_wNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = ssNoSynth_2_wNoSynth_buffer_enqw$whas && (!CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop || ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_2_wNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop && ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; // rule RL_sinks_1_0_warnDoPut assign CAN_FIRE_RL_sinks_1_0_warnDoPut = CAN_FIRE_RL_sink_selected_3 && !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sinks_1_0_warnDoPut = CAN_FIRE_RL_sinks_1_0_warnDoPut ; // rule RL_sinks_1_0_doPut assign CAN_FIRE_RL_sinks_1_0_doPut = msNoSynth_0_bNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_3 ; assign WILL_FIRE_RL_sinks_1_0_doPut = CAN_FIRE_RL_sinks_1_0_doPut ; // rule RL_ifcs_0_drainNoRouteResponse assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = ifcs_0_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_0_doPut && msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && !WILL_FIRE_RL_sinks_1_0_doPut ; // rule RL_ifcs_0_nonRoutableGenRsp assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_noRoute_inner_pendingReq$port1__read && ifcs_0_noRouteRsp$FULL_N && (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) ; assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; // rule __me_check_323 assign CAN_FIRE___me_check_323 = 1'b1 ; assign WILL_FIRE___me_check_323 = 1'b1 ; // rule __me_check_324 assign CAN_FIRE___me_check_324 = 1'b1 ; assign WILL_FIRE___me_check_324 = 1'b1 ; // rule __me_check_327 assign CAN_FIRE___me_check_327 = 1'b1 ; assign WILL_FIRE___me_check_327 = 1'b1 ; // rule RL_merged_0_awFlit assign CAN_FIRE_RL_merged_0_awFlit = msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut) && merged_0_awff$FULL_N ; assign WILL_FIRE_RL_merged_0_awFlit = CAN_FIRE_RL_merged_0_awFlit ; // rule RL_msNoSynth_0_awNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut && (!CAN_FIRE_RL_merged_0_awFlit || msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; // rule RL_msNoSynth_0_awNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = CAN_FIRE_RL_merged_0_awFlit && msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; // rule RL_merged_0_wFlit assign CAN_FIRE_RL_merged_0_wFlit = msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut) && merged_0_wff$FULL_N ; assign WILL_FIRE_RL_merged_0_wFlit = CAN_FIRE_RL_merged_0_wFlit ; // rule RL_msNoSynth_0_wNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut && (!CAN_FIRE_RL_merged_0_wFlit || msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; // rule RL_msNoSynth_0_wNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = CAN_FIRE_RL_merged_0_wFlit && msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; // rule RL_merged_0_genFirst assign CAN_FIRE_RL_merged_0_genFirst = merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && merged_0_doDrop$whas && merged_0_flitLeft == 8'd0 ; assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; // rule RL_merged_0_genOther assign CAN_FIRE_RL_merged_0_genOther = merged_0_wff$EMPTY_N && merged_0_doDrop$whas && merged_0_flitLeft != 8'd0 ; assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; // rule RL_ifcs_0_snk_warnDoPut assign CAN_FIRE_RL_ifcs_0_snk_warnDoPut = ifcs_0_snk_putWire$whas && !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_0_snk_warnDoPut = CAN_FIRE_RL_ifcs_0_snk_warnDoPut ; // rule RL_ifcs_0_snk_doPut assign CAN_FIRE_RL_ifcs_0_snk_doPut = msNoSynth_0_bNoSynth_buffer_ff$FULL_N && ifcs_0_snk_putWire$whas ; assign WILL_FIRE_RL_ifcs_0_snk_doPut = CAN_FIRE_RL_ifcs_0_snk_doPut ; // rule RL_msNoSynth_0_bNoSynth_src_setPeek assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_ifcs_0_snk_doPut) ; assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek ; // rule RL_msNoSynth_0_bNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; // rule RL_proc_uncached_bSynth_snk_warnDoPut assign CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && !proc$master1_b_canPut ; assign WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut ; // rule RL_proc_uncached_bSynth_snk_doPut assign CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut = proc$RDY_master1_b_put && CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; assign WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut = CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; // rule RL_msNoSynth_0_bNoSynth_src_doDrop assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; // rule RL_msNoSynth_0_bNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ifcs_0_snk_doPut && (!CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop || msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; // rule RL_msNoSynth_0_bNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop && msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; // rule RL_sinks_1_1_warnDoPut assign CAN_FIRE_RL_sinks_1_1_warnDoPut = CAN_FIRE_RL_sink_selected_4 && !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sinks_1_1_warnDoPut = CAN_FIRE_RL_sinks_1_1_warnDoPut ; // rule RL_sinks_1_1_doPut assign CAN_FIRE_RL_sinks_1_1_doPut = msNoSynth_1_bNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_4 ; assign WILL_FIRE_RL_sinks_1_1_doPut = CAN_FIRE_RL_sinks_1_1_doPut ; // rule RL_ifcs_1_drainNoRouteResponse assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = ifcs_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_doPut && msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && !WILL_FIRE_RL_sinks_1_1_doPut ; // rule RL_ifcs_1_nonRoutableGenRsp assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && ifcs_1_noRoute_inner_pendingReq$port1__read && ifcs_1_noRouteRsp$FULL_N && (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) ; assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; // rule __me_check_331 assign CAN_FIRE___me_check_331 = 1'b1 ; assign WILL_FIRE___me_check_331 = 1'b1 ; // rule __me_check_332 assign CAN_FIRE___me_check_332 = 1'b1 ; assign WILL_FIRE___me_check_332 = 1'b1 ; // rule __me_check_335 assign CAN_FIRE___me_check_335 = 1'b1 ; assign WILL_FIRE___me_check_335 = 1'b1 ; // rule RL_merged_1_genFirst assign CAN_FIRE_RL_merged_1_genFirst = merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && merged_1_doDrop$whas && merged_1_flitLeft == 8'd0 ; assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; // rule RL_merged_1_genOther assign CAN_FIRE_RL_merged_1_genOther = merged_1_wff$EMPTY_N && merged_1_doDrop$whas && merged_1_flitLeft != 8'd0 ; assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; // rule RL_ifcs_1_snk_warnDoPut assign CAN_FIRE_RL_ifcs_1_snk_warnDoPut = ifcs_1_snk_putWire$whas && !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_1_snk_warnDoPut = CAN_FIRE_RL_ifcs_1_snk_warnDoPut ; // rule RL_ifcs_1_snk_doPut assign CAN_FIRE_RL_ifcs_1_snk_doPut = msNoSynth_1_bNoSynth_buffer_ff$FULL_N && ifcs_1_snk_putWire$whas ; assign WILL_FIRE_RL_ifcs_1_snk_doPut = CAN_FIRE_RL_ifcs_1_snk_doPut ; // rule RL_msNoSynth_1_bNoSynth_src_setPeek assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_ifcs_1_snk_doPut) ; assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek ; // rule RL_msNoSynth_1_bNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; // rule RL_msNoSynth_1_bNoSynth_src_doDrop assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; // rule RL_msNoSynth_1_bNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ifcs_1_snk_doPut && (!CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop || msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; // rule RL_msNoSynth_1_bNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop && msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; // rule RL_ifcs_0_1_firstFlit assign CAN_FIRE_RL_ifcs_0_1_firstFlit = msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && ifcs_0_1_innerReq$FULL_N && ifcs_0_1_innerRoute$FULL_N && ifcs_0_1_state == 2'd0 && msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit = CAN_FIRE_RL_ifcs_0_1_firstFlit ; // rule RL_ifcs_0_1_followFlits assign CAN_FIRE_RL_ifcs_0_1_followFlits = msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && ifcs_0_1_innerReq$FULL_N && ifcs_0_1_state == 2'd1 && msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ifcs_0_1_followFlits = CAN_FIRE_RL_ifcs_0_1_followFlits ; // rule RL_ifcs_0_1_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit = msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && ifcs_0_1_noRoute_flitCount == 9'd0 && ifcs_0_1_state == 2'd0 && msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ; // rule RL_ifcs_0_1_drainFlits assign CAN_FIRE_RL_ifcs_0_1_drainFlits = (msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) && ifcs_0_1_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_1_drainFlits = CAN_FIRE_RL_ifcs_0_1_drainFlits ; // rule __me_check_384 assign CAN_FIRE___me_check_384 = 1'b1 ; assign WILL_FIRE___me_check_384 = 1'b1 ; // rule RL_ifcs_0_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_1_firstFlit_1 = ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && ifcs_0_1_routeBack$FULL_N && !ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit_1 = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; // rule RL_ifcs_0_1_followFlits_1 assign CAN_FIRE_RL_ifcs_0_1_followFlits_1 = ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_followFlits_1 = CAN_FIRE_RL_ifcs_0_1_followFlits_1 ; // rule __me_check_396 assign CAN_FIRE___me_check_396 = 1'b1 ; assign WILL_FIRE___me_check_396 = 1'b1 ; // rule RL_ssNoSynth_0_rNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut && (!ssNoSynth_0_rNoSynth_buffer_dequeueing$whas || ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_0_rNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = ssNoSynth_0_rNoSynth_buffer_dequeueing$whas && ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; // rule RL_ifcs_1_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_1_firstFlit_1 = ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && ifcs_1_1_rspBack$FULL_N && ifcs_1_1_routeBack$FULL_N && !ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; // rule RL_ifcs_1_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_1_followFlits_1 = ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && ifcs_1_1_rspBack$FULL_N && ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_1_followFlits_1 ; // rule __me_check_398 assign CAN_FIRE___me_check_398 = 1'b1 ; assign WILL_FIRE___me_check_398 = 1'b1 ; // rule RL_ssNoSynth_1_rNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut && (!ssNoSynth_1_rNoSynth_buffer_dequeueing$whas || ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_1_rNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = ssNoSynth_1_rNoSynth_buffer_dequeueing$whas && ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; // rule RL_sinks_1_0_warnDoPut_1 assign CAN_FIRE_RL_sinks_1_0_warnDoPut_1 = CAN_FIRE_RL_sink_selected_5 && !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sinks_1_0_warnDoPut_1 = CAN_FIRE_RL_sinks_1_0_warnDoPut_1 ; // rule RL_sinks_1_0_doPut_1 assign CAN_FIRE_RL_sinks_1_0_doPut_1 = ssNoSynth_0_arNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_5 ; assign WILL_FIRE_RL_sinks_1_0_doPut_1 = CAN_FIRE_RL_sinks_1_0_doPut_1 ; // rule RL_ssNoSynth_0_arNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_sinks_1_0_doPut_1) ; assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek ; // rule RL_ssNoSynth_0_arNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; // rule RL_slave_vector_0_arSynth_snk_warnDoPut assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && !uncached_mem_shim_arff$FULL_N ; assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut ; // rule RL_uncached_mem_master_arSynth_src_doDrop assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = uncached_mem_shim_arff$EMPTY_N && uncached_mem_master_arSynth_src_dropWire$whas ; assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; // rule RL_slave_vector_0_arSynth_snk_doPut assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut = uncached_mem_shim_arff$FULL_N && CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut = CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; // rule RL_ssNoSynth_0_arNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; // rule RL_ssNoSynth_0_arNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = CAN_FIRE_RL_sinks_1_0_doPut_1 && (!CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop || ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_0_arNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop && ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; // rule RL_sinks_1_1_warnDoPut_1 assign CAN_FIRE_RL_sinks_1_1_warnDoPut_1 = CAN_FIRE_RL_sink_selected_6 && !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sinks_1_1_warnDoPut_1 = CAN_FIRE_RL_sinks_1_1_warnDoPut_1 ; // rule RL_sinks_1_1_doPut_1 assign CAN_FIRE_RL_sinks_1_1_doPut_1 = ssNoSynth_1_arNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_6 ; assign WILL_FIRE_RL_sinks_1_1_doPut_1 = CAN_FIRE_RL_sinks_1_1_doPut_1 ; // rule RL_ssNoSynth_1_arNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_sinks_1_1_doPut_1) ; assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek ; // rule RL_ssNoSynth_1_arNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = debug_module$RDY_hart0_gpr_mem_client_request_get && proc$RDY_hart0_gpr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = debug_module$RDY_hart0_csr_mem_client_request_get && proc$RDY_hart0_csr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ssNoSynth_1_arNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; // rule RL_ssNoSynth_1_arNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = CAN_FIRE_RL_sinks_1_1_doPut_1 && (!CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop || ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_1_arNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop && ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; // rule RL_sinks_1_2_warnDoPut assign CAN_FIRE_RL_sinks_1_2_warnDoPut = CAN_FIRE_RL_sink_selected_7 && !ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sinks_1_2_warnDoPut = CAN_FIRE_RL_sinks_1_2_warnDoPut ; // rule RL_sinks_1_2_doPut assign CAN_FIRE_RL_sinks_1_2_doPut = ssNoSynth_2_arNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_7 ; assign WILL_FIRE_RL_sinks_1_2_doPut = CAN_FIRE_RL_sinks_1_2_doPut ; // rule RL_ssNoSynth_2_arNoSynth_src_setPeek assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT && (ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_sinks_1_2_doPut) ; assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek ; // rule RL_ssNoSynth_2_arNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; // rule RL_ssNoSynth_2_bNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = proc$debug_module_mem_server_bvalid && ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; // rule RL_ssNoSynth_2_bNoSynth_forwardReady assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; // rule RL_ssNoSynth_2_bNoSynth_snk_warnDoPut assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit && !ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut ; // rule RL_ssNoSynth_2_bNoSynth_snk_doPut assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = ssNoSynth_2_bNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut ; // rule RL_ssNoSynth_2_arNoSynth_src_doDrop assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; // rule RL_ssNoSynth_2_arNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = CAN_FIRE_RL_sinks_1_2_doPut && (!CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop || ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_2_arNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop && ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; // rule RL_ssNoSynth_2_rNoSynth_forwardFlit assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = proc$debug_module_mem_server_rvalid && ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; // rule RL_ssNoSynth_2_rNoSynth_forwardReady assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; // rule RL_ssNoSynth_2_rNoSynth_snk_warnDoPut assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit && !ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut ; // rule RL_ssNoSynth_2_rNoSynth_snk_doPut assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = ssNoSynth_2_rNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut ; // rule RL_ifcs_2_firstFlit assign CAN_FIRE_RL_ifcs_2_firstFlit = ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && ifcs_2_rspBack$FULL_N && ifcs_2_routeBack$FULL_N && !ifcs_2_state ; assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; // rule RL_ifcs_2_followFlits assign CAN_FIRE_RL_ifcs_2_followFlits = ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && ifcs_2_rspBack$FULL_N && ifcs_2_state ; assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; // rule __me_check_341 assign CAN_FIRE___me_check_341 = 1'b1 ; assign WILL_FIRE___me_check_341 = 1'b1 ; // rule RL_ssNoSynth_2_bNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut && (!ssNoSynth_2_bNoSynth_buffer_dequeueing$whas || ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_2_bNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = ssNoSynth_2_bNoSynth_buffer_dequeueing$whas && ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; // rule RL_ifcs_2_1_firstFlit assign CAN_FIRE_RL_ifcs_2_1_firstFlit = ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && ifcs_2_1_rspBack$FULL_N && ifcs_2_1_routeBack$FULL_N && !ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_firstFlit = CAN_FIRE_RL_ifcs_2_1_firstFlit ; // rule RL_ifcs_2_1_followFlits assign CAN_FIRE_RL_ifcs_2_1_followFlits = ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && ifcs_2_1_rspBack$FULL_N && ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_followFlits = CAN_FIRE_RL_ifcs_2_1_followFlits ; // rule __me_check_400 assign CAN_FIRE___me_check_400 = 1'b1 ; assign WILL_FIRE___me_check_400 = 1'b1 ; // rule RL_ssNoSynth_2_rNoSynth_buffer_enqueue assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut && (!ssNoSynth_2_rNoSynth_buffer_dequeueing$whas || ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; // rule RL_ssNoSynth_2_rNoSynth_buffer_dequeue assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = ssNoSynth_2_rNoSynth_buffer_dequeueing$whas && ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; // rule RL_sinks_1_1_0_warnDoPut assign CAN_FIRE_RL_sinks_1_1_0_warnDoPut = CAN_FIRE_RL_sink_selected_8 && !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sinks_1_1_0_warnDoPut = CAN_FIRE_RL_sinks_1_1_0_warnDoPut ; // rule RL_sinks_1_1_0_doPut assign CAN_FIRE_RL_sinks_1_1_0_doPut = msNoSynth_0_rNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_8 ; assign WILL_FIRE_RL_sinks_1_1_0_doPut = CAN_FIRE_RL_sinks_1_1_0_doPut ; // rule RL_ifcs_0_1_drainNoRouteResponse assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = ifcs_0_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_0_doPut && msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && !WILL_FIRE_RL_sinks_1_1_0_doPut ; // rule RL_ifcs_0_1_nonRoutableGenRsp assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = x__h95031 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && (x__h95031 != 9'd1 || msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) ; assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; // rule __me_check_382 assign CAN_FIRE___me_check_382 = 1'b1 ; assign WILL_FIRE___me_check_382 = 1'b1 ; // rule __me_check_383 assign CAN_FIRE___me_check_383 = 1'b1 ; assign WILL_FIRE___me_check_383 = 1'b1 ; // rule __me_check_386 assign CAN_FIRE___me_check_386 = 1'b1 ; assign WILL_FIRE___me_check_386 = 1'b1 ; // rule RL_msNoSynth_0_arNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut && (!msNoSynth_0_arNoSynth_buffer_dequeueing$whas || msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; // rule RL_msNoSynth_0_arNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = msNoSynth_0_arNoSynth_buffer_dequeueing$whas && msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; // rule RL_ifcs_0_1_snk_warnDoPut assign CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut = ifcs_0_1_snk_putWire$whas && !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut = CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut ; // rule RL_ifcs_0_1_snk_doPut assign CAN_FIRE_RL_ifcs_0_1_snk_doPut = msNoSynth_0_rNoSynth_buffer_ff$FULL_N && ifcs_0_1_snk_putWire$whas ; assign WILL_FIRE_RL_ifcs_0_1_snk_doPut = CAN_FIRE_RL_ifcs_0_1_snk_doPut ; // rule RL_msNoSynth_0_rNoSynth_src_setPeek assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_ifcs_0_1_snk_doPut) ; assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek ; // rule RL_msNoSynth_0_rNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; // rule RL_proc_uncached_rSynth_snk_warnDoPut assign CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && !proc$master1_r_canPut ; assign WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut ; // rule RL_proc_uncached_rSynth_snk_doPut assign CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut = proc$RDY_master1_r_put && CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; assign WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut = CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; // rule RL_msNoSynth_0_rNoSynth_src_doDrop assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; // rule RL_msNoSynth_0_rNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ifcs_0_1_snk_doPut && (!CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop || msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; // rule RL_msNoSynth_0_rNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop && msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; // rule RL_sinks_1_1_1_warnDoPut assign CAN_FIRE_RL_sinks_1_1_1_warnDoPut = CAN_FIRE_RL_sink_selected_9 && !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sinks_1_1_1_warnDoPut = CAN_FIRE_RL_sinks_1_1_1_warnDoPut ; // rule RL_sinks_1_1_1_doPut assign CAN_FIRE_RL_sinks_1_1_1_doPut = msNoSynth_1_rNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_9 ; assign WILL_FIRE_RL_sinks_1_1_1_doPut = CAN_FIRE_RL_sinks_1_1_1_doPut ; // rule RL_ifcs_1_1_drainNoRouteResponse assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = ifcs_1_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_1_doPut && msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && !WILL_FIRE_RL_sinks_1_1_1_doPut ; // rule RL_ifcs_1_1_snk_warnDoPut assign CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut = ifcs_1_1_snk_putWire$whas && !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut = CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut ; // rule RL_ifcs_1_1_snk_doPut assign CAN_FIRE_RL_ifcs_1_1_snk_doPut = msNoSynth_1_rNoSynth_buffer_ff$FULL_N && ifcs_1_1_snk_putWire$whas ; assign WILL_FIRE_RL_ifcs_1_1_snk_doPut = CAN_FIRE_RL_ifcs_1_1_snk_doPut ; // rule RL_msNoSynth_1_rNoSynth_src_setPeek assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_ifcs_1_1_snk_doPut) ; assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek ; // rule RL_msNoSynth_1_rNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; // rule RL_msNoSynth_1_awNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = debug_module$master_awvalid && msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; // rule RL_msNoSynth_1_awNoSynth_forwardReady assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; // rule RL_msNoSynth_1_awNoSynth_snk_warnDoPut assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit && !msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut ; // rule RL_msNoSynth_1_awNoSynth_snk_doPut assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = msNoSynth_1_awNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut ; // rule RL_msNoSynth_1_wNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = debug_module$master_wvalid && msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; // rule RL_msNoSynth_1_wNoSynth_forwardReady assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; // rule RL_msNoSynth_1_wNoSynth_snk_warnDoPut assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit && !msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut ; // rule RL_msNoSynth_1_wNoSynth_snk_doPut assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = msNoSynth_1_wNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut ; // rule RL_msNoSynth_1_arNoSynth_forwardFlit assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = debug_module$master_arvalid && msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; // rule RL_msNoSynth_1_arNoSynth_forwardReady assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; // rule RL_msNoSynth_1_arNoSynth_snk_warnDoPut assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit && !msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut ; // rule RL_msNoSynth_1_arNoSynth_snk_doPut assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = msNoSynth_1_arNoSynth_buffer_ff$FULL_N && CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut ; // rule RL_msNoSynth_1_rNoSynth_src_doDrop assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; // rule RL_msNoSynth_1_rNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = CAN_FIRE_RL_ifcs_1_1_snk_doPut && (!CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop || msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; // rule RL_msNoSynth_1_rNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop && msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; // rule RL_merged_1_awFlit assign CAN_FIRE_RL_merged_1_awFlit = msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut) && merged_1_awff$FULL_N ; assign WILL_FIRE_RL_merged_1_awFlit = CAN_FIRE_RL_merged_1_awFlit ; // rule RL_msNoSynth_1_awNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut && (!CAN_FIRE_RL_merged_1_awFlit || msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; // rule RL_msNoSynth_1_awNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = CAN_FIRE_RL_merged_1_awFlit && msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; // rule RL_merged_1_wFlit assign CAN_FIRE_RL_merged_1_wFlit = msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && (msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut) && merged_1_wff$FULL_N ; assign WILL_FIRE_RL_merged_1_wFlit = CAN_FIRE_RL_merged_1_wFlit ; // rule RL_msNoSynth_1_wNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut && (!CAN_FIRE_RL_merged_1_wFlit || msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; // rule RL_msNoSynth_1_wNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = CAN_FIRE_RL_merged_1_wFlit && msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; // rule RL_ifcs_1_1_firstFlit assign CAN_FIRE_RL_ifcs_1_1_firstFlit = msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && ifcs_1_1_innerReq$FULL_N && ifcs_1_1_innerRoute$FULL_N && ifcs_1_1_state == 2'd0 && msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 == 2'd1 ; assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; // rule RL_ifcs_1_1_followFlits assign CAN_FIRE_RL_ifcs_1_1_followFlits = msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && ifcs_1_1_innerReq$FULL_N && ifcs_1_1_state == 2'd1 && msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ifcs_1_1_followFlits = CAN_FIRE_RL_ifcs_1_1_followFlits ; // rule RL_ifcs_1_1_nonRoutableFlit assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && ifcs_1_1_noRoute_flitCount == 9'd0 && ifcs_1_1_state == 2'd0 && msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 != 2'd1 ; assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; // rule RL_ifcs_1_1_nonRoutableGenRsp assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = x__h97630 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && (x__h97630 != 9'd1 || msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) ; assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; // rule RL_ifcs_1_1_drainFlits assign CAN_FIRE_RL_ifcs_1_1_drainFlits = (msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) && ifcs_1_1_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; // rule __me_check_390 assign CAN_FIRE___me_check_390 = 1'b1 ; assign WILL_FIRE___me_check_390 = 1'b1 ; // rule __me_check_391 assign CAN_FIRE___me_check_391 = 1'b1 ; assign WILL_FIRE___me_check_391 = 1'b1 ; // rule __me_check_392 assign CAN_FIRE___me_check_392 = 1'b1 ; assign WILL_FIRE___me_check_392 = 1'b1 ; // rule __me_check_394 assign CAN_FIRE___me_check_394 = 1'b1 ; assign WILL_FIRE___me_check_394 = 1'b1 ; // rule RL_msNoSynth_1_arNoSynth_buffer_enqueue assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut && (!msNoSynth_1_arNoSynth_buffer_dequeueing$whas || msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; // rule RL_msNoSynth_1_arNoSynth_buffer_dequeue assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = msNoSynth_1_arNoSynth_buffer_dequeueing$whas && msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; // rule RL_cached_mem_master_awSynth_src_setPeek assign CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; assign WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; // rule RL_cached_mem_master_awSynth_src_warnDoDrop assign CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = cached_mem_master_awSynth_src_dropWire$whas && !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; assign WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop ; // rule RL_cached_mem_master_awSynth_src_doDrop assign CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop = cached_mem_master_awSynth_src_dropWire$whas && tagController_tmp_shimMaster_awff_rv$port1__read[99] ; assign WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop = CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop && !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; // rule RL_tagController_tmp_ug_master_u_aw_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = tagController_tmp_shimMaster_awff_rv$port1__read[99] && CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; // rule RL_cached_mem_master_wSynth_src_setPeek assign CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; assign WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; // rule RL_cached_mem_master_wSynth_src_warnDoDrop assign CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = cached_mem_master_wSynth_src_dropWire$whas && !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; assign WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop ; // rule RL_cached_mem_master_wSynth_src_doDrop assign CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop = cached_mem_master_wSynth_src_dropWire$whas && tagController_tmp_shimMaster_wff_rv$port1__read[73] ; assign WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop = CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop && !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; // rule RL_tagController_tmp_ug_master_u_w_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = tagController_tmp_shimMaster_wff_rv$port1__read[73] && CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; // rule RL_cached_mem_master_bSynth_snk_warnDoPut assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && tagController_tmp_shimMaster_bff_rv[8] ; assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut ; // rule RL_cached_mem_master_bSynth_snk_doPut assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut = cpu_imem_master_bvalid && !tagController_tmp_shimMaster_bff_rv[8] ; assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut = CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; // rule RL_tagController_tmp_ug_master_u_b_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && tagController_tmp_shimMaster_bff_rv[8] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; // rule RL_tagController_tmp_ug_master_u_b_doPut assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = !tagController_tmp_shimMaster_bff_rv[8] && CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; // rule RL_cached_mem_master_arSynth_src_setPeek assign CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; assign WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; // rule RL_cached_mem_master_arSynth_src_warnDoDrop assign CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = cached_mem_master_arSynth_src_dropWire$whas && !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; assign WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop ; // rule RL_cached_mem_master_arSynth_src_doDrop assign CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop = cached_mem_master_arSynth_src_dropWire$whas && tagController_tmp_shimMaster_arff_rv$port1__read[99] ; assign WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop = CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop && !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; // rule RL_tagController_tmp_ug_master_u_ar_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = tagController_tmp_shimMaster_arff_rv$port1__read[99] && CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; // rule RL_cached_mem_master_rSynth_snk_warnDoPut assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && tagController_tmp_shimMaster_rff_rv[73] ; assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut ; // rule RL_cached_mem_master_rSynth_snk_doPut assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut = cpu_imem_master_rvalid && !tagController_tmp_shimMaster_rff_rv[73] ; assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut = CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; // rule RL_tagController_tmp_ug_master_u_r_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && tagController_tmp_shimMaster_rff_rv[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; // rule RL_tagController_tmp_ug_master_u_r_doPut assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = !tagController_tmp_shimMaster_rff_rv[73] && CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; // rule RL_tagController_tmp_passMemoryResponseWrite assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = tagController_tmp_shimMaster_bff_rv$port1__read[8] && tagController_tmp_tagCon$RDY_memory_response_put ; assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; // rule RL_tagController_tmp_passMemoryResponseRead assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = tagController_tmp_shimMaster_rff_rv$port1__read[73] && tagController_tmp_tagCon$RDY_memory_response_put ; assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; // rule RL_tagController_tmp_propagateReset assign CAN_FIRE_RL_tagController_tmp_propagateReset = !tagController_tmp_reset_done ; assign WILL_FIRE_RL_tagController_tmp_propagateReset = CAN_FIRE_RL_tagController_tmp_propagateReset ; // inputs to muxes for submodule ports assign MUX_activeSource_0$write_1__SEL_1 = WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && !ifcs_0_innerReq$D_OUT[1] ; assign MUX_activeSource_1_1_0$write_1__SEL_1 = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && !ifcs_0_1_rspBack$D_OUT[1] ; assign MUX_activeSource_1_1_0$write_1__SEL_2 = WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && !ifcs_1_1_rspBack$D_OUT[1] ; assign MUX_activeSource_1_1_0$write_1__SEL_3 = WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && !ifcs_2_1_rspBack$D_OUT[1] ; assign MUX_flitToSink_0$wset_1__SEL_1 = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] ; assign MUX_flitToSink_0$wset_1__SEL_3 = WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerRoute$D_OUT[0] ; assign MUX_flitToSink_1$wset_1__SEL_1 = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] ; assign MUX_flitToSink_1$wset_1__SEL_3 = WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerRoute$D_OUT[1] ; assign MUX_flitToSink_1_0$wset_1__SEL_1 = WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_0$wset_1__SEL_2 = WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_0$wset_1__SEL_3 = WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_0$wset_1__SEL_4 = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && ifcs_0_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_0$wset_1__SEL_5 = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && ifcs_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_0$wset_1__SEL_6 = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && ifcs_2_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_0_1$wset_1__SEL_1 = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] ; assign MUX_flitToSink_1_0_1$wset_1__SEL_3 = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerRoute$D_OUT[0] ; assign MUX_flitToSink_1_1$wset_1__SEL_1 = WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1$wset_1__SEL_2 = WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1$wset_1__SEL_3 = WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1$wset_1__SEL_4 = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && ifcs_0_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1$wset_1__SEL_5 = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && ifcs_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1$wset_1__SEL_6 = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && ifcs_2_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1_0$wset_1__SEL_1 = WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_1_0$wset_1__SEL_2 = WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_1_0$wset_1__SEL_3 = WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_1_0$wset_1__SEL_4 = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_1_0$wset_1__SEL_5 = WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_1_0$wset_1__SEL_6 = WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_routeBack$D_OUT[0] ; assign MUX_flitToSink_1_1_1$wset_1__SEL_1 = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] ; assign MUX_flitToSink_1_1_1$wset_1__SEL_3 = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerRoute$D_OUT[1] ; assign MUX_flitToSink_1_1_1_1$wset_1__SEL_1 = WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1_1_1$wset_1__SEL_2 = WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1_1_1$wset_1__SEL_3 = WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1_1_1$wset_1__SEL_4 = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1_1_1$wset_1__SEL_5 = WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_1_1_1$wset_1__SEL_6 = WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_routeBack$D_OUT[1] ; assign MUX_flitToSink_1_2$wset_1__SEL_1 = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] ; assign MUX_flitToSink_1_2$wset_1__SEL_3 = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerRoute$D_OUT[2] ; assign MUX_flitToSink_2$wset_1__SEL_1 = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] ; assign MUX_flitToSink_2$wset_1__SEL_3 = WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerRoute$D_OUT[2] ; assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_0_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_firstFlit && IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_0_state$write_1__SEL_2 = WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_0_state$write_1__PSEL_3 = WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits ; assign MUX_ifcs_0_state$write_1__SEL_3 = MUX_ifcs_0_state$write_1__PSEL_3 && IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_1_1_followFlits_1 && ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_1_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits ; assign MUX_ifcs_1_state$write_1__SEL_1 = MUX_ifcs_1_state$write_1__PSEL_1 && IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; assign MUX_ifcs_1_state$write_1__SEL_2 = WILL_FIRE_RL_ifcs_1_firstFlit && IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_1_state$write_1__SEL_3 = WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_2_1_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_2_1_followFlits && ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_proc$start_1__SEL_1 = WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 ; assign MUX_split_0_flitLeft$write_1__SEL_1 = WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] ; assign MUX_split_0_flitLeft$write_1__SEL_2 = WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[172] ; assign MUX_split_1_flitLeft$write_1__SEL_1 = WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] ; assign MUX_split_1_flitLeft$write_1__SEL_2 = WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[172] ; assign MUX_split_2_flitLeft$write_1__SEL_1 = WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] ; assign MUX_split_2_flitLeft$write_1__SEL_2 = WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[172] ; assign MUX_state$write_1__SEL_1 = WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] ; assign MUX_state$write_1__SEL_2 = WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] ; assign MUX_state_1_1_1$write_1__SEL_1 = WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] ; assign MUX_state_1_1_1$write_1__SEL_2 = WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] ; assign MUX_state_1_1_1$write_1__SEL_3 = WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] ; assign MUX_activeSource_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign MUX_activeSource_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign MUX_activeSource_1_1_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign MUX_activeSource_1_1_1_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign MUX_activeSource_1_1_2$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; always@(MUX_flitToSink_1_1_0$wset_1__SEL_1 or MUX_flitToSink_1_1_0$wset_1__SEL_4 or ifcs_0_1_rspBack$D_OUT or MUX_flitToSink_1_1_0$wset_1__SEL_2 or MUX_flitToSink_1_1_0$wset_1__SEL_5 or ifcs_1_1_rspBack$D_OUT or MUX_flitToSink_1_1_0$wset_1__SEL_3 or MUX_flitToSink_1_1_0$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) begin case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_0$wset_1__SEL_1 || MUX_flitToSink_1_1_0$wset_1__SEL_4: MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_2 || MUX_flitToSink_1_1_0$wset_1__SEL_5: MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_3 || MUX_flitToSink_1_1_0$wset_1__SEL_6: MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; default: MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = 72'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ; endcase end always@(MUX_flitToSink_1_0$wset_1__SEL_1 or MUX_flitToSink_1_0$wset_1__SEL_4 or ifcs_0_rspBack$D_OUT or MUX_flitToSink_1_0$wset_1__SEL_2 or MUX_flitToSink_1_0$wset_1__SEL_5 or ifcs_1_rspBack$D_OUT or MUX_flitToSink_1_0$wset_1__SEL_3 or MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) begin case (1'b1) // synopsys parallel_case MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; default: MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = 6'bxxxxxx /* unspecified value */ ; endcase end always@(MUX_flitToSink_1_1_1_1$wset_1__SEL_1 or MUX_flitToSink_1_1_1_1$wset_1__SEL_4 or ifcs_0_1_rspBack$D_OUT or MUX_flitToSink_1_1_1_1$wset_1__SEL_2 or MUX_flitToSink_1_1_1_1$wset_1__SEL_5 or ifcs_1_1_rspBack$D_OUT or MUX_flitToSink_1_1_1_1$wset_1__SEL_3 or MUX_flitToSink_1_1_1_1$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) begin case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1_1$wset_1__SEL_4: MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1_1_1$wset_1__SEL_5: MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1_1_1$wset_1__SEL_6: MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; default: MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = 72'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ; endcase end always@(MUX_flitToSink_1_1$wset_1__SEL_1 or MUX_flitToSink_1_1$wset_1__SEL_4 or ifcs_0_rspBack$D_OUT or MUX_flitToSink_1_1$wset_1__SEL_2 or MUX_flitToSink_1_1$wset_1__SEL_5 or ifcs_1_rspBack$D_OUT or MUX_flitToSink_1_1$wset_1__SEL_3 or MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) begin case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; default: MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = 6'bxxxxxx /* unspecified value */ ; endcase end assign MUX_merged_0_flitLeft$write_1__VAL_2 = merged_0_flitLeft - 8'd1 ; assign MUX_merged_1_flitLeft$write_1__VAL_2 = merged_1_flitLeft - 8'd1 ; assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = rg_hart0_reset_delay - 8'd1 ; assign MUX_split_0_flitLeft$write_1__VAL_1 = split_0_flitLeft - 8'd1 ; assign MUX_split_1_flitLeft$write_1__VAL_1 = split_1_flitLeft - 8'd1 ; assign MUX_split_2_flitLeft$write_1__VAL_1 = split_2_flitLeft - 8'd1 ; assign MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1 = { tmp__h8177[39:3], 4'd0, tagController_tmp_awreqff$D_OUT[97:93], 3'd1, tagController_tmp_shimSlave_wff_rv$port1__read[1], tagController_tmp_awreqff$D_OUT[14:11] < 4'd4, 1'd0, tagController_tmp_shimSlave_wff_rv$port1__read[9:2], 8'd255, tagController_tmp_shimSlave_wff_rv$port1__read[0], tagController_tmp_shimSlave_wff_rv$port1__read[73:10], tagController_tmp_awreqff$D_OUT[28:21] } ; assign MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2 = { tagController_tmp_shimSlave_arff_rv$port1__read[68:29], 1'b0, tagController_tmp_shimSlave_arff_rv$port1__read[97:93], 3'd0, 83'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ , tagController_tmp_shimSlave_arff_rv$port1__read[14:11] < 4'd4, 2'd0, tagController_tmp_shimSlave_arff_rv$port1__read[23:18] } ; assign MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1 = { tagController_tmp_shimMaster_bff_rv$port1__read[7:2], 4'd1, 2'bxx /* unspecified value */ , 65'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ; assign MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2 = { tagController_tmp_shimMaster_rff_rv$port1__read[72:67], 4'd0, tagController_tmp_shimMaster_rff_rv$port1__read[0], 1'd0, tagController_tmp_shimMaster_rff_rv$port1__read[67:3] } ; // inlined wires assign proc_uncached_wSynth_src_peekWire$wget = { proc$master1_w_peek[73:1], 1'd0 } ; assign proc_uncached_bSynth_snk_putWire$wget = msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_bNoSynth_buffer_ff$D_OUT : msNoSynth_0_bNoSynth_buffer_enqw$wget ; assign proc_uncached_rSynth_snk_putWire$wget = msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_rNoSynth_buffer_ff$D_OUT : msNoSynth_0_rNoSynth_buffer_enqw$wget ; assign uncached_mem_master_awSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_awff$D_OUT } ; assign uncached_mem_master_bSynth_snk_putWire$wget = { cpu_dmem_master_bid, cpu_dmem_master_bresp } ; assign uncached_mem_master_bSynth_snk_putWire$whas = cpu_dmem_master_bvalid && uncached_mem_shim_bff$FULL_N ; assign uncached_mem_master_arSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_arff$D_OUT } ; assign uncached_mem_master_rSynth_snk_putWire$wget = { cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast } ; assign uncached_mem_master_rSynth_snk_putWire$whas = cpu_dmem_master_rvalid && uncached_mem_shim_rff$FULL_N ; assign tagController_tmp_ug_slave_u_aw_putWire$wget = tmp2_awNoSynth_buffer_ff$EMPTY_N ? tmp2_awNoSynth_buffer_ff$D_OUT : tmp2_awNoSynth_buffer_enqw$wget ; assign tagController_tmp_ug_slave_u_w_putWire$wget = tmp2_wNoSynth_buffer_ff$EMPTY_N ? tmp2_wNoSynth_buffer_ff$D_OUT : tmp2_wNoSynth_buffer_enqw$wget ; assign tagController_tmp_ug_slave_u_ar_putWire$wget = tmp2_arNoSynth_buffer_ff$EMPTY_N ? tmp2_arNoSynth_buffer_ff$D_OUT : tmp2_arNoSynth_buffer_enqw$wget ; assign tagController_tmp_ug_master_u_b_putWire$wget = { cpu_imem_master_bid, cpu_imem_master_bresp } ; assign tagController_tmp_ug_master_u_r_putWire$wget = { cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast } ; assign tmp2_awNoSynth_buffer_enqw$wget = { proc$master0_awid, proc$master0_awaddr, proc$master0_awlen, proc$master0_awsize, proc$master0_awburst, proc$master0_awlock, proc$master0_awcache, proc$master0_awprot, proc$master0_awqos, proc$master0_awregion } ; assign tmp2_wNoSynth_buffer_enqw$wget = { proc$master0_wdata, proc$master0_wstrb, proc$master0_wlast, proc$master0_wuser } ; assign tmp2_bNoSynth_src_peekWire$wget = tmp2_bNoSynth_buffer_ff$EMPTY_N ? tmp2_bNoSynth_buffer_ff$D_OUT : tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; assign tmp2_arNoSynth_buffer_enqw$wget = { proc$master0_arid, proc$master0_araddr, proc$master0_arlen, proc$master0_arsize, proc$master0_arburst, proc$master0_arlock, proc$master0_arcache, proc$master0_arprot, proc$master0_arqos, proc$master0_arregion } ; assign tmp2_rNoSynth_src_peekWire$wget = tmp2_rNoSynth_buffer_ff$EMPTY_N ? tmp2_rNoSynth_buffer_ff$D_OUT : tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; assign slave_vector_0_awSynth_snk_putWire$wget = ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_0_awNoSynth_buffer_ff$D_OUT : split_0_doPut$wget[171:74] ; assign slave_vector_0_wSynth_snk_putWire$wget = ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_0_wNoSynth_buffer_ff$D_OUT : split_0_doPut$wget[73:0] ; assign slave_vector_0_arSynth_snk_putWire$wget = ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_0_arNoSynth_buffer_ff$D_OUT : ssNoSynth_0_arNoSynth_buffer_enqw$wget ; assign msNoSynth_0_bNoSynth_buffer_enqw$wget = WILL_FIRE_RL_sinks_1_0_doPut ? MUX_ifcs_0_snk_putWire$wset_1__VAL_1 : ifcs_0_noRouteRsp$D_OUT ; assign msNoSynth_0_rNoSynth_buffer_enqw$wget = WILL_FIRE_RL_sinks_1_1_0_doPut ? MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 : ifcs_0_1_noRouteRsp$D_OUT ; assign msNoSynth_1_awNoSynth_buffer_enqw$wget = { debug_module$master_awid, debug_module$master_awaddr, debug_module$master_awlen, debug_module$master_awsize, debug_module$master_awburst, debug_module$master_awlock, debug_module$master_awcache, debug_module$master_awprot, debug_module$master_awqos, debug_module$master_awregion } ; assign msNoSynth_1_wNoSynth_buffer_enqw$wget = { debug_module$master_wdata, debug_module$master_wstrb, debug_module$master_wlast, debug_module$master_wuser } ; assign msNoSynth_1_bNoSynth_buffer_enqw$wget = WILL_FIRE_RL_sinks_1_1_doPut ? MUX_ifcs_1_snk_putWire$wset_1__VAL_1 : ifcs_1_noRouteRsp$D_OUT ; assign msNoSynth_1_bNoSynth_src_peekWire$wget = msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_bNoSynth_buffer_ff$D_OUT : msNoSynth_1_bNoSynth_buffer_enqw$wget ; assign msNoSynth_1_arNoSynth_buffer_enqw$wget = { debug_module$master_arid, debug_module$master_araddr, debug_module$master_arlen, debug_module$master_arsize, debug_module$master_arburst, debug_module$master_arlock, debug_module$master_arcache, debug_module$master_arprot, debug_module$master_arqos, debug_module$master_arregion } ; assign msNoSynth_1_rNoSynth_buffer_enqw$wget = WILL_FIRE_RL_sinks_1_1_1_doPut ? MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 : ifcs_1_1_noRouteRsp$D_OUT ; assign msNoSynth_1_rNoSynth_src_peekWire$wget = msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_rNoSynth_buffer_ff$D_OUT : msNoSynth_1_rNoSynth_buffer_enqw$wget ; assign ssNoSynth_0_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] || WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[172] ; assign ssNoSynth_0_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_0_1$wset_1__SEL_1 || MUX_flitToSink_1_0_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; assign ssNoSynth_1_awNoSynth_src_peekWire$wget = ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_1_awNoSynth_buffer_ff$D_OUT : split_1_doPut$wget[171:74] ; assign ssNoSynth_1_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] || WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[172] ; assign ssNoSynth_1_wNoSynth_src_peekWire$wget = ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_1_wNoSynth_buffer_ff$D_OUT : split_1_doPut$wget[73:0] ; assign ssNoSynth_1_bNoSynth_buffer_enqw$wget = { plic$axi4_slave_bid, plic$axi4_slave_bresp } ; assign ssNoSynth_1_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; assign ssNoSynth_1_arNoSynth_src_peekWire$wget = ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_1_arNoSynth_buffer_ff$D_OUT : ssNoSynth_1_arNoSynth_buffer_enqw$wget ; assign ssNoSynth_1_rNoSynth_buffer_enqw$wget = { plic$axi4_slave_rid, plic$axi4_slave_rdata, plic$axi4_slave_rresp, plic$axi4_slave_rlast, plic$axi4_slave_ruser } ; assign ssNoSynth_2_awNoSynth_src_peekWire$wget = ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_2_awNoSynth_buffer_ff$D_OUT : split_2_doPut$wget[171:74] ; assign ssNoSynth_2_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] || WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[172] ; assign ssNoSynth_2_wNoSynth_src_peekWire$wget = ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_2_wNoSynth_buffer_ff$D_OUT : split_2_doPut$wget[73:0] ; assign ssNoSynth_2_bNoSynth_buffer_enqw$wget = { proc$debug_module_mem_server_bid, proc$debug_module_mem_server_bresp } ; assign ssNoSynth_2_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_2$wset_1__SEL_1 || MUX_flitToSink_1_2$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; assign ssNoSynth_2_arNoSynth_src_peekWire$wget = ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_2_arNoSynth_buffer_ff$D_OUT : ssNoSynth_2_arNoSynth_buffer_enqw$wget ; assign ssNoSynth_2_rNoSynth_buffer_enqw$wget = { proc$debug_module_mem_server_rid, proc$debug_module_mem_server_rdata, proc$debug_module_mem_server_rresp, proc$debug_module_mem_server_rlast, proc$debug_module_mem_server_ruser } ; assign merged_0_outflit$wget = { 1'd0, merged_0_awff$D_OUT, merged_0_wff$D_OUT } ; assign merged_1_outflit$wget = { 1'd0, merged_1_awff$D_OUT, merged_1_wff$D_OUT } ; assign split_0_doPut$wget = (MUX_flitToSink_0$wset_1__SEL_1 || MUX_flitToSink_0$wset_1__SEL_3) ? ifcs_0_innerReq$D_OUT : ifcs_1_innerReq$D_OUT ; assign split_1_doPut$wget = (MUX_flitToSink_1$wset_1__SEL_1 || MUX_flitToSink_1$wset_1__SEL_3) ? ifcs_0_innerReq$D_OUT : ifcs_1_innerReq$D_OUT ; assign split_2_doPut$wget = (MUX_flitToSink_2$wset_1__SEL_1 || MUX_flitToSink_2$wset_1__SEL_3) ? ifcs_0_innerReq$D_OUT : ifcs_1_innerReq$D_OUT ; assign ifcs_0_snk_putWire$whas = WILL_FIRE_RL_sinks_1_0_doPut || WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; assign ifcs_1_snk_putWire$whas = WILL_FIRE_RL_sinks_1_1_doPut || WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign reqWires_0$wget = (!ifcs_0_innerRoute$D_OUT[0] || !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0] ; assign reqWires_1$wget = (!ifcs_1_innerRoute$D_OUT[0] || !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0] ; assign flitToSink_0$whas = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] || WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[0] || WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerRoute$D_OUT[0] || WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerRoute$D_OUT[0] ; assign flitToSink_1$whas = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] || WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[1] || WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerRoute$D_OUT[1] || WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerRoute$D_OUT[1] ; assign flitToSink_2$whas = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] || WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[2] || WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerRoute$D_OUT[2] || WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerRoute$D_OUT[2] ; assign reqWires_1_0$wget = (!ifcs_0_routeBack$D_OUT[0] || !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_0_routeBack$D_OUT[1] && msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_0_routeBack$D_OUT[0] ; assign reqWires_1_1$wget = (!ifcs_1_routeBack$D_OUT[0] || !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_1_routeBack$D_OUT[1] && msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_1_routeBack$D_OUT[0] ; assign reqWires_1_2$wget = (!ifcs_2_routeBack$D_OUT[0] || !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_2_routeBack$D_OUT[1] && msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_2_routeBack$D_OUT[0] ; assign flitToSink_1_0$whas = WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] || WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] || WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] || WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && ifcs_0_routeBack$D_OUT[0] || WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && ifcs_1_routeBack$D_OUT[0] || WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && ifcs_2_routeBack$D_OUT[0] ; assign flitToSink_1_1$whas = WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] || WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] || WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && ifcs_0_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && ifcs_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && ifcs_2_routeBack$D_OUT[1] ; assign ifcs_0_1_snk_putWire$whas = WILL_FIRE_RL_sinks_1_1_0_doPut || WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; assign ifcs_1_1_snk_putWire$whas = WILL_FIRE_RL_sinks_1_1_1_doPut || WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign reqWires_1_0_1$wget = (!ifcs_0_1_innerRoute$D_OUT[0] || !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : ifcs_0_1_innerRoute$D_OUT[0] ; assign reqWires_1_1_1$wget = (!ifcs_1_1_innerRoute$D_OUT[0] || !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : ifcs_1_1_innerRoute$D_OUT[0] ; assign flitToSink_1_0_1$whas = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] || WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[0] || WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerRoute$D_OUT[0] || WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && ifcs_1_1_innerRoute$D_OUT[0] ; assign flitToSink_1_1_1$whas = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] || WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[1] || WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerRoute$D_OUT[1] || WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && ifcs_1_1_innerRoute$D_OUT[1] ; assign flitToSink_1_2$whas = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] || WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[2] || WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerRoute$D_OUT[2] || WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && ifcs_1_1_innerRoute$D_OUT[2] ; assign reqWires_1_1_0$wget = (!ifcs_0_1_routeBack$D_OUT[0] || !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0] ; assign reqWires_1_1_1_1$wget = (!ifcs_1_1_routeBack$D_OUT[0] || !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0] ; assign reqWires_1_1_2$wget = (!ifcs_2_1_routeBack$D_OUT[0] || !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0] ; assign flitToSink_1_1_0$whas = WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] || WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] || WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] || WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_routeBack$D_OUT[0] || WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_routeBack$D_OUT[0] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_routeBack$D_OUT[0] ; assign flitToSink_1_1_1_1$whas = WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] || WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] || WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_routeBack$D_OUT[1] ; assign uncached_mem_master_awSynth_src_dropWire$whas = uncached_mem_shim_awff$EMPTY_N && cpu_dmem_master_awready ; assign uncached_mem_master_wSynth_src_dropWire$whas = uncached_mem_shim_wff$EMPTY_N && cpu_dmem_master_wready ; assign uncached_mem_master_arSynth_src_dropWire$whas = uncached_mem_shim_arff$EMPTY_N && cpu_dmem_master_arready ; assign msNoSynth_0_arNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && x__h95031 == 9'd1 || WILL_FIRE_RL_ifcs_0_1_drainFlits || WILL_FIRE_RL_ifcs_0_1_followFlits || WILL_FIRE_RL_ifcs_0_1_firstFlit ; assign msNoSynth_1_arNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && x__h97630 == 9'd1 || WILL_FIRE_RL_ifcs_1_1_drainFlits || WILL_FIRE_RL_ifcs_1_1_followFlits || WILL_FIRE_RL_ifcs_1_1_firstFlit ; assign ssNoSynth_0_bNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_0_followFlits_1 || WILL_FIRE_RL_ifcs_0_firstFlit_1 ; assign ssNoSynth_0_rNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_0_1_followFlits_1 || WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; assign ssNoSynth_1_bNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_1_followFlits_1 || WILL_FIRE_RL_ifcs_1_firstFlit_1 ; assign ssNoSynth_1_rNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_1_1_followFlits_1 || WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; assign ssNoSynth_2_bNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_2_followFlits || WILL_FIRE_RL_ifcs_2_firstFlit ; assign ssNoSynth_2_rNoSynth_buffer_dequeueing$whas = WILL_FIRE_RL_ifcs_2_1_followFlits || WILL_FIRE_RL_ifcs_2_1_firstFlit ; assign merged_0_doDrop$whas = WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp || WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits || WILL_FIRE_RL_ifcs_0_firstFlit ; assign merged_1_doDrop$whas = WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp || WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits || WILL_FIRE_RL_ifcs_1_firstFlit ; assign sourceSelect_1_0$whas = WILL_FIRE_RL_arbitrate_1 && IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign sourceSelect_1_1$whas = WILL_FIRE_RL_arbitrate_1 && IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign sourceSelect_1_2$whas = WILL_FIRE_RL_arbitrate_1 && IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign sourceSelect_1_0_1$whas = WILL_FIRE_RL_arbitrate_2 && IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign sourceSelect_1_1_1$whas = WILL_FIRE_RL_arbitrate_2 && IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; assign cached_mem_master_awSynth_src_dropWire$whas = tagController_tmp_shimMaster_awff_rv$port1__read[99] && cpu_imem_master_awready ; assign cached_mem_master_wSynth_src_dropWire$whas = tagController_tmp_shimMaster_wff_rv$port1__read[73] && cpu_imem_master_wready ; assign cached_mem_master_arSynth_src_dropWire$whas = tagController_tmp_shimMaster_arff_rv$port1__read[99] && cpu_imem_master_arready ; assign tagController_tmp_shimSlave_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_slave_u_aw_putWire$wget } ; assign tagController_tmp_shimSlave_awff_rv$port1__read = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut ? tagController_tmp_shimSlave_awff_rv$port0__write_1 : tagController_tmp_shimSlave_awff_rv ; assign tagController_tmp_shimSlave_awff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_getCacheAW ? tagController_tmp_shimSlave_arff_rv$port1__write_1 : tagController_tmp_shimSlave_awff_rv$port1__read ; assign tagController_tmp_shimSlave_awff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimSlave_arff_rv$port1__write_1 : tagController_tmp_shimSlave_awff_rv$port2__read ; assign tagController_tmp_shimSlave_wff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_slave_u_w_putWire$wget } ; assign tagController_tmp_shimSlave_wff_rv$port1__read = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut ? tagController_tmp_shimSlave_wff_rv$port0__write_1 : tagController_tmp_shimSlave_wff_rv ; assign tagController_tmp_shimSlave_wff_rv$port1__write_1 = { 1'd0, 74'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ; assign tagController_tmp_shimSlave_wff_rv$port2__read = WILL_FIRE_RL_tagController_tmp_passCacheWrite ? tagController_tmp_shimSlave_wff_rv$port1__write_1 : tagController_tmp_shimSlave_wff_rv$port1__read ; assign tagController_tmp_shimSlave_wff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimSlave_wff_rv$port1__write_1 : tagController_tmp_shimSlave_wff_rv$port2__read ; assign tagController_tmp_shimSlave_bff_rv$EN_port0__write = WILL_FIRE_RL_tagController_tmp_passCacheResponse && tagController_tmp_tagCon$cache_response_get[68:67] != 2'd0 ; assign tagController_tmp_shimSlave_bff_rv$port0__write_1 = { 1'd1, (tagController_tmp_tagCon$cache_response_get[68:67] == 2'd1) ? tagController_tmp_tagCon$cache_response_get[75:71] : 5'd0, 2'd0 } ; assign tagController_tmp_shimSlave_bff_rv$port1__read = tagController_tmp_shimSlave_bff_rv$EN_port0__write ? tagController_tmp_shimSlave_bff_rv$port0__write_1 : tagController_tmp_shimSlave_bff_rv ; assign tagController_tmp_shimSlave_bff_rv$port1__write_1 = { 1'd0, 7'bxxxxxxx /* unspecified value */ } ; assign tagController_tmp_shimSlave_bff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop ? tagController_tmp_shimSlave_bff_rv$port1__write_1 : tagController_tmp_shimSlave_bff_rv$port1__read ; assign tagController_tmp_shimSlave_bff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimSlave_bff_rv$port1__write_1 : tagController_tmp_shimSlave_bff_rv$port2__read ; assign tagController_tmp_shimSlave_arff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_slave_u_ar_putWire$wget } ; assign tagController_tmp_shimSlave_arff_rv$port1__read = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut ? tagController_tmp_shimSlave_arff_rv$port0__write_1 : tagController_tmp_shimSlave_arff_rv ; assign tagController_tmp_shimSlave_arff_rv$port1__write_1 = { 1'd0, 98'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ; assign tagController_tmp_shimSlave_arff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_passCacheRead ? tagController_tmp_shimSlave_arff_rv$port1__write_1 : tagController_tmp_shimSlave_arff_rv$port1__read ; assign tagController_tmp_shimSlave_arff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimSlave_arff_rv$port1__write_1 : tagController_tmp_shimSlave_arff_rv$port2__read ; assign tagController_tmp_shimSlave_rff_rv$EN_port0__write = WILL_FIRE_RL_tagController_tmp_passCacheResponse && tagController_tmp_tagCon$cache_response_get[68:67] == 2'd0 ; assign tagController_tmp_shimSlave_rff_rv$port0__write_1 = { 1'd1, tagController_tmp_tagCon$cache_response_get[75:71], tagController_tmp_tagCon$cache_response_get[63:0], 2'd0, tagController_tmp_tagCon$cache_response_get[66], tagController_tmp_tagCon$cache_response_get[64] } ; assign tagController_tmp_shimSlave_rff_rv$port1__read = tagController_tmp_shimSlave_rff_rv$EN_port0__write ? tagController_tmp_shimSlave_rff_rv$port0__write_1 : tagController_tmp_shimSlave_rff_rv ; assign tagController_tmp_shimSlave_rff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop ? tagController_tmp_shimMaster_rff_rv$port1__write_1 : tagController_tmp_shimSlave_rff_rv$port1__read ; assign tagController_tmp_shimSlave_rff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimMaster_rff_rv$port1__write_1 : tagController_tmp_shimSlave_rff_rv$port2__read ; assign tagController_tmp_shimMaster_awff_rv$EN_port0__write = WILL_FIRE_RL_tagController_tmp_passMemoryRequest && tagController_tmp_tagCon$memory_request_get[93:92] == 2'd1 && !tagController_tmp_doneSendingAW ; assign tagController_tmp_shimMaster_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_tagCon$memory_request_get[100:95], aw_awaddr__h10619, tagController_tmp_tagCon$memory_request_get[7:0], aw_awsize_val__h12358, 3'd2, x__h14024, 11'd0 } ; assign tagController_tmp_shimMaster_awff_rv$port1__read = tagController_tmp_shimMaster_awff_rv$EN_port0__write ? tagController_tmp_shimMaster_awff_rv$port0__write_1 : tagController_tmp_shimMaster_awff_rv ; assign tagController_tmp_shimMaster_awff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ? tagController_tmp_shimMaster_arff_rv$port1__write_1 : tagController_tmp_shimMaster_awff_rv$port1__read ; assign tagController_tmp_shimMaster_awff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimMaster_arff_rv$port1__write_1 : tagController_tmp_shimMaster_awff_rv$port2__read ; assign tagController_tmp_shimMaster_wff_rv$EN_port0__write = WILL_FIRE_RL_tagController_tmp_passMemoryRequest && tagController_tmp_tagCon$memory_request_get[93:92] == 2'd1 ; assign tagController_tmp_shimMaster_wff_rv$port0__write_1 = { 1'd1, tagController_tmp_tagCon$memory_request_get[71:8], tagController_tmp_tagCon$memory_request_get[88:81], tagController_tmp_tagCon$memory_request_get[91] } ; assign tagController_tmp_shimMaster_wff_rv$port1__read = tagController_tmp_shimMaster_wff_rv$EN_port0__write ? tagController_tmp_shimMaster_wff_rv$port0__write_1 : tagController_tmp_shimMaster_wff_rv ; assign tagController_tmp_shimMaster_wff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ? tagController_tmp_shimMaster_rff_rv$port1__write_1 : tagController_tmp_shimMaster_wff_rv$port1__read ; assign tagController_tmp_shimMaster_wff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimMaster_rff_rv$port1__write_1 : tagController_tmp_shimMaster_wff_rv$port2__read ; assign tagController_tmp_shimMaster_bff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_master_u_b_putWire$wget } ; assign tagController_tmp_shimMaster_bff_rv$port1__read = CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ? tagController_tmp_shimMaster_bff_rv$port0__write_1 : tagController_tmp_shimMaster_bff_rv ; assign tagController_tmp_shimMaster_bff_rv$port1__write_1 = { 1'd0, 8'bxxxxxxxx /* unspecified value */ } ; assign tagController_tmp_shimMaster_bff_rv$port2__read = WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite ? tagController_tmp_shimMaster_bff_rv$port1__write_1 : tagController_tmp_shimMaster_bff_rv$port1__read ; assign tagController_tmp_shimMaster_bff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimMaster_bff_rv$port1__write_1 : tagController_tmp_shimMaster_bff_rv$port2__read ; assign tagController_tmp_shimMaster_arff_rv$EN_port0__write = WILL_FIRE_RL_tagController_tmp_passMemoryRequest && tagController_tmp_tagCon$memory_request_get[93:92] != 2'd1 ; assign tagController_tmp_shimMaster_arff_rv$port0__write_1 = { 1'd1, v_arid__h15367, v_araddr__h15368, v_arlen__h15369, v_arsize_val__h15414, 3'd2, x__h15432, 11'd0 } ; assign tagController_tmp_shimMaster_arff_rv$port1__read = tagController_tmp_shimMaster_arff_rv$EN_port0__write ? tagController_tmp_shimMaster_arff_rv$port0__write_1 : tagController_tmp_shimMaster_arff_rv ; assign tagController_tmp_shimMaster_arff_rv$port1__write_1 = { 1'd0, 99'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ; assign tagController_tmp_shimMaster_arff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ? tagController_tmp_shimMaster_arff_rv$port1__write_1 : tagController_tmp_shimMaster_arff_rv$port1__read ; assign tagController_tmp_shimMaster_arff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimMaster_arff_rv$port1__write_1 : tagController_tmp_shimMaster_arff_rv$port2__read ; assign tagController_tmp_shimMaster_rff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_master_u_r_putWire$wget } ; assign tagController_tmp_shimMaster_rff_rv$port1__read = CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ? tagController_tmp_shimMaster_rff_rv$port0__write_1 : tagController_tmp_shimMaster_rff_rv ; assign tagController_tmp_shimMaster_rff_rv$port1__write_1 = { 1'd0, 73'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ; assign tagController_tmp_shimMaster_rff_rv$port2__read = CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ? tagController_tmp_shimMaster_rff_rv$port1__write_1 : tagController_tmp_shimMaster_rff_rv$port1__read ; assign tagController_tmp_shimMaster_rff_rv$port3__read = (!tagController_tmp_reset_done) ? tagController_tmp_shimMaster_rff_rv$port1__write_1 : tagController_tmp_shimMaster_rff_rv$port2__read ; assign ifcs_0_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && CAN_FIRE_RL_merged_0_passFlit && !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_currentReq$port1__read = ifcs_0_noRoute_inner_currentReq$EN_port0__write ? merged_0_outflit$wget[170:74] : ifcs_0_noRoute_inner_currentReq ; assign ifcs_0_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && CAN_FIRE_RL_merged_0_passFlit && !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_pendingReq$port1__read = ifcs_0_noRoute_inner_pendingReq$EN_port0__write || ifcs_0_noRoute_inner_pendingReq ; assign ifcs_0_noRoute_inner_pendingReq$port2__read = !CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp && ifcs_0_noRoute_inner_pendingReq$port1__read ; assign ifcs_1_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && CAN_FIRE_RL_merged_1_passFlit && !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_currentReq$port1__read = ifcs_1_noRoute_inner_currentReq$EN_port0__write ? merged_1_outflit$wget[170:74] : ifcs_1_noRoute_inner_currentReq ; assign ifcs_1_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && CAN_FIRE_RL_merged_1_passFlit && !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_pendingReq$port1__read = ifcs_1_noRoute_inner_pendingReq$EN_port0__write || ifcs_1_noRoute_inner_pendingReq ; assign ifcs_1_noRoute_inner_pendingReq$port2__read = !CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp && ifcs_1_noRoute_inner_pendingReq$port1__read ; assign ifcs_0_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? msNoSynth_0_arNoSynth_buffer_ff$D_OUT : ifcs_0_1_noRoute_currentReq ; assign ifcs_0_1_noRoute_flitCount$port0__write_1 = { 1'd0, x__h94928 } + 9'd1 ; assign ifcs_0_1_noRoute_flitCount$port1__write_1 = x__h95031 - 9'd1 ; assign ifcs_0_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ? ifcs_0_1_noRoute_flitCount$port1__write_1 : x__h95031 ; assign ifcs_1_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? msNoSynth_1_arNoSynth_buffer_ff$D_OUT : ifcs_1_1_noRoute_currentReq ; assign ifcs_1_1_noRoute_flitCount$port0__write_1 = { 1'd0, x__h97527 } + 9'd1 ; assign ifcs_1_1_noRoute_flitCount$port1__write_1 = x__h97630 - 9'd1 ; assign ifcs_1_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ? ifcs_1_1_noRoute_flitCount$port1__write_1 : x__h97630 ; // register activeSource_0 assign activeSource_0$D_IN = MUX_activeSource_0$write_1__SEL_1 ? MUX_activeSource_0$write_1__VAL_1 : MUX_activeSource_0$write_1__VAL_1 ; assign activeSource_0$EN = WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && !ifcs_0_innerReq$D_OUT[1] || WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && !ifcs_1_innerReq$D_OUT[1] ; // register activeSource_1 assign activeSource_1$D_IN = MUX_activeSource_0$write_1__SEL_1 ? MUX_activeSource_1$write_1__VAL_1 : MUX_activeSource_1$write_1__VAL_1 ; assign activeSource_1$EN = WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && !ifcs_0_innerReq$D_OUT[1] || WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && !ifcs_1_innerReq$D_OUT[1] ; // register activeSource_1_0 assign activeSource_1_0$D_IN = 1'b0 ; assign activeSource_1_0$EN = 1'b0 ; // register activeSource_1_0_1 assign activeSource_1_0_1$D_IN = 1'b0 ; assign activeSource_1_0_1$EN = 1'b0 ; // register activeSource_1_1 assign activeSource_1_1$D_IN = 1'b0 ; assign activeSource_1_1$EN = 1'b0 ; // register activeSource_1_1_0 always@(MUX_activeSource_1_1_0$write_1__SEL_1 or MUX_activeSource_1_1_0$write_1__VAL_1 or MUX_activeSource_1_1_0$write_1__SEL_2 or MUX_activeSource_1_1_0$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_activeSource_1_1_0$write_1__SEL_1: activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; MUX_activeSource_1_1_0$write_1__SEL_2: activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; MUX_activeSource_1_1_0$write_1__SEL_3: activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; default: activeSource_1_1_0$D_IN = 1'bx /* unspecified value */ ; endcase end assign activeSource_1_1_0$EN = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && !ifcs_0_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && !ifcs_1_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && !ifcs_2_1_rspBack$D_OUT[1] ; // register activeSource_1_1_1 assign activeSource_1_1_1$D_IN = 1'b0 ; assign activeSource_1_1_1$EN = 1'b0 ; // register activeSource_1_1_1_1 always@(MUX_activeSource_1_1_0$write_1__SEL_1 or MUX_activeSource_1_1_1_1$write_1__VAL_1 or MUX_activeSource_1_1_0$write_1__SEL_2 or MUX_activeSource_1_1_0$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_activeSource_1_1_0$write_1__SEL_1: activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; MUX_activeSource_1_1_0$write_1__SEL_2: activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; MUX_activeSource_1_1_0$write_1__SEL_3: activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; default: activeSource_1_1_1_1$D_IN = 1'bx /* unspecified value */ ; endcase end assign activeSource_1_1_1_1$EN = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && !ifcs_0_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && !ifcs_1_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && !ifcs_2_1_rspBack$D_OUT[1] ; // register activeSource_1_1_2 always@(MUX_activeSource_1_1_0$write_1__SEL_1 or MUX_activeSource_1_1_2$write_1__VAL_1 or MUX_activeSource_1_1_0$write_1__SEL_2 or MUX_activeSource_1_1_0$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_activeSource_1_1_0$write_1__SEL_1: activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; MUX_activeSource_1_1_0$write_1__SEL_2: activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; MUX_activeSource_1_1_0$write_1__SEL_3: activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; default: activeSource_1_1_2$D_IN = 1'bx /* unspecified value */ ; endcase end assign activeSource_1_1_2$EN = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && !ifcs_0_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && !ifcs_1_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && !ifcs_2_1_rspBack$D_OUT[1] ; // register activeSource_1_2 assign activeSource_1_2$D_IN = 1'b0 ; assign activeSource_1_2$EN = 1'b0 ; // register arbiter_1_1_firstHot assign arbiter_1_1_firstHot$D_IN = IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; assign arbiter_1_1_firstHot$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect assign arbiter_1_1_lastSelect$D_IN = IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign arbiter_1_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect_1 assign arbiter_1_1_lastSelect_1$D_IN = IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign arbiter_1_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_firstHot assign arbiter_1_firstHot$D_IN = IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign arbiter_1_firstHot$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_firstHot_1 assign arbiter_1_firstHot_1$D_IN = IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; assign arbiter_1_firstHot_1$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_1_lastSelect assign arbiter_1_lastSelect$D_IN = IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign arbiter_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_1 assign arbiter_1_lastSelect_1$D_IN = IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign arbiter_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_2 assign arbiter_1_lastSelect_2$D_IN = IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign arbiter_1_lastSelect_2$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_firstHot assign arbiter_firstHot$D_IN = IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign arbiter_firstHot$EN = CAN_FIRE_RL_arbitrate ; // register arbiter_lastSelect assign arbiter_lastSelect$D_IN = IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign arbiter_lastSelect$EN = CAN_FIRE_RL_arbitrate ; // register ifcs_0_1_noRoute_currentReq assign ifcs_0_1_noRoute_currentReq$D_IN = ifcs_0_1_noRoute_currentReq$port1__read ; assign ifcs_0_1_noRoute_currentReq$EN = 1'b1 ; // register ifcs_0_1_noRoute_flitCount assign ifcs_0_1_noRoute_flitCount$D_IN = ifcs_0_1_noRoute_flitCount$port2__read ; assign ifcs_0_1_noRoute_flitCount$EN = 1'b1 ; // register ifcs_0_1_state assign ifcs_0_1_state$D_IN = 2'd0 ; assign ifcs_0_1_state$EN = WILL_FIRE_RL_ifcs_0_1_drainFlits || WILL_FIRE_RL_ifcs_0_1_followFlits ; // register ifcs_0_1_state_1 assign ifcs_0_1_state_1$D_IN = !MUX_ifcs_0_1_state_1$write_1__SEL_1 ; assign ifcs_0_1_state_1$EN = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && !ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_0_noRoute_inner_currentReq assign ifcs_0_noRoute_inner_currentReq$D_IN = ifcs_0_noRoute_inner_currentReq$port1__read ; assign ifcs_0_noRoute_inner_currentReq$EN = 1'b1 ; // register ifcs_0_noRoute_inner_pendingReq assign ifcs_0_noRoute_inner_pendingReq$D_IN = ifcs_0_noRoute_inner_pendingReq$port2__read ; assign ifcs_0_noRoute_inner_pendingReq$EN = 1'b1 ; // register ifcs_0_state always@(MUX_ifcs_0_state$write_1__SEL_1 or MUX_ifcs_0_state$write_1__SEL_2 or MUX_ifcs_0_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd1; MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd2; MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd0; default: ifcs_0_state$D_IN = 2'bxx /* unspecified value */ ; endcase end assign ifcs_0_state$EN = WILL_FIRE_RL_ifcs_0_firstFlit && IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || (WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits) && IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; // register ifcs_0_state_1 assign ifcs_0_state_1$D_IN = 1'd0 ; assign ifcs_0_state_1$EN = CAN_FIRE_RL_ifcs_0_followFlits_1 ; // register ifcs_1_1_noRoute_currentReq assign ifcs_1_1_noRoute_currentReq$D_IN = ifcs_1_1_noRoute_currentReq$port1__read ; assign ifcs_1_1_noRoute_currentReq$EN = 1'b1 ; // register ifcs_1_1_noRoute_flitCount assign ifcs_1_1_noRoute_flitCount$D_IN = ifcs_1_1_noRoute_flitCount$port2__read ; assign ifcs_1_1_noRoute_flitCount$EN = 1'b1 ; // register ifcs_1_1_state assign ifcs_1_1_state$D_IN = 2'd0 ; assign ifcs_1_1_state$EN = WILL_FIRE_RL_ifcs_1_1_drainFlits || WILL_FIRE_RL_ifcs_1_1_followFlits ; // register ifcs_1_1_state_1 assign ifcs_1_1_state_1$D_IN = !MUX_ifcs_1_1_state_1$write_1__SEL_1 ; assign ifcs_1_1_state_1$EN = WILL_FIRE_RL_ifcs_1_1_followFlits_1 && ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && !ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_1_noRoute_inner_currentReq assign ifcs_1_noRoute_inner_currentReq$D_IN = ifcs_1_noRoute_inner_currentReq$port1__read ; assign ifcs_1_noRoute_inner_currentReq$EN = 1'b1 ; // register ifcs_1_noRoute_inner_pendingReq assign ifcs_1_noRoute_inner_pendingReq$D_IN = ifcs_1_noRoute_inner_pendingReq$port2__read ; assign ifcs_1_noRoute_inner_pendingReq$EN = 1'b1 ; // register ifcs_1_state always@(MUX_ifcs_1_state$write_1__SEL_1 or MUX_ifcs_1_state$write_1__SEL_2 or MUX_ifcs_1_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd0; MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd1; MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd2; default: ifcs_1_state$D_IN = 2'bxx /* unspecified value */ ; endcase end assign ifcs_1_state$EN = (WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits) && IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 || WILL_FIRE_RL_ifcs_1_firstFlit && IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; // register ifcs_1_state_1 assign ifcs_1_state_1$D_IN = 1'd0 ; assign ifcs_1_state_1$EN = CAN_FIRE_RL_ifcs_1_followFlits_1 ; // register ifcs_2_1_state assign ifcs_2_1_state$D_IN = !MUX_ifcs_2_1_state$write_1__SEL_1 ; assign ifcs_2_1_state$EN = WILL_FIRE_RL_ifcs_2_1_followFlits && ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_2_1_firstFlit && !ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_2_state assign ifcs_2_state$D_IN = 1'd0 ; assign ifcs_2_state$EN = CAN_FIRE_RL_ifcs_2_followFlits ; // register merged_0_flitLeft assign merged_0_flitLeft$D_IN = WILL_FIRE_RL_merged_0_genFirst ? merged_0_awff$D_OUT[28:21] : MUX_merged_0_flitLeft$write_1__VAL_2 ; assign merged_0_flitLeft$EN = WILL_FIRE_RL_merged_0_genFirst || WILL_FIRE_RL_merged_0_genOther ; // register merged_1_flitLeft assign merged_1_flitLeft$D_IN = WILL_FIRE_RL_merged_1_genFirst ? merged_1_awff$D_OUT[28:21] : MUX_merged_1_flitLeft$write_1__VAL_2 ; assign merged_1_flitLeft$EN = WILL_FIRE_RL_merged_1_genFirst || WILL_FIRE_RL_merged_1_genOther ; // register rg_fromhost_addr assign rg_fromhost_addr$D_IN = start_fromhost_addr ; assign rg_fromhost_addr$EN = EN_start ; // register rg_hart0_reset_delay assign rg_hart0_reset_delay$D_IN = WILL_FIRE_RL_rl_dm_hart0_reset_wait ? MUX_rg_hart0_reset_delay$write_1__VAL_1 : 8'd210 ; assign rg_hart0_reset_delay$EN = WILL_FIRE_RL_rl_dm_hart0_reset_wait || WILL_FIRE_RL_rl_dm_hart0_reset ; // register rg_tohost_addr assign rg_tohost_addr$D_IN = start_tohost_addr ; assign rg_tohost_addr$EN = EN_start ; // register split_0_flitLeft assign split_0_flitLeft$D_IN = MUX_split_0_flitLeft$write_1__SEL_1 ? MUX_split_0_flitLeft$write_1__VAL_1 : split_0_doPut$wget[102:95] ; assign split_0_flitLeft$EN = ssNoSynth_0_wNoSynth_buffer_enqw$whas ; // register split_1_flitLeft assign split_1_flitLeft$D_IN = MUX_split_1_flitLeft$write_1__SEL_1 ? MUX_split_1_flitLeft$write_1__VAL_1 : split_1_doPut$wget[102:95] ; assign split_1_flitLeft$EN = ssNoSynth_1_wNoSynth_buffer_enqw$whas ; // register split_2_flitLeft assign split_2_flitLeft$D_IN = MUX_split_2_flitLeft$write_1__SEL_1 ? MUX_split_2_flitLeft$write_1__VAL_1 : split_2_doPut$wget[102:95] ; assign split_2_flitLeft$EN = ssNoSynth_2_wNoSynth_buffer_enqw$whas ; // register state assign state$D_IN = !MUX_state$write_1__SEL_1 && !MUX_state$write_1__SEL_2 ; assign state$EN = WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] || WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] || WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && !ifcs_0_innerReq$D_OUT[1] || WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && !ifcs_1_innerReq$D_OUT[1] ; // register state_1 assign state_1$D_IN = 1'd0 ; assign state_1$EN = WILL_FIRE_RL_burst_4 || WILL_FIRE_RL_burst_3 || WILL_FIRE_RL_burst_2 ; // register state_1_1 assign state_1_1$D_IN = 1'd0 ; assign state_1_1$EN = WILL_FIRE_RL_burst_6 || WILL_FIRE_RL_burst_5 ; // register state_1_1_1 assign state_1_1_1$D_IN = !MUX_state_1_1_1$write_1__SEL_1 && !MUX_state_1_1_1$write_1__SEL_2 && !MUX_state_1_1_1$write_1__SEL_3 ; assign state_1_1_1$EN = WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] || WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] || WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && !ifcs_0_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && !ifcs_1_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && !ifcs_2_1_rspBack$D_OUT[1] ; // register tagController_tmp_addrOffset assign tagController_tmp_addrOffset$D_IN = tagController_tmp_shimSlave_wff_rv$port1__read[1] ? 64'd0 : x__h8018 ; assign tagController_tmp_addrOffset$EN = WILL_FIRE_RL_tagController_tmp_passCacheWrite ; // register tagController_tmp_doneSendingAW assign tagController_tmp_doneSendingAW$D_IN = !tagController_tmp_tagCon$memory_request_get[91] ; assign tagController_tmp_doneSendingAW$EN = WILL_FIRE_RL_tagController_tmp_passMemoryRequest && tagController_tmp_tagCon$memory_request_get[93:92] == 2'd1 ; // register tagController_tmp_reset_done assign tagController_tmp_reset_done$D_IN = 1'd1 ; assign tagController_tmp_reset_done$EN = CAN_FIRE_RL_tagController_tmp_propagateReset ; // register tagController_tmp_shimMaster_arff_rv assign tagController_tmp_shimMaster_arff_rv$D_IN = tagController_tmp_shimMaster_arff_rv$port3__read ; assign tagController_tmp_shimMaster_arff_rv$EN = 1'b1 ; // register tagController_tmp_shimMaster_awff_rv assign tagController_tmp_shimMaster_awff_rv$D_IN = tagController_tmp_shimMaster_awff_rv$port3__read ; assign tagController_tmp_shimMaster_awff_rv$EN = 1'b1 ; // register tagController_tmp_shimMaster_bff_rv assign tagController_tmp_shimMaster_bff_rv$D_IN = tagController_tmp_shimMaster_bff_rv$port3__read ; assign tagController_tmp_shimMaster_bff_rv$EN = 1'b1 ; // register tagController_tmp_shimMaster_rff_rv assign tagController_tmp_shimMaster_rff_rv$D_IN = tagController_tmp_shimMaster_rff_rv$port3__read ; assign tagController_tmp_shimMaster_rff_rv$EN = 1'b1 ; // register tagController_tmp_shimMaster_wff_rv assign tagController_tmp_shimMaster_wff_rv$D_IN = tagController_tmp_shimMaster_wff_rv$port3__read ; assign tagController_tmp_shimMaster_wff_rv$EN = 1'b1 ; // register tagController_tmp_shimSlave_arff_rv assign tagController_tmp_shimSlave_arff_rv$D_IN = tagController_tmp_shimSlave_arff_rv$port3__read ; assign tagController_tmp_shimSlave_arff_rv$EN = 1'b1 ; // register tagController_tmp_shimSlave_awff_rv assign tagController_tmp_shimSlave_awff_rv$D_IN = tagController_tmp_shimSlave_awff_rv$port3__read ; assign tagController_tmp_shimSlave_awff_rv$EN = 1'b1 ; // register tagController_tmp_shimSlave_bff_rv assign tagController_tmp_shimSlave_bff_rv$D_IN = tagController_tmp_shimSlave_bff_rv$port3__read ; assign tagController_tmp_shimSlave_bff_rv$EN = 1'b1 ; // register tagController_tmp_shimSlave_rff_rv assign tagController_tmp_shimSlave_rff_rv$D_IN = tagController_tmp_shimSlave_rff_rv$port3__read ; assign tagController_tmp_shimSlave_rff_rv$EN = 1'b1 ; // register tagController_tmp_shimSlave_wff_rv assign tagController_tmp_shimSlave_wff_rv$D_IN = tagController_tmp_shimSlave_wff_rv$port3__read ; assign tagController_tmp_shimSlave_wff_rv$EN = 1'b1 ; // submodule debug_module assign debug_module$dmi_read_addr_dm_addr = dmi_read_addr_dm_addr ; assign debug_module$dmi_write_dm_addr = dmi_write_dm_addr ; assign debug_module$dmi_write_dm_word = dmi_write_dm_word ; assign debug_module$hart0_client_run_halt_response_put = proc$hart0_run_halt_server_response_get ; assign debug_module$hart0_csr_mem_client_response_put = proc$hart0_csr_mem_server_response_get ; assign debug_module$hart0_fpr_mem_client_response_put = 65'h0 ; assign debug_module$hart0_gpr_mem_client_response_put = proc$hart0_gpr_mem_server_response_get ; assign debug_module$hart0_reset_client_response_put = 1'd1 ; assign debug_module$master_arready = msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign debug_module$master_awready = msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; assign debug_module$master_bid = msNoSynth_1_bNoSynth_src_peekWire$wget[5:2] ; assign debug_module$master_bresp = msNoSynth_1_bNoSynth_src_peekWire$wget[1:0] ; assign debug_module$master_bvalid = msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign debug_module$master_rdata = msNoSynth_1_rNoSynth_src_peekWire$wget[67:4] ; assign debug_module$master_rid = msNoSynth_1_rNoSynth_src_peekWire$wget[71:68] ; assign debug_module$master_rlast = msNoSynth_1_rNoSynth_src_peekWire$wget[1] ; assign debug_module$master_rresp = msNoSynth_1_rNoSynth_src_peekWire$wget[3:2] ; assign debug_module$master_ruser = msNoSynth_1_rNoSynth_src_peekWire$wget[0] ; assign debug_module$master_rvalid = msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; assign debug_module$master_wready = msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; assign debug_module$ndm_reset_client_response_put = ndm_reset_client_response_put ; assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; assign debug_module$EN_dmi_read_data = EN_dmi_read_data ; assign debug_module$EN_dmi_write = EN_dmi_write ; assign debug_module$EN_hart0_reset_client_request_get = CAN_FIRE_RL_rl_dm_hart0_reset ; assign debug_module$EN_hart0_reset_client_response_put = MUX_proc$start_1__SEL_1 ; assign debug_module$EN_hart0_client_run_halt_request_get = CAN_FIRE_RL_ClientServerRequest ; assign debug_module$EN_hart0_client_run_halt_response_put = CAN_FIRE_RL_ClientServerResponse ; assign debug_module$EN_hart0_get_other_req_get = debug_module$RDY_hart0_get_other_req_get ; assign debug_module$EN_hart0_gpr_mem_client_request_get = CAN_FIRE_RL_ClientServerRequest_1 ; assign debug_module$EN_hart0_gpr_mem_client_response_put = CAN_FIRE_RL_ClientServerResponse_1 ; assign debug_module$EN_hart0_fpr_mem_client_request_get = 1'b0 ; assign debug_module$EN_hart0_fpr_mem_client_response_put = 1'b0 ; assign debug_module$EN_hart0_csr_mem_client_request_get = CAN_FIRE_RL_ClientServerRequest_2 ; assign debug_module$EN_hart0_csr_mem_client_response_put = CAN_FIRE_RL_ClientServerResponse_2 ; assign debug_module$EN_ndm_reset_client_request_get = EN_ndm_reset_client_request_get ; assign debug_module$EN_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; // submodule dm_hart0_reset_controller assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; // submodule ifcs_0_1_innerReq assign ifcs_0_1_innerReq$D_IN = { fatReq_arid__h94350, msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:0] : proc$master1_ar_peek[92:0] } ; assign ifcs_0_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_1_followFlits || WILL_FIRE_RL_ifcs_0_1_firstFlit ; assign ifcs_0_1_innerReq$DEQ = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || WILL_FIRE_RL_burst_5 ; assign ifcs_0_1_innerReq$CLR = 1'b0 ; // submodule ifcs_0_1_innerRoute assign ifcs_0_1_innerRoute$D_IN = { !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) } ; assign ifcs_0_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit ; assign ifcs_0_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || WILL_FIRE_RL_burst_5 ; assign ifcs_0_1_innerRoute$CLR = 1'b0 ; // submodule ifcs_0_1_noRouteRsp assign ifcs_0_1_noRouteRsp$D_IN = { ifcs_0_1_noRoute_currentReq$port1__read[96:93], 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ , 2'd3, x__h95031 == 9'd1, 1'bx /* unspecified value */ } ; assign ifcs_0_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; assign ifcs_0_1_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; assign ifcs_0_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_1_routeBack assign ifcs_0_1_routeBack$D_IN = 2'd1 << x__h98423[4] ; assign ifcs_0_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; assign ifcs_0_1_routeBack$DEQ = WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$D_OUT[1] ; assign ifcs_0_1_routeBack$CLR = 1'b0 ; // submodule ifcs_0_1_rspBack assign ifcs_0_1_rspBack$D_IN = { x__h98423[3:0], ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[67:0] : uncached_mem_shim_rff$D_OUT[67:0] } ; assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; assign ifcs_0_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_7 ; assign ifcs_0_1_rspBack$CLR = 1'b0 ; // submodule ifcs_0_innerReq assign ifcs_0_innerReq$D_IN = { !CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171], IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 } ; assign ifcs_0_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_followFlits || WILL_FIRE_RL_ifcs_0_firstFlit ; assign ifcs_0_innerReq$DEQ = WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N || WILL_FIRE_RL_burst ; assign ifcs_0_innerReq$CLR = 1'b0 ; // submodule ifcs_0_innerRoute assign ifcs_0_innerRoute$D_IN = { !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) } ; assign ifcs_0_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit ; assign ifcs_0_innerRoute$DEQ = WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] || WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerReq$D_OUT[1] ; assign ifcs_0_innerRoute$CLR = 1'b0 ; // submodule ifcs_0_noRouteRsp assign ifcs_0_noRouteRsp$D_IN = { ifcs_0_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_0_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; assign ifcs_0_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; assign ifcs_0_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_routeBack assign ifcs_0_routeBack$D_IN = 2'd1 << x__h62633[4] ; assign ifcs_0_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; assign ifcs_0_routeBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || WILL_FIRE_RL_burst_2 ; assign ifcs_0_routeBack$CLR = 1'b0 ; // submodule ifcs_0_rspBack assign ifcs_0_rspBack$D_IN = { x__h62633[3:0], ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[1:0] : uncached_mem_shim_bff$D_OUT[1:0] } ; assign ifcs_0_rspBack$ENQ = ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; assign ifcs_0_rspBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || WILL_FIRE_RL_burst_2 ; assign ifcs_0_rspBack$CLR = 1'b0 ; // submodule ifcs_1_1_innerReq assign ifcs_1_1_innerReq$D_IN = { fatReq_arid__h96952, msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:0] : msNoSynth_1_arNoSynth_buffer_enqw$wget[92:0] } ; assign ifcs_1_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_1_followFlits || WILL_FIRE_RL_ifcs_1_1_firstFlit ; assign ifcs_1_1_innerReq$DEQ = WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || WILL_FIRE_RL_burst_6 ; assign ifcs_1_1_innerReq$CLR = 1'b0 ; // submodule ifcs_1_1_innerRoute assign ifcs_1_1_innerRoute$D_IN = { !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) } ; assign ifcs_1_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit ; assign ifcs_1_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || WILL_FIRE_RL_burst_6 ; assign ifcs_1_1_innerRoute$CLR = 1'b0 ; // submodule ifcs_1_1_noRouteRsp assign ifcs_1_1_noRouteRsp$D_IN = { ifcs_1_1_noRoute_currentReq$port1__read[96:93], 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ , 2'd3, x__h97630 == 9'd1, 1'bx /* unspecified value */ } ; assign ifcs_1_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; assign ifcs_1_1_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign ifcs_1_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_1_routeBack assign ifcs_1_1_routeBack$D_IN = 2'd1 << x__h99378[4] ; assign ifcs_1_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; assign ifcs_1_1_routeBack$DEQ = WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$D_OUT[1] ; assign ifcs_1_1_routeBack$CLR = 1'b0 ; // submodule ifcs_1_1_rspBack assign ifcs_1_1_rspBack$D_IN = { x__h99378[3:0], ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[67:0] : ssNoSynth_1_rNoSynth_buffer_enqw$wget[67:0] } ; assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; assign ifcs_1_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_8 ; assign ifcs_1_1_rspBack$CLR = 1'b0 ; // submodule ifcs_1_innerReq assign ifcs_1_innerReq$D_IN = { !CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171], IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 } ; assign ifcs_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_followFlits || WILL_FIRE_RL_ifcs_1_firstFlit ; assign ifcs_1_innerReq$DEQ = WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N || WILL_FIRE_RL_burst_1 ; assign ifcs_1_innerReq$CLR = 1'b0 ; // submodule ifcs_1_innerRoute assign ifcs_1_innerRoute$D_IN = { !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) } ; assign ifcs_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit ; assign ifcs_1_innerRoute$DEQ = WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] || WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerReq$D_OUT[1] ; assign ifcs_1_innerRoute$CLR = 1'b0 ; // submodule ifcs_1_noRouteRsp assign ifcs_1_noRouteRsp$D_IN = { ifcs_1_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; assign ifcs_1_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign ifcs_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_routeBack assign ifcs_1_routeBack$D_IN = 2'd1 << x__h63524[4] ; assign ifcs_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; assign ifcs_1_routeBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_3 ; assign ifcs_1_routeBack$CLR = 1'b0 ; // submodule ifcs_1_rspBack assign ifcs_1_rspBack$D_IN = { x__h63524[3:0], ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[1:0] : ssNoSynth_1_bNoSynth_buffer_enqw$wget[1:0] } ; assign ifcs_1_rspBack$ENQ = ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; assign ifcs_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_3 ; assign ifcs_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_1_routeBack assign ifcs_2_1_routeBack$D_IN = 2'd1 << x__h100333[4] ; assign ifcs_2_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_1_firstFlit ; assign ifcs_2_1_routeBack$DEQ = WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$D_OUT[1] ; assign ifcs_2_1_routeBack$CLR = 1'b0 ; // submodule ifcs_2_1_rspBack assign ifcs_2_1_rspBack$D_IN = { x__h100333[3:0], ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[67:0] : ssNoSynth_2_rNoSynth_buffer_enqw$wget[67:0] } ; assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; assign ifcs_2_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_9 ; assign ifcs_2_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_routeBack assign ifcs_2_routeBack$D_IN = 2'd1 << x__h64415[4] ; assign ifcs_2_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_firstFlit ; assign ifcs_2_routeBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || WILL_FIRE_RL_burst_4 ; assign ifcs_2_routeBack$CLR = 1'b0 ; // submodule ifcs_2_rspBack assign ifcs_2_rspBack$D_IN = { x__h64415[3:0], ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[1:0] : ssNoSynth_2_bNoSynth_buffer_enqw$wget[1:0] } ; assign ifcs_2_rspBack$ENQ = ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; assign ifcs_2_rspBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || WILL_FIRE_RL_burst_4 ; assign ifcs_2_rspBack$CLR = 1'b0 ; // submodule merged_0_awff assign merged_0_awff$D_IN = msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_awNoSynth_buffer_ff$D_OUT : proc$master1_aw_peek ; assign merged_0_awff$ENQ = CAN_FIRE_RL_merged_0_awFlit ; assign merged_0_awff$DEQ = CAN_FIRE_RL_merged_0_genFirst ; assign merged_0_awff$CLR = 1'b0 ; // submodule merged_0_wff assign merged_0_wff$D_IN = msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_wNoSynth_buffer_ff$D_OUT : proc_uncached_wSynth_src_peekWire$wget ; assign merged_0_wff$ENQ = CAN_FIRE_RL_merged_0_wFlit ; assign merged_0_wff$DEQ = WILL_FIRE_RL_merged_0_genOther || WILL_FIRE_RL_merged_0_genFirst ; assign merged_0_wff$CLR = 1'b0 ; // submodule merged_1_awff assign merged_1_awff$D_IN = msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_awNoSynth_buffer_ff$D_OUT : msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign merged_1_awff$ENQ = CAN_FIRE_RL_merged_1_awFlit ; assign merged_1_awff$DEQ = CAN_FIRE_RL_merged_1_genFirst ; assign merged_1_awff$CLR = 1'b0 ; // submodule merged_1_wff assign merged_1_wff$D_IN = msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_wNoSynth_buffer_ff$D_OUT : msNoSynth_1_wNoSynth_buffer_enqw$wget ; assign merged_1_wff$ENQ = CAN_FIRE_RL_merged_1_wFlit ; assign merged_1_wff$DEQ = WILL_FIRE_RL_merged_1_genOther || WILL_FIRE_RL_merged_1_genFirst ; assign merged_1_wff$CLR = 1'b0 ; // submodule msNoSynth_0_arNoSynth_buffer_ff assign msNoSynth_0_arNoSynth_buffer_ff$D_IN = proc$master1_ar_peek ; assign msNoSynth_0_arNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; assign msNoSynth_0_arNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; assign msNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_0_arNoSynth_buffer_firstValid assign msNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_0_arNoSynth_buffer_firstValid$EN = msNoSynth_0_arNoSynth_buffer_dequeueing$whas ; // submodule msNoSynth_0_awNoSynth_buffer_ff assign msNoSynth_0_awNoSynth_buffer_ff$D_IN = proc$master1_aw_peek ; assign msNoSynth_0_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; assign msNoSynth_0_awNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; assign msNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_0_awNoSynth_buffer_firstValid assign msNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_0_awNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_merged_0_awFlit ; // submodule msNoSynth_0_bNoSynth_buffer_ff assign msNoSynth_0_bNoSynth_buffer_ff$D_IN = msNoSynth_0_bNoSynth_buffer_enqw$wget ; assign msNoSynth_0_bNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; assign msNoSynth_0_bNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; assign msNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_0_bNoSynth_buffer_firstValid assign msNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_0_bNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; // submodule msNoSynth_0_rNoSynth_buffer_ff assign msNoSynth_0_rNoSynth_buffer_ff$D_IN = msNoSynth_0_rNoSynth_buffer_enqw$wget ; assign msNoSynth_0_rNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; assign msNoSynth_0_rNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; assign msNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_0_rNoSynth_buffer_firstValid assign msNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_0_rNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; // submodule msNoSynth_0_wNoSynth_buffer_ff assign msNoSynth_0_wNoSynth_buffer_ff$D_IN = proc_uncached_wSynth_src_peekWire$wget ; assign msNoSynth_0_wNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; assign msNoSynth_0_wNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; assign msNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_0_wNoSynth_buffer_firstValid assign msNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_0_wNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_merged_0_wFlit ; // submodule msNoSynth_1_arNoSynth_buffer_ff assign msNoSynth_1_arNoSynth_buffer_ff$D_IN = msNoSynth_1_arNoSynth_buffer_enqw$wget ; assign msNoSynth_1_arNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; assign msNoSynth_1_arNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; assign msNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_1_arNoSynth_buffer_firstValid assign msNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_1_arNoSynth_buffer_firstValid$EN = msNoSynth_1_arNoSynth_buffer_dequeueing$whas ; // submodule msNoSynth_1_awNoSynth_buffer_ff assign msNoSynth_1_awNoSynth_buffer_ff$D_IN = msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign msNoSynth_1_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; assign msNoSynth_1_awNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; assign msNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_1_awNoSynth_buffer_firstValid assign msNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_1_awNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_merged_1_awFlit ; // submodule msNoSynth_1_bNoSynth_buffer_ff assign msNoSynth_1_bNoSynth_buffer_ff$D_IN = msNoSynth_1_bNoSynth_buffer_enqw$wget ; assign msNoSynth_1_bNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; assign msNoSynth_1_bNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; assign msNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_1_bNoSynth_buffer_firstValid assign msNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_1_bNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; // submodule msNoSynth_1_rNoSynth_buffer_ff assign msNoSynth_1_rNoSynth_buffer_ff$D_IN = msNoSynth_1_rNoSynth_buffer_enqw$wget ; assign msNoSynth_1_rNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; assign msNoSynth_1_rNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; assign msNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_1_rNoSynth_buffer_firstValid assign msNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_1_rNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; // submodule msNoSynth_1_wNoSynth_buffer_ff assign msNoSynth_1_wNoSynth_buffer_ff$D_IN = msNoSynth_1_wNoSynth_buffer_enqw$wget ; assign msNoSynth_1_wNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; assign msNoSynth_1_wNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; assign msNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; // submodule msNoSynth_1_wNoSynth_buffer_firstValid assign msNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign msNoSynth_1_wNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_merged_1_wFlit ; // submodule plic assign plic$axi4_slave_araddr = ssNoSynth_1_arNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_arburst = ssNoSynth_1_arNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_arcache = ssNoSynth_1_arNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_arid = ssNoSynth_1_arNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_arlen = ssNoSynth_1_arNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_arlock = ssNoSynth_1_arNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_arprot = ssNoSynth_1_arNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_arqos = ssNoSynth_1_arNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_arregion = ssNoSynth_1_arNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_arsize = ssNoSynth_1_arNoSynth_src_peekWire$wget[20:18] ; assign plic$axi4_slave_arvalid = ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign plic$axi4_slave_awaddr = ssNoSynth_1_awNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_awburst = ssNoSynth_1_awNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_awcache = ssNoSynth_1_awNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_awid = ssNoSynth_1_awNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_awlen = ssNoSynth_1_awNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_awlock = ssNoSynth_1_awNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_awprot = ssNoSynth_1_awNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_awqos = ssNoSynth_1_awNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_awregion = ssNoSynth_1_awNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_awsize = ssNoSynth_1_awNoSynth_src_peekWire$wget[20:18] ; assign plic$axi4_slave_awvalid = ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; assign plic$axi4_slave_bready = ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; assign plic$axi4_slave_rready = ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign plic$axi4_slave_wdata = ssNoSynth_1_wNoSynth_src_peekWire$wget[73:10] ; assign plic$axi4_slave_wlast = ssNoSynth_1_wNoSynth_src_peekWire$wget[1] ; assign plic$axi4_slave_wstrb = ssNoSynth_1_wNoSynth_src_peekWire$wget[9:2] ; assign plic$axi4_slave_wuser = ssNoSynth_1_wNoSynth_src_peekWire$wget[0] ; assign plic$axi4_slave_wvalid = ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_range[127:64] ; assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_range[127:64] + soc_map$m_plic_addr_range[63:0] ; assign plic$set_verbosity_verbosity = 4'h0 ; assign plic$v_sources_0_m_interrupt_req_set_not_clear = core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; assign plic$v_sources_10_m_interrupt_req_set_not_clear = core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; assign plic$v_sources_11_m_interrupt_req_set_not_clear = core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; assign plic$v_sources_12_m_interrupt_req_set_not_clear = core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; assign plic$v_sources_13_m_interrupt_req_set_not_clear = core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; assign plic$v_sources_14_m_interrupt_req_set_not_clear = core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; assign plic$v_sources_15_m_interrupt_req_set_not_clear = core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; assign plic$v_sources_1_m_interrupt_req_set_not_clear = core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; assign plic$v_sources_2_m_interrupt_req_set_not_clear = core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; assign plic$v_sources_3_m_interrupt_req_set_not_clear = core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; assign plic$v_sources_4_m_interrupt_req_set_not_clear = core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; assign plic$v_sources_5_m_interrupt_req_set_not_clear = core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; assign plic$v_sources_6_m_interrupt_req_set_not_clear = core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; assign plic$v_sources_7_m_interrupt_req_set_not_clear = core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; assign plic$v_sources_8_m_interrupt_req_set_not_clear = core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; assign plic$v_sources_9_m_interrupt_req_set_not_clear = core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; assign plic$EN_server_reset_request_put = 1'b0 ; assign plic$EN_server_reset_response_get = 1'b0 ; assign plic$EN_set_addr_map = EN_start ; // submodule proc assign proc$debug_module_mem_server_araddr = ssNoSynth_2_arNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_arburst = ssNoSynth_2_arNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_arcache = ssNoSynth_2_arNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_arid = ssNoSynth_2_arNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_arlen = ssNoSynth_2_arNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_arlock = ssNoSynth_2_arNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_arprot = ssNoSynth_2_arNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_arqos = ssNoSynth_2_arNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_arregion = ssNoSynth_2_arNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_arsize = ssNoSynth_2_arNoSynth_src_peekWire$wget[20:18] ; assign proc$debug_module_mem_server_arvalid = ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; assign proc$debug_module_mem_server_awaddr = ssNoSynth_2_awNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_awburst = ssNoSynth_2_awNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_awcache = ssNoSynth_2_awNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_awid = ssNoSynth_2_awNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_awlen = ssNoSynth_2_awNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_awlock = ssNoSynth_2_awNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_awprot = ssNoSynth_2_awNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_awqos = ssNoSynth_2_awNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_awregion = ssNoSynth_2_awNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_awsize = ssNoSynth_2_awNoSynth_src_peekWire$wget[20:18] ; assign proc$debug_module_mem_server_awvalid = ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; assign proc$debug_module_mem_server_bready = ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; assign proc$debug_module_mem_server_rready = ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; assign proc$debug_module_mem_server_wdata = ssNoSynth_2_wNoSynth_src_peekWire$wget[73:10] ; assign proc$debug_module_mem_server_wlast = ssNoSynth_2_wNoSynth_src_peekWire$wget[1] ; assign proc$debug_module_mem_server_wstrb = ssNoSynth_2_wNoSynth_src_peekWire$wget[9:2] ; assign proc$debug_module_mem_server_wuser = ssNoSynth_2_wNoSynth_src_peekWire$wget[0] ; assign proc$debug_module_mem_server_wvalid = ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; assign proc$hart0_csr_mem_server_request_put = debug_module$hart0_csr_mem_client_request_get ; assign proc$hart0_fpr_mem_server_request_put = 70'h0 ; assign proc$hart0_gpr_mem_server_request_put = debug_module$hart0_gpr_mem_client_request_get ; assign proc$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ; assign proc$hart0_run_halt_server_request_put = debug_module$hart0_client_run_halt_request_get ; assign proc$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; assign proc$master0_arready = tmp2_arNoSynth_buffer_ff$FULL_N ; assign proc$master0_awready = tmp2_awNoSynth_buffer_ff$FULL_N ; assign proc$master0_bid = tmp2_bNoSynth_src_peekWire$wget[6:2] ; assign proc$master0_bresp = tmp2_bNoSynth_src_peekWire$wget[1:0] ; assign proc$master0_bvalid = tmp2_bNoSynth_buffer_ff$EMPTY_N ; assign proc$master0_rdata = tmp2_rNoSynth_src_peekWire$wget[67:4] ; assign proc$master0_rid = tmp2_rNoSynth_src_peekWire$wget[72:68] ; assign proc$master0_rlast = tmp2_rNoSynth_src_peekWire$wget[1] ; assign proc$master0_rresp = tmp2_rNoSynth_src_peekWire$wget[3:2] ; assign proc$master0_ruser = tmp2_rNoSynth_src_peekWire$wget[0] ; assign proc$master0_rvalid = tmp2_rNoSynth_buffer_ff$EMPTY_N ; assign proc$master0_wready = tmp2_wNoSynth_buffer_ff$FULL_N ; assign proc$master1_b_put_val = proc_uncached_bSynth_snk_putWire$wget ; assign proc$master1_r_put_val = { proc_uncached_rSynth_snk_putWire$wget[71:1], 1'd0 } ; assign proc$non_maskable_interrupt_req_set_not_clear = 1'd0 ; assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; assign proc$start_fromhostAddr = MUX_proc$start_1__SEL_1 ? rg_fromhost_addr : start_fromhost_addr ; assign proc$start_running = MUX_proc$start_1__SEL_1 || start_is_running ; assign proc$start_startpc = 64'h0000000070000000 ; assign proc$start_tohostAddr = MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; assign proc$EN_start = WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 || EN_start ; assign proc$EN_master1_aw_drop = CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; assign proc$EN_master1_w_drop = CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; assign proc$EN_master1_b_put = CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; assign proc$EN_master1_ar_drop = CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; assign proc$EN_master1_r_put = CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; assign proc$EN_set_verbosity = EN_set_verbosity ; assign proc$EN_hart0_run_halt_server_request_put = CAN_FIRE_RL_ClientServerRequest ; assign proc$EN_hart0_run_halt_server_response_get = CAN_FIRE_RL_ClientServerResponse ; assign proc$EN_hart0_gpr_mem_server_request_put = CAN_FIRE_RL_ClientServerRequest_1 ; assign proc$EN_hart0_gpr_mem_server_response_get = CAN_FIRE_RL_ClientServerResponse_1 ; assign proc$EN_hart0_fpr_mem_server_request_put = 1'b0 ; assign proc$EN_hart0_fpr_mem_server_response_get = 1'b0 ; assign proc$EN_hart0_csr_mem_server_request_put = CAN_FIRE_RL_ClientServerRequest_2 ; assign proc$EN_hart0_csr_mem_server_response_get = CAN_FIRE_RL_ClientServerResponse_2 ; assign proc$EN_hart0_put_other_req_put = debug_module$RDY_hart0_get_other_req_get ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_IO_addr_imem_not_dmem = 1'b0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // submodule ssNoSynth_0_arNoSynth_buffer_ff assign ssNoSynth_0_arNoSynth_buffer_ff$D_IN = ssNoSynth_0_arNoSynth_buffer_enqw$wget ; assign ssNoSynth_0_arNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; assign ssNoSynth_0_arNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; assign ssNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_0_arNoSynth_buffer_firstValid assign ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_0_arNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; // submodule ssNoSynth_0_awNoSynth_buffer_ff assign ssNoSynth_0_awNoSynth_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; assign ssNoSynth_0_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; assign ssNoSynth_0_awNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; assign ssNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_0_awNoSynth_buffer_firstValid assign ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_0_awNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; // submodule ssNoSynth_0_bNoSynth_buffer_ff assign ssNoSynth_0_bNoSynth_buffer_ff$D_IN = uncached_mem_shim_bff$D_OUT ; assign ssNoSynth_0_bNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; assign ssNoSynth_0_bNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; assign ssNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_0_bNoSynth_buffer_firstValid assign ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_0_bNoSynth_buffer_firstValid$EN = ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; // submodule ssNoSynth_0_rNoSynth_buffer_ff assign ssNoSynth_0_rNoSynth_buffer_ff$D_IN = uncached_mem_shim_rff$D_OUT ; assign ssNoSynth_0_rNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; assign ssNoSynth_0_rNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; assign ssNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_0_rNoSynth_buffer_firstValid assign ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_0_rNoSynth_buffer_firstValid$EN = ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; // submodule ssNoSynth_0_wNoSynth_buffer_ff assign ssNoSynth_0_wNoSynth_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; assign ssNoSynth_0_wNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; assign ssNoSynth_0_wNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; assign ssNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_0_wNoSynth_buffer_firstValid assign ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_0_wNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; // submodule ssNoSynth_1_arNoSynth_buffer_ff assign ssNoSynth_1_arNoSynth_buffer_ff$D_IN = ssNoSynth_1_arNoSynth_buffer_enqw$wget ; assign ssNoSynth_1_arNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; assign ssNoSynth_1_arNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; assign ssNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_1_arNoSynth_buffer_firstValid assign ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_1_arNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; // submodule ssNoSynth_1_awNoSynth_buffer_ff assign ssNoSynth_1_awNoSynth_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; assign ssNoSynth_1_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; assign ssNoSynth_1_awNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; assign ssNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_1_awNoSynth_buffer_firstValid assign ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_1_awNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; // submodule ssNoSynth_1_bNoSynth_buffer_ff assign ssNoSynth_1_bNoSynth_buffer_ff$D_IN = ssNoSynth_1_bNoSynth_buffer_enqw$wget ; assign ssNoSynth_1_bNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; assign ssNoSynth_1_bNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; assign ssNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_1_bNoSynth_buffer_firstValid assign ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_1_bNoSynth_buffer_firstValid$EN = ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; // submodule ssNoSynth_1_rNoSynth_buffer_ff assign ssNoSynth_1_rNoSynth_buffer_ff$D_IN = ssNoSynth_1_rNoSynth_buffer_enqw$wget ; assign ssNoSynth_1_rNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; assign ssNoSynth_1_rNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; assign ssNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_1_rNoSynth_buffer_firstValid assign ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_1_rNoSynth_buffer_firstValid$EN = ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; // submodule ssNoSynth_1_wNoSynth_buffer_ff assign ssNoSynth_1_wNoSynth_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; assign ssNoSynth_1_wNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; assign ssNoSynth_1_wNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; assign ssNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_1_wNoSynth_buffer_firstValid assign ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_1_wNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; // submodule ssNoSynth_2_arNoSynth_buffer_ff assign ssNoSynth_2_arNoSynth_buffer_ff$D_IN = ssNoSynth_2_arNoSynth_buffer_enqw$wget ; assign ssNoSynth_2_arNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; assign ssNoSynth_2_arNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; assign ssNoSynth_2_arNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_2_arNoSynth_buffer_firstValid assign ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_2_arNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; // submodule ssNoSynth_2_awNoSynth_buffer_ff assign ssNoSynth_2_awNoSynth_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; assign ssNoSynth_2_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; assign ssNoSynth_2_awNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; assign ssNoSynth_2_awNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_2_awNoSynth_buffer_firstValid assign ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_2_awNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; // submodule ssNoSynth_2_bNoSynth_buffer_ff assign ssNoSynth_2_bNoSynth_buffer_ff$D_IN = ssNoSynth_2_bNoSynth_buffer_enqw$wget ; assign ssNoSynth_2_bNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; assign ssNoSynth_2_bNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; assign ssNoSynth_2_bNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_2_bNoSynth_buffer_firstValid assign ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_2_bNoSynth_buffer_firstValid$EN = ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; // submodule ssNoSynth_2_rNoSynth_buffer_ff assign ssNoSynth_2_rNoSynth_buffer_ff$D_IN = ssNoSynth_2_rNoSynth_buffer_enqw$wget ; assign ssNoSynth_2_rNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; assign ssNoSynth_2_rNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; assign ssNoSynth_2_rNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_2_rNoSynth_buffer_firstValid assign ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_2_rNoSynth_buffer_firstValid$EN = ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; // submodule ssNoSynth_2_wNoSynth_buffer_ff assign ssNoSynth_2_wNoSynth_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; assign ssNoSynth_2_wNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; assign ssNoSynth_2_wNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; assign ssNoSynth_2_wNoSynth_buffer_ff$CLR = 1'b0 ; // submodule ssNoSynth_2_wNoSynth_buffer_firstValid assign ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign ssNoSynth_2_wNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; // submodule tagController_tmp_awreqff assign tagController_tmp_awreqff$D_IN = tagController_tmp_shimSlave_awff_rv$port1__read[97:0] ; assign tagController_tmp_awreqff$ENQ = CAN_FIRE_RL_tagController_tmp_getCacheAW ; assign tagController_tmp_awreqff$DEQ = WILL_FIRE_RL_tagController_tmp_passCacheWrite && tagController_tmp_shimSlave_wff_rv$port1__read[1] ; assign tagController_tmp_awreqff$CLR = 1'b0 ; // submodule tagController_tmp_newRst assign tagController_tmp_newRst$ASSERT_IN = CAN_FIRE_RL_tagController_tmp_propagateReset ; // submodule tagController_tmp_tagCon assign tagController_tmp_tagCon$cache_request_put_val = WILL_FIRE_RL_tagController_tmp_passCacheWrite ? MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1 : MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2 ; assign tagController_tmp_tagCon$memory_response_put_val = WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite ? MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1 : MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2 ; assign tagController_tmp_tagCon$EN_cache_request_put = WILL_FIRE_RL_tagController_tmp_passCacheWrite || WILL_FIRE_RL_tagController_tmp_passCacheRead ; assign tagController_tmp_tagCon$EN_cache_response_get = CAN_FIRE_RL_tagController_tmp_passCacheResponse ; assign tagController_tmp_tagCon$EN_memory_request_get = CAN_FIRE_RL_tagController_tmp_passMemoryRequest ; assign tagController_tmp_tagCon$EN_memory_response_put = WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite || WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; // submodule tmp2_arNoSynth_buffer_ff assign tmp2_arNoSynth_buffer_ff$D_IN = tmp2_arNoSynth_buffer_enqw$wget ; assign tmp2_arNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; assign tmp2_arNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; assign tmp2_arNoSynth_buffer_ff$CLR = 1'b0 ; // submodule tmp2_arNoSynth_buffer_firstValid assign tmp2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign tmp2_arNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; // submodule tmp2_awNoSynth_buffer_ff assign tmp2_awNoSynth_buffer_ff$D_IN = tmp2_awNoSynth_buffer_enqw$wget ; assign tmp2_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; assign tmp2_awNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; assign tmp2_awNoSynth_buffer_ff$CLR = 1'b0 ; // submodule tmp2_awNoSynth_buffer_firstValid assign tmp2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign tmp2_awNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; // submodule tmp2_bNoSynth_buffer_ff assign tmp2_bNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; assign tmp2_bNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; assign tmp2_bNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; assign tmp2_bNoSynth_buffer_ff$CLR = 1'b0 ; // submodule tmp2_bNoSynth_buffer_firstValid assign tmp2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign tmp2_bNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; // submodule tmp2_rNoSynth_buffer_ff assign tmp2_rNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; assign tmp2_rNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; assign tmp2_rNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; assign tmp2_rNoSynth_buffer_ff$CLR = 1'b0 ; // submodule tmp2_rNoSynth_buffer_firstValid assign tmp2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign tmp2_rNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; // submodule tmp2_wNoSynth_buffer_ff assign tmp2_wNoSynth_buffer_ff$D_IN = tmp2_wNoSynth_buffer_enqw$wget ; assign tmp2_wNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; assign tmp2_wNoSynth_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; assign tmp2_wNoSynth_buffer_ff$CLR = 1'b0 ; // submodule tmp2_wNoSynth_buffer_firstValid assign tmp2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; assign tmp2_wNoSynth_buffer_firstValid$EN = CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; // submodule uncached_mem_shim_arff assign uncached_mem_shim_arff$D_IN = slave_vector_0_arSynth_snk_putWire$wget ; assign uncached_mem_shim_arff$ENQ = CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; assign uncached_mem_shim_arff$DEQ = CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; assign uncached_mem_shim_arff$CLR = 1'b0 ; // submodule uncached_mem_shim_awff assign uncached_mem_shim_awff$D_IN = slave_vector_0_awSynth_snk_putWire$wget ; assign uncached_mem_shim_awff$ENQ = CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; assign uncached_mem_shim_awff$DEQ = CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; assign uncached_mem_shim_awff$CLR = 1'b0 ; // submodule uncached_mem_shim_bff assign uncached_mem_shim_bff$D_IN = uncached_mem_master_bSynth_snk_putWire$wget[6:0] ; assign uncached_mem_shim_bff$ENQ = CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; assign uncached_mem_shim_bff$DEQ = CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; assign uncached_mem_shim_bff$CLR = 1'b0 ; // submodule uncached_mem_shim_rff assign uncached_mem_shim_rff$D_IN = { uncached_mem_master_rSynth_snk_putWire$wget[71:0], 1'd0 } ; assign uncached_mem_shim_rff$ENQ = CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; assign uncached_mem_shim_rff$DEQ = CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; assign uncached_mem_shim_rff$CLR = 1'b0 ; // submodule uncached_mem_shim_wff assign uncached_mem_shim_wff$D_IN = slave_vector_0_wSynth_snk_putWire$wget ; assign uncached_mem_shim_wff$ENQ = CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; assign uncached_mem_shim_wff$DEQ = CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; assign uncached_mem_shim_wff$CLR = 1'b0 ; // remaining internal signals assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 = ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527)) ? 2'd1 : 2'd0 ; assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 = ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) ? 2'd1 : 2'd0 ; assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 = IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 + ((!IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) ? 2'd1 : 2'd0) ; assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 = ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621)) ? 2'd1 : 2'd0 ; assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 = ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) ? 2'd1 : 2'd0 ; assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 = IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 + ((!IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) ? 2'd1 : 2'd0) ; assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 = ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223)) ? 2'd1 : 2'd0 ; assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 = ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) ? 2'd1 : 2'd0 ; assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 = IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 + ((!IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) ? 2'd1 : 2'd0) ; assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 = ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318)) ? 2'd1 : 2'd0 ; assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 = ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) ? 2'd1 : 2'd0 ; assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 = IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 + ((!IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) ? 2'd1 : 2'd0) ; assign IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 = (!ifcs_0_1_innerRoute$D_OUT[1] || !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_innerRoute$D_OUT[2] && ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_0_1_innerRoute$D_OUT[1] ; assign IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 = (!ifcs_0_innerRoute$D_OUT[1] || !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_0_innerRoute$D_OUT[2] && IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_0_innerRoute$D_OUT[1] ; assign IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 = (!ifcs_1_1_innerRoute$D_OUT[1] || !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_innerRoute$D_OUT[2] && ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_1_1_innerRoute$D_OUT[1] ; assign IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 = (!ifcs_1_innerRoute$D_OUT[1] || !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_1_innerRoute$D_OUT[2] && IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_1_innerRoute$D_OUT[1] ; assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 = (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? x__h118621 | y__h118622 : arbiter_1_1_lastSelect ; assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 = (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? x__h118809 | y__h118810 : arbiter_1_1_lastSelect_1 ; assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 = (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? x__h118990 | y__h118991 : arbiter_1_1_firstHot ; assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 = (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? x__h85347 | y__h85348 : arbiter_1_lastSelect ; assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 = (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? x__h85535 | y__h85536 : arbiter_1_lastSelect_1 ; assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 = (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? x__h85716 | y__h85717 : arbiter_1_firstHot ; assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 = (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? x__h106172 | y__h106173 : arbiter_1_lastSelect_2 ; assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 = (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? x__h106313 | y__h106314 : arbiter_1_firstHot_1 ; assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 = (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? x__h70399 | y__h70400 : arbiter_lastSelect ; assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 = (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? x__h70540 | y__h70541 : arbiter_firstHot ; assign IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 = (merged_0_flitLeft == 8'd0) ? merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N : merged_0_wff$EMPTY_N ; assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 = merged_0_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519 = x__h56240 < soc_map$m_mem0_controller_addr_range[63:0] ; assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 = merged_0_outflit$wget[166:103] < soc_map$m_plic_addr_range[127:64] ; assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527 = x__h56275 < soc_map$m_plic_addr_range[63:0] ; assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 = (CAN_FIRE_RL_merged_0_passFlit && !merged_0_outflit$wget[171]) ? { 1'd0, merged_0_outflit$wget[170:0] } : { 98'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ , CAN_FIRE_RL_merged_0_passFlit ? merged_0_outflit$wget[73:0] : merged_0_wff$D_OUT } ; assign IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 = CAN_FIRE_RL_merged_0_passFlit ? !merged_0_outflit$wget[1] : !merged_0_wff$D_OUT[1] ; assign IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 = CAN_FIRE_RL_merged_0_passFlit ? merged_0_outflit$wget[1] : merged_0_wff$D_OUT[1] ; assign IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 = (merged_1_flitLeft == 8'd0) ? merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N : merged_1_wff$EMPTY_N ; assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 = merged_1_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616 = x__h59752 < soc_map$m_mem0_controller_addr_range[63:0] ; assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 = merged_1_outflit$wget[166:103] < soc_map$m_plic_addr_range[127:64] ; assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621 = x__h59777 < soc_map$m_plic_addr_range[63:0] ; assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 = (CAN_FIRE_RL_merged_1_passFlit && !merged_1_outflit$wget[171]) ? { 1'd1, merged_1_outflit$wget[170:0] } : { 98'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ , CAN_FIRE_RL_merged_1_passFlit ? merged_1_outflit$wget[73:0] : merged_1_wff$D_OUT } ; assign IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 = CAN_FIRE_RL_merged_1_passFlit ? !merged_1_outflit$wget[1] : !merged_1_wff$D_OUT[1] ; assign IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 = CAN_FIRE_RL_merged_1_passFlit ? merged_1_outflit$wget[1] : merged_1_wff$D_OUT[1] ; assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 = addr__h93766 < soc_map$m_mem0_controller_addr_range[127:64] ; assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218 = x__h93842 < soc_map$m_mem0_controller_addr_range[63:0] ; assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 = addr__h93766 < soc_map$m_plic_addr_range[127:64] ; assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223 = x__h93867 < soc_map$m_plic_addr_range[63:0] ; assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 = addr__h96383 < soc_map$m_mem0_controller_addr_range[127:64] ; assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313 = x__h96459 < soc_map$m_mem0_controller_addr_range[63:0] ; assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 = addr__h96383 < soc_map$m_plic_addr_range[127:64] ; assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318 = x__h96484 < soc_map$m_plic_addr_range[63:0] ; assign IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 = (split_0_flitLeft == 8'd0) ? ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : ssNoSynth_0_wNoSynth_buffer_ff$FULL_N ; assign IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 = (split_1_flitLeft == 8'd0) ? ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : ssNoSynth_1_wNoSynth_buffer_ff$FULL_N ; assign IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 = (split_2_flitLeft == 8'd0) ? ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : ssNoSynth_2_wNoSynth_buffer_ff$FULL_N ; assign SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22 = {2{SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750}} ; assign SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12 = {2{SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059}} ; assign SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17 = {2{SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553}} ; assign SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7 = {2{SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852}} ; assign SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 = x__h118149 | y__h118150 ; assign SEXT_arbiter_1_1_firstHot__q19 = {2{arbiter_1_1_firstHot}} ; assign SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 = x__h118013 | y__h118014 ; assign SEXT_arbiter_1_1_lastSelect_1__q21 = {2{arbiter_1_1_lastSelect_1}} ; assign SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 = x__h117862 | y__h117863 ; assign SEXT_arbiter_1_1_lastSelect__q20 = {2{arbiter_1_1_lastSelect}} ; assign SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 = x__h84875 | y__h84876 ; assign SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 = x__h105807 | y__h105808 ; assign SEXT_arbiter_1_firstHot_1__q15 = {2{arbiter_1_firstHot_1}} ; assign SEXT_arbiter_1_firstHot__q9 = {2{arbiter_1_firstHot}} ; assign SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 = x__h84588 | y__h84589 ; assign SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 = x__h84739 | y__h84740 ; assign SEXT_arbiter_1_lastSelect_1__q11 = {2{arbiter_1_lastSelect_1}} ; assign SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 = x__h105704 | y__h105705 ; assign SEXT_arbiter_1_lastSelect_2__q16 = {2{arbiter_1_lastSelect_2}} ; assign SEXT_arbiter_1_lastSelect__q10 = {2{arbiter_1_lastSelect}} ; assign SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 = x__h70034 | y__h70035 ; assign SEXT_arbiter_firstHot__q5 = {2{arbiter_firstHot}} ; assign SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 = x__h69931 | y__h69932 ; assign SEXT_arbiter_lastSelect__q6 = {2{arbiter_lastSelect}} ; assign SEXT_x0458__q8 = {2{x__h70458}} ; assign SEXT_x06231__q18 = {2{x__h106231}} ; assign SEXT_x18683__q23 = {2{x__h118683}} ; assign SEXT_x18717__q24 = {2{x__h118717}} ; assign SEXT_x5409__q13 = {2{x__h85409}} ; assign SEXT_x5443__q14 = {2{x__h85443}} ; assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224 = x__h12428 + y__h12429 ; assign addr__h93766 = msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:29] : proc$master1_ar_peek[92:29] ; assign addr__h96383 = msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:29] : msNoSynth_1_arNoSynth_buffer_enqw$wget[92:29] ; assign arcache__h15356 = tagController_tmp_tagCon$memory_request_get[8] ? 4'd0 : 4'd15 ; assign arlen__h15352 = { 5'd0, tagController_tmp_tagCon$memory_request_get[5:3] } ; assign aw_awaddr__h10619 = tmp__h10402 + { 60'd0, x__h10694 } ; assign aw_awsize_val__h12358 = _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[0] ? 3'd0 : (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[1] ? 3'd1 : (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[2] ? 3'd2 : (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[3] ? 3'd3 : 3'd4))) ; assign fatReq_arid__h94350 = { 1'd0, msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_arNoSynth_buffer_ff$D_OUT[96:93] : proc$master1_ar_peek[96:93] } ; assign fatReq_arid__h96952 = { 1'd1, msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_arNoSynth_buffer_ff$D_OUT[96:93] : msNoSynth_1_arNoSynth_buffer_enqw$wget[96:93] } ; assign reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 = CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget || CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget || CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget ; assign reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 = CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget || CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget || CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget ; assign split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 = CAN_FIRE_RL_sinks_0_doPut && (split_0_doPut$wget[172] || ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; assign split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 = CAN_FIRE_RL_sinks_1_doPut && (split_1_doPut$wget[172] || ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; assign split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 = CAN_FIRE_RL_sinks_2_doPut && (split_2_doPut$wget[172] || ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; assign state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 = state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && ((!ifcs_0_routeBack$D_OUT[0] || !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_0_routeBack$D_OUT[1] && msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_0_routeBack$D_OUT[0]) ; assign state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 = state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && ((!ifcs_1_routeBack$D_OUT[0] || !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_1_routeBack$D_OUT[1] && msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_1_routeBack$D_OUT[0]) ; assign state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 = state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && ((!ifcs_2_routeBack$D_OUT[0] || !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_2_routeBack$D_OUT[1] && msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_2_routeBack$D_OUT[0]) ; assign state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 = state_1_1_1 && activeSource_1_1_0 && ifcs_0_1_routeBack$EMPTY_N && ((!ifcs_0_1_routeBack$D_OUT[0] || !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0]) ; assign state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 = state_1_1_1 && activeSource_1_1_1_1 && ifcs_1_1_routeBack$EMPTY_N && ((!ifcs_1_1_routeBack$D_OUT[0] || !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0]) ; assign state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 = state_1_1_1 && activeSource_1_1_2 && ifcs_2_1_routeBack$EMPTY_N && ((!ifcs_2_1_routeBack$D_OUT[0] || !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0]) ; assign state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 = state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && ((!ifcs_0_1_innerRoute$D_OUT[0] || !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : ifcs_0_1_innerRoute$D_OUT[0]) ; assign state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 = state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && ((!ifcs_1_1_innerRoute$D_OUT[0] || !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : ifcs_1_1_innerRoute$D_OUT[0]) ; assign state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 = state && activeSource_0 && ifcs_0_innerRoute$EMPTY_N && ((!ifcs_0_innerRoute$D_OUT[0] || !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0]) ; assign state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 = state && activeSource_1 && ifcs_1_innerRoute$EMPTY_N && ((!ifcs_1_innerRoute$D_OUT[0] || !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0]) ; assign tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4 = tagController_tmp_shimMaster_arff_rv$port1__read[98:0] ; assign tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2 = tagController_tmp_shimMaster_awff_rv$port1__read[98:0] ; assign tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3 = tagController_tmp_shimMaster_wff_rv$port1__read[72:0] ; assign tmp__h10402 = { 24'd0, x__h10651 } ; assign tmp__h8177 = tagController_tmp_awreqff$D_OUT[92:29] + tagController_tmp_addrOffset ; assign uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1 = uncached_mem_shim_wff$D_OUT[73:1] ; assign v_araddr__h15368 = { 24'd0, tagController_tmp_tagCon$memory_request_get[140:101] } ; assign v_arid__h15367 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[100:95] : 6'd0 ; assign v_arlen__h15369 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? arlen__h15352 : 8'd0 ; assign v_arsize_val__h15414 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[2:0] : 3'b0 ; assign x__h100333 = ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[72:68] : ssNoSynth_2_rNoSynth_buffer_enqw$wget[72:68] ; assign x__h105704 = SEXT_arbiter_1_lastSelect_2__q16[0] & (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; assign x__h105807 = SEXT_arbiter_1_firstHot_1__q15[0] & (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; assign x__h106172 = SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & arbiter_1_firstHot_1 ; assign x__h106231 = !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 && SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 ; assign x__h106313 = SEXT_x06231__q18[0] & arbiter_1_firstHot_1 ; assign x__h10651 = { tagController_tmp_tagCon$memory_request_get[140:104], 3'd0 } ; assign x__h10694 = tagController_tmp_tagCon$memory_request_get[81] ? 4'd0 : (tagController_tmp_tagCon$memory_request_get[82] ? 4'd1 : (tagController_tmp_tagCon$memory_request_get[83] ? 4'd2 : (tagController_tmp_tagCon$memory_request_get[84] ? 4'd3 : (tagController_tmp_tagCon$memory_request_get[85] ? 4'd4 : (tagController_tmp_tagCon$memory_request_get[86] ? 4'd5 : (tagController_tmp_tagCon$memory_request_get[87] ? 4'd6 : (tagController_tmp_tagCon$memory_request_get[88] ? 4'd7 : 4'd8))))))) ; assign x__h117862 = x__h117864 | y__h117865 ; assign x__h117864 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; assign x__h118013 = x__h118015 | y__h118016 ; assign x__h118015 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; assign x__h118149 = x__h118151 | y__h118152 ; assign x__h118151 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; assign x__h118621 = x__h118623 | y__h118624 ; assign x__h118623 = SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_firstHot ; assign x__h118683 = !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 ; assign x__h118717 = !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 ; assign x__h118809 = x__h118811 | y__h118812 ; assign x__h118811 = SEXT_x18683__q23[0] & arbiter_1_1_firstHot ; assign x__h118990 = x__h118992 | y__h118993 ; assign x__h118992 = SEXT_x18717__q24[0] & arbiter_1_1_firstHot ; assign x__h12428 = x__h12440 + y__h12441 ; assign x__h12440 = x__h12452 + y__h12453 ; assign x__h12452 = x__h12464 + y__h12465 ; assign x__h12464 = x__h12476 + y__h12477 ; assign x__h12476 = x__h12488 + y__h12489 ; assign x__h12488 = x__h12500 + y__h12501 ; assign x__h12500 = { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; assign x__h14024 = tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; assign x__h15432 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? arcache__h15356 : 4'd0 ; assign x__h56240 = merged_0_outflit$wget[166:103] - soc_map$m_mem0_controller_addr_range[127:64] ; assign x__h56275 = merged_0_outflit$wget[166:103] - soc_map$m_plic_addr_range[127:64] ; assign x__h59752 = merged_1_outflit$wget[166:103] - soc_map$m_mem0_controller_addr_range[127:64] ; assign x__h59777 = merged_1_outflit$wget[166:103] - soc_map$m_plic_addr_range[127:64] ; assign x__h62633 = ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[6:2] : uncached_mem_shim_bff$D_OUT[6:2] ; assign x__h63524 = ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[6:2] : ssNoSynth_1_bNoSynth_buffer_enqw$wget[6:2] ; assign x__h64415 = ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[6:2] : ssNoSynth_2_bNoSynth_buffer_enqw$wget[6:2] ; assign x__h69931 = SEXT_arbiter_lastSelect__q6[0] & (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; assign x__h70034 = SEXT_arbiter_firstHot__q5[0] & (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; assign x__h70399 = SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & arbiter_firstHot ; assign x__h70458 = !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 && SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 ; assign x__h70540 = SEXT_x0458__q8[0] & arbiter_firstHot ; assign x__h8018 = tagController_tmp_addrOffset + (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; assign x__h84588 = x__h84590 | y__h84591 ; assign x__h84590 = SEXT_arbiter_1_lastSelect__q10[0] & (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; assign x__h84739 = x__h84741 | y__h84742 ; assign x__h84741 = SEXT_arbiter_1_lastSelect_1__q11[0] & (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; assign x__h84875 = x__h84877 | y__h84878 ; assign x__h84877 = SEXT_arbiter_1_firstHot__q9[0] & (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; assign x__h85347 = x__h85349 | y__h85350 ; assign x__h85349 = SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & arbiter_1_firstHot ; assign x__h85409 = !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 ; assign x__h85443 = !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 ; assign x__h85535 = x__h85537 | y__h85538 ; assign x__h85537 = SEXT_x5409__q13[0] & arbiter_1_firstHot ; assign x__h85716 = x__h85718 | y__h85719 ; assign x__h85718 = SEXT_x5443__q14[0] & arbiter_1_firstHot ; assign x__h93842 = addr__h93766 - soc_map$m_mem0_controller_addr_range[127:64] ; assign x__h93867 = addr__h93766 - soc_map$m_plic_addr_range[127:64] ; assign x__h94928 = msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_0_arNoSynth_buffer_ff$D_OUT[28:21] : proc$master1_ar_peek[28:21] ; assign x__h95031 = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? ifcs_0_1_noRoute_flitCount$port0__write_1 : ifcs_0_1_noRoute_flitCount ; assign x__h96459 = addr__h96383 - soc_map$m_mem0_controller_addr_range[127:64] ; assign x__h96484 = addr__h96383 - soc_map$m_plic_addr_range[127:64] ; assign x__h97527 = msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_arNoSynth_buffer_ff$D_OUT[28:21] : msNoSynth_1_arNoSynth_buffer_enqw$wget[28:21] ; assign x__h97630 = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? ifcs_1_1_noRoute_flitCount$port0__write_1 : ifcs_1_1_noRoute_flitCount ; assign x__h98423 = ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[72:68] : uncached_mem_shim_rff$D_OUT[72:68] ; assign x__h99378 = ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[72:68] : ssNoSynth_1_rNoSynth_buffer_enqw$wget[72:68] ; assign y__h105705 = SEXT_arbiter_1_firstHot_1__q15[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; assign y__h105808 = SEXT_arbiter_1_lastSelect_2__q16[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; assign y__h106173 = SEXT_x06231__q18[0] & arbiter_1_lastSelect_2 ; assign y__h106314 = SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & arbiter_1_lastSelect_2 ; assign y__h117863 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; assign y__h117865 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; assign y__h118014 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; assign y__h118016 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; assign y__h118150 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; assign y__h118152 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; assign y__h118622 = SEXT_x18717__q24[0] & arbiter_1_1_lastSelect ; assign y__h118624 = SEXT_x18683__q23[0] & arbiter_1_1_lastSelect_1 ; assign y__h118810 = SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect ; assign y__h118812 = SEXT_x18717__q24[0] & arbiter_1_1_lastSelect_1 ; assign y__h118991 = SEXT_x18683__q23[0] & arbiter_1_1_lastSelect ; assign y__h118993 = SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect_1 ; assign y__h12429 = { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; assign y__h12441 = { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; assign y__h12453 = { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; assign y__h12465 = { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; assign y__h12477 = { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; assign y__h12489 = { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; assign y__h12501 = { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; assign y__h69932 = SEXT_arbiter_firstHot__q5[0] & (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; assign y__h70035 = SEXT_arbiter_lastSelect__q6[0] & (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; assign y__h70400 = SEXT_x0458__q8[0] & arbiter_lastSelect ; assign y__h70541 = SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & arbiter_lastSelect ; assign y__h84589 = SEXT_arbiter_1_firstHot__q9[0] & (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; assign y__h84591 = SEXT_arbiter_1_lastSelect_1__q11[0] & (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; assign y__h84740 = SEXT_arbiter_1_lastSelect__q10[0] & (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; assign y__h84742 = SEXT_arbiter_1_firstHot__q9[0] & (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; assign y__h84876 = SEXT_arbiter_1_lastSelect_1__q11[0] & (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; assign y__h84878 = SEXT_arbiter_1_lastSelect__q10[0] & (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; assign y__h85348 = SEXT_x5443__q14[0] & arbiter_1_lastSelect ; assign y__h85350 = SEXT_x5409__q13[0] & arbiter_1_lastSelect_1 ; assign y__h85536 = SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & arbiter_1_lastSelect ; assign y__h85538 = SEXT_x5443__q14[0] & arbiter_1_lastSelect_1 ; assign y__h85717 = SEXT_x5409__q13[0] & arbiter_1_lastSelect ; assign y__h85719 = SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & arbiter_1_lastSelect_1 ; // handling of inlined registers always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin activeSource_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY 1'd1; arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY 97'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ; ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY 97'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ; ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_0_state <= `BSV_ASSIGNMENT_DELAY 2'd0; ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY 97'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ; ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY 97'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ; ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY 1'd0; ifcs_2_state <= `BSV_ASSIGNMENT_DELAY 1'd0; merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; state <= `BSV_ASSIGNMENT_DELAY 1'd0; state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; state_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; state_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (activeSource_0$EN) activeSource_0 <= `BSV_ASSIGNMENT_DELAY activeSource_0$D_IN; if (activeSource_1$EN) activeSource_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1$D_IN; if (activeSource_1_0$EN) activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0$D_IN; if (activeSource_1_0_1$EN) activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0_1$D_IN; if (activeSource_1_1$EN) activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1$D_IN; if (activeSource_1_1_0$EN) activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_0$D_IN; if (activeSource_1_1_1$EN) activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_1$D_IN; if (activeSource_1_1_1_1$EN) activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_1_1$D_IN; if (activeSource_1_1_2$EN) activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_2$D_IN; if (activeSource_1_2$EN) activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_2$D_IN; if (arbiter_1_1_firstHot$EN) arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_1_1_firstHot$D_IN; if (arbiter_1_1_lastSelect$EN) arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY arbiter_1_1_lastSelect$D_IN; if (arbiter_1_1_lastSelect_1$EN) arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY arbiter_1_1_lastSelect_1$D_IN; if (arbiter_1_firstHot$EN) arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_1_firstHot$D_IN; if (arbiter_1_firstHot_1$EN) arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY arbiter_1_firstHot_1$D_IN; if (arbiter_1_lastSelect$EN) arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY arbiter_1_lastSelect$D_IN; if (arbiter_1_lastSelect_1$EN) arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY arbiter_1_lastSelect_1$D_IN; if (arbiter_1_lastSelect_2$EN) arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY arbiter_1_lastSelect_2$D_IN; if (arbiter_firstHot$EN) arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_firstHot$D_IN; if (arbiter_lastSelect$EN) arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY arbiter_lastSelect$D_IN; if (ifcs_0_1_noRoute_currentReq$EN) ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_noRoute_currentReq$D_IN; if (ifcs_0_1_noRoute_flitCount$EN) ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_noRoute_flitCount$D_IN; if (ifcs_0_1_state$EN) ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state$D_IN; if (ifcs_0_1_state_1$EN) ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state_1$D_IN; if (ifcs_0_noRoute_inner_currentReq$EN) ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY ifcs_0_noRoute_inner_currentReq$D_IN; if (ifcs_0_noRoute_inner_pendingReq$EN) ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY ifcs_0_noRoute_inner_pendingReq$D_IN; if (ifcs_0_state$EN) ifcs_0_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_state$D_IN; if (ifcs_0_state_1$EN) ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_state_1$D_IN; if (ifcs_1_1_noRoute_currentReq$EN) ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_noRoute_currentReq$D_IN; if (ifcs_1_1_noRoute_flitCount$EN) ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_noRoute_flitCount$D_IN; if (ifcs_1_1_state$EN) ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state$D_IN; if (ifcs_1_1_state_1$EN) ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state_1$D_IN; if (ifcs_1_noRoute_inner_currentReq$EN) ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY ifcs_1_noRoute_inner_currentReq$D_IN; if (ifcs_1_noRoute_inner_pendingReq$EN) ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY ifcs_1_noRoute_inner_pendingReq$D_IN; if (ifcs_1_state$EN) ifcs_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_state$D_IN; if (ifcs_1_state_1$EN) ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_state_1$D_IN; if (ifcs_2_1_state$EN) ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_1_state$D_IN; if (ifcs_2_state$EN) ifcs_2_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_state$D_IN; if (merged_0_flitLeft$EN) merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_0_flitLeft$D_IN; if (merged_1_flitLeft$EN) merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_1_flitLeft$D_IN; if (rg_fromhost_addr$EN) rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; if (rg_hart0_reset_delay$EN) rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_hart0_reset_delay$D_IN; if (rg_tohost_addr$EN) rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; if (split_0_flitLeft$EN) split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY split_0_flitLeft$D_IN; if (split_1_flitLeft$EN) split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY split_1_flitLeft$D_IN; if (split_2_flitLeft$EN) split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY split_2_flitLeft$D_IN; if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN; if (state_1$EN) state_1 <= `BSV_ASSIGNMENT_DELAY state_1$D_IN; if (state_1_1$EN) state_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1$D_IN; if (state_1_1_1$EN) state_1_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1_1$D_IN; end if (hart0_reset$RST_OUT == `BSV_RESET_VALUE) begin tagController_tmp_addrOffset <= `BSV_ASSIGNMENT_DELAY 64'd0; tagController_tmp_doneSendingAW <= `BSV_ASSIGNMENT_DELAY 1'd0; tagController_tmp_reset_done <= `BSV_ASSIGNMENT_DELAY 1'd0; tagController_tmp_shimMaster_arff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 99'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; tagController_tmp_shimMaster_awff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 99'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; tagController_tmp_shimMaster_bff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 8'bxxxxxxxx /* unspecified value */ }; tagController_tmp_shimMaster_rff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 73'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; tagController_tmp_shimMaster_wff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 73'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; tagController_tmp_shimSlave_arff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 98'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; tagController_tmp_shimSlave_awff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 98'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; tagController_tmp_shimSlave_bff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 7'bxxxxxxx /* unspecified value */ }; tagController_tmp_shimSlave_rff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 73'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; tagController_tmp_shimSlave_wff_rv <= `BSV_ASSIGNMENT_DELAY { 1'd0, 74'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ }; end else begin if (tagController_tmp_addrOffset$EN) tagController_tmp_addrOffset <= `BSV_ASSIGNMENT_DELAY tagController_tmp_addrOffset$D_IN; if (tagController_tmp_doneSendingAW$EN) tagController_tmp_doneSendingAW <= `BSV_ASSIGNMENT_DELAY tagController_tmp_doneSendingAW$D_IN; if (tagController_tmp_reset_done$EN) tagController_tmp_reset_done <= `BSV_ASSIGNMENT_DELAY tagController_tmp_reset_done$D_IN; if (tagController_tmp_shimMaster_arff_rv$EN) tagController_tmp_shimMaster_arff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimMaster_arff_rv$D_IN; if (tagController_tmp_shimMaster_awff_rv$EN) tagController_tmp_shimMaster_awff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimMaster_awff_rv$D_IN; if (tagController_tmp_shimMaster_bff_rv$EN) tagController_tmp_shimMaster_bff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimMaster_bff_rv$D_IN; if (tagController_tmp_shimMaster_rff_rv$EN) tagController_tmp_shimMaster_rff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimMaster_rff_rv$D_IN; if (tagController_tmp_shimMaster_wff_rv$EN) tagController_tmp_shimMaster_wff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimMaster_wff_rv$D_IN; if (tagController_tmp_shimSlave_arff_rv$EN) tagController_tmp_shimSlave_arff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimSlave_arff_rv$D_IN; if (tagController_tmp_shimSlave_awff_rv$EN) tagController_tmp_shimSlave_awff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimSlave_awff_rv$D_IN; if (tagController_tmp_shimSlave_bff_rv$EN) tagController_tmp_shimSlave_bff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimSlave_bff_rv$D_IN; if (tagController_tmp_shimSlave_rff_rv$EN) tagController_tmp_shimSlave_rff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimSlave_rff_rv$D_IN; if (tagController_tmp_shimSlave_wff_rv$EN) tagController_tmp_shimSlave_wff_rv <= `BSV_ASSIGNMENT_DELAY tagController_tmp_shimSlave_wff_rv$D_IN; end end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin activeSource_0 = 1'h0; activeSource_1 = 1'h0; activeSource_1_0 = 1'h0; activeSource_1_0_1 = 1'h0; activeSource_1_1 = 1'h0; activeSource_1_1_0 = 1'h0; activeSource_1_1_1 = 1'h0; activeSource_1_1_1_1 = 1'h0; activeSource_1_1_2 = 1'h0; activeSource_1_2 = 1'h0; arbiter_1_1_firstHot = 1'h0; arbiter_1_1_lastSelect = 1'h0; arbiter_1_1_lastSelect_1 = 1'h0; arbiter_1_firstHot = 1'h0; arbiter_1_firstHot_1 = 1'h0; arbiter_1_lastSelect = 1'h0; arbiter_1_lastSelect_1 = 1'h0; arbiter_1_lastSelect_2 = 1'h0; arbiter_firstHot = 1'h0; arbiter_lastSelect = 1'h0; ifcs_0_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; ifcs_0_1_noRoute_flitCount = 9'h0AA; ifcs_0_1_state = 2'h2; ifcs_0_1_state_1 = 1'h0; ifcs_0_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; ifcs_0_noRoute_inner_pendingReq = 1'h0; ifcs_0_state = 2'h2; ifcs_0_state_1 = 1'h0; ifcs_1_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; ifcs_1_1_noRoute_flitCount = 9'h0AA; ifcs_1_1_state = 2'h2; ifcs_1_1_state_1 = 1'h0; ifcs_1_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; ifcs_1_noRoute_inner_pendingReq = 1'h0; ifcs_1_state = 2'h2; ifcs_1_state_1 = 1'h0; ifcs_2_1_state = 1'h0; ifcs_2_state = 1'h0; merged_0_flitLeft = 8'hAA; merged_1_flitLeft = 8'hAA; rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; rg_hart0_reset_delay = 8'hAA; rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; split_0_flitLeft = 8'hAA; split_1_flitLeft = 8'hAA; split_2_flitLeft = 8'hAA; state = 1'h0; state_1 = 1'h0; state_1_1 = 1'h0; state_1_1_1 = 1'h0; tagController_tmp_addrOffset = 64'hAAAAAAAAAAAAAAAA; tagController_tmp_doneSendingAW = 1'h0; tagController_tmp_reset_done = 1'h0; tagController_tmp_shimMaster_arff_rv = 100'hAAAAAAAAAAAAAAAAAAAAAAAAA; tagController_tmp_shimMaster_awff_rv = 100'hAAAAAAAAAAAAAAAAAAAAAAAAA; tagController_tmp_shimMaster_bff_rv = 9'h0AA; tagController_tmp_shimMaster_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA; tagController_tmp_shimMaster_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; tagController_tmp_shimSlave_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; tagController_tmp_shimSlave_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; tagController_tmp_shimSlave_bff_rv = 8'hAA; tagController_tmp_shimSlave_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA; tagController_tmp_shimSlave_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin v__h27379 = $stime; #0; end v__h27373 = v__h27379 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", v__h27373, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin v__h27522 = $stime; #0; end v__h27516 = v__h27522 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", v__h27516, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin v__h71933 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h71933, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) begin v__h71322 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h71322, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin v__h75942 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h75942, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) begin v__h75331 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h75331, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && WILL_FIRE_RL_burst) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 113, column 32: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected] and\n [RL_burst] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_source_selected || WILL_FIRE_RL_burst) && (WILL_FIRE_RL_source_selected_1 || WILL_FIRE_RL_burst_1)) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected, RL_burst]\n and [RL_source_selected_1, RL_burst_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && WILL_FIRE_RL_burst_1) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_1] and\n [RL_burst_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sink_selected && WILL_FIRE_RL_sink_selected_1) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected] and\n [RL_sink_selected_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_sink_selected || WILL_FIRE_RL_sink_selected_1) && WILL_FIRE_RL_sink_selected_2) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected,\n RL_sink_selected_1] and [RL_sink_selected_2] ) fired in the same clock\n cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_1 && !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_1 && !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin v__h87108 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h87108, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) begin v__h86727 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h86727, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin v__h89178 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h89178, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) begin v__h88797 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h88797, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin v__h91077 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h91077, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) begin v__h90696 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h90696, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3) && (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin v__h107706 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h107706, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) begin v__h107095 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h107095, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin v__h110599 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h110599, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) begin v__h109988 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h109988, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && WILL_FIRE_RL_burst_5) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5] and\n [RL_burst_5] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_source_selected_5 || WILL_FIRE_RL_burst_5) && (WILL_FIRE_RL_source_selected_6 || WILL_FIRE_RL_burst_6)) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5,\n RL_burst_5] and [RL_source_selected_6, RL_burst_6] ) fired in the same clock\n cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && WILL_FIRE_RL_burst_6) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_6] and\n [RL_burst_6] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sink_selected_5 && WILL_FIRE_RL_sink_selected_6) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5] and\n [RL_sink_selected_6] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_sink_selected_5 || WILL_FIRE_RL_sink_selected_6) && WILL_FIRE_RL_sink_selected_7) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5,\n RL_sink_selected_6] and [RL_sink_selected_7] ) fired in the same clock\n cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin v__h120386 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h120386, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) begin v__h120005 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h120005, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin v__h122877 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h122877, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) begin v__h122496 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h122496, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && WILL_FIRE_RL_burst_8) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_8] and\n [RL_burst_8] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin v__h125187 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", v__h125187, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write(" is not a valid one-hot path.", "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) begin v__h124806 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", v__h124806, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && WILL_FIRE_RL_burst_7) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7] and\n [RL_burst_7] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7) && (WILL_FIRE_RL_source_selected_8 || WILL_FIRE_RL_burst_8)) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7] and [RL_source_selected_8, RL_burst_8] ) fired in the same clock\n cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7 || WILL_FIRE_RL_source_selected_8 || WILL_FIRE_RL_burst_8) && (WILL_FIRE_RL_source_selected_9 || WILL_FIRE_RL_burst_9)) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7, RL_source_selected_8, RL_burst_8] and [RL_source_selected_9,\n RL_burst_9] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && WILL_FIRE_RL_burst_9) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_9] and\n [RL_burst_9] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sink_selected_8 && WILL_FIRE_RL_sink_selected_9) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_8] and\n [RL_sink_selected_9] ) fired in the same clock cycle.\n"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && WILL_FIRE_RL_ifcs_0_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && WILL_FIRE_RL_ifcs_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && WILL_FIRE_RL_ifcs_0_followFlits_1) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && WILL_FIRE_RL_ifcs_1_followFlits_1) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_0_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) $display("splitWrite - Expecting FirstFlit of merged write"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && split_0_doPut$wget[1] && split_0_flitLeft > 8'd1) $display("splitWrite - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && split_0_doPut$wget[1] && split_0_flitLeft > 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && !split_0_doPut$wget[1] && split_0_flitLeft == 8'd1) $display("splitWrite - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && !split_0_doPut$wget[1] && split_0_flitLeft == 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) $display("splitWrite - Expecting OtherFlit of merged write"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) $display("splitWrite - Expecting FirstFlit of merged write"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && split_1_doPut$wget[1] && split_1_flitLeft > 8'd1) $display("splitWrite - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && split_1_doPut$wget[1] && split_1_flitLeft > 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && !split_1_doPut$wget[1] && split_1_flitLeft == 8'd1) $display("splitWrite - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && !split_1_doPut$wget[1] && split_1_flitLeft == 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) $display("splitWrite - Expecting OtherFlit of merged write"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_2_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) $display("splitWrite - Expecting FirstFlit of merged write"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && split_2_doPut$wget[1] && split_2_flitLeft > 8'd1) $display("splitWrite - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && split_2_doPut$wget[1] && split_2_flitLeft > 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && !split_2_doPut$wget[1] && split_2_flitLeft == 8'd1) $display("splitWrite - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && !split_2_doPut$wget[1] && split_2_flitLeft == 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) $display("splitWrite - Expecting OtherFlit of merged write"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_0_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_drainFlits && WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && merged_0_flitLeft > 8'd1) $display("%m - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && merged_0_flitLeft > 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && merged_0_flitLeft == 8'd1) $display("%m - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && merged_0_flitLeft == 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_1_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_drainFlits && WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && merged_1_flitLeft > 8'd1) $display("%m - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && merged_1_flitLeft > 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && merged_1_flitLeft == 8'd1) $display("%m - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && merged_1_flitLeft == 8'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && WILL_FIRE_RL_ifcs_0_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && WILL_FIRE_RL_ifcs_0_1_followFlits_1) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && WILL_FIRE_RL_ifcs_1_1_followFlits_1) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_0_warnDoPut_1) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_1_warnDoPut_1) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin v__h128915 = $stime; #0; end v__h128909 = v__h128915 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", v__h128909, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_2_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_2_1_firstFlit && WILL_FIRE_RL_ifcs_2_1_followFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_1_0_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_followFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_followFlits && WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_followFlits && WILL_FIRE_RL_ifcs_0_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_followFlits && WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_drainFlits && WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sinks_1_1_1_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_followFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_followFlits && WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_followFlits && WILL_FIRE_RL_ifcs_1_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_followFlits && WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && WILL_FIRE_RL_ifcs_1_1_drainFlits) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_drainFlits && WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) $display("WARNING: %m - putting into a Sink that can't be put into"); end // synopsys translate_on endmodule // mkCoreW