// // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // // On Thu Jul 16 18:15:02 BST 2020 // // // Ports: // Name I/O size props // capInspect O 64 // capInspect_a I 163 // capInspect_b I 163 // capInspect_func I 4 // // Combinational paths from inputs to outputs: // (capInspect_a, capInspect_b, capInspect_func) -> capInspect // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module module_capInspect(capInspect_a, capInspect_b, capInspect_func, capInspect); // value method capInspect input [162 : 0] capInspect_a; input [162 : 0] capInspect_b; input [3 : 0] capInspect_func; output [63 : 0] capInspect; // signals for module outputs reg [63 : 0] capInspect; // remaining internal signals reg [63 : 0] CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5; wire [65 : 0] addTop__h1361, addTop__h686, capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50, capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82, in__h2270, length__h2030, result__h1299, result__h1958, ret__h1365, ret__h690, x__h1358, x__h2025, x__h2288, x__h683, y__h2287; wire [63 : 0] addBase__h2072, addBase__h2423, bot__h2075, bot__h2426, x__h2234, x__h2236; wire [51 : 0] mask__h1362, mask__h687; wire [49 : 0] capInspect_a_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q2, capInspect_b_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q4, mask__h2073, mask__h2424; wire [30 : 0] x__h2326; wire [15 : 0] offset__h2222, x__h1451, x__h2035, x__h489, x__h623, x__h792; wire [1 : 0] capInspect_a_BITS_1_TO_0__q1, capInspect_b_BITS_1_TO_0__q3; wire capInspect_a_BITS_43_TO_38_6_ULT_51_0_AND_NOT__ETC___d63, capInspect_b_BITS_43_TO_38_7_ULT_51_2_AND_NOT__ETC___d95, capInspect_b_BIT_162_EQ_capInspect_a_BIT_162_A_ETC___d39, x__h1510, x__h2164, x__h27, x__h851; // value method capInspect always@(capInspect_func or capInspect_a or bot__h2426 or x__h27 or x__h2025 or bot__h2075 or x__h2164 or x__h2234 or in__h2270 or x__h2326 or CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5) begin case (capInspect_func) 4'd0: capInspect = { 63'd0, x__h27 }; 4'd2: capInspect = x__h2025[63:0]; 4'd3: capInspect = bot__h2075; 4'd4: capInspect = { 63'd0, capInspect_a[162] }; 4'd5: capInspect = { 63'd0, x__h2164 }; 4'd6: capInspect = capInspect_a[159:96]; 4'd7: capInspect = x__h2234 | in__h2270[63:0]; 4'd8: capInspect = { 63'd0, capInspect_a[65] }; 4'd9: capInspect = { 33'd0, x__h2326 }; 4'd10: capInspect = CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5; default: capInspect = capInspect_a[162] ? capInspect_a[159:96] - bot__h2426 : 64'd0; endcase end // remaining internal signals assign addBase__h2072 = { {48{x__h489[15]}}, x__h489 } << capInspect_a[43:38] ; assign addBase__h2423 = { {48{x__h623[15]}}, x__h623 } << capInspect_b[43:38] ; assign addTop__h1361 = { {50{x__h1451[15]}}, x__h1451 } << capInspect_b[43:38] ; assign addTop__h686 = { {50{x__h792[15]}}, x__h792 } << capInspect_a[43:38] ; assign bot__h2075 = { capInspect_a[159:110] & mask__h2073, 14'd0 } + addBase__h2072 ; assign bot__h2426 = { capInspect_b[159:110] & mask__h2424, 14'd0 } + addBase__h2423 ; assign capInspect_a_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q2 = capInspect_a[159:110] + ({ {48{capInspect_a_BITS_1_TO_0__q1[1]}}, capInspect_a_BITS_1_TO_0__q1 } << capInspect_a[43:38]) ; assign capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50 = { capInspect_a[161:110] & mask__h687, 14'd0 } + addTop__h686 ; assign capInspect_a_BITS_1_TO_0__q1 = capInspect_a[1:0] ; assign capInspect_a_BITS_43_TO_38_6_ULT_51_0_AND_NOT__ETC___d63 = capInspect_a[43:38] < 6'd51 && capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[64:63] - { 1'd0, x__h851 } > 2'd1 ; assign capInspect_b_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q4 = capInspect_b[159:110] + ({ {48{capInspect_b_BITS_1_TO_0__q3[1]}}, capInspect_b_BITS_1_TO_0__q3 } << capInspect_b[43:38]) ; assign capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82 = { capInspect_b[161:110] & mask__h1362, 14'd0 } + addTop__h1361 ; assign capInspect_b_BITS_1_TO_0__q3 = capInspect_b[1:0] ; assign capInspect_b_BITS_43_TO_38_7_ULT_51_2_AND_NOT__ETC___d95 = capInspect_b[43:38] < 6'd51 && capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[64:63] - { 1'd0, x__h1510 } > 2'd1 ; assign capInspect_b_BIT_162_EQ_capInspect_a_BIT_162_A_ETC___d39 = capInspect_b[162] == capInspect_a[162] && { 12'd0, capInspect_a[81:78] & capInspect_b[81:78], 3'd0, capInspect_a[77:66] & capInspect_b[77:66] } == x__h2326 && bot__h2075 >= bot__h2426 ; assign in__h2270 = capInspect_a[161:96] & y__h2287 ; assign length__h2030 = { 50'd0, x__h2035 } << capInspect_a[43:38] ; assign mask__h1362 = 52'hFFFFFFFFFFFFF << capInspect_b[43:38] ; assign mask__h2073 = 50'h3FFFFFFFFFFFF << capInspect_a[43:38] ; assign mask__h2424 = 50'h3FFFFFFFFFFFF << capInspect_b[43:38] ; assign mask__h687 = 52'hFFFFFFFFFFFFF << capInspect_a[43:38] ; assign offset__h2222 = { 2'd0, capInspect_a[95:82] } - x__h489 ; assign result__h1299 = { 1'd0, ~capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[64], capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[63:0] } ; assign result__h1958 = { 1'd0, ~capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[64], capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[63:0] } ; assign ret__h1365 = { 1'd0, capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[64:0] } ; assign ret__h690 = { 1'd0, capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[64:0] } ; assign x__h1358 = capInspect_b_BITS_43_TO_38_7_ULT_51_2_AND_NOT__ETC___d95 ? result__h1958 : ret__h1365 ; assign x__h1451 = { capInspect_b[3:2], capInspect_b[37:24] } ; assign x__h1510 = (capInspect_b[43:38] == 6'd50) ? capInspect_b[23] : capInspect_b_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q4[49] ; assign x__h2025 = (capInspect_a[43:38] < 6'd52) ? length__h2030 : 66'h3FFFFFFFFFFFFFFFF ; assign x__h2035 = x__h792 - x__h489 ; assign x__h2164 = capInspect_a[62:45] != 18'd262143 ; assign x__h2234 = x__h2236 << capInspect_a[43:38] ; assign x__h2236 = { {48{offset__h2222[15]}}, offset__h2222 } ; assign x__h2288 = 66'h3FFFFFFFFFFFFFFFF << capInspect_a[43:38] ; assign x__h2326 = { 12'd0, capInspect_a[81:78], 3'h0, capInspect_a[77:66] } ; assign x__h27 = capInspect_b_BIT_162_EQ_capInspect_a_BIT_162_A_ETC___d39 && x__h683[64:0] <= x__h1358[64:0] ; assign x__h489 = { capInspect_a[1:0], capInspect_a[23:10] } ; assign x__h623 = { capInspect_b[1:0], capInspect_b[23:10] } ; assign x__h683 = capInspect_a_BITS_43_TO_38_6_ULT_51_0_AND_NOT__ETC___d63 ? result__h1299 : ret__h690 ; assign x__h792 = { capInspect_a[3:2], capInspect_a[37:24] } ; assign x__h851 = (capInspect_a[43:38] == 6'd50) ? capInspect_a[23] : capInspect_a_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q2[49] ; assign y__h2287 = ~x__h2288 ; always@(capInspect_a) begin case (capInspect_a[62:45]) 18'd262140: CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 = 64'hFFFFFFFFFFFFFFFC; 18'd262141: CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 = 64'hFFFFFFFFFFFFFFFD; 18'd262142: CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 = 64'hFFFFFFFFFFFFFFFE; 18'd262143: CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 = 64'hFFFFFFFFFFFFFFFF; default: CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 = { 46'd0, capInspect_a[62:45] }; endcase end endmodule // module_capInspect