// // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // // // Ports: // Name I/O size props // getControlFlow O 130 // getControlFlow_dInst I 72 // getControlFlow_rVal1 I 64 // getControlFlow_rVal2 I 64 // getControlFlow_pc I 64 // getControlFlow_ppc I 64 // // Combinational paths from inputs to outputs: // (getControlFlow_dInst, // getControlFlow_rVal1, // getControlFlow_rVal2, // getControlFlow_pc, // getControlFlow_ppc) -> getControlFlow // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module module_getControlFlow(getControlFlow_dInst, getControlFlow_rVal1, getControlFlow_rVal2, getControlFlow_pc, getControlFlow_ppc, getControlFlow); // value method getControlFlow input [71 : 0] getControlFlow_dInst; input [63 : 0] getControlFlow_rVal1; input [63 : 0] getControlFlow_rVal2; input [63 : 0] getControlFlow_pc; input [63 : 0] getControlFlow_ppc; output [129 : 0] getControlFlow; // signals for module outputs wire [129 : 0] getControlFlow; // remaining internal signals wire [63 : 0] x__h50; wire [31 : 0] x__h114; wire aluBr___d9; // value method getControlFlow assign getControlFlow = { getControlFlow_pc, x__h50, getControlFlow_dInst[66:64] == 3'd1 && aluBr___d9, x__h50 != getControlFlow_ppc } ; // remaining internal signals module_aluBr instance_aluBr_0(.aluBr_a(getControlFlow_rVal1), .aluBr_b(getControlFlow_rVal2), .aluBr_brFunc(getControlFlow_dInst[48:46]), .aluBr(aluBr___d9)); module_brAddrCalc instance_brAddrCalc_1(.brAddrCalc_pc(getControlFlow_pc), .brAddrCalc_val(getControlFlow_rVal1), .brAddrCalc_iType(getControlFlow_dInst[71:67]), .brAddrCalc_imm({ {32{x__h114[31]}}, x__h114 }), .brAddrCalc_taken(getControlFlow_dInst[66:64] == 3'd1 && aluBr___d9), .brAddrCalc(x__h50)); assign x__h114 = getControlFlow_dInst[31:0] ; endmodule // module_getControlFlow