ssith user ssith_processor 1.0 master0 AWID master0_awid AWADDR master0_awaddr AWLEN master0_awlen AWSIZE master0_awsize AWBURST master0_awburst AWLOCK master0_awlock AWCACHE master0_awcache AWPROT master0_awprot AWREGION master0_awregion AWQOS master0_awqos AWVALID master0_awvalid AWREADY master0_awready WID master0_wid WDATA master0_wdata WSTRB master0_wstrb WLAST master0_wlast WVALID master0_wvalid WREADY master0_wready BID master0_bid BRESP master0_bresp BVALID master0_bvalid BREADY master0_bready ARID master0_arid ARADDR master0_araddr ARLEN master0_arlen ARSIZE master0_arsize ARBURST master0_arburst ARLOCK master0_arlock ARCACHE master0_arcache ARPROT master0_arprot ARREGION master0_arregion ARQOS master0_arqos ARVALID master0_arvalid ARREADY master0_arready RID master0_rid RDATA master0_rdata RRESP master0_rresp RLAST master0_rlast RVALID master0_rvalid RREADY master0_rready master1 AWID master1_awid AWADDR master1_awaddr AWLEN master1_awlen AWSIZE master1_awsize AWBURST master1_awburst AWLOCK master1_awlock AWCACHE master1_awcache AWPROT master1_awprot AWREGION master1_awregion AWQOS master1_awqos AWVALID master1_awvalid AWREADY master1_awready WID master1_wid WDATA master1_wdata WSTRB master1_wstrb WLAST master1_wlast WVALID master1_wvalid WREADY master1_wready BID master1_bid BRESP master1_bresp BVALID master1_bvalid BREADY master1_bready ARID master1_arid ARADDR master1_araddr ARLEN master1_arlen ARSIZE master1_arsize ARBURST master1_arburst ARLOCK master1_arlock ARCACHE master1_arcache ARPROT master1_arprot ARREGION master1_arregion ARQOS master1_arqos ARVALID master1_arvalid ARREADY master1_arready RID master1_rid RDATA master1_rdata RRESP master1_rresp RLAST master1_rlast RVALID master1_rvalid RREADY master1_rready RST_N RST RST_N POLARITY ACTIVE_LOW CLK CLK CLK ASSOCIATED_BUSIF master0:master1:tv_verifier_info_tx ASSOCIATED_RESET RST_N tv_verifier_info_tx TDATA tv_verifier_info_tx_tdata TSTRB tv_verifier_info_tx_tstrb TKEEP tv_verifier_info_tx_tkeep TLAST tv_verifier_info_tx_tlast TVALID tv_verifier_info_tx_tvalid TREADY tv_verifier_info_tx_tready master0 16777216T 64 master1 16777216T 64 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog mkP2_Core xilinx_anylanguagesynthesis_view_fileset viewChecksum 073ddeff xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog mkP2_Core xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum a38db3fe xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 CLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation RST_N in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awaddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awcache out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_wvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_wid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_wdata out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_wstrb out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_wlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_bid in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_bready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_araddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arcache out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master0_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_rid in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master0_rready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awaddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awcache out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_wvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_wid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_wdata out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_wstrb out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_wlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_bid in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_bready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_araddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arcache out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation master1_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_rid in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 master1_rready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cpu_external_interrupt_req in 15 0 std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tv_verifier_info_tx_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tv_verifier_info_tx_tdata out 607 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tv_verifier_info_tx_tstrb out 75 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tv_verifier_info_tx_tkeep out 75 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tv_verifier_info_tx_tlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tv_verifier_info_tx_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 jtag_tdi in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation jtag_tms in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation jtag_tclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation jtag_tdo out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation CLK_jtag_tclk_out out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation CLK_GATE_jtag_tclk_out out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset src/p2_constraints.xdc xdc USED_IN_implementation USED_IN_synthesis hdl/BRAM2.v verilogSource hdl/FIFO1.v verilogSource hdl/FIFO2.v verilogSource hdl/FIFO20.v verilogSource hdl/MakeClock.v verilogSource hdl/RegFile.v verilogSource hdl/SizedFIFO.v verilogSource hdl/SizedFIFO0.v verilogSource hdl/SyncFIFOLevel.v verilogSource hdl/SyncHandshake.v verilogSource hdl/SyncResetA.v verilogSource hdl/mkBranch_Predictor.v verilogSource hdl/mkCPU.v verilogSource hdl/mkCSR_MIE.v verilogSource hdl/mkCSR_MIP.v verilogSource hdl/mkCSR_RegFile.v verilogSource hdl/mkCore.v verilogSource hdl/mkDM_Abstract_Commands.v verilogSource hdl/mkDM_Run_Control.v verilogSource hdl/mkDM_System_Bus.v verilogSource hdl/mkDebug_Module.v verilogSource hdl/mkGPR_RegFile.v verilogSource hdl/mkJtagTap.v verilogSource hdl/mkMMU_Cache.v verilogSource hdl/mkNear_Mem.v verilogSource hdl/mkRISCV_MBox.v verilogSource hdl/mkSoC_Map.v verilogSource hdl/mkTLB.v verilogSource hdl/mkP2_Core.v verilogSource CHECKSUM_d463a775 hdl/mkDM_Mem_Tap.v verilogSource xil_defaultlib hdl/mkIntMul_32.v verilogSource hdl/mkDM_CSR_Tap.v verilogSource xil_defaultlib hdl/mkTV_Encode.v verilogSource xil_defaultlib hdl/ClockGen.v verilogSource hdl/mkDM_GPR_Tap.v verilogSource xil_defaultlib hdl/mkTV_Xactor.v verilogSource xil_defaultlib hdl/mkIntMul_64.v verilogSource hdl/mkFabric_2x3.v verilogSource hdl/mkNear_Mem_IO_AXI4.v verilogSource hdl/mkPLIC_16_2_7.v verilogSource hdl/mkFBox_Core.v verilogSource hdl/mkFBox_Top.v verilogSource hdl/mkFPR_RegFile.v verilogSource hdl/mkFPU.v verilogSource hdl/FIFOL1.v verilogSource CHECKSUM_bfe3b3df xilinx_anylanguagebehavioralsimulation_view_fileset hdl/BRAM2.v verilogSource hdl/FIFO1.v verilogSource hdl/FIFO2.v verilogSource hdl/FIFO20.v verilogSource hdl/MakeClock.v verilogSource hdl/RegFile.v verilogSource hdl/SizedFIFO.v verilogSource hdl/SizedFIFO0.v verilogSource hdl/SyncFIFOLevel.v verilogSource hdl/SyncHandshake.v verilogSource hdl/SyncResetA.v verilogSource hdl/mkBranch_Predictor.v verilogSource hdl/mkCPU.v verilogSource hdl/mkCSR_MIE.v verilogSource hdl/mkCSR_MIP.v verilogSource hdl/mkCSR_RegFile.v verilogSource hdl/mkCore.v verilogSource hdl/mkDM_Abstract_Commands.v verilogSource hdl/mkDM_Run_Control.v verilogSource hdl/mkDM_System_Bus.v verilogSource hdl/mkDebug_Module.v verilogSource hdl/mkGPR_RegFile.v verilogSource hdl/mkJtagTap.v verilogSource hdl/mkMMU_Cache.v verilogSource hdl/mkNear_Mem.v verilogSource hdl/mkRISCV_MBox.v verilogSource hdl/mkSoC_Map.v verilogSource hdl/mkTLB.v verilogSource hdl/mkP2_Core.v verilogSource hdl/ClockGen.v verilogSource hdl/mkFabric_2x3.v verilogSource hdl/mkIntMul_32.v verilogSource hdl/mkIntMul_64.v verilogSource hdl/mkNear_Mem_IO_AXI4.v verilogSource hdl/mkPLIC_16_2_7.v verilogSource hdl/mkFBox_Core.v verilogSource hdl/mkFBox_Top.v verilogSource hdl/mkFPR_RegFile.v verilogSource hdl/mkFPU.v verilogSource hdl/FIFOL1.v verilogSource xilinx_xpgui_view_fileset xgui/ssith_processor_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 mkP2_Core_v1_0 Component_Name mkP2_Core_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu virtexuplus kintexuplus zynquplus kintexu /UserIP mkP2_Core_v1_0 package_project 6 2019-03-16T16:37:14Z /export/home/stoy/examples/galois/gfe1/bluespec-processors/P2/Flute/src_SSITH_P2/xilinx_ip 2017.4