// // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // // // Ports: // Name I/O size props // RDY_server_reset_request_put O 1 reg // RDY_server_reset_response_get O 1 // read_csr O 65 // read_csr_port2 O 65 // mav_read_csr O 65 // mav_csr_write O 64 // read_frm O 3 reg // read_misa O 28 const // read_mstatus O 64 reg // read_sstatus O 64 // read_ustatus O 64 // read_satp O 64 reg // csr_trap_actions O 194 // RDY_csr_trap_actions O 1 const // csr_ret_actions O 130 // RDY_csr_ret_actions O 1 const // read_csr_minstret O 64 reg // read_csr_mcycle O 64 reg // read_csr_mtime O 64 reg // access_permitted_1 O 1 // access_permitted_2 O 1 // csr_counter_read_fault O 1 // csr_mip_read O 64 // interrupt_pending O 5 // wfi_resume O 1 // read_dpc O 64 reg // RDY_read_dpc O 1 const // RDY_write_dpc O 1 const // dcsr_break_enters_debug O 1 // RDY_dcsr_break_enters_debug O 1 const // read_dcsr_step O 1 reg // RDY_read_dcsr_step O 1 const // RDY_debug O 1 const // CLK I 1 clock // RST_N I 1 reset // read_csr_csr_addr I 12 // read_csr_port2_csr_addr I 12 // mav_read_csr_csr_addr I 12 // mav_csr_write_csr_addr I 12 // mav_csr_write_word I 64 // ma_update_fcsr_fflags_flags I 5 // ma_update_mstatus_fs_fs I 2 // csr_trap_actions_from_priv I 2 // csr_trap_actions_pc I 64 // csr_trap_actions_interrupt I 1 // csr_trap_actions_exc_code I 4 // csr_trap_actions_xtval I 64 // csr_ret_actions_from_priv I 2 // access_permitted_1_priv I 2 // access_permitted_1_csr_addr I 12 // access_permitted_1_read_not_write I 1 // access_permitted_2_priv I 2 // access_permitted_2_csr_addr I 12 // access_permitted_2_read_not_write I 1 // csr_counter_read_fault_priv I 2 // csr_counter_read_fault_csr_addr I 12 // m_external_interrupt_req_set_not_clear I 1 reg // s_external_interrupt_req_set_not_clear I 1 reg // timer_interrupt_req_set_not_clear I 1 reg // software_interrupt_req_set_not_clear I 1 reg // interrupt_pending_cur_priv I 2 // write_dpc_pc I 64 // dcsr_break_enters_debug_cur_priv I 2 // write_dcsr_cause_priv_cause I 3 // write_dcsr_cause_priv_priv I 2 // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_ma_update_fcsr_fflags I 1 // EN_ma_update_mstatus_fs I 1 // EN_csr_minstret_incr I 1 // EN_write_dpc I 1 // EN_write_dcsr_cause_priv I 1 // EN_debug I 1 unused // EN_mav_read_csr I 1 unused // EN_mav_csr_write I 1 // EN_csr_trap_actions I 1 // EN_csr_ret_actions I 1 // // Combinational paths from inputs to outputs: // read_csr_csr_addr -> read_csr // read_csr_port2_csr_addr -> read_csr_port2 // (access_permitted_1_priv, // access_permitted_1_csr_addr, // access_permitted_1_read_not_write) -> access_permitted_1 // (access_permitted_2_priv, // access_permitted_2_csr_addr, // access_permitted_2_read_not_write) -> access_permitted_2 // (csr_counter_read_fault_priv, // csr_counter_read_fault_csr_addr) -> csr_counter_read_fault // interrupt_pending_cur_priv -> interrupt_pending // dcsr_break_enters_debug_cur_priv -> dcsr_break_enters_debug // mav_read_csr_csr_addr -> mav_read_csr // (mav_csr_write_csr_addr, // mav_csr_write_word, // EN_mav_csr_write) -> mav_csr_write // (csr_trap_actions_from_priv, // csr_trap_actions_interrupt, // csr_trap_actions_exc_code) -> csr_trap_actions // csr_ret_actions_from_priv -> csr_ret_actions // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkCSR_RegFile(CLK, RST_N, EN_server_reset_request_put, RDY_server_reset_request_put, EN_server_reset_response_get, RDY_server_reset_response_get, read_csr_csr_addr, read_csr, read_csr_port2_csr_addr, read_csr_port2, mav_read_csr_csr_addr, EN_mav_read_csr, mav_read_csr, mav_csr_write_csr_addr, mav_csr_write_word, EN_mav_csr_write, mav_csr_write, read_frm, ma_update_fcsr_fflags_flags, EN_ma_update_fcsr_fflags, ma_update_mstatus_fs_fs, EN_ma_update_mstatus_fs, read_misa, read_mstatus, read_sstatus, read_ustatus, read_satp, csr_trap_actions_from_priv, csr_trap_actions_pc, csr_trap_actions_interrupt, csr_trap_actions_exc_code, csr_trap_actions_xtval, EN_csr_trap_actions, csr_trap_actions, RDY_csr_trap_actions, csr_ret_actions_from_priv, EN_csr_ret_actions, csr_ret_actions, RDY_csr_ret_actions, read_csr_minstret, EN_csr_minstret_incr, read_csr_mcycle, read_csr_mtime, access_permitted_1_priv, access_permitted_1_csr_addr, access_permitted_1_read_not_write, access_permitted_1, access_permitted_2_priv, access_permitted_2_csr_addr, access_permitted_2_read_not_write, access_permitted_2, csr_counter_read_fault_priv, csr_counter_read_fault_csr_addr, csr_counter_read_fault, csr_mip_read, m_external_interrupt_req_set_not_clear, s_external_interrupt_req_set_not_clear, timer_interrupt_req_set_not_clear, software_interrupt_req_set_not_clear, interrupt_pending_cur_priv, interrupt_pending, wfi_resume, read_dpc, RDY_read_dpc, write_dpc_pc, EN_write_dpc, RDY_write_dpc, dcsr_break_enters_debug_cur_priv, dcsr_break_enters_debug, RDY_dcsr_break_enters_debug, read_dcsr_step, RDY_read_dcsr_step, write_dcsr_cause_priv_cause, write_dcsr_cause_priv_priv, EN_write_dcsr_cause_priv, EN_debug, RDY_debug); input CLK; input RST_N; // action method server_reset_request_put input EN_server_reset_request_put; output RDY_server_reset_request_put; // action method server_reset_response_get input EN_server_reset_response_get; output RDY_server_reset_response_get; // value method read_csr input [11 : 0] read_csr_csr_addr; output [64 : 0] read_csr; // value method read_csr_port2 input [11 : 0] read_csr_port2_csr_addr; output [64 : 0] read_csr_port2; // actionvalue method mav_read_csr input [11 : 0] mav_read_csr_csr_addr; input EN_mav_read_csr; output [64 : 0] mav_read_csr; // actionvalue method mav_csr_write input [11 : 0] mav_csr_write_csr_addr; input [63 : 0] mav_csr_write_word; input EN_mav_csr_write; output [63 : 0] mav_csr_write; // value method read_frm output [2 : 0] read_frm; // action method ma_update_fcsr_fflags input [4 : 0] ma_update_fcsr_fflags_flags; input EN_ma_update_fcsr_fflags; // action method ma_update_mstatus_fs input [1 : 0] ma_update_mstatus_fs_fs; input EN_ma_update_mstatus_fs; // value method read_misa output [27 : 0] read_misa; // value method read_mstatus output [63 : 0] read_mstatus; // value method read_sstatus output [63 : 0] read_sstatus; // value method read_ustatus output [63 : 0] read_ustatus; // value method read_satp output [63 : 0] read_satp; // actionvalue method csr_trap_actions input [1 : 0] csr_trap_actions_from_priv; input [63 : 0] csr_trap_actions_pc; input csr_trap_actions_interrupt; input [3 : 0] csr_trap_actions_exc_code; input [63 : 0] csr_trap_actions_xtval; input EN_csr_trap_actions; output [193 : 0] csr_trap_actions; output RDY_csr_trap_actions; // actionvalue method csr_ret_actions input [1 : 0] csr_ret_actions_from_priv; input EN_csr_ret_actions; output [129 : 0] csr_ret_actions; output RDY_csr_ret_actions; // value method read_csr_minstret output [63 : 0] read_csr_minstret; // action method csr_minstret_incr input EN_csr_minstret_incr; // value method read_csr_mcycle output [63 : 0] read_csr_mcycle; // value method read_csr_mtime output [63 : 0] read_csr_mtime; // value method access_permitted_1 input [1 : 0] access_permitted_1_priv; input [11 : 0] access_permitted_1_csr_addr; input access_permitted_1_read_not_write; output access_permitted_1; // value method access_permitted_2 input [1 : 0] access_permitted_2_priv; input [11 : 0] access_permitted_2_csr_addr; input access_permitted_2_read_not_write; output access_permitted_2; // value method csr_counter_read_fault input [1 : 0] csr_counter_read_fault_priv; input [11 : 0] csr_counter_read_fault_csr_addr; output csr_counter_read_fault; // value method csr_mip_read output [63 : 0] csr_mip_read; // action method m_external_interrupt_req input m_external_interrupt_req_set_not_clear; // action method s_external_interrupt_req input s_external_interrupt_req_set_not_clear; // action method timer_interrupt_req input timer_interrupt_req_set_not_clear; // action method software_interrupt_req input software_interrupt_req_set_not_clear; // value method interrupt_pending input [1 : 0] interrupt_pending_cur_priv; output [4 : 0] interrupt_pending; // value method wfi_resume output wfi_resume; // value method read_dpc output [63 : 0] read_dpc; output RDY_read_dpc; // action method write_dpc input [63 : 0] write_dpc_pc; input EN_write_dpc; output RDY_write_dpc; // value method dcsr_break_enters_debug input [1 : 0] dcsr_break_enters_debug_cur_priv; output dcsr_break_enters_debug; output RDY_dcsr_break_enters_debug; // value method read_dcsr_step output read_dcsr_step; output RDY_read_dcsr_step; // action method write_dcsr_cause_priv input [2 : 0] write_dcsr_cause_priv_cause; input [1 : 0] write_dcsr_cause_priv_priv; input EN_write_dcsr_cause_priv; // action method debug input EN_debug; output RDY_debug; // signals for module outputs reg dcsr_break_enters_debug; wire [193 : 0] csr_trap_actions; wire [129 : 0] csr_ret_actions; wire [64 : 0] mav_read_csr, read_csr, read_csr_port2; wire [63 : 0] csr_mip_read, mav_csr_write, read_csr_mcycle, read_csr_minstret, read_csr_mtime, read_dpc, read_mstatus, read_satp, read_sstatus, read_ustatus; wire [27 : 0] read_misa; wire [4 : 0] interrupt_pending; wire [2 : 0] read_frm; wire RDY_csr_ret_actions, RDY_csr_trap_actions, RDY_dcsr_break_enters_debug, RDY_debug, RDY_read_dcsr_step, RDY_read_dpc, RDY_server_reset_request_put, RDY_server_reset_response_get, RDY_write_dpc, access_permitted_1, access_permitted_2, csr_counter_read_fault, read_dcsr_step, wfi_resume; // register cfg_verbosity reg [3 : 0] cfg_verbosity; wire [3 : 0] cfg_verbosity$D_IN; wire cfg_verbosity$EN; // register csr_mstatus_rg_mstatus reg [63 : 0] csr_mstatus_rg_mstatus; reg [63 : 0] csr_mstatus_rg_mstatus$D_IN; wire csr_mstatus_rg_mstatus$EN; // register rg_dcsr reg [31 : 0] rg_dcsr; reg [31 : 0] rg_dcsr$D_IN; wire rg_dcsr$EN; // register rg_dpc reg [63 : 0] rg_dpc; reg [63 : 0] rg_dpc$D_IN; wire rg_dpc$EN; // register rg_dscratch0 reg [63 : 0] rg_dscratch0; wire [63 : 0] rg_dscratch0$D_IN; wire rg_dscratch0$EN; // register rg_dscratch1 reg [63 : 0] rg_dscratch1; wire [63 : 0] rg_dscratch1$D_IN; wire rg_dscratch1$EN; // register rg_fflags reg [4 : 0] rg_fflags; reg [4 : 0] rg_fflags$D_IN; wire rg_fflags$EN; // register rg_frm reg [2 : 0] rg_frm; wire [2 : 0] rg_frm$D_IN; wire rg_frm$EN; // register rg_mcause reg [4 : 0] rg_mcause; reg [4 : 0] rg_mcause$D_IN; wire rg_mcause$EN; // register rg_mcounteren reg [2 : 0] rg_mcounteren; wire [2 : 0] rg_mcounteren$D_IN; wire rg_mcounteren$EN; // register rg_mcycle reg [63 : 0] rg_mcycle; wire [63 : 0] rg_mcycle$D_IN; wire rg_mcycle$EN; // register rg_medeleg reg [15 : 0] rg_medeleg; wire [15 : 0] rg_medeleg$D_IN; wire rg_medeleg$EN; // register rg_mepc reg [63 : 0] rg_mepc; wire [63 : 0] rg_mepc$D_IN; wire rg_mepc$EN; // register rg_mideleg reg [11 : 0] rg_mideleg; wire [11 : 0] rg_mideleg$D_IN; wire rg_mideleg$EN; // register rg_minstret reg [63 : 0] rg_minstret; wire [63 : 0] rg_minstret$D_IN; wire rg_minstret$EN; // register rg_mscratch reg [63 : 0] rg_mscratch; wire [63 : 0] rg_mscratch$D_IN; wire rg_mscratch$EN; // register rg_mtval reg [63 : 0] rg_mtval; wire [63 : 0] rg_mtval$D_IN; wire rg_mtval$EN; // register rg_mtvec reg [62 : 0] rg_mtvec; wire [62 : 0] rg_mtvec$D_IN; wire rg_mtvec$EN; // register rg_satp reg [63 : 0] rg_satp; wire [63 : 0] rg_satp$D_IN; wire rg_satp$EN; // register rg_scause reg [4 : 0] rg_scause; reg [4 : 0] rg_scause$D_IN; wire rg_scause$EN; // register rg_sepc reg [63 : 0] rg_sepc; wire [63 : 0] rg_sepc$D_IN; wire rg_sepc$EN; // register rg_sscratch reg [63 : 0] rg_sscratch; wire [63 : 0] rg_sscratch$D_IN; wire rg_sscratch$EN; // register rg_state reg rg_state; wire rg_state$D_IN, rg_state$EN; // register rg_stval reg [63 : 0] rg_stval; wire [63 : 0] rg_stval$D_IN; wire rg_stval$EN; // register rg_stvec reg [62 : 0] rg_stvec; wire [62 : 0] rg_stvec$D_IN; wire rg_stvec$EN; // register rg_tdata1 reg [63 : 0] rg_tdata1; wire [63 : 0] rg_tdata1$D_IN; wire rg_tdata1$EN; // register rg_tdata2 reg [63 : 0] rg_tdata2; wire [63 : 0] rg_tdata2$D_IN; wire rg_tdata2$EN; // register rg_tdata3 reg [63 : 0] rg_tdata3; wire [63 : 0] rg_tdata3$D_IN; wire rg_tdata3$EN; // register rg_tselect reg [63 : 0] rg_tselect; wire [63 : 0] rg_tselect$D_IN; wire rg_tselect$EN; // ports of submodule csr_mie wire [63 : 0] csr_mie$fav_sie_write, csr_mie$fav_sie_write_wordxl, csr_mie$fav_write, csr_mie$fav_write_wordxl, csr_mie$fv_read, csr_mie$fv_sie_read; wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa; wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset; // ports of submodule csr_mip wire [63 : 0] csr_mip$fav_sip_write, csr_mip$fav_sip_write_wordxl, csr_mip$fav_write, csr_mip$fav_write_wordxl, csr_mip$fv_read, csr_mip$fv_sip_read; wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa; wire csr_mip$EN_fav_sip_write, csr_mip$EN_fav_write, csr_mip$EN_reset, csr_mip$m_external_interrupt_req_req, csr_mip$s_external_interrupt_req_req, csr_mip$software_interrupt_req_req, csr_mip$timer_interrupt_req_req; // ports of submodule f_reset_rsps wire f_reset_rsps$CLR, f_reset_rsps$DEQ, f_reset_rsps$EMPTY_N, f_reset_rsps$ENQ, f_reset_rsps$FULL_N; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr, soc_map$m_mtvec_reset_value, soc_map$m_pc_reset_value; // rule scheduling signals wire CAN_FIRE_RL_rl_mcycle_incr, CAN_FIRE_RL_rl_reset_start, CAN_FIRE_RL_rl_upd_minstret_csrrx, CAN_FIRE_RL_rl_upd_minstret_incr, CAN_FIRE_csr_minstret_incr, CAN_FIRE_csr_ret_actions, CAN_FIRE_csr_trap_actions, CAN_FIRE_debug, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_ma_update_fcsr_fflags, CAN_FIRE_ma_update_mstatus_fs, CAN_FIRE_mav_csr_write, CAN_FIRE_mav_read_csr, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_server_reset_request_put, CAN_FIRE_server_reset_response_get, CAN_FIRE_software_interrupt_req, CAN_FIRE_timer_interrupt_req, CAN_FIRE_write_dcsr_cause_priv, CAN_FIRE_write_dpc, WILL_FIRE_RL_rl_mcycle_incr, WILL_FIRE_RL_rl_reset_start, WILL_FIRE_RL_rl_upd_minstret_csrrx, WILL_FIRE_RL_rl_upd_minstret_incr, WILL_FIRE_csr_minstret_incr, WILL_FIRE_csr_ret_actions, WILL_FIRE_csr_trap_actions, WILL_FIRE_debug, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_ma_update_fcsr_fflags, WILL_FIRE_ma_update_mstatus_fs, WILL_FIRE_mav_csr_write, WILL_FIRE_mav_read_csr, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_server_reset_request_put, WILL_FIRE_server_reset_response_get, WILL_FIRE_software_interrupt_req, WILL_FIRE_timer_interrupt_req, WILL_FIRE_write_dcsr_cause_priv, WILL_FIRE_write_dpc; // inputs to muxes for submodule ports wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2, MUX_csr_mstatus_rg_mstatus$write_1__VAL_4, MUX_csr_mstatus_rg_mstatus$write_1__VAL_5, MUX_rg_minstret$write_1__VAL_1, MUX_rg_minstret$write_1__VAL_2; wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; wire [31 : 0] MUX_rg_dcsr$write_1__VAL_3; wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1; wire [4 : 0] MUX_rg_fflags$write_1__VAL_3, MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3; wire [2 : 0] MUX_rg_frm$write_1__VAL_1; wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5, MUX_rg_dcsr$write_1__SEL_2, MUX_rg_dpc$write_1__SEL_2, MUX_rg_fflags$write_1__SEL_2, MUX_rg_frm$write_1__SEL_1, MUX_rg_mcause$write_1__SEL_2, MUX_rg_mcause$write_1__SEL_3, MUX_rg_mcounteren$write_1__SEL_1, MUX_rg_medeleg$write_1__SEL_1, MUX_rg_mideleg$write_1__SEL_1, MUX_rg_mtvec$write_1__SEL_1, MUX_rg_satp$write_1__SEL_1, MUX_rg_scause$write_1__SEL_3, MUX_rg_sepc$write_1__SEL_1, MUX_rg_state$write_1__SEL_2, MUX_rg_stvec$write_1__SEL_1, MUX_rg_tdata1$write_1__SEL_1, MUX_rw_minstret$wset_1__SEL_1; // remaining internal signals reg [63 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796, IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316, IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556, x__h13817, y_avValue_fst__h9989; reg [61 : 0] CASE_new_priv1818_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1; reg CASE_new_priv1818_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2, IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840, IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943; wire [63 : 0] IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366, IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559, _theResult___fst__h13973, _theResult___fst__h14174, csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552, csr_mstatus_rg_mstatus_19_AND_INV_1_SL_1_CONCA_ETC___d1358, exc_pc___1__h12968, exc_pc__h12901, mask__h12026, mask__h12043, mask__h13994, mask__h14011, v__h11823, v__h6024, v__h6168, v__h6282, v__h7660, v__h7696, v__h8366, v__h8428, v__h8584, v__h9354, val__h12027, val__h12044, val__h14012, vector_offset__h12902, wordxl1__h7791, x__h10796, x__h12025, x__h12038, x__h12055, x__h13818, x__h13993, x__h14006, x__h14023, y__h12039, y__h12056, y__h14007, y__h14024, y_avValue_fst__h12874; wire [31 : 0] new_dcsr__h9357; wire [22 : 0] fixed_up_val_23__h10209, fixed_up_val_23__h11867, fixed_up_val_23__h13880, fixed_up_val_23__h6333, fixed_up_val_23__h7832; wire [5 : 0] ie_from_x__h13957, ie_to_x__h11944, pie_from_x__h13958, pie_to_x__h11945; wire [3 : 0] IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2021, IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2023, IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2024, IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2026; wire [1 : 0] IF_csr_mstatus_rg_mstatus_19_BITS_12_TO_11_37__ETC___d839, _theResult____h15604, _theResult____h15816, _theResult____h16028, _theResult____h16240, _theResult____h16452, _theResult____h16664, _theResult____h16876, _theResult____h17088, _theResult____h17300, _theResult___fst__h11956, new_priv__h11818, to_y__h14173; wire NOT_access_permitted_1_csr_addr_ULT_0xC03_580__ETC___d1688, NOT_access_permitted_2_csr_addr_ULT_0xC03_693__ETC___d1799, NOT_cfg_verbosity_read__029_ULE_1_030_031_AND__ETC___d1486, NOT_cfg_verbosity_read__029_ULE_1_030_031_AND__ETC___d1536, NOT_cfg_verbosity_read__029_ULE_1_030___d1031, NOT_csr_mip_fv_read__69_BIT_0_910_001_OR_NOT_c_ETC___d2008, NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1946, NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1973, NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d2000, NOT_csr_mip_fv_read__69_BIT_1_877_974_OR_NOT_c_ETC___d1981, NOT_csr_mip_fv_read__69_BIT_3_844_947_OR_NOT_c_ETC___d1954, NOT_csr_mip_fv_read__69_BIT_5_888_983_OR_NOT_c_ETC___d1990, NOT_csr_mip_fv_read__69_BIT_7_855_956_OR_NOT_c_ETC___d1963, NOT_csr_mip_fv_read__69_BIT_8_899_992_OR_NOT_c_ETC___d1999, NOT_csr_mip_fv_read__69_BIT_9_866_965_OR_NOT_c_ETC___d1972, b__h12042, b__h14010, csr_mip_fv_read__69_BIT_0_910_AND_csr_mie_fv_r_ETC___d1919, csr_mip_fv_read__69_BIT_11_826_AND_csr_mie_fv__ETC___d1843, csr_mip_fv_read__69_BIT_11_826_AND_csr_mie_fv__ETC___d1909, csr_mip_fv_read__69_BIT_1_877_AND_csr_mie_fv_r_ETC___d1886, csr_mip_fv_read__69_BIT_3_844_AND_csr_mie_fv_r_ETC___d1853, csr_mip_fv_read__69_BIT_4_921_AND_csr_mie_fv_r_ETC___d1930, csr_mip_fv_read__69_BIT_5_888_AND_csr_mie_fv_r_ETC___d1897, csr_mip_fv_read__69_BIT_7_855_AND_csr_mie_fv_r_ETC___d1864, csr_mip_fv_read__69_BIT_8_899_AND_csr_mie_fv_r_ETC___d1908, csr_mip_fv_read__69_BIT_9_866_AND_csr_mie_fv_r_ETC___d1875, deleg_bit___1__h11965, deleg_bit___1__h11980, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1832, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1850, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1861, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1872, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1883, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1894, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1905, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1916, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1831, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1849, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1860, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1871, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1882, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1893, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1904, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1915, mav_csr_write_csr_addr_ULE_0x33F___d804, mav_csr_write_csr_addr_ULE_0xB1F___d800, mav_csr_write_csr_addr_ULT_0x323_03_OR_NOT_mav_ETC___d1027, mav_csr_write_csr_addr_ULT_0x323___d803, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d811, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d817, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d829, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d866, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d868, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d873, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d875, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d877, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d882, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d884, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d886, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d888, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d895, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d898, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d900, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d902, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d904, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d906, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d908, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d910, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d912, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d916, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d918, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d920, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d922, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d924, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d926, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d936, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d938, mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d940, mav_csr_write_csr_addr_ULT_0xB03___d799, sd__h10208, sd__h11866, sd__h13879, sd__h7831; // action method server_reset_request_put assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; // action method server_reset_response_get assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; assign CAN_FIRE_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; // value method read_csr assign read_csr = { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || read_csr_csr_addr == 12'h001 || read_csr_csr_addr == 12'h002 || read_csr_csr_addr == 12'h003 || read_csr_csr_addr == 12'hC00 || read_csr_csr_addr == 12'hC02 || read_csr_csr_addr == 12'h100 || read_csr_csr_addr == 12'h102 || read_csr_csr_addr == 12'h103 || read_csr_csr_addr == 12'h104 || read_csr_csr_addr == 12'h105 || read_csr_csr_addr == 12'h106 || read_csr_csr_addr == 12'h140 || read_csr_csr_addr == 12'h141 || read_csr_csr_addr == 12'h142 || read_csr_csr_addr == 12'h143 || read_csr_csr_addr == 12'h144 || read_csr_csr_addr == 12'h180 || read_csr_csr_addr == 12'h302 || read_csr_csr_addr == 12'h303 || read_csr_csr_addr == 12'hF11 || read_csr_csr_addr == 12'hF12 || read_csr_csr_addr == 12'hF13 || read_csr_csr_addr == 12'hF14 || read_csr_csr_addr == 12'h300 || read_csr_csr_addr == 12'h301 || read_csr_csr_addr == 12'h304 || read_csr_csr_addr == 12'h305 || read_csr_csr_addr == 12'h306 || read_csr_csr_addr == 12'h340 || read_csr_csr_addr == 12'h341 || read_csr_csr_addr == 12'h342 || read_csr_csr_addr == 12'h343 || read_csr_csr_addr == 12'h344 || read_csr_csr_addr == 12'hB00 || read_csr_csr_addr == 12'hB02 || read_csr_csr_addr == 12'h7A0 || read_csr_csr_addr == 12'h7A1 || read_csr_csr_addr == 12'h7A2 || read_csr_csr_addr == 12'h7A3 || read_csr_csr_addr == 12'h7B0 || read_csr_csr_addr == 12'h7B1 || read_csr_csr_addr == 12'h7B2 || read_csr_csr_addr == 12'h7B3, (read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F) ? 64'd0 : IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 } ; // value method read_csr_port2 assign read_csr_port2 = { read_csr_port2_csr_addr >= 12'hC03 && read_csr_port2_csr_addr <= 12'hC1F || read_csr_port2_csr_addr >= 12'hB03 && read_csr_port2_csr_addr <= 12'hB1F || read_csr_port2_csr_addr >= 12'h323 && read_csr_port2_csr_addr <= 12'h33F || read_csr_port2_csr_addr == 12'h001 || read_csr_port2_csr_addr == 12'h002 || read_csr_port2_csr_addr == 12'h003 || read_csr_port2_csr_addr == 12'hC00 || read_csr_port2_csr_addr == 12'hC02 || read_csr_port2_csr_addr == 12'h100 || read_csr_port2_csr_addr == 12'h102 || read_csr_port2_csr_addr == 12'h103 || read_csr_port2_csr_addr == 12'h104 || read_csr_port2_csr_addr == 12'h105 || read_csr_port2_csr_addr == 12'h106 || read_csr_port2_csr_addr == 12'h140 || read_csr_port2_csr_addr == 12'h141 || read_csr_port2_csr_addr == 12'h142 || read_csr_port2_csr_addr == 12'h143 || read_csr_port2_csr_addr == 12'h144 || read_csr_port2_csr_addr == 12'h180 || read_csr_port2_csr_addr == 12'h302 || read_csr_port2_csr_addr == 12'h303 || read_csr_port2_csr_addr == 12'hF11 || read_csr_port2_csr_addr == 12'hF12 || read_csr_port2_csr_addr == 12'hF13 || read_csr_port2_csr_addr == 12'hF14 || read_csr_port2_csr_addr == 12'h300 || read_csr_port2_csr_addr == 12'h301 || read_csr_port2_csr_addr == 12'h304 || read_csr_port2_csr_addr == 12'h305 || read_csr_port2_csr_addr == 12'h306 || read_csr_port2_csr_addr == 12'h340 || read_csr_port2_csr_addr == 12'h341 || read_csr_port2_csr_addr == 12'h342 || read_csr_port2_csr_addr == 12'h343 || read_csr_port2_csr_addr == 12'h344 || read_csr_port2_csr_addr == 12'hB00 || read_csr_port2_csr_addr == 12'hB02 || read_csr_port2_csr_addr == 12'h7A0 || read_csr_port2_csr_addr == 12'h7A1 || read_csr_port2_csr_addr == 12'h7A2 || read_csr_port2_csr_addr == 12'h7A3 || read_csr_port2_csr_addr == 12'h7B0 || read_csr_port2_csr_addr == 12'h7B1 || read_csr_port2_csr_addr == 12'h7B2 || read_csr_port2_csr_addr == 12'h7B3, (read_csr_port2_csr_addr >= 12'hC03 && read_csr_port2_csr_addr <= 12'hC1F || read_csr_port2_csr_addr >= 12'hB03 && read_csr_port2_csr_addr <= 12'hB1F || read_csr_port2_csr_addr >= 12'h323 && read_csr_port2_csr_addr <= 12'h33F) ? 64'd0 : IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 } ; // actionvalue method mav_read_csr assign mav_read_csr = { mav_read_csr_csr_addr >= 12'hC03 && mav_read_csr_csr_addr <= 12'hC1F || mav_read_csr_csr_addr >= 12'hB03 && mav_read_csr_csr_addr <= 12'hB1F || mav_read_csr_csr_addr >= 12'h323 && mav_read_csr_csr_addr <= 12'h33F || mav_read_csr_csr_addr == 12'h001 || mav_read_csr_csr_addr == 12'h002 || mav_read_csr_csr_addr == 12'h003 || mav_read_csr_csr_addr == 12'hC00 || mav_read_csr_csr_addr == 12'hC02 || mav_read_csr_csr_addr == 12'h100 || mav_read_csr_csr_addr == 12'h102 || mav_read_csr_csr_addr == 12'h103 || mav_read_csr_csr_addr == 12'h104 || mav_read_csr_csr_addr == 12'h105 || mav_read_csr_csr_addr == 12'h106 || mav_read_csr_csr_addr == 12'h140 || mav_read_csr_csr_addr == 12'h141 || mav_read_csr_csr_addr == 12'h142 || mav_read_csr_csr_addr == 12'h143 || mav_read_csr_csr_addr == 12'h144 || mav_read_csr_csr_addr == 12'h180 || mav_read_csr_csr_addr == 12'h302 || mav_read_csr_csr_addr == 12'h303 || mav_read_csr_csr_addr == 12'hF11 || mav_read_csr_csr_addr == 12'hF12 || mav_read_csr_csr_addr == 12'hF13 || mav_read_csr_csr_addr == 12'hF14 || mav_read_csr_csr_addr == 12'h300 || mav_read_csr_csr_addr == 12'h301 || mav_read_csr_csr_addr == 12'h304 || mav_read_csr_csr_addr == 12'h305 || mav_read_csr_csr_addr == 12'h306 || mav_read_csr_csr_addr == 12'h340 || mav_read_csr_csr_addr == 12'h341 || mav_read_csr_csr_addr == 12'h342 || mav_read_csr_csr_addr == 12'h343 || mav_read_csr_csr_addr == 12'h344 || mav_read_csr_csr_addr == 12'hB00 || mav_read_csr_csr_addr == 12'hB02 || mav_read_csr_csr_addr == 12'h7A0 || mav_read_csr_csr_addr == 12'h7A1 || mav_read_csr_csr_addr == 12'h7A2 || mav_read_csr_csr_addr == 12'h7A3 || mav_read_csr_csr_addr == 12'h7B0 || mav_read_csr_csr_addr == 12'h7B1 || mav_read_csr_csr_addr == 12'h7B2 || mav_read_csr_csr_addr == 12'h7B3, (mav_read_csr_csr_addr >= 12'hC03 && mav_read_csr_csr_addr <= 12'hC1F || mav_read_csr_csr_addr >= 12'hB03 && mav_read_csr_csr_addr <= 12'hB1F || mav_read_csr_csr_addr >= 12'h323 && mav_read_csr_csr_addr <= 12'h33F) ? 64'd0 : IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 } ; assign CAN_FIRE_mav_read_csr = 1'd1 ; assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; // actionvalue method mav_csr_write assign mav_csr_write = (!mav_csr_write_csr_addr_ULT_0xB03___d799 && mav_csr_write_csr_addr_ULE_0xB1F___d800 || !mav_csr_write_csr_addr_ULT_0x323___d803 && mav_csr_write_csr_addr_ULE_0x33F___d804) ? 64'd0 : y_avValue_fst__h9989 ; assign CAN_FIRE_mav_csr_write = 1'd1 ; assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; // value method read_frm assign read_frm = rg_frm ; // action method ma_update_fcsr_fflags assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ; assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ; // action method ma_update_mstatus_fs assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ; assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ; // value method read_misa assign read_misa = 28'd135532845 ; // value method read_mstatus assign read_mstatus = csr_mstatus_rg_mstatus ; // value method read_sstatus assign read_sstatus = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] } ; // value method read_ustatus assign read_ustatus = { 59'd0, csr_mstatus_rg_mstatus[4], 3'd0, csr_mstatus_rg_mstatus[0] } ; // value method read_satp assign read_satp = rg_satp ; // actionvalue method csr_trap_actions assign csr_trap_actions = { x__h10796, x__h13817, x__h13818, new_priv__h11818 } ; assign RDY_csr_trap_actions = 1'd1 ; assign CAN_FIRE_csr_trap_actions = 1'd1 ; assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; // actionvalue method csr_ret_actions assign csr_ret_actions = (csr_ret_actions_from_priv == 2'b11) ? { rg_mepc, csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552[12:11], _theResult___fst__h13973 } : { rg_sepc, to_y__h14173, _theResult___fst__h14174 } ; assign RDY_csr_ret_actions = 1'd1 ; assign CAN_FIRE_csr_ret_actions = 1'd1 ; assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; // value method read_csr_minstret assign read_csr_minstret = rg_minstret ; // action method csr_minstret_incr assign CAN_FIRE_csr_minstret_incr = 1'd1 ; assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; // value method read_csr_mcycle assign read_csr_mcycle = rg_mcycle ; // value method read_csr_mtime assign read_csr_mtime = rg_mcycle ; // value method access_permitted_1 assign access_permitted_1 = NOT_access_permitted_1_csr_addr_ULT_0xC03_580__ETC___d1688 && (access_permitted_1_read_not_write || access_permitted_1_csr_addr[11:10] != 2'b11) ; // value method access_permitted_2 assign access_permitted_2 = NOT_access_permitted_2_csr_addr_ULT_0xC03_693__ETC___d1799 && (access_permitted_2_read_not_write || access_permitted_2_csr_addr[11:10] != 2'b11) ; // value method csr_counter_read_fault assign csr_counter_read_fault = (csr_counter_read_fault_priv == 2'b01 || csr_counter_read_fault_priv == 2'b0) && (csr_counter_read_fault_csr_addr == 12'hC00 && !rg_mcounteren[0] || csr_counter_read_fault_csr_addr == 12'hC01 && !rg_mcounteren[1] || csr_counter_read_fault_csr_addr == 12'hC02 && !rg_mcounteren[2] || csr_counter_read_fault_csr_addr >= 12'hC03 && csr_counter_read_fault_csr_addr <= 12'hC1F) ; // value method csr_mip_read assign csr_mip_read = csr_mip$fv_read ; // action method m_external_interrupt_req assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; // action method s_external_interrupt_req assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; // action method timer_interrupt_req assign CAN_FIRE_timer_interrupt_req = 1'd1 ; assign WILL_FIRE_timer_interrupt_req = 1'd1 ; // action method software_interrupt_req assign CAN_FIRE_software_interrupt_req = 1'd1 ; assign WILL_FIRE_software_interrupt_req = 1'd1 ; // value method interrupt_pending assign interrupt_pending = { csr_mip_fv_read__69_BIT_11_826_AND_csr_mie_fv__ETC___d1909 || csr_mip_fv_read__69_BIT_0_910_AND_csr_mie_fv_r_ETC___d1919 || csr_mip_fv_read__69_BIT_4_921_AND_csr_mie_fv_r_ETC___d1930, IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2026 } ; // value method wfi_resume assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 64'd0 ; // value method read_dpc assign read_dpc = rg_dpc ; assign RDY_read_dpc = 1'd1 ; // action method write_dpc assign RDY_write_dpc = 1'd1 ; assign CAN_FIRE_write_dpc = 1'd1 ; assign WILL_FIRE_write_dpc = EN_write_dpc ; // value method dcsr_break_enters_debug always@(dcsr_break_enters_debug_cur_priv or rg_dcsr) begin case (dcsr_break_enters_debug_cur_priv) 2'b01: dcsr_break_enters_debug = rg_dcsr[13]; 2'b11: dcsr_break_enters_debug = rg_dcsr[15]; default: dcsr_break_enters_debug = rg_dcsr[12]; endcase end assign RDY_dcsr_break_enters_debug = 1'd1 ; // value method read_dcsr_step assign read_dcsr_step = rg_dcsr[2] ; assign RDY_read_dcsr_step = 1'd1 ; // action method write_dcsr_cause_priv assign CAN_FIRE_write_dcsr_cause_priv = 1'd1 ; assign WILL_FIRE_write_dcsr_cause_priv = EN_write_dcsr_cause_priv ; // action method debug assign RDY_debug = 1'd1 ; assign CAN_FIRE_debug = 1'd1 ; assign WILL_FIRE_debug = EN_debug ; // submodule csr_mie mkCSR_MIE csr_mie(.CLK(CLK), .RST_N(RST_N), .fav_sie_write_misa(csr_mie$fav_sie_write_misa), .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl), .fav_write_misa(csr_mie$fav_write_misa), .fav_write_wordxl(csr_mie$fav_write_wordxl), .EN_reset(csr_mie$EN_reset), .EN_fav_write(csr_mie$EN_fav_write), .EN_fav_sie_write(csr_mie$EN_fav_sie_write), .fv_read(csr_mie$fv_read), .fav_write(csr_mie$fav_write), .fv_sie_read(csr_mie$fv_sie_read), .fav_sie_write(csr_mie$fav_sie_write)); // submodule csr_mip mkCSR_MIP csr_mip(.CLK(CLK), .RST_N(RST_N), .fav_sip_write_misa(csr_mip$fav_sip_write_misa), .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl), .fav_write_misa(csr_mip$fav_write_misa), .fav_write_wordxl(csr_mip$fav_write_wordxl), .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), .software_interrupt_req_req(csr_mip$software_interrupt_req_req), .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), .EN_reset(csr_mip$EN_reset), .EN_fav_write(csr_mip$EN_fav_write), .EN_fav_sip_write(csr_mip$EN_fav_sip_write), .fv_read(csr_mip$fv_read), .fav_write(csr_mip$fav_write), .fv_sip_read(csr_mip$fv_sip_read), .fav_sip_write(csr_mip$fav_sip_write)); // submodule f_reset_rsps FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), .CLK(CLK), .ENQ(f_reset_rsps$ENQ), .DEQ(f_reset_rsps$DEQ), .CLR(f_reset_rsps$CLR), .FULL_N(f_reset_rsps$FULL_N), .EMPTY_N(f_reset_rsps$EMPTY_N)); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), .m_plic_addr_base(), .m_plic_addr_size(), .m_plic_addr_lim(), .m_near_mem_io_addr_base(), .m_near_mem_io_addr_size(), .m_near_mem_io_addr_lim(), .m_flash_mem_addr_base(), .m_flash_mem_addr_size(), .m_flash_mem_addr_lim(), .m_ethernet_0_addr_base(), .m_ethernet_0_addr_size(), .m_ethernet_0_addr_lim(), .m_dma_0_addr_base(), .m_dma_0_addr_size(), .m_dma_0_addr_lim(), .m_uart16550_0_addr_base(), .m_uart16550_0_addr_size(), .m_uart16550_0_addr_lim(), .m_gpio_0_addr_base(), .m_gpio_0_addr_size(), .m_gpio_0_addr_lim(), .m_boot_rom_addr_base(), .m_boot_rom_addr_size(), .m_boot_rom_addr_lim(), .m_ddr4_0_uncached_addr_base(), .m_ddr4_0_uncached_addr_size(), .m_ddr4_0_uncached_addr_lim(), .m_ddr4_0_cached_addr_base(), .m_ddr4_0_cached_addr_size(), .m_ddr4_0_cached_addr_lim(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), .m_pc_reset_value(soc_map$m_pc_reset_value), .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), .m_nmivec_reset_value()); // rule RL_rl_reset_start assign CAN_FIRE_RL_rl_reset_start = !rg_state ; assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; // rule RL_rl_mcycle_incr assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; // rule RL_rl_upd_minstret_csrrx assign CAN_FIRE_RL_rl_upd_minstret_csrrx = MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; assign WILL_FIRE_RL_rl_upd_minstret_csrrx = CAN_FIRE_RL_rl_upd_minstret_csrrx ; // rule RL_rl_upd_minstret_incr assign CAN_FIRE_RL_rl_upd_minstret_incr = !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; assign WILL_FIRE_RL_rl_upd_minstret_incr = CAN_FIRE_RL_rl_upd_minstret_incr ; // inputs to muxes for submodule ports assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d829 ; assign MUX_rg_dcsr$write_1__SEL_2 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d926 ; assign MUX_rg_dpc$write_1__SEL_2 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d936 ; assign MUX_rg_fflags$write_1__SEL_2 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d811 ; assign MUX_rg_frm$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d817 ; assign MUX_rg_mcause$write_1__SEL_2 = EN_csr_trap_actions && new_priv__h11818 == 2'b11 ; assign MUX_rg_mcause$write_1__SEL_3 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d908 ; assign MUX_rg_mcounteren$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d902 ; assign MUX_rg_medeleg$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d888 ; assign MUX_rg_mideleg$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d895 ; assign MUX_rg_mtvec$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d900 ; assign MUX_rg_satp$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d886 ; assign MUX_rg_scause$write_1__SEL_3 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d877 ; assign MUX_rg_sepc$write_1__SEL_1 = EN_csr_trap_actions && new_priv__h11818 == 2'b01 ; assign MUX_rg_state$write_1__SEL_2 = CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; assign MUX_rg_stvec$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d868 ; assign MUX_rg_tdata1$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d920 ; assign MUX_rw_minstret$wset_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d916 ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 = { sd__h13879, 40'd5120, fixed_up_val_23__h13880 } ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 = { sd__h10208, 40'd5120, fixed_up_val_23__h10209 } ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = { sd__h7831, 40'd5120, (mav_csr_write_csr_addr == 12'h100) ? fixed_up_val_23__h6333 : fixed_up_val_23__h7832 } ; assign MUX_rg_dcsr$write_1__VAL_3 = { rg_dcsr[31:9], write_dcsr_cause_priv_cause, rg_dcsr[5:2], write_dcsr_cause_priv_priv } ; assign MUX_rg_fflags$write_1__VAL_3 = rg_fflags | ma_update_fcsr_fflags_flags ; assign MUX_rg_frm$write_1__VAL_1 = (mav_csr_write_csr_addr == 12'h002) ? mav_csr_write_word[2:0] : mav_csr_write_word[7:5] ; assign MUX_rg_mcause$write_1__VAL_2 = { csr_trap_actions_interrupt, csr_trap_actions_exc_code } ; assign MUX_rg_mcause$write_1__VAL_3 = { mav_csr_write_word[63], mav_csr_write_word[3:0] } ; assign MUX_rg_medeleg$write_1__VAL_1 = { mav_csr_write_word[15], 1'd0, mav_csr_write_word[13:12], 2'd0, mav_csr_write_word[9:0] } ; assign MUX_rg_minstret$write_1__VAL_1 = MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ; assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; assign MUX_rg_mtvec$write_1__VAL_1 = { mav_csr_write_word[63:2], mav_csr_write_word[0] } ; assign MUX_rg_mtvec$write_1__VAL_2 = { soc_map$m_mtvec_reset_value[63:2], soc_map$m_mtvec_reset_value[0] } ; // register cfg_verbosity assign cfg_verbosity$D_IN = 4'h0 ; assign cfg_verbosity$EN = 1'b0 ; // register csr_mstatus_rg_mstatus always@(WILL_FIRE_RL_rl_reset_start or EN_csr_ret_actions or MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or EN_csr_trap_actions or v__h11823 or EN_ma_update_mstatus_fs or MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or MUX_csr_mstatus_rg_mstatus$write_1__VAL_5) case (1'b1) WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 64'h0000000A00002000; EN_csr_ret_actions: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_2; EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h11823; EN_ma_update_mstatus_fs: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_4; MUX_csr_mstatus_rg_mstatus$write_1__SEL_5: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; default: csr_mstatus_rg_mstatus$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase assign csr_mstatus_rg_mstatus$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d829 || EN_csr_trap_actions || EN_ma_update_mstatus_fs || EN_csr_ret_actions || WILL_FIRE_RL_rl_reset_start ; // register rg_dcsr always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_dcsr$write_1__SEL_2 or new_dcsr__h9357 or EN_write_dcsr_cause_priv or MUX_rg_dcsr$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_dcsr$D_IN = 32'd1073741843; MUX_rg_dcsr$write_1__SEL_2: rg_dcsr$D_IN = new_dcsr__h9357; EN_write_dcsr_cause_priv: rg_dcsr$D_IN = MUX_rg_dcsr$write_1__VAL_3; default: rg_dcsr$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase assign rg_dcsr$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d926 || EN_write_dcsr_cause_priv || WILL_FIRE_RL_rl_reset_start ; // register rg_dpc always@(WILL_FIRE_RL_rl_reset_start or soc_map$m_pc_reset_value or MUX_rg_dpc$write_1__SEL_2 or mav_csr_write_word or EN_write_dpc or write_dpc_pc) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_dpc$D_IN = soc_map$m_pc_reset_value; MUX_rg_dpc$write_1__SEL_2: rg_dpc$D_IN = mav_csr_write_word; EN_write_dpc: rg_dpc$D_IN = write_dpc_pc; default: rg_dpc$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase assign rg_dpc$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d936 || EN_write_dpc || WILL_FIRE_RL_rl_reset_start ; // register rg_dscratch0 assign rg_dscratch0$D_IN = mav_csr_write_word ; assign rg_dscratch0$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d938 ; // register rg_dscratch1 assign rg_dscratch1$D_IN = mav_csr_write_word ; assign rg_dscratch1$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d940 ; // register rg_fflags always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_fflags$write_1__SEL_2 or mav_csr_write_word or EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0; MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0]; EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3; default: rg_fflags$D_IN = 5'b01010 /* unspecified value */ ; endcase assign rg_fflags$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d811 || EN_ma_update_fcsr_fflags || WILL_FIRE_RL_rl_reset_start ; // register rg_frm assign rg_frm$D_IN = MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ; assign rg_frm$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d817 || WILL_FIRE_RL_rl_reset_start ; // register rg_mcause always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_mcause$write_1__SEL_2 or MUX_rg_mcause$write_1__VAL_2 or MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; MUX_rg_mcause$write_1__SEL_2: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; MUX_rg_mcause$write_1__SEL_3: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; endcase assign rg_mcause$EN = EN_csr_trap_actions && new_priv__h11818 == 2'b11 || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d908 || WILL_FIRE_RL_rl_reset_start ; // register rg_mcounteren assign rg_mcounteren$D_IN = MUX_rg_mcounteren$write_1__SEL_1 ? mav_csr_write_word[2:0] : 3'd0 ; assign rg_mcounteren$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d902 || WILL_FIRE_RL_rl_reset_start ; // register rg_mcycle assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; assign rg_mcycle$EN = 1'd1 ; // register rg_medeleg assign rg_medeleg$D_IN = MUX_rg_medeleg$write_1__SEL_1 ? MUX_rg_medeleg$write_1__VAL_1 : 16'd0 ; assign rg_medeleg$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d888 || WILL_FIRE_RL_rl_reset_start ; // register rg_mepc assign rg_mepc$D_IN = MUX_rg_mcause$write_1__SEL_2 ? csr_trap_actions_pc : mav_csr_write_word ; assign rg_mepc$EN = EN_csr_trap_actions && new_priv__h11818 == 2'b11 || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d906 ; // register rg_mideleg assign rg_mideleg$D_IN = MUX_rg_mideleg$write_1__SEL_1 ? mav_csr_write_word[11:0] : 12'd0 ; assign rg_mideleg$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d895 || WILL_FIRE_RL_rl_reset_start ; // register rg_minstret assign rg_minstret$D_IN = WILL_FIRE_RL_rl_upd_minstret_csrrx ? MUX_rg_minstret$write_1__VAL_1 : MUX_rg_minstret$write_1__VAL_2 ; assign rg_minstret$EN = WILL_FIRE_RL_rl_upd_minstret_csrrx || WILL_FIRE_RL_rl_upd_minstret_incr ; // register rg_mscratch assign rg_mscratch$D_IN = mav_csr_write_word ; assign rg_mscratch$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d904 ; // register rg_mtval assign rg_mtval$D_IN = MUX_rg_mcause$write_1__SEL_2 ? csr_trap_actions_xtval : mav_csr_write_word ; assign rg_mtval$EN = EN_csr_trap_actions && new_priv__h11818 == 2'b11 || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d910 ; // register rg_mtvec assign rg_mtvec$D_IN = MUX_rg_mtvec$write_1__SEL_1 ? MUX_rg_mtvec$write_1__VAL_1 : MUX_rg_mtvec$write_1__VAL_2 ; assign rg_mtvec$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d900 || WILL_FIRE_RL_rl_reset_start ; // register rg_satp assign rg_satp$D_IN = MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 64'd0 ; assign rg_satp$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d886 || WILL_FIRE_RL_rl_reset_start ; // register rg_scause always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_sepc$write_1__SEL_1 or MUX_rg_mcause$write_1__VAL_2 or MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0; MUX_rg_sepc$write_1__SEL_1: rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2; MUX_rg_scause$write_1__SEL_3: rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3; default: rg_scause$D_IN = 5'b01010 /* unspecified value */ ; endcase assign rg_scause$EN = EN_csr_trap_actions && new_priv__h11818 == 2'b01 || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d877 || WILL_FIRE_RL_rl_reset_start ; // register rg_sepc assign rg_sepc$D_IN = MUX_rg_sepc$write_1__SEL_1 ? csr_trap_actions_pc : mav_csr_write_word ; assign rg_sepc$EN = EN_csr_trap_actions && new_priv__h11818 == 2'b01 || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d875 ; // register rg_sscratch assign rg_sscratch$D_IN = mav_csr_write_word ; assign rg_sscratch$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d873 ; // register rg_state assign rg_state$D_IN = !EN_server_reset_request_put ; assign rg_state$EN = EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; // register rg_stval assign rg_stval$D_IN = MUX_rg_sepc$write_1__SEL_1 ? csr_trap_actions_xtval : mav_csr_write_word ; assign rg_stval$EN = EN_csr_trap_actions && new_priv__h11818 == 2'b01 || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d882 ; // register rg_stvec assign rg_stvec$D_IN = MUX_rg_stvec$write_1__SEL_1 ? MUX_rg_mtvec$write_1__VAL_1 : MUX_rg_mtvec$write_1__VAL_2 ; assign rg_stvec$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d868 || WILL_FIRE_RL_rl_reset_start ; // register rg_tdata1 assign rg_tdata1$D_IN = MUX_rg_tdata1$write_1__SEL_1 ? mav_csr_write_word : 64'd0 ; assign rg_tdata1$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d920 || WILL_FIRE_RL_rl_reset_start ; // register rg_tdata2 assign rg_tdata2$D_IN = mav_csr_write_word ; assign rg_tdata2$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d922 ; // register rg_tdata3 assign rg_tdata3$D_IN = mav_csr_write_word ; assign rg_tdata3$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d924 ; // register rg_tselect assign rg_tselect$D_IN = mav_csr_write_word ; assign rg_tselect$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d918 ; // submodule csr_mie assign csr_mie$fav_sie_write_misa = 28'd135532845 ; assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ; assign csr_mie$fav_write_misa = 28'd135532845 ; assign csr_mie$fav_write_wordxl = mav_csr_write_word ; assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; assign csr_mie$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d898 ; assign csr_mie$EN_fav_sie_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d866 ; // submodule csr_mip assign csr_mip$fav_sip_write_misa = 28'd135532845 ; assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ; assign csr_mip$fav_write_misa = 28'd135532845 ; assign csr_mip$fav_write_wordxl = mav_csr_write_word ; assign csr_mip$m_external_interrupt_req_req = m_external_interrupt_req_set_not_clear ; assign csr_mip$s_external_interrupt_req_req = s_external_interrupt_req_set_not_clear ; assign csr_mip$software_interrupt_req_req = software_interrupt_req_set_not_clear ; assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; assign csr_mip$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d912 ; assign csr_mip$EN_fav_sip_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d884 ; // submodule f_reset_rsps assign f_reset_rsps$ENQ = EN_server_reset_request_put ; assign f_reset_rsps$DEQ = EN_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals assign IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366 = (new_priv__h11818 == 2'b11) ? { csr_mstatus_rg_mstatus_19_AND_INV_1_SL_1_CONCA_ETC___d1358[63:13], csr_trap_actions_from_priv, csr_mstatus_rg_mstatus_19_AND_INV_1_SL_1_CONCA_ETC___d1358[10:0] } : { csr_mstatus_rg_mstatus_19_AND_INV_1_SL_1_CONCA_ETC___d1358[63:9], csr_trap_actions_from_priv[0], csr_mstatus_rg_mstatus_19_AND_INV_1_SL_1_CONCA_ETC___d1358[7:0] } ; assign IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2021 = (NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1946 && NOT_csr_mip_fv_read__69_BIT_3_844_947_OR_NOT_c_ETC___d1954 && NOT_csr_mip_fv_read__69_BIT_7_855_956_OR_NOT_c_ETC___d1963) ? 4'd9 : ((NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1946 && NOT_csr_mip_fv_read__69_BIT_3_844_947_OR_NOT_c_ETC___d1954) ? 4'd7 : (NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1946 ? 4'd3 : 4'd11)) ; assign IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2023 = (NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1973 && NOT_csr_mip_fv_read__69_BIT_1_877_974_OR_NOT_c_ETC___d1981) ? 4'd5 : (NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1973 ? 4'd1 : IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2021) ; assign IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2024 = (NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1973 && NOT_csr_mip_fv_read__69_BIT_1_877_974_OR_NOT_c_ETC___d1981 && NOT_csr_mip_fv_read__69_BIT_5_888_983_OR_NOT_c_ETC___d1990) ? 4'd8 : IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2023 ; assign IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2026 = (NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d2000 && NOT_csr_mip_fv_read__69_BIT_0_910_001_OR_NOT_c_ETC___d2008) ? 4'd4 : (NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d2000 ? 4'd0 : IF_NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_N_ETC___d2024) ; assign IF_csr_mstatus_rg_mstatus_19_BITS_12_TO_11_37__ETC___d839 = (csr_mstatus_rg_mstatus[12:11] == 2'b10) ? 2'b01 : csr_mstatus_rg_mstatus[12:11] ; assign IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559 = (csr_ret_actions_from_priv == 2'b11) ? _theResult___fst__h13973 : _theResult___fst__h14174 ; assign NOT_access_permitted_1_csr_addr_ULT_0xC03_580__ETC___d1688 = (access_permitted_1_csr_addr >= 12'hC03 && access_permitted_1_csr_addr <= 12'hC1F || access_permitted_1_csr_addr >= 12'hB03 && access_permitted_1_csr_addr <= 12'hB1F || access_permitted_1_csr_addr >= 12'h323 && access_permitted_1_csr_addr <= 12'h33F || access_permitted_1_csr_addr == 12'h001 || access_permitted_1_csr_addr == 12'h002 || access_permitted_1_csr_addr == 12'h003 || access_permitted_1_csr_addr == 12'hC00 || access_permitted_1_csr_addr == 12'hC02 || access_permitted_1_csr_addr == 12'h100 || access_permitted_1_csr_addr == 12'h102 || access_permitted_1_csr_addr == 12'h103 || access_permitted_1_csr_addr == 12'h104 || access_permitted_1_csr_addr == 12'h105 || access_permitted_1_csr_addr == 12'h106 || access_permitted_1_csr_addr == 12'h140 || access_permitted_1_csr_addr == 12'h141 || access_permitted_1_csr_addr == 12'h142 || access_permitted_1_csr_addr == 12'h143 || access_permitted_1_csr_addr == 12'h144 || access_permitted_1_csr_addr == 12'h180 || access_permitted_1_csr_addr == 12'h302 || access_permitted_1_csr_addr == 12'h303 || access_permitted_1_csr_addr == 12'hF11 || access_permitted_1_csr_addr == 12'hF12 || access_permitted_1_csr_addr == 12'hF13 || access_permitted_1_csr_addr == 12'hF14 || access_permitted_1_csr_addr == 12'h300 || access_permitted_1_csr_addr == 12'h301 || access_permitted_1_csr_addr == 12'h304 || access_permitted_1_csr_addr == 12'h305 || access_permitted_1_csr_addr == 12'h306 || access_permitted_1_csr_addr == 12'h340 || access_permitted_1_csr_addr == 12'h341 || access_permitted_1_csr_addr == 12'h342 || access_permitted_1_csr_addr == 12'h343 || access_permitted_1_csr_addr == 12'h344 || access_permitted_1_csr_addr == 12'hB00 || access_permitted_1_csr_addr == 12'hB02 || access_permitted_1_csr_addr == 12'h7A0 || access_permitted_1_csr_addr == 12'h7A1 || access_permitted_1_csr_addr == 12'h7A2 || access_permitted_1_csr_addr == 12'h7A3 || access_permitted_1_csr_addr == 12'h7B0 || access_permitted_1_csr_addr == 12'h7B1 || access_permitted_1_csr_addr == 12'h7B2 || access_permitted_1_csr_addr == 12'h7B3) && access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && (access_permitted_1_csr_addr != 12'h180 || !csr_mstatus_rg_mstatus[20]) ; assign NOT_access_permitted_2_csr_addr_ULT_0xC03_693__ETC___d1799 = (access_permitted_2_csr_addr >= 12'hC03 && access_permitted_2_csr_addr <= 12'hC1F || access_permitted_2_csr_addr >= 12'hB03 && access_permitted_2_csr_addr <= 12'hB1F || access_permitted_2_csr_addr >= 12'h323 && access_permitted_2_csr_addr <= 12'h33F || access_permitted_2_csr_addr == 12'h001 || access_permitted_2_csr_addr == 12'h002 || access_permitted_2_csr_addr == 12'h003 || access_permitted_2_csr_addr == 12'hC00 || access_permitted_2_csr_addr == 12'hC02 || access_permitted_2_csr_addr == 12'h100 || access_permitted_2_csr_addr == 12'h102 || access_permitted_2_csr_addr == 12'h103 || access_permitted_2_csr_addr == 12'h104 || access_permitted_2_csr_addr == 12'h105 || access_permitted_2_csr_addr == 12'h106 || access_permitted_2_csr_addr == 12'h140 || access_permitted_2_csr_addr == 12'h141 || access_permitted_2_csr_addr == 12'h142 || access_permitted_2_csr_addr == 12'h143 || access_permitted_2_csr_addr == 12'h144 || access_permitted_2_csr_addr == 12'h180 || access_permitted_2_csr_addr == 12'h302 || access_permitted_2_csr_addr == 12'h303 || access_permitted_2_csr_addr == 12'hF11 || access_permitted_2_csr_addr == 12'hF12 || access_permitted_2_csr_addr == 12'hF13 || access_permitted_2_csr_addr == 12'hF14 || access_permitted_2_csr_addr == 12'h300 || access_permitted_2_csr_addr == 12'h301 || access_permitted_2_csr_addr == 12'h304 || access_permitted_2_csr_addr == 12'h305 || access_permitted_2_csr_addr == 12'h306 || access_permitted_2_csr_addr == 12'h340 || access_permitted_2_csr_addr == 12'h341 || access_permitted_2_csr_addr == 12'h342 || access_permitted_2_csr_addr == 12'h343 || access_permitted_2_csr_addr == 12'h344 || access_permitted_2_csr_addr == 12'hB00 || access_permitted_2_csr_addr == 12'hB02 || access_permitted_2_csr_addr == 12'h7A0 || access_permitted_2_csr_addr == 12'h7A1 || access_permitted_2_csr_addr == 12'h7A2 || access_permitted_2_csr_addr == 12'h7A3 || access_permitted_2_csr_addr == 12'h7B0 || access_permitted_2_csr_addr == 12'h7B1 || access_permitted_2_csr_addr == 12'h7B2 || access_permitted_2_csr_addr == 12'h7B3) && access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && (access_permitted_2_csr_addr != 12'h180 || !csr_mstatus_rg_mstatus[20]) ; assign NOT_cfg_verbosity_read__029_ULE_1_030_031_AND__ETC___d1486 = NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code != 4'd0 && csr_trap_actions_exc_code != 4'd1 && csr_trap_actions_exc_code != 4'd2 && csr_trap_actions_exc_code != 4'd3 && csr_trap_actions_exc_code != 4'd4 && csr_trap_actions_exc_code != 4'd5 && csr_trap_actions_exc_code != 4'd6 && csr_trap_actions_exc_code != 4'd7 && csr_trap_actions_exc_code != 4'd8 && csr_trap_actions_exc_code != 4'd9 && csr_trap_actions_exc_code != 4'd10 && csr_trap_actions_exc_code != 4'd11 ; assign NOT_cfg_verbosity_read__029_ULE_1_030_031_AND__ETC___d1536 = NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code != 4'd0 && csr_trap_actions_exc_code != 4'd1 && csr_trap_actions_exc_code != 4'd2 && csr_trap_actions_exc_code != 4'd3 && csr_trap_actions_exc_code != 4'd4 && csr_trap_actions_exc_code != 4'd5 && csr_trap_actions_exc_code != 4'd6 && csr_trap_actions_exc_code != 4'd7 && csr_trap_actions_exc_code != 4'd8 && csr_trap_actions_exc_code != 4'd9 && csr_trap_actions_exc_code != 4'd11 && csr_trap_actions_exc_code != 4'd12 && csr_trap_actions_exc_code != 4'd13 && csr_trap_actions_exc_code != 4'd15 ; assign NOT_cfg_verbosity_read__029_ULE_1_030___d1031 = cfg_verbosity > 4'd1 ; assign NOT_csr_mip_fv_read__69_BIT_0_910_001_OR_NOT_c_ETC___d2008 = !csr_mip$fv_read[0] || !csr_mie$fv_read[0] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1915 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1916 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1946 = !csr_mip$fv_read[11] || !csr_mie$fv_read[11] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1831 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1832 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1973 = NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1946 && NOT_csr_mip_fv_read__69_BIT_3_844_947_OR_NOT_c_ETC___d1954 && NOT_csr_mip_fv_read__69_BIT_7_855_956_OR_NOT_c_ETC___d1963 && NOT_csr_mip_fv_read__69_BIT_9_866_965_OR_NOT_c_ETC___d1972 ; assign NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d2000 = NOT_csr_mip_fv_read__69_BIT_11_826_932_OR_NOT__ETC___d1973 && NOT_csr_mip_fv_read__69_BIT_1_877_974_OR_NOT_c_ETC___d1981 && NOT_csr_mip_fv_read__69_BIT_5_888_983_OR_NOT_c_ETC___d1990 && NOT_csr_mip_fv_read__69_BIT_8_899_992_OR_NOT_c_ETC___d1999 ; assign NOT_csr_mip_fv_read__69_BIT_1_877_974_OR_NOT_c_ETC___d1981 = !csr_mip$fv_read[1] || !csr_mie$fv_read[1] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1882 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1883 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign NOT_csr_mip_fv_read__69_BIT_3_844_947_OR_NOT_c_ETC___d1954 = !csr_mip$fv_read[3] || !csr_mie$fv_read[3] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1849 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1850 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign NOT_csr_mip_fv_read__69_BIT_5_888_983_OR_NOT_c_ETC___d1990 = !csr_mip$fv_read[5] || !csr_mie$fv_read[5] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1893 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1894 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign NOT_csr_mip_fv_read__69_BIT_7_855_956_OR_NOT_c_ETC___d1963 = !csr_mip$fv_read[7] || !csr_mie$fv_read[7] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1860 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1861 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign NOT_csr_mip_fv_read__69_BIT_8_899_992_OR_NOT_c_ETC___d1999 = !csr_mip$fv_read[8] || !csr_mie$fv_read[8] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1904 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1905 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign NOT_csr_mip_fv_read__69_BIT_9_866_965_OR_NOT_c_ETC___d1972 = !csr_mip$fv_read[9] || !csr_mie$fv_read[9] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1871 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1872 || IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943) ; assign _theResult____h15604 = rg_mideleg[11] ? 2'b01 : 2'b11 ; assign _theResult____h15816 = rg_mideleg[3] ? 2'b01 : 2'b11 ; assign _theResult____h16028 = rg_mideleg[7] ? 2'b01 : 2'b11 ; assign _theResult____h16240 = rg_mideleg[9] ? 2'b01 : 2'b11 ; assign _theResult____h16452 = rg_mideleg[1] ? 2'b01 : 2'b11 ; assign _theResult____h16664 = rg_mideleg[5] ? 2'b01 : 2'b11 ; assign _theResult____h16876 = rg_mideleg[8] ? 2'b01 : 2'b11 ; assign _theResult____h17088 = rg_mideleg[0] ? 2'b01 : 2'b11 ; assign _theResult____h17300 = rg_mideleg[4] ? 2'b01 : 2'b11 ; assign _theResult___fst__h11956 = (csr_trap_actions_interrupt ? deleg_bit___1__h11965 : deleg_bit___1__h11980) ? 2'b01 : 2'b11 ; assign _theResult___fst__h13973 = { csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552[63:13], 2'd0, csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552[10:0] } ; assign _theResult___fst__h14174 = { csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552[63:9], 1'd0, csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552[7:0] } ; assign b__h12042 = csr_mstatus_rg_mstatus[ie_to_x__h11944] ; assign b__h14010 = csr_mstatus_rg_mstatus[pie_from_x__h13958] ; assign csr_mip_fv_read__69_BIT_0_910_AND_csr_mie_fv_r_ETC___d1919 = csr_mip$fv_read[0] && csr_mie$fv_read[0] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1915 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1916 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_11_826_AND_csr_mie_fv__ETC___d1843 = csr_mip$fv_read[11] && csr_mie$fv_read[11] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1831 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1832 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_11_826_AND_csr_mie_fv__ETC___d1909 = csr_mip_fv_read__69_BIT_11_826_AND_csr_mie_fv__ETC___d1843 || csr_mip_fv_read__69_BIT_3_844_AND_csr_mie_fv_r_ETC___d1853 || csr_mip_fv_read__69_BIT_7_855_AND_csr_mie_fv_r_ETC___d1864 || csr_mip_fv_read__69_BIT_9_866_AND_csr_mie_fv_r_ETC___d1875 || csr_mip_fv_read__69_BIT_1_877_AND_csr_mie_fv_r_ETC___d1886 || csr_mip_fv_read__69_BIT_5_888_AND_csr_mie_fv_r_ETC___d1897 || csr_mip_fv_read__69_BIT_8_899_AND_csr_mie_fv_r_ETC___d1908 ; assign csr_mip_fv_read__69_BIT_1_877_AND_csr_mie_fv_r_ETC___d1886 = csr_mip$fv_read[1] && csr_mie$fv_read[1] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1882 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1883 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_3_844_AND_csr_mie_fv_r_ETC___d1853 = csr_mip$fv_read[3] && csr_mie$fv_read[3] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1849 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1850 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_4_921_AND_csr_mie_fv_r_ETC___d1930 = csr_mip$fv_read[4] && csr_mie$fv_read[4] && (interrupt_pending_cur_priv < _theResult____h17300 || interrupt_pending_cur_priv == _theResult____h17300 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_5_888_AND_csr_mie_fv_r_ETC___d1897 = csr_mip$fv_read[5] && csr_mie$fv_read[5] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1893 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1894 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_7_855_AND_csr_mie_fv_r_ETC___d1864 = csr_mip$fv_read[7] && csr_mie$fv_read[7] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1860 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1861 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_8_899_AND_csr_mie_fv_r_ETC___d1908 = csr_mip$fv_read[8] && csr_mie$fv_read[8] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1904 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1905 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mip_fv_read__69_BIT_9_866_AND_csr_mie_fv_r_ETC___d1875 = csr_mip$fv_read[9] && csr_mie$fv_read[9] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1871 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1872 && IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840) ; assign csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552 = x__h14006 | mask__h13994 ; assign csr_mstatus_rg_mstatus_19_AND_INV_1_SL_1_CONCA_ETC___d1358 = x__h12038 | val__h12027 ; assign deleg_bit___1__h11965 = rg_mideleg[csr_trap_actions_exc_code] ; assign deleg_bit___1__h11980 = rg_medeleg[csr_trap_actions_exc_code] ; assign exc_pc___1__h12968 = exc_pc__h12901 + vector_offset__h12902 ; assign exc_pc__h12901 = { CASE_new_priv1818_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1, 2'd0 } ; assign fixed_up_val_23__h10209 = { csr_mstatus_rg_mstatus[22:17], 2'd0, ma_update_mstatus_fs_fs, IF_csr_mstatus_rg_mstatus_19_BITS_12_TO_11_37__ETC___d839, csr_mstatus_rg_mstatus[10:5], 1'd0, csr_mstatus_rg_mstatus[3:1], 1'd0 } ; assign fixed_up_val_23__h11867 = { IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[22:17], 2'd0, IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[14:13], (IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[12:11] == 2'b10) ? 2'b01 : IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[12:11], IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[10:5], 1'd0, IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[3:1], 1'd0 } ; assign fixed_up_val_23__h13880 = { IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559[22:17], 2'd0, IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559[14:13], (IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559[12:11] == 2'b10) ? 2'b01 : IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559[12:11], IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559[10:5], 1'd0, IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559[3:1], 1'd0 } ; assign fixed_up_val_23__h6333 = { csr_mstatus_rg_mstatus[22:20], mav_csr_write_word[19:18], csr_mstatus_rg_mstatus[17], 2'd0, mav_csr_write_word[14:13], IF_csr_mstatus_rg_mstatus_19_BITS_12_TO_11_37__ETC___d839, csr_mstatus_rg_mstatus[10:9], mav_csr_write_word[8], csr_mstatus_rg_mstatus[7:6], mav_csr_write_word[5], 1'd0, csr_mstatus_rg_mstatus[3:2], mav_csr_write_word[1], 1'd0 } ; assign fixed_up_val_23__h7832 = { mav_csr_write_word[22:17], 2'd0, mav_csr_write_word[14:13], (mav_csr_write_word[12:11] == 2'b10) ? 2'b01 : mav_csr_write_word[12:11], mav_csr_write_word[10:5], 1'd0, mav_csr_write_word[3:1], 1'd0 } ; assign ie_from_x__h13957 = { 4'd0, csr_ret_actions_from_priv } ; assign ie_to_x__h11944 = { 4'd0, new_priv__h11818 } ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1832 = interrupt_pending_cur_priv == _theResult____h15604 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1850 = interrupt_pending_cur_priv == _theResult____h15816 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1861 = interrupt_pending_cur_priv == _theResult____h16028 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1872 = interrupt_pending_cur_priv == _theResult____h16240 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1883 = interrupt_pending_cur_priv == _theResult____h16452 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1894 = interrupt_pending_cur_priv == _theResult____h16664 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1905 = interrupt_pending_cur_priv == _theResult____h16876 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_50_ETC___d1916 = interrupt_pending_cur_priv == _theResult____h17088 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1831 = interrupt_pending_cur_priv < _theResult____h15604 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1849 = interrupt_pending_cur_priv < _theResult____h15816 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1860 = interrupt_pending_cur_priv < _theResult____h16028 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1871 = interrupt_pending_cur_priv < _theResult____h16240 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1882 = interrupt_pending_cur_priv < _theResult____h16452 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1893 = interrupt_pending_cur_priv < _theResult____h16664 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1904 = interrupt_pending_cur_priv < _theResult____h16876 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_5_ETC___d1915 = interrupt_pending_cur_priv < _theResult____h17088 ; assign mask__h12026 = 64'd1 << ie_to_x__h11944 ; assign mask__h12043 = 64'd1 << pie_to_x__h11945 ; assign mask__h13994 = 64'd1 << pie_from_x__h13958 ; assign mask__h14011 = 64'd1 << ie_from_x__h13957 ; assign mav_csr_write_csr_addr_ULE_0x33F___d804 = mav_csr_write_csr_addr <= 12'h33F ; assign mav_csr_write_csr_addr_ULE_0xB1F___d800 = mav_csr_write_csr_addr <= 12'hB1F ; assign mav_csr_write_csr_addr_ULT_0x323_03_OR_NOT_mav_ETC___d1027 = (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr != 12'h001 && mav_csr_write_csr_addr != 12'h002 && mav_csr_write_csr_addr != 12'h003 && mav_csr_write_csr_addr != 12'h100 && mav_csr_write_csr_addr != 12'h102 && mav_csr_write_csr_addr != 12'h103 && mav_csr_write_csr_addr != 12'h104 && mav_csr_write_csr_addr != 12'h105 && mav_csr_write_csr_addr != 12'h106 && mav_csr_write_csr_addr != 12'h140 && mav_csr_write_csr_addr != 12'h141 && mav_csr_write_csr_addr != 12'h142 && mav_csr_write_csr_addr != 12'h143 && mav_csr_write_csr_addr != 12'h144 && mav_csr_write_csr_addr != 12'h180 && mav_csr_write_csr_addr != 12'h302 && mav_csr_write_csr_addr != 12'h303 && mav_csr_write_csr_addr != 12'hF11 && mav_csr_write_csr_addr != 12'hF12 && mav_csr_write_csr_addr != 12'hF13 && mav_csr_write_csr_addr != 12'hF14 && mav_csr_write_csr_addr != 12'h300 && mav_csr_write_csr_addr != 12'h301 && mav_csr_write_csr_addr != 12'h304 && mav_csr_write_csr_addr != 12'h305 && mav_csr_write_csr_addr != 12'h306 && mav_csr_write_csr_addr != 12'h340 && mav_csr_write_csr_addr != 12'h341 && mav_csr_write_csr_addr != 12'h342 && mav_csr_write_csr_addr != 12'h343 && mav_csr_write_csr_addr != 12'h344 && mav_csr_write_csr_addr != 12'hB00 && mav_csr_write_csr_addr != 12'hB02 && mav_csr_write_csr_addr != 12'h7A0 && mav_csr_write_csr_addr != 12'h7A1 && mav_csr_write_csr_addr != 12'h7A2 && mav_csr_write_csr_addr != 12'h7A3 && mav_csr_write_csr_addr != 12'h7B0 && mav_csr_write_csr_addr != 12'h7B1 && mav_csr_write_csr_addr != 12'h7B2 && mav_csr_write_csr_addr != 12'h7B3 ; assign mav_csr_write_csr_addr_ULT_0x323___d803 = mav_csr_write_csr_addr < 12'h323 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d811 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && (mav_csr_write_csr_addr == 12'h001 || mav_csr_write_csr_addr == 12'h003) ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d817 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && (mav_csr_write_csr_addr == 12'h002 || mav_csr_write_csr_addr == 12'h003) ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d829 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && (mav_csr_write_csr_addr == 12'h100 || mav_csr_write_csr_addr == 12'h300) ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d866 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h104 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d868 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h105 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d873 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h140 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d875 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h141 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d877 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h142 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d882 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h143 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d884 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h144 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d886 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h180 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d888 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h302 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d895 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h303 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d898 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h304 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d900 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h305 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d902 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h306 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d904 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h340 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d906 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h341 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d908 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h342 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d910 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h343 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d912 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h344 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d916 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'hB02 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d918 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7A0 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d920 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7A1 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d922 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7A2 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d924 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7A3 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d926 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7B0 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d936 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7B1 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d938 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7B2 ; assign mav_csr_write_csr_addr_ULT_0xB03_99_OR_NOT_mav_ETC___d940 = (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && (mav_csr_write_csr_addr_ULT_0x323___d803 || !mav_csr_write_csr_addr_ULE_0x33F___d804) && mav_csr_write_csr_addr == 12'h7B3 ; assign mav_csr_write_csr_addr_ULT_0xB03___d799 = mav_csr_write_csr_addr < 12'hB03 ; assign new_dcsr__h9357 = { rg_dcsr[31:16], mav_csr_write_word[15:9], rg_dcsr[8:5], mav_csr_write_word[4], rg_dcsr[3], mav_csr_write_word[2:0] } ; assign new_priv__h11818 = (csr_trap_actions_from_priv == 2'b11) ? csr_trap_actions_from_priv : _theResult___fst__h11956 ; assign pie_from_x__h13958 = { 4'd1, csr_ret_actions_from_priv } ; assign pie_to_x__h11945 = { 4'd1, new_priv__h11818 } ; assign sd__h10208 = ma_update_mstatus_fs_fs == 2'h3 ; assign sd__h11866 = IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[14:13] == 2'h3 ; assign sd__h13879 = IF_csr_ret_actions_from_priv_EQ_0b11_539_THEN__ETC___d1559[14:13] == 2'h3 ; assign sd__h7831 = mav_csr_write_word[14:13] == 2'h3 ; assign to_y__h14173 = { 1'b0, csr_mstatus_rg_mstatus_19_AND_INV_1_SL_0_CONCA_ETC___d1552[8] } ; assign v__h11823 = { sd__h11866, 40'd5120, fixed_up_val_23__h11867 } ; assign v__h6024 = { 59'd0, mav_csr_write_word[4:0] } ; assign v__h6168 = { 56'd0, mav_csr_write_word[7:0] } ; assign v__h6282 = { sd__h7831, 43'd8192, mav_csr_write_word[19:18], 3'd0, mav_csr_write_word[14:13], 4'd0, mav_csr_write_word[8], 2'd0, mav_csr_write_word[5], 3'd0, mav_csr_write_word[1], 1'd0 } ; assign v__h7660 = { 48'd0, mav_csr_write_word[15], 1'd0, mav_csr_write_word[13:12], 2'd0, mav_csr_write_word[9:0] } ; assign v__h7696 = { 52'd0, mav_csr_write_word[11:0] } ; assign v__h8366 = { mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ; assign v__h8428 = { 61'd0, mav_csr_write_word[2:0] } ; assign v__h8584 = { mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ; assign v__h9354 = { 32'd0, new_dcsr__h9357 } ; assign val__h12027 = 64'd0 << ie_to_x__h11944 ; assign val__h12044 = { 63'd0, b__h12042 } << pie_to_x__h11945 ; assign val__h14012 = { 63'd0, b__h14010 } << ie_from_x__h13957 ; assign vector_offset__h12902 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ; assign wordxl1__h7791 = { sd__h7831, 40'd5120, fixed_up_val_23__h7832 } ; assign x__h10796 = (csr_trap_actions_interrupt && CASE_new_priv1818_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2) ? exc_pc___1__h12968 : exc_pc__h12901 ; assign x__h12025 = x__h12055 | val__h12044 ; assign x__h12038 = x__h12025 & y__h12039 ; assign x__h12055 = csr_mstatus_rg_mstatus & y__h12056 ; assign x__h13818 = { csr_trap_actions_interrupt, 59'd0, csr_trap_actions_exc_code } ; assign x__h13993 = x__h14023 | val__h14012 ; assign x__h14006 = x__h13993 & y__h14007 ; assign x__h14023 = csr_mstatus_rg_mstatus & y__h14024 ; assign y__h12039 = ~mask__h12026 ; assign y__h12056 = ~mask__h12043 ; assign y__h14007 = ~mask__h13994 ; assign y__h14024 = ~mask__h14011 ; assign y_avValue_fst__h12874 = { sd__h11866, 43'd8192, IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[19:18], 3'd0, IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[14:13], 4'd0, IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[8], 2'd0, IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[5], 3'd0, IF_IF_csr_trap_actions_from_priv_EQ_0b11_338_T_ETC___d1366[1], 1'd0 } ; always@(mav_csr_write_csr_addr or v__h6024 or v__h8428 or v__h6168 or v__h6282 or csr_mie$fav_sie_write or v__h8366 or mav_csr_write_word or v__h8584 or csr_mip$fav_sip_write or wordxl1__h7791 or v__h7660 or v__h7696 or csr_mie$fav_write or csr_mip$fav_write or v__h9354) begin case (mav_csr_write_csr_addr) 12'h001: y_avValue_fst__h9989 = v__h6024; 12'h002, 12'h306: y_avValue_fst__h9989 = v__h8428; 12'h003: y_avValue_fst__h9989 = v__h6168; 12'h100: y_avValue_fst__h9989 = v__h6282; 12'h102, 12'h103, 12'h106, 12'h301, 12'hF11, 12'hF12, 12'hF13, 12'hF14: y_avValue_fst__h9989 = 64'd0; 12'h104: y_avValue_fst__h9989 = csr_mie$fav_sie_write; 12'h105, 12'h305: y_avValue_fst__h9989 = v__h8366; 12'h140, 12'h141, 12'h143, 12'h180, 12'h340, 12'h341, 12'h343, 12'h7A0, 12'h7A1, 12'h7A2, 12'h7A3, 12'h7B1, 12'h7B2, 12'h7B3, 12'hB00, 12'hB02: y_avValue_fst__h9989 = mav_csr_write_word; 12'h142, 12'h342: y_avValue_fst__h9989 = v__h8584; 12'h144: y_avValue_fst__h9989 = csr_mip$fav_sip_write; 12'h300: y_avValue_fst__h9989 = wordxl1__h7791; 12'h302: y_avValue_fst__h9989 = v__h7660; 12'h303: y_avValue_fst__h9989 = v__h7696; 12'h304: y_avValue_fst__h9989 = csr_mie$fav_write; 12'h344: y_avValue_fst__h9989 = csr_mip$fav_write; 12'h7B0: y_avValue_fst__h9989 = v__h9354; default: y_avValue_fst__h9989 = 64'd0; endcase end always@(new_priv__h11818 or rg_mtvec or rg_stvec) begin case (new_priv__h11818) 2'b01: CASE_new_priv1818_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_stvec[62:1]; 2'b11: CASE_new_priv1818_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_mtvec[62:1]; default: CASE_new_priv1818_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_mtvec[62:1]; endcase end always@(new_priv__h11818 or rg_mtvec or rg_stvec) begin case (new_priv__h11818) 2'b01: CASE_new_priv1818_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_stvec[0]; 2'b11: CASE_new_priv1818_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_mtvec[0]; default: CASE_new_priv1818_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_mtvec[0]; endcase end always@(new_priv__h11818 or v__h11823 or y_avValue_fst__h12874) begin case (new_priv__h11818) 2'b01: x__h13817 = y_avValue_fst__h12874; 2'b11: x__h13817 = v__h11823; default: x__h13817 = v__h11823; endcase end always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) begin case (interrupt_pending_cur_priv) 2'b0: IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840 = csr_mstatus_rg_mstatus[0]; 2'b01: IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840 = csr_mstatus_rg_mstatus[1]; default: IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1840 = interrupt_pending_cur_priv == 2'b11 && csr_mstatus_rg_mstatus[3]; endcase end always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) begin case (interrupt_pending_cur_priv) 2'b0: IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943 = !csr_mstatus_rg_mstatus[0]; 2'b01: IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943 = !csr_mstatus_rg_mstatus[1]; default: IF_interrupt_pending_cur_priv_EQ_0b0_833_THEN__ETC___d1943 = interrupt_pending_cur_priv != 2'b11 || !csr_mstatus_rg_mstatus[3]; endcase end always@(read_csr_csr_addr or rg_dscratch1 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_tdata3 or rg_dcsr or rg_dpc or rg_dscratch0 or rg_mcycle or rg_minstret) begin case (read_csr_csr_addr) 12'h001: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { 59'd0, rg_fflags }; 12'h002: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { 61'd0, rg_frm }; 12'h003: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = 64'd0; 12'h104: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = csr_mie$fv_sie_read; 12'h105: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_sscratch; 12'h141: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_sepc; 12'h142: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_stval; 12'h144: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = csr_mip$fv_sip_read; 12'h180: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_satp; 12'h300: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = csr_mstatus_rg_mstatus; 12'h301: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = 64'h800000000014112D; 12'h302: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { 48'd0, rg_medeleg }; 12'h303: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { 52'd0, rg_mideleg }; 12'h304: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = csr_mie$fv_read; 12'h305: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { 61'd0, rg_mcounteren }; 12'h340: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_mscratch; 12'h341: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_mepc; 12'h342: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_mtval; 12'h344: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = csr_mip$fv_read; 12'h7A0: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_tselect; 12'h7A1: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_tdata1; 12'h7A2: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_tdata2; 12'h7A3: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_tdata3; 12'h7B0: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = { 32'd0, rg_dcsr }; 12'h7B1: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_dpc; 12'h7B2: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_dscratch0; 12'hB00, 12'hC00: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_mcycle; 12'hB02, 12'hC02: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_minstret; default: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d316 = rg_dscratch1; endcase end always@(read_csr_port2_csr_addr or rg_dscratch1 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_tdata3 or rg_dcsr or rg_dpc or rg_dscratch0 or rg_mcycle or rg_minstret) begin case (read_csr_port2_csr_addr) 12'h001: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { 59'd0, rg_fflags }; 12'h002: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { 61'd0, rg_frm }; 12'h003: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = 64'd0; 12'h104: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = csr_mie$fv_sie_read; 12'h105: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_sscratch; 12'h141: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_sepc; 12'h142: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_stval; 12'h144: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = csr_mip$fv_sip_read; 12'h180: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_satp; 12'h300: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = csr_mstatus_rg_mstatus; 12'h301: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = 64'h800000000014112D; 12'h302: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { 48'd0, rg_medeleg }; 12'h303: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { 52'd0, rg_mideleg }; 12'h304: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = csr_mie$fv_read; 12'h305: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { 61'd0, rg_mcounteren }; 12'h340: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_mscratch; 12'h341: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_mepc; 12'h342: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_mtval; 12'h344: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = csr_mip$fv_read; 12'h7A0: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_tselect; 12'h7A1: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_tdata1; 12'h7A2: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_tdata2; 12'h7A3: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_tdata3; 12'h7B0: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = { 32'd0, rg_dcsr }; 12'h7B1: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_dpc; 12'h7B2: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_dscratch0; 12'hB00, 12'hC00: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_mcycle; 12'hB02, 12'hC02: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_minstret; default: IF_read_csr_port2_csr_addr_EQ_0x1_31_THEN_0_CO_ETC___d556 = rg_dscratch1; endcase end always@(mav_read_csr_csr_addr or rg_dscratch1 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_tdata3 or rg_dcsr or rg_dpc or rg_dscratch0 or rg_mcycle or rg_minstret) begin case (mav_read_csr_csr_addr) 12'h001: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { 59'd0, rg_fflags }; 12'h002: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { 61'd0, rg_frm }; 12'h003: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = 64'd0; 12'h104: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = csr_mie$fv_sie_read; 12'h105: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_sscratch; 12'h141: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_sepc; 12'h142: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_stval; 12'h144: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = csr_mip$fv_sip_read; 12'h180: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_satp; 12'h300: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = csr_mstatus_rg_mstatus; 12'h301: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = 64'h800000000014112D; 12'h302: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { 48'd0, rg_medeleg }; 12'h303: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { 52'd0, rg_mideleg }; 12'h304: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = csr_mie$fv_read; 12'h305: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { 61'd0, rg_mcounteren }; 12'h340: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_mscratch; 12'h341: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_mepc; 12'h342: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_mtval; 12'h344: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = csr_mip$fv_read; 12'h7A0: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_tselect; 12'h7A1: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_tdata1; 12'h7A2: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_tdata2; 12'h7A3: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_tdata3; 12'h7B0: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = { 32'd0, rg_dcsr }; 12'h7B1: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_dpc; 12'h7B2: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_dscratch0; 12'hB00, 12'hC00: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_mcycle; 12'hB02, 12'hC02: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_minstret; default: IF_mav_read_csr_csr_addr_EQ_0x1_71_THEN_0_CONC_ETC___d796 = rg_dscratch1; endcase end // handling of inlined registers always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000A00002000; rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (cfg_verbosity$EN) cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; if (csr_mstatus_rg_mstatus$EN) csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY csr_mstatus_rg_mstatus$D_IN; if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; if (rg_minstret$EN) rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; end if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; if (rg_dscratch0$EN) rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; if (rg_dscratch1$EN) rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN; if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN; if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; if (rg_mcounteren$EN) rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN; if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN; if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN; if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN; if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN; if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN; if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN; if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin cfg_verbosity = 4'hA; csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA; rg_dcsr = 32'hAAAAAAAA; rg_dpc = 64'hAAAAAAAAAAAAAAAA; rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; rg_fflags = 5'h0A; rg_frm = 3'h2; rg_mcause = 5'h0A; rg_mcounteren = 3'h2; rg_mcycle = 64'hAAAAAAAAAAAAAAAA; rg_medeleg = 16'hAAAA; rg_mepc = 64'hAAAAAAAAAAAAAAAA; rg_mideleg = 12'hAAA; rg_minstret = 64'hAAAAAAAAAAAAAAAA; rg_mscratch = 64'hAAAAAAAAAAAAAAAA; rg_mtval = 64'hAAAAAAAAAAAAAAAA; rg_mtvec = 63'h2AAAAAAAAAAAAAAA; rg_satp = 64'hAAAAAAAAAAAAAAAA; rg_scause = 5'h0A; rg_sepc = 64'hAAAAAAAAAAAAAAAA; rg_sscratch = 64'hAAAAAAAAAAAAAAAA; rg_state = 1'h0; rg_stval = 64'hAAAAAAAAAAAAAAAA; rg_stvec = 63'h2AAAAAAAAAAAAAAA; rg_tdata1 = 64'hAAAAAAAAAAAAAAAA; rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; rg_tselect = 64'hAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sstatus = 0x%0h", { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sip = 0x%0h", csr_mip$fv_sip_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sie = 0x%0h", csr_mie$fv_sie_read); if (RST_N != `BSV_RESET_VALUE) if (EN_mav_csr_write && (mav_csr_write_csr_addr_ULT_0xB03___d799 || !mav_csr_write_csr_addr_ULE_0xB1F___d800) && mav_csr_write_csr_addr_ULT_0x323_03_OR_NOT_mav_ETC___d1027 && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", rg_mcycle, mav_csr_write_csr_addr, mav_csr_write_word); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", csr_trap_actions_from_priv, csr_trap_actions_pc, csr_trap_actions_interrupt, csr_trap_actions_exc_code, csr_trap_actions_xtval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" priv %0d: ", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" ip: 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" ie: 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" edeleg: 0x%0h", 16'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" ideleg: 0x%0h", 12'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" cause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_scause[4] && rg_scause[3:0] != 4'd0 && rg_scause[3:0] != 4'd1 && rg_scause[3:0] != 4'd2 && rg_scause[3:0] != 4'd3 && rg_scause[3:0] != 4'd4 && rg_scause[3:0] != 4'd5 && rg_scause[3:0] != 4'd6 && rg_scause[3:0] != 4'd7 && rg_scause[3:0] != 4'd8 && rg_scause[3:0] != 4'd9 && rg_scause[3:0] != 4'd10 && rg_scause[3:0] != 4'd11) $write("unknown interrupt Exc_Code %d", rg_scause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_scause[4] && rg_scause[3:0] != 4'd0 && rg_scause[3:0] != 4'd1 && rg_scause[3:0] != 4'd2 && rg_scause[3:0] != 4'd3 && rg_scause[3:0] != 4'd4 && rg_scause[3:0] != 4'd5 && rg_scause[3:0] != 4'd6 && rg_scause[3:0] != 4'd7 && rg_scause[3:0] != 4'd8 && rg_scause[3:0] != 4'd9 && rg_scause[3:0] != 4'd11 && rg_scause[3:0] != 4'd12 && rg_scause[3:0] != 4'd13 && rg_scause[3:0] != 4'd15) $write("unknown trap Exc_Code %d", rg_scause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" status: 0x%0h", { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" tvec: 0x%0h", { rg_stvec[62:1], 1'b0, rg_stvec[0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" epc: 0x%0h", rg_sepc); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" tval: 0x%0h", rg_stval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" priv %0d: ", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" ip: 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" ie: 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" edeleg: 0x%0h", rg_medeleg); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" ideleg: 0x%0h", rg_mideleg); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" cause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && rg_mcause[4] && rg_mcause[3:0] != 4'd0 && rg_mcause[3:0] != 4'd1 && rg_mcause[3:0] != 4'd2 && rg_mcause[3:0] != 4'd3 && rg_mcause[3:0] != 4'd4 && rg_mcause[3:0] != 4'd5 && rg_mcause[3:0] != 4'd6 && rg_mcause[3:0] != 4'd7 && rg_mcause[3:0] != 4'd8 && rg_mcause[3:0] != 4'd9 && rg_mcause[3:0] != 4'd10 && rg_mcause[3:0] != 4'd11) $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !rg_mcause[4] && rg_mcause[3:0] != 4'd0 && rg_mcause[3:0] != 4'd1 && rg_mcause[3:0] != 4'd2 && rg_mcause[3:0] != 4'd3 && rg_mcause[3:0] != 4'd4 && rg_mcause[3:0] != 4'd5 && rg_mcause[3:0] != 4'd6 && rg_mcause[3:0] != 4'd7 && rg_mcause[3:0] != 4'd8 && rg_mcause[3:0] != 4'd9 && rg_mcause[3:0] != 4'd11 && rg_mcause[3:0] != 4'd12 && rg_mcause[3:0] != 4'd13 && rg_mcause[3:0] != 4'd15) $write("unknown trap Exc_Code %d", rg_mcause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" status: 0x%0h", csr_mstatus_rg_mstatus); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" epc: 0x%0h", rg_mepc); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" tval: 0x%0h", rg_mtval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" Return: new pc 0x%0h ", x__h10796); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" new mstatus:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write("MStatus{", "sd:%0d", x__h13817[14:13] == 2'h3 || x__h13817[16:15] == 2'h3); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" sxl:%0d uxl:%0d", x__h13817[35:34], x__h13817[33:32]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" tsr:%0d", x__h13817[22]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" tw:%0d", x__h13817[21]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" tvm:%0d", x__h13817[20]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" mxr:%0d", x__h13817[19]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" sum:%0d", x__h13817[18]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" mprv:%0d", x__h13817[17]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" xs:%0d", x__h13817[16:15]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" fs:%0d", x__h13817[14:13]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" mpp:%0d", x__h13817[12:11]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" spp:%0d", x__h13817[8]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" pies:%0d_%0d%0d", x__h13817[7], x__h13817[5], x__h13817[4]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" ies:%0d_%0d%0d", x__h13817[3], x__h13817[1], x__h13817[0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write("}"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" new xcause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030_031_AND__ETC___d1486) $write("unknown interrupt Exc_Code %d", csr_trap_actions_exc_code); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031 && !csr_trap_actions_interrupt && csr_trap_actions_exc_code == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030_031_AND__ETC___d1536) $write("unknown trap Exc_Code %d", csr_trap_actions_exc_code); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $write(" new priv %0d", new_priv__h11818); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display(""); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", rg_mcycle, m_external_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", rg_mcycle, s_external_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display("%0d: CSR_RegFile: timer_interrupt_req: %x", rg_mcycle, timer_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__029_ULE_1_030___d1031) $display("%0d: CSR_RegFile: software_interrupt_req: %x", rg_mcycle, software_interrupt_req_set_not_clear); end // synopsys translate_on endmodule // mkCSR_RegFile