//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_request_put                O     1
// response_get                   O    69
// RDY_response_get               O     1
// CLK                            I     1 clock
// RST_N                          I     1 reset
// request_put                    I   131
// EN_request_put                 I     1
// EN_response_get                I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDoubleDiv(CLK,
		   RST_N,

		   request_put,
		   EN_request_put,
		   RDY_request_put,

		   EN_response_get,
		   response_get,
		   RDY_response_get);
  input  CLK;
  input  RST_N;

  // action method request_put
  input  [130 : 0] request_put;
  input  EN_request_put;
  output RDY_request_put;

  // actionvalue method response_get
  input  EN_response_get;
  output [68 : 0] response_get;
  output RDY_response_get;

  // signals for module outputs
  wire [68 : 0] response_get;
  wire RDY_request_put, RDY_response_get;

  // ports of submodule fpu
  wire [130 : 0] fpu$request_put;
  wire [68 : 0] fpu$response_get;
  wire fpu$EN_request_put,
       fpu$EN_response_get,
       fpu$RDY_request_put,
       fpu$RDY_response_get;

  // rule scheduling signals
  wire CAN_FIRE_request_put,
       CAN_FIRE_response_get,
       WILL_FIRE_request_put,
       WILL_FIRE_response_get;

  // action method request_put
  assign RDY_request_put = fpu$RDY_request_put ;
  assign CAN_FIRE_request_put = fpu$RDY_request_put ;
  assign WILL_FIRE_request_put = EN_request_put ;

  // actionvalue method response_get
  assign response_get = fpu$response_get ;
  assign RDY_response_get = fpu$RDY_response_get ;
  assign CAN_FIRE_response_get = fpu$RDY_response_get ;
  assign WILL_FIRE_response_get = EN_response_get ;

  // submodule fpu
  mkXilinxFpDiv fpu(.CLK(CLK),
		    .RST_N(RST_N),
		    .request_put(fpu$request_put),
		    .EN_request_put(fpu$EN_request_put),
		    .EN_response_get(fpu$EN_response_get),
		    .RDY_request_put(fpu$RDY_request_put),
		    .response_get(fpu$response_get),
		    .RDY_response_get(fpu$RDY_response_get));

  // submodule fpu
  assign fpu$request_put = request_put ;
  assign fpu$EN_request_put = EN_request_put ;
  assign fpu$EN_response_get = EN_response_get ;
endmodule  // mkDoubleDiv