.section .data
.align 12
# Root Table (L2) 
# Since we map 1GiB, this is the ONLY table we need.
l2_table:
    .quad 0
    .quad 0
    # Entry 2 maps 0x80000000 - 0xBFFFFFFF
    # PPN 0x80000, Flags: D A G U R W X V (0xCF)
    .quad (0x80000 << 10) | 0xCF 
    .fill 509, 8, 0

.section .text
.globl _start
.align 4
_start:
    # 1. Get the address of our table
    cllc    ca0, l2_table
    cgetaddr t0, ca0
    
    # 2. Convert address to PPN
    srli    t0, t0, 12
    
    # 3. Construct SATP with Mode 8 (Sv39)
    # The FIXME suggests bit 63 must be 1.
    li      t1, 8
    slli    t1, t1, 60
    or      t0, t0, t1       # t0 = (8 << 60) | PPN
    
    # 4. Critical Write Sequence
    sfence.vma               # Flush before enabling
    csrw    sptbr, t0         # Write to SATP
    sfence.vma               # Flush after enabling
    
    # 5. Transition to Virtual Space
    # We load an address from the .data section (0x80002000)
    # If paging is ON, the DTLB trace should now show (sv39)
    li        t1, 0x80002000
    cspecialr ca1, pcc
    csetaddr  ca1, ca1, t1
    
    ld        t2, 0(ca1)     # Trigger a DTLB lookup

    # 6. Exit / Finish
    # (Assuming your tohost logic)
    li      t1, 1
    csd     t1, 0(c1)

loop: j loop