// // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // // // Ports: // Name I/O size props // RDY_enq O 1 // RDY_deq O 1 // first_data O 43 // RDY_first_data O 1 // first_poisoned O 1 // RDY_first_poisoned O 1 // RDY_specUpdate_incorrectSpeculation O 1 const // RDY_specUpdate_correctSpeculation O 1 const // CLK I 1 clock // RST_N I 1 reset // enq_x I 43 // specUpdate_incorrectSpeculation_kill_all I 1 // specUpdate_incorrectSpeculation_kill_tag I 4 // specUpdate_correctSpeculation_mask I 12 // EN_enq I 1 // EN_deq I 1 // EN_specUpdate_incorrectSpeculation I 1 // EN_specUpdate_correctSpeculation I 1 // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkFmaExecQ(CLK, RST_N, enq_x, EN_enq, RDY_enq, EN_deq, RDY_deq, first_data, RDY_first_data, first_poisoned, RDY_first_poisoned, specUpdate_incorrectSpeculation_kill_all, specUpdate_incorrectSpeculation_kill_tag, EN_specUpdate_incorrectSpeculation, RDY_specUpdate_incorrectSpeculation, specUpdate_correctSpeculation_mask, EN_specUpdate_correctSpeculation, RDY_specUpdate_correctSpeculation); input CLK; input RST_N; // action method enq input [42 : 0] enq_x; input EN_enq; output RDY_enq; // action method deq input EN_deq; output RDY_deq; // value method first_data output [42 : 0] first_data; output RDY_first_data; // value method first_poisoned output first_poisoned; output RDY_first_poisoned; // action method specUpdate_incorrectSpeculation input specUpdate_incorrectSpeculation_kill_all; input [3 : 0] specUpdate_incorrectSpeculation_kill_tag; input EN_specUpdate_incorrectSpeculation; output RDY_specUpdate_incorrectSpeculation; // action method specUpdate_correctSpeculation input [11 : 0] specUpdate_correctSpeculation_mask; input EN_specUpdate_correctSpeculation; output RDY_specUpdate_correctSpeculation; // signals for module outputs reg RDY_deq, first_poisoned; wire [42 : 0] first_data; wire RDY_enq, RDY_first_data, RDY_first_poisoned, RDY_specUpdate_correctSpeculation, RDY_specUpdate_incorrectSpeculation; // inlined wires reg m_m_valid_for_enq_wire$wget; wire [11 : 0] m_m_specBits_0_lat_1$wget, m_m_specBits_1_lat_1$wget; wire m_m_poisoned_0_lat_0$whas, m_m_poisoned_1_lat_0$whas, m_m_poisoned_2_lat_0$whas, m_m_poisoned_3_lat_0$whas, m_m_valid_0_lat_0$whas, m_m_valid_0_lat_1$whas, m_m_valid_1_lat_0$whas, m_m_valid_1_lat_1$whas, m_m_valid_2_lat_0$whas, m_m_valid_2_lat_1$whas, m_m_valid_3_lat_0$whas, m_m_valid_3_lat_1$whas; // register m_m_deqP reg [1 : 0] m_m_deqP; wire [1 : 0] m_m_deqP$D_IN; wire m_m_deqP$EN; // register m_m_enqP reg [1 : 0] m_m_enqP; wire [1 : 0] m_m_enqP$D_IN; wire m_m_enqP$EN; // register m_m_poisoned_0_rl reg m_m_poisoned_0_rl; wire m_m_poisoned_0_rl$D_IN, m_m_poisoned_0_rl$EN; // register m_m_poisoned_1_rl reg m_m_poisoned_1_rl; wire m_m_poisoned_1_rl$D_IN, m_m_poisoned_1_rl$EN; // register m_m_poisoned_2_rl reg m_m_poisoned_2_rl; wire m_m_poisoned_2_rl$D_IN, m_m_poisoned_2_rl$EN; // register m_m_poisoned_3_rl reg m_m_poisoned_3_rl; wire m_m_poisoned_3_rl$D_IN, m_m_poisoned_3_rl$EN; // register m_m_row_0 reg [30 : 0] m_m_row_0; wire [30 : 0] m_m_row_0$D_IN; wire m_m_row_0$EN; // register m_m_row_1 reg [30 : 0] m_m_row_1; wire [30 : 0] m_m_row_1$D_IN; wire m_m_row_1$EN; // register m_m_row_2 reg [30 : 0] m_m_row_2; wire [30 : 0] m_m_row_2$D_IN; wire m_m_row_2$EN; // register m_m_row_3 reg [30 : 0] m_m_row_3; wire [30 : 0] m_m_row_3$D_IN; wire m_m_row_3$EN; // register m_m_specBits_0_rl reg [11 : 0] m_m_specBits_0_rl; wire [11 : 0] m_m_specBits_0_rl$D_IN; wire m_m_specBits_0_rl$EN; // register m_m_specBits_1_rl reg [11 : 0] m_m_specBits_1_rl; wire [11 : 0] m_m_specBits_1_rl$D_IN; wire m_m_specBits_1_rl$EN; // register m_m_specBits_2_rl reg [11 : 0] m_m_specBits_2_rl; wire [11 : 0] m_m_specBits_2_rl$D_IN; wire m_m_specBits_2_rl$EN; // register m_m_specBits_3_rl reg [11 : 0] m_m_specBits_3_rl; wire [11 : 0] m_m_specBits_3_rl$D_IN; wire m_m_specBits_3_rl$EN; // register m_m_valid_0_rl reg m_m_valid_0_rl; wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN; // register m_m_valid_1_rl reg m_m_valid_1_rl; wire m_m_valid_1_rl$D_IN, m_m_valid_1_rl$EN; // register m_m_valid_2_rl reg m_m_valid_2_rl; wire m_m_valid_2_rl$D_IN, m_m_valid_2_rl$EN; // register m_m_valid_3_rl reg m_m_valid_3_rl; wire m_m_valid_3_rl$D_IN, m_m_valid_3_rl$EN; // ports of submodule m_m_poisoned_0_dummy2_0 wire m_m_poisoned_0_dummy2_0$D_IN, m_m_poisoned_0_dummy2_0$EN, m_m_poisoned_0_dummy2_0$Q_OUT; // ports of submodule m_m_poisoned_0_dummy2_1 wire m_m_poisoned_0_dummy2_1$D_IN, m_m_poisoned_0_dummy2_1$EN, m_m_poisoned_0_dummy2_1$Q_OUT; // ports of submodule m_m_poisoned_1_dummy2_0 wire m_m_poisoned_1_dummy2_0$D_IN, m_m_poisoned_1_dummy2_0$EN, m_m_poisoned_1_dummy2_0$Q_OUT; // ports of submodule m_m_poisoned_1_dummy2_1 wire m_m_poisoned_1_dummy2_1$D_IN, m_m_poisoned_1_dummy2_1$EN, m_m_poisoned_1_dummy2_1$Q_OUT; // ports of submodule m_m_poisoned_2_dummy2_0 wire m_m_poisoned_2_dummy2_0$D_IN, m_m_poisoned_2_dummy2_0$EN, m_m_poisoned_2_dummy2_0$Q_OUT; // ports of submodule m_m_poisoned_2_dummy2_1 wire m_m_poisoned_2_dummy2_1$D_IN, m_m_poisoned_2_dummy2_1$EN, m_m_poisoned_2_dummy2_1$Q_OUT; // ports of submodule m_m_poisoned_3_dummy2_0 wire m_m_poisoned_3_dummy2_0$D_IN, m_m_poisoned_3_dummy2_0$EN, m_m_poisoned_3_dummy2_0$Q_OUT; // ports of submodule m_m_poisoned_3_dummy2_1 wire m_m_poisoned_3_dummy2_1$D_IN, m_m_poisoned_3_dummy2_1$EN, m_m_poisoned_3_dummy2_1$Q_OUT; // ports of submodule m_m_specBits_0_dummy2_0 wire m_m_specBits_0_dummy2_0$D_IN, m_m_specBits_0_dummy2_0$EN, m_m_specBits_0_dummy2_0$Q_OUT; // ports of submodule m_m_specBits_0_dummy2_1 wire m_m_specBits_0_dummy2_1$D_IN, m_m_specBits_0_dummy2_1$EN, m_m_specBits_0_dummy2_1$Q_OUT; // ports of submodule m_m_specBits_1_dummy2_0 wire m_m_specBits_1_dummy2_0$D_IN, m_m_specBits_1_dummy2_0$EN, m_m_specBits_1_dummy2_0$Q_OUT; // ports of submodule m_m_specBits_1_dummy2_1 wire m_m_specBits_1_dummy2_1$D_IN, m_m_specBits_1_dummy2_1$EN, m_m_specBits_1_dummy2_1$Q_OUT; // ports of submodule m_m_specBits_2_dummy2_0 wire m_m_specBits_2_dummy2_0$D_IN, m_m_specBits_2_dummy2_0$EN, m_m_specBits_2_dummy2_0$Q_OUT; // ports of submodule m_m_specBits_2_dummy2_1 wire m_m_specBits_2_dummy2_1$D_IN, m_m_specBits_2_dummy2_1$EN, m_m_specBits_2_dummy2_1$Q_OUT; // ports of submodule m_m_specBits_3_dummy2_0 wire m_m_specBits_3_dummy2_0$D_IN, m_m_specBits_3_dummy2_0$EN, m_m_specBits_3_dummy2_0$Q_OUT; // ports of submodule m_m_specBits_3_dummy2_1 wire m_m_specBits_3_dummy2_1$D_IN, m_m_specBits_3_dummy2_1$EN, m_m_specBits_3_dummy2_1$Q_OUT; // ports of submodule m_m_valid_0_dummy2_0 wire m_m_valid_0_dummy2_0$D_IN, m_m_valid_0_dummy2_0$EN, m_m_valid_0_dummy2_0$Q_OUT; // ports of submodule m_m_valid_0_dummy2_1 wire m_m_valid_0_dummy2_1$D_IN, m_m_valid_0_dummy2_1$EN, m_m_valid_0_dummy2_1$Q_OUT; // ports of submodule m_m_valid_1_dummy2_0 wire m_m_valid_1_dummy2_0$D_IN, m_m_valid_1_dummy2_0$EN, m_m_valid_1_dummy2_0$Q_OUT; // ports of submodule m_m_valid_1_dummy2_1 wire m_m_valid_1_dummy2_1$D_IN, m_m_valid_1_dummy2_1$EN, m_m_valid_1_dummy2_1$Q_OUT; // ports of submodule m_m_valid_2_dummy2_0 wire m_m_valid_2_dummy2_0$D_IN, m_m_valid_2_dummy2_0$EN, m_m_valid_2_dummy2_0$Q_OUT; // ports of submodule m_m_valid_2_dummy2_1 wire m_m_valid_2_dummy2_1$D_IN, m_m_valid_2_dummy2_1$EN, m_m_valid_2_dummy2_1$Q_OUT; // ports of submodule m_m_valid_3_dummy2_0 wire m_m_valid_3_dummy2_0$D_IN, m_m_valid_3_dummy2_0$EN, m_m_valid_3_dummy2_0$Q_OUT; // ports of submodule m_m_valid_3_dummy2_1 wire m_m_valid_3_dummy2_1$D_IN, m_m_valid_3_dummy2_1$EN, m_m_valid_3_dummy2_1$Q_OUT; // rule scheduling signals wire CAN_FIRE_RL_m_m_poisoned_0_canon, CAN_FIRE_RL_m_m_poisoned_1_canon, CAN_FIRE_RL_m_m_poisoned_2_canon, CAN_FIRE_RL_m_m_poisoned_3_canon, CAN_FIRE_RL_m_m_setEnqWire, CAN_FIRE_RL_m_m_specBits_0_canon, CAN_FIRE_RL_m_m_specBits_1_canon, CAN_FIRE_RL_m_m_specBits_2_canon, CAN_FIRE_RL_m_m_specBits_3_canon, CAN_FIRE_RL_m_m_valid_0_canon, CAN_FIRE_RL_m_m_valid_1_canon, CAN_FIRE_RL_m_m_valid_2_canon, CAN_FIRE_RL_m_m_valid_3_canon, CAN_FIRE_deq, CAN_FIRE_enq, CAN_FIRE_specUpdate_correctSpeculation, CAN_FIRE_specUpdate_incorrectSpeculation, WILL_FIRE_RL_m_m_poisoned_0_canon, WILL_FIRE_RL_m_m_poisoned_1_canon, WILL_FIRE_RL_m_m_poisoned_2_canon, WILL_FIRE_RL_m_m_poisoned_3_canon, WILL_FIRE_RL_m_m_setEnqWire, WILL_FIRE_RL_m_m_specBits_0_canon, WILL_FIRE_RL_m_m_specBits_1_canon, WILL_FIRE_RL_m_m_specBits_2_canon, WILL_FIRE_RL_m_m_specBits_3_canon, WILL_FIRE_RL_m_m_valid_0_canon, WILL_FIRE_RL_m_m_valid_1_canon, WILL_FIRE_RL_m_m_valid_2_canon, WILL_FIRE_RL_m_m_valid_3_canon, WILL_FIRE_deq, WILL_FIRE_enq, WILL_FIRE_specUpdate_correctSpeculation, WILL_FIRE_specUpdate_incorrectSpeculation; // remaining internal signals reg [11 : 0] SEL_ARR_IF_m_m_specBits_0_dummy2_0_read__28_AN_ETC___d245; reg [6 : 0] SEL_ARR_m_m_row_0_27_BITS_19_TO_13_92_m_m_row__ETC___d197; reg [5 : 0] SEL_ARR_m_m_row_0_27_BITS_5_TO_0_19_m_m_row_1__ETC___d224; reg [4 : 0] SEL_ARR_m_m_row_0_27_BITS_10_TO_6_13_m_m_row_1_ETC___d218; reg [2 : 0] SEL_ARR_m_m_row_0_27_BITS_30_TO_28_28_m_m_row__ETC___d136; reg SEL_ARR_NOT_m_m_row_0_27_BIT_20_81_82_NOT_m_m__ETC___d190, SEL_ARR_m_m_row_0_27_BIT_11_07_m_m_row_1_29_BI_ETC___d212, SEL_ARR_m_m_row_0_27_BIT_12_98_m_m_row_1_29_BI_ETC___d203, SEL_ARR_m_m_row_0_27_BIT_21_75_m_m_row_1_29_BI_ETC___d180, SEL_ARR_m_m_row_0_27_BIT_22_67_m_m_row_1_29_BI_ETC___d172, SEL_ARR_m_m_row_0_27_BIT_23_61_m_m_row_1_29_BI_ETC___d166, SEL_ARR_m_m_row_0_27_BIT_24_55_m_m_row_1_29_BI_ETC___d160, SEL_ARR_m_m_row_0_27_BIT_25_49_m_m_row_1_29_BI_ETC___d154, SEL_ARR_m_m_row_0_27_BIT_26_43_m_m_row_1_29_BI_ETC___d148, SEL_ARR_m_m_row_0_27_BIT_27_37_m_m_row_1_29_BI_ETC___d142; wire [11 : 0] IF_m_m_specBits_0_lat_0_whas__9_THEN_m_m_specB_ETC___d62, IF_m_m_specBits_1_lat_0_whas__6_THEN_m_m_specB_ETC___d69, IF_m_m_specBits_2_lat_0_whas__3_THEN_m_m_specB_ETC___d76, IF_m_m_specBits_3_lat_0_whas__0_THEN_m_m_specB_ETC___d83, bs__h19541, bs__h19773, bs__h20005, bs__h20237, n__read__h20527, n__read__h20968, n__read__h21409, n__read__h21850, upd__h10415, upd__h11344, upd__h12273, upd__h9486; // action method enq assign RDY_enq = !m_m_valid_for_enq_wire$wget ; assign CAN_FIRE_enq = !m_m_valid_for_enq_wire$wget ; assign WILL_FIRE_enq = EN_enq ; // action method deq always@(m_m_deqP or m_m_valid_0_dummy2_0$Q_OUT or m_m_valid_0_dummy2_1$Q_OUT or m_m_valid_0_rl or m_m_valid_1_dummy2_0$Q_OUT or m_m_valid_1_dummy2_1$Q_OUT or m_m_valid_1_rl or m_m_valid_2_dummy2_0$Q_OUT or m_m_valid_2_dummy2_1$Q_OUT or m_m_valid_2_rl or m_m_valid_3_dummy2_0$Q_OUT or m_m_valid_3_dummy2_1$Q_OUT or m_m_valid_3_rl) begin case (m_m_deqP) 2'd0: RDY_deq = m_m_valid_0_dummy2_0$Q_OUT && m_m_valid_0_dummy2_1$Q_OUT && m_m_valid_0_rl; 2'd1: RDY_deq = m_m_valid_1_dummy2_0$Q_OUT && m_m_valid_1_dummy2_1$Q_OUT && m_m_valid_1_rl; 2'd2: RDY_deq = m_m_valid_2_dummy2_0$Q_OUT && m_m_valid_2_dummy2_1$Q_OUT && m_m_valid_2_rl; 2'd3: RDY_deq = m_m_valid_3_dummy2_0$Q_OUT && m_m_valid_3_dummy2_1$Q_OUT && m_m_valid_3_rl; endcase end assign CAN_FIRE_deq = RDY_deq ; assign WILL_FIRE_deq = EN_deq ; // value method first_data assign first_data = { SEL_ARR_m_m_row_0_27_BITS_30_TO_28_28_m_m_row__ETC___d136, SEL_ARR_m_m_row_0_27_BIT_27_37_m_m_row_1_29_BI_ETC___d142, SEL_ARR_m_m_row_0_27_BIT_26_43_m_m_row_1_29_BI_ETC___d148, SEL_ARR_m_m_row_0_27_BIT_25_49_m_m_row_1_29_BI_ETC___d154, SEL_ARR_m_m_row_0_27_BIT_24_55_m_m_row_1_29_BI_ETC___d160, SEL_ARR_m_m_row_0_27_BIT_23_61_m_m_row_1_29_BI_ETC___d166, SEL_ARR_m_m_row_0_27_BIT_22_67_m_m_row_1_29_BI_ETC___d172, SEL_ARR_m_m_row_0_27_BIT_21_75_m_m_row_1_29_BI_ETC___d180, !SEL_ARR_NOT_m_m_row_0_27_BIT_20_81_82_NOT_m_m__ETC___d190, SEL_ARR_m_m_row_0_27_BITS_19_TO_13_92_m_m_row__ETC___d197, SEL_ARR_m_m_row_0_27_BIT_12_98_m_m_row_1_29_BI_ETC___d203, SEL_ARR_m_m_row_0_27_BIT_11_07_m_m_row_1_29_BI_ETC___d212, SEL_ARR_m_m_row_0_27_BITS_10_TO_6_13_m_m_row_1_ETC___d218, SEL_ARR_m_m_row_0_27_BITS_5_TO_0_19_m_m_row_1__ETC___d224, SEL_ARR_IF_m_m_specBits_0_dummy2_0_read__28_AN_ETC___d245 } ; assign RDY_first_data = RDY_deq ; // value method first_poisoned always@(m_m_deqP or m_m_poisoned_0_dummy2_0$Q_OUT or m_m_poisoned_0_dummy2_1$Q_OUT or m_m_poisoned_0_rl or m_m_poisoned_1_dummy2_0$Q_OUT or m_m_poisoned_1_dummy2_1$Q_OUT or m_m_poisoned_1_rl or m_m_poisoned_2_dummy2_0$Q_OUT or m_m_poisoned_2_dummy2_1$Q_OUT or m_m_poisoned_2_rl or m_m_poisoned_3_dummy2_0$Q_OUT or m_m_poisoned_3_dummy2_1$Q_OUT or m_m_poisoned_3_rl) begin case (m_m_deqP) 2'd0: first_poisoned = m_m_poisoned_0_dummy2_0$Q_OUT && m_m_poisoned_0_dummy2_1$Q_OUT && m_m_poisoned_0_rl; 2'd1: first_poisoned = m_m_poisoned_1_dummy2_0$Q_OUT && m_m_poisoned_1_dummy2_1$Q_OUT && m_m_poisoned_1_rl; 2'd2: first_poisoned = m_m_poisoned_2_dummy2_0$Q_OUT && m_m_poisoned_2_dummy2_1$Q_OUT && m_m_poisoned_2_rl; 2'd3: first_poisoned = m_m_poisoned_3_dummy2_0$Q_OUT && m_m_poisoned_3_dummy2_1$Q_OUT && m_m_poisoned_3_rl; endcase end assign RDY_first_poisoned = RDY_deq ; // action method specUpdate_incorrectSpeculation assign RDY_specUpdate_incorrectSpeculation = 1'd1 ; assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ; assign WILL_FIRE_specUpdate_incorrectSpeculation = EN_specUpdate_incorrectSpeculation ; // action method specUpdate_correctSpeculation assign RDY_specUpdate_correctSpeculation = 1'd1 ; assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ; assign WILL_FIRE_specUpdate_correctSpeculation = EN_specUpdate_correctSpeculation ; // submodule m_m_poisoned_0_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_0_dummy2_0(.CLK(CLK), .D_IN(m_m_poisoned_0_dummy2_0$D_IN), .EN(m_m_poisoned_0_dummy2_0$EN), .Q_OUT(m_m_poisoned_0_dummy2_0$Q_OUT)); // submodule m_m_poisoned_0_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_0_dummy2_1(.CLK(CLK), .D_IN(m_m_poisoned_0_dummy2_1$D_IN), .EN(m_m_poisoned_0_dummy2_1$EN), .Q_OUT(m_m_poisoned_0_dummy2_1$Q_OUT)); // submodule m_m_poisoned_1_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_1_dummy2_0(.CLK(CLK), .D_IN(m_m_poisoned_1_dummy2_0$D_IN), .EN(m_m_poisoned_1_dummy2_0$EN), .Q_OUT(m_m_poisoned_1_dummy2_0$Q_OUT)); // submodule m_m_poisoned_1_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_1_dummy2_1(.CLK(CLK), .D_IN(m_m_poisoned_1_dummy2_1$D_IN), .EN(m_m_poisoned_1_dummy2_1$EN), .Q_OUT(m_m_poisoned_1_dummy2_1$Q_OUT)); // submodule m_m_poisoned_2_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_2_dummy2_0(.CLK(CLK), .D_IN(m_m_poisoned_2_dummy2_0$D_IN), .EN(m_m_poisoned_2_dummy2_0$EN), .Q_OUT(m_m_poisoned_2_dummy2_0$Q_OUT)); // submodule m_m_poisoned_2_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_2_dummy2_1(.CLK(CLK), .D_IN(m_m_poisoned_2_dummy2_1$D_IN), .EN(m_m_poisoned_2_dummy2_1$EN), .Q_OUT(m_m_poisoned_2_dummy2_1$Q_OUT)); // submodule m_m_poisoned_3_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_3_dummy2_0(.CLK(CLK), .D_IN(m_m_poisoned_3_dummy2_0$D_IN), .EN(m_m_poisoned_3_dummy2_0$EN), .Q_OUT(m_m_poisoned_3_dummy2_0$Q_OUT)); // submodule m_m_poisoned_3_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_poisoned_3_dummy2_1(.CLK(CLK), .D_IN(m_m_poisoned_3_dummy2_1$D_IN), .EN(m_m_poisoned_3_dummy2_1$EN), .Q_OUT(m_m_poisoned_3_dummy2_1$Q_OUT)); // submodule m_m_specBits_0_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_0(.CLK(CLK), .D_IN(m_m_specBits_0_dummy2_0$D_IN), .EN(m_m_specBits_0_dummy2_0$EN), .Q_OUT(m_m_specBits_0_dummy2_0$Q_OUT)); // submodule m_m_specBits_0_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_1(.CLK(CLK), .D_IN(m_m_specBits_0_dummy2_1$D_IN), .EN(m_m_specBits_0_dummy2_1$EN), .Q_OUT(m_m_specBits_0_dummy2_1$Q_OUT)); // submodule m_m_specBits_1_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_1_dummy2_0(.CLK(CLK), .D_IN(m_m_specBits_1_dummy2_0$D_IN), .EN(m_m_specBits_1_dummy2_0$EN), .Q_OUT(m_m_specBits_1_dummy2_0$Q_OUT)); // submodule m_m_specBits_1_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_1_dummy2_1(.CLK(CLK), .D_IN(m_m_specBits_1_dummy2_1$D_IN), .EN(m_m_specBits_1_dummy2_1$EN), .Q_OUT(m_m_specBits_1_dummy2_1$Q_OUT)); // submodule m_m_specBits_2_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_2_dummy2_0(.CLK(CLK), .D_IN(m_m_specBits_2_dummy2_0$D_IN), .EN(m_m_specBits_2_dummy2_0$EN), .Q_OUT(m_m_specBits_2_dummy2_0$Q_OUT)); // submodule m_m_specBits_2_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_2_dummy2_1(.CLK(CLK), .D_IN(m_m_specBits_2_dummy2_1$D_IN), .EN(m_m_specBits_2_dummy2_1$EN), .Q_OUT(m_m_specBits_2_dummy2_1$Q_OUT)); // submodule m_m_specBits_3_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_3_dummy2_0(.CLK(CLK), .D_IN(m_m_specBits_3_dummy2_0$D_IN), .EN(m_m_specBits_3_dummy2_0$EN), .Q_OUT(m_m_specBits_3_dummy2_0$Q_OUT)); // submodule m_m_specBits_3_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_3_dummy2_1(.CLK(CLK), .D_IN(m_m_specBits_3_dummy2_1$D_IN), .EN(m_m_specBits_3_dummy2_1$EN), .Q_OUT(m_m_specBits_3_dummy2_1$Q_OUT)); // submodule m_m_valid_0_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_0(.CLK(CLK), .D_IN(m_m_valid_0_dummy2_0$D_IN), .EN(m_m_valid_0_dummy2_0$EN), .Q_OUT(m_m_valid_0_dummy2_0$Q_OUT)); // submodule m_m_valid_0_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_1(.CLK(CLK), .D_IN(m_m_valid_0_dummy2_1$D_IN), .EN(m_m_valid_0_dummy2_1$EN), .Q_OUT(m_m_valid_0_dummy2_1$Q_OUT)); // submodule m_m_valid_1_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_1_dummy2_0(.CLK(CLK), .D_IN(m_m_valid_1_dummy2_0$D_IN), .EN(m_m_valid_1_dummy2_0$EN), .Q_OUT(m_m_valid_1_dummy2_0$Q_OUT)); // submodule m_m_valid_1_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_1_dummy2_1(.CLK(CLK), .D_IN(m_m_valid_1_dummy2_1$D_IN), .EN(m_m_valid_1_dummy2_1$EN), .Q_OUT(m_m_valid_1_dummy2_1$Q_OUT)); // submodule m_m_valid_2_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_2_dummy2_0(.CLK(CLK), .D_IN(m_m_valid_2_dummy2_0$D_IN), .EN(m_m_valid_2_dummy2_0$EN), .Q_OUT(m_m_valid_2_dummy2_0$Q_OUT)); // submodule m_m_valid_2_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_2_dummy2_1(.CLK(CLK), .D_IN(m_m_valid_2_dummy2_1$D_IN), .EN(m_m_valid_2_dummy2_1$EN), .Q_OUT(m_m_valid_2_dummy2_1$Q_OUT)); // submodule m_m_valid_3_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_3_dummy2_0(.CLK(CLK), .D_IN(m_m_valid_3_dummy2_0$D_IN), .EN(m_m_valid_3_dummy2_0$EN), .Q_OUT(m_m_valid_3_dummy2_0$Q_OUT)); // submodule m_m_valid_3_dummy2_1 RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_3_dummy2_1(.CLK(CLK), .D_IN(m_m_valid_3_dummy2_1$D_IN), .EN(m_m_valid_3_dummy2_1$EN), .Q_OUT(m_m_valid_3_dummy2_1$Q_OUT)); // rule RL_m_m_setEnqWire assign CAN_FIRE_RL_m_m_setEnqWire = 1'd1 ; assign WILL_FIRE_RL_m_m_setEnqWire = 1'd1 ; // rule RL_m_m_valid_0_canon assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ; // rule RL_m_m_valid_1_canon assign CAN_FIRE_RL_m_m_valid_1_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_valid_1_canon = 1'd1 ; // rule RL_m_m_valid_2_canon assign CAN_FIRE_RL_m_m_valid_2_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_valid_2_canon = 1'd1 ; // rule RL_m_m_valid_3_canon assign CAN_FIRE_RL_m_m_valid_3_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_valid_3_canon = 1'd1 ; // rule RL_m_m_poisoned_0_canon assign CAN_FIRE_RL_m_m_poisoned_0_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_poisoned_0_canon = 1'd1 ; // rule RL_m_m_poisoned_1_canon assign CAN_FIRE_RL_m_m_poisoned_1_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_poisoned_1_canon = 1'd1 ; // rule RL_m_m_poisoned_2_canon assign CAN_FIRE_RL_m_m_poisoned_2_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_poisoned_2_canon = 1'd1 ; // rule RL_m_m_poisoned_3_canon assign CAN_FIRE_RL_m_m_poisoned_3_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_poisoned_3_canon = 1'd1 ; // rule RL_m_m_specBits_0_canon assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ; // rule RL_m_m_specBits_1_canon assign CAN_FIRE_RL_m_m_specBits_1_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_specBits_1_canon = 1'd1 ; // rule RL_m_m_specBits_2_canon assign CAN_FIRE_RL_m_m_specBits_2_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_specBits_2_canon = 1'd1 ; // rule RL_m_m_specBits_3_canon assign CAN_FIRE_RL_m_m_specBits_3_canon = 1'd1 ; assign WILL_FIRE_RL_m_m_specBits_3_canon = 1'd1 ; // inlined wires assign m_m_valid_0_lat_0$whas = EN_deq && m_m_deqP == 2'd0 ; assign m_m_valid_0_lat_1$whas = EN_enq && m_m_enqP == 2'd0 ; assign m_m_valid_1_lat_0$whas = EN_deq && m_m_deqP == 2'd1 ; assign m_m_valid_1_lat_1$whas = EN_enq && m_m_enqP == 2'd1 ; assign m_m_valid_2_lat_0$whas = EN_deq && m_m_deqP == 2'd2 ; assign m_m_valid_2_lat_1$whas = EN_enq && m_m_enqP == 2'd2 ; assign m_m_valid_3_lat_0$whas = EN_deq && m_m_deqP == 2'd3 ; assign m_m_valid_3_lat_1$whas = EN_enq && m_m_enqP == 2'd3 ; assign m_m_poisoned_0_lat_0$whas = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h19541[specUpdate_incorrectSpeculation_kill_tag]) ; assign m_m_poisoned_1_lat_0$whas = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h19773[specUpdate_incorrectSpeculation_kill_tag]) ; assign m_m_poisoned_2_lat_0$whas = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h20005[specUpdate_incorrectSpeculation_kill_tag]) ; assign m_m_poisoned_3_lat_0$whas = EN_specUpdate_incorrectSpeculation && (specUpdate_incorrectSpeculation_kill_all || bs__h20237[specUpdate_incorrectSpeculation_kill_tag]) ; assign m_m_specBits_0_lat_1$wget = n__read__h20527 & specUpdate_correctSpeculation_mask ; assign m_m_specBits_1_lat_1$wget = n__read__h20968 & specUpdate_correctSpeculation_mask ; always@(m_m_enqP or m_m_valid_0_dummy2_0$Q_OUT or m_m_valid_0_dummy2_1$Q_OUT or m_m_valid_0_rl or m_m_valid_1_dummy2_0$Q_OUT or m_m_valid_1_dummy2_1$Q_OUT or m_m_valid_1_rl or m_m_valid_2_dummy2_0$Q_OUT or m_m_valid_2_dummy2_1$Q_OUT or m_m_valid_2_rl or m_m_valid_3_dummy2_0$Q_OUT or m_m_valid_3_dummy2_1$Q_OUT or m_m_valid_3_rl) begin case (m_m_enqP) 2'd0: m_m_valid_for_enq_wire$wget = m_m_valid_0_dummy2_0$Q_OUT && m_m_valid_0_dummy2_1$Q_OUT && m_m_valid_0_rl; 2'd1: m_m_valid_for_enq_wire$wget = m_m_valid_1_dummy2_0$Q_OUT && m_m_valid_1_dummy2_1$Q_OUT && m_m_valid_1_rl; 2'd2: m_m_valid_for_enq_wire$wget = m_m_valid_2_dummy2_0$Q_OUT && m_m_valid_2_dummy2_1$Q_OUT && m_m_valid_2_rl; 2'd3: m_m_valid_for_enq_wire$wget = m_m_valid_3_dummy2_0$Q_OUT && m_m_valid_3_dummy2_1$Q_OUT && m_m_valid_3_rl; endcase end // register m_m_deqP assign m_m_deqP$D_IN = (m_m_deqP == 2'd3) ? 2'd0 : m_m_deqP + 2'd1 ; assign m_m_deqP$EN = EN_deq ; // register m_m_enqP assign m_m_enqP$D_IN = (m_m_enqP == 2'd3) ? 2'd0 : m_m_enqP + 2'd1 ; assign m_m_enqP$EN = EN_enq ; // register m_m_poisoned_0_rl assign m_m_poisoned_0_rl$D_IN = !m_m_valid_0_lat_1$whas && (m_m_poisoned_0_lat_0$whas || m_m_poisoned_0_rl) ; assign m_m_poisoned_0_rl$EN = 1'd1 ; // register m_m_poisoned_1_rl assign m_m_poisoned_1_rl$D_IN = !m_m_valid_1_lat_1$whas && (m_m_poisoned_1_lat_0$whas || m_m_poisoned_1_rl) ; assign m_m_poisoned_1_rl$EN = 1'd1 ; // register m_m_poisoned_2_rl assign m_m_poisoned_2_rl$D_IN = !m_m_valid_2_lat_1$whas && (m_m_poisoned_2_lat_0$whas || m_m_poisoned_2_rl) ; assign m_m_poisoned_2_rl$EN = 1'd1 ; // register m_m_poisoned_3_rl assign m_m_poisoned_3_rl$D_IN = !m_m_valid_3_lat_1$whas && (m_m_poisoned_3_lat_0$whas || m_m_poisoned_3_rl) ; assign m_m_poisoned_3_rl$EN = 1'd1 ; // register m_m_row_0 assign m_m_row_0$D_IN = enq_x[42:12] ; assign m_m_row_0$EN = m_m_valid_0_lat_1$whas ; // register m_m_row_1 assign m_m_row_1$D_IN = enq_x[42:12] ; assign m_m_row_1$EN = m_m_valid_1_lat_1$whas ; // register m_m_row_2 assign m_m_row_2$D_IN = enq_x[42:12] ; assign m_m_row_2$EN = m_m_valid_2_lat_1$whas ; // register m_m_row_3 assign m_m_row_3$D_IN = enq_x[42:12] ; assign m_m_row_3$EN = m_m_valid_3_lat_1$whas ; // register m_m_specBits_0_rl assign m_m_specBits_0_rl$D_IN = EN_specUpdate_correctSpeculation ? upd__h9486 : IF_m_m_specBits_0_lat_0_whas__9_THEN_m_m_specB_ETC___d62 ; assign m_m_specBits_0_rl$EN = 1'd1 ; // register m_m_specBits_1_rl assign m_m_specBits_1_rl$D_IN = EN_specUpdate_correctSpeculation ? upd__h10415 : IF_m_m_specBits_1_lat_0_whas__6_THEN_m_m_specB_ETC___d69 ; assign m_m_specBits_1_rl$EN = 1'd1 ; // register m_m_specBits_2_rl assign m_m_specBits_2_rl$D_IN = EN_specUpdate_correctSpeculation ? upd__h11344 : IF_m_m_specBits_2_lat_0_whas__3_THEN_m_m_specB_ETC___d76 ; assign m_m_specBits_2_rl$EN = 1'd1 ; // register m_m_specBits_3_rl assign m_m_specBits_3_rl$D_IN = EN_specUpdate_correctSpeculation ? upd__h12273 : IF_m_m_specBits_3_lat_0_whas__0_THEN_m_m_specB_ETC___d83 ; assign m_m_specBits_3_rl$EN = 1'd1 ; // register m_m_valid_0_rl assign m_m_valid_0_rl$D_IN = m_m_valid_0_lat_1$whas || !m_m_valid_0_lat_0$whas && m_m_valid_0_rl ; assign m_m_valid_0_rl$EN = 1'd1 ; // register m_m_valid_1_rl assign m_m_valid_1_rl$D_IN = m_m_valid_1_lat_1$whas || !m_m_valid_1_lat_0$whas && m_m_valid_1_rl ; assign m_m_valid_1_rl$EN = 1'd1 ; // register m_m_valid_2_rl assign m_m_valid_2_rl$D_IN = m_m_valid_2_lat_1$whas || !m_m_valid_2_lat_0$whas && m_m_valid_2_rl ; assign m_m_valid_2_rl$EN = 1'd1 ; // register m_m_valid_3_rl assign m_m_valid_3_rl$D_IN = m_m_valid_3_lat_1$whas || !m_m_valid_3_lat_0$whas && m_m_valid_3_rl ; assign m_m_valid_3_rl$EN = 1'd1 ; // submodule m_m_poisoned_0_dummy2_0 assign m_m_poisoned_0_dummy2_0$D_IN = 1'd1 ; assign m_m_poisoned_0_dummy2_0$EN = m_m_poisoned_0_lat_0$whas ; // submodule m_m_poisoned_0_dummy2_1 assign m_m_poisoned_0_dummy2_1$D_IN = 1'd1 ; assign m_m_poisoned_0_dummy2_1$EN = m_m_valid_0_lat_1$whas ; // submodule m_m_poisoned_1_dummy2_0 assign m_m_poisoned_1_dummy2_0$D_IN = 1'd1 ; assign m_m_poisoned_1_dummy2_0$EN = m_m_poisoned_1_lat_0$whas ; // submodule m_m_poisoned_1_dummy2_1 assign m_m_poisoned_1_dummy2_1$D_IN = 1'd1 ; assign m_m_poisoned_1_dummy2_1$EN = m_m_valid_1_lat_1$whas ; // submodule m_m_poisoned_2_dummy2_0 assign m_m_poisoned_2_dummy2_0$D_IN = 1'd1 ; assign m_m_poisoned_2_dummy2_0$EN = m_m_poisoned_2_lat_0$whas ; // submodule m_m_poisoned_2_dummy2_1 assign m_m_poisoned_2_dummy2_1$D_IN = 1'd1 ; assign m_m_poisoned_2_dummy2_1$EN = m_m_valid_2_lat_1$whas ; // submodule m_m_poisoned_3_dummy2_0 assign m_m_poisoned_3_dummy2_0$D_IN = 1'd1 ; assign m_m_poisoned_3_dummy2_0$EN = m_m_poisoned_3_lat_0$whas ; // submodule m_m_poisoned_3_dummy2_1 assign m_m_poisoned_3_dummy2_1$D_IN = 1'd1 ; assign m_m_poisoned_3_dummy2_1$EN = m_m_valid_3_lat_1$whas ; // submodule m_m_specBits_0_dummy2_0 assign m_m_specBits_0_dummy2_0$D_IN = 1'd1 ; assign m_m_specBits_0_dummy2_0$EN = m_m_valid_0_lat_1$whas ; // submodule m_m_specBits_0_dummy2_1 assign m_m_specBits_0_dummy2_1$D_IN = 1'd1 ; assign m_m_specBits_0_dummy2_1$EN = EN_specUpdate_correctSpeculation ; // submodule m_m_specBits_1_dummy2_0 assign m_m_specBits_1_dummy2_0$D_IN = 1'd1 ; assign m_m_specBits_1_dummy2_0$EN = m_m_valid_1_lat_1$whas ; // submodule m_m_specBits_1_dummy2_1 assign m_m_specBits_1_dummy2_1$D_IN = 1'd1 ; assign m_m_specBits_1_dummy2_1$EN = EN_specUpdate_correctSpeculation ; // submodule m_m_specBits_2_dummy2_0 assign m_m_specBits_2_dummy2_0$D_IN = 1'd1 ; assign m_m_specBits_2_dummy2_0$EN = m_m_valid_2_lat_1$whas ; // submodule m_m_specBits_2_dummy2_1 assign m_m_specBits_2_dummy2_1$D_IN = 1'd1 ; assign m_m_specBits_2_dummy2_1$EN = EN_specUpdate_correctSpeculation ; // submodule m_m_specBits_3_dummy2_0 assign m_m_specBits_3_dummy2_0$D_IN = 1'd1 ; assign m_m_specBits_3_dummy2_0$EN = m_m_valid_3_lat_1$whas ; // submodule m_m_specBits_3_dummy2_1 assign m_m_specBits_3_dummy2_1$D_IN = 1'd1 ; assign m_m_specBits_3_dummy2_1$EN = EN_specUpdate_correctSpeculation ; // submodule m_m_valid_0_dummy2_0 assign m_m_valid_0_dummy2_0$D_IN = 1'd1 ; assign m_m_valid_0_dummy2_0$EN = m_m_valid_0_lat_0$whas ; // submodule m_m_valid_0_dummy2_1 assign m_m_valid_0_dummy2_1$D_IN = 1'd1 ; assign m_m_valid_0_dummy2_1$EN = m_m_valid_0_lat_1$whas ; // submodule m_m_valid_1_dummy2_0 assign m_m_valid_1_dummy2_0$D_IN = 1'd1 ; assign m_m_valid_1_dummy2_0$EN = m_m_valid_1_lat_0$whas ; // submodule m_m_valid_1_dummy2_1 assign m_m_valid_1_dummy2_1$D_IN = 1'd1 ; assign m_m_valid_1_dummy2_1$EN = m_m_valid_1_lat_1$whas ; // submodule m_m_valid_2_dummy2_0 assign m_m_valid_2_dummy2_0$D_IN = 1'd1 ; assign m_m_valid_2_dummy2_0$EN = m_m_valid_2_lat_0$whas ; // submodule m_m_valid_2_dummy2_1 assign m_m_valid_2_dummy2_1$D_IN = 1'd1 ; assign m_m_valid_2_dummy2_1$EN = m_m_valid_2_lat_1$whas ; // submodule m_m_valid_3_dummy2_0 assign m_m_valid_3_dummy2_0$D_IN = 1'd1 ; assign m_m_valid_3_dummy2_0$EN = m_m_valid_3_lat_0$whas ; // submodule m_m_valid_3_dummy2_1 assign m_m_valid_3_dummy2_1$D_IN = 1'd1 ; assign m_m_valid_3_dummy2_1$EN = m_m_valid_3_lat_1$whas ; // remaining internal signals assign IF_m_m_specBits_0_lat_0_whas__9_THEN_m_m_specB_ETC___d62 = m_m_valid_0_lat_1$whas ? enq_x[11:0] : m_m_specBits_0_rl ; assign IF_m_m_specBits_1_lat_0_whas__6_THEN_m_m_specB_ETC___d69 = m_m_valid_1_lat_1$whas ? enq_x[11:0] : m_m_specBits_1_rl ; assign IF_m_m_specBits_2_lat_0_whas__3_THEN_m_m_specB_ETC___d76 = m_m_valid_2_lat_1$whas ? enq_x[11:0] : m_m_specBits_2_rl ; assign IF_m_m_specBits_3_lat_0_whas__0_THEN_m_m_specB_ETC___d83 = m_m_valid_3_lat_1$whas ? enq_x[11:0] : m_m_specBits_3_rl ; assign bs__h19541 = (m_m_specBits_0_dummy2_0$Q_OUT && m_m_specBits_0_dummy2_1$Q_OUT) ? m_m_specBits_0_rl : 12'd0 ; assign bs__h19773 = (m_m_specBits_1_dummy2_0$Q_OUT && m_m_specBits_1_dummy2_1$Q_OUT) ? m_m_specBits_1_rl : 12'd0 ; assign bs__h20005 = (m_m_specBits_2_dummy2_0$Q_OUT && m_m_specBits_2_dummy2_1$Q_OUT) ? m_m_specBits_2_rl : 12'd0 ; assign bs__h20237 = (m_m_specBits_3_dummy2_0$Q_OUT && m_m_specBits_3_dummy2_1$Q_OUT) ? m_m_specBits_3_rl : 12'd0 ; assign n__read__h20527 = m_m_specBits_0_dummy2_1$Q_OUT ? IF_m_m_specBits_0_lat_0_whas__9_THEN_m_m_specB_ETC___d62 : 12'd0 ; assign n__read__h20968 = m_m_specBits_1_dummy2_1$Q_OUT ? IF_m_m_specBits_1_lat_0_whas__6_THEN_m_m_specB_ETC___d69 : 12'd0 ; assign n__read__h21409 = m_m_specBits_2_dummy2_1$Q_OUT ? IF_m_m_specBits_2_lat_0_whas__3_THEN_m_m_specB_ETC___d76 : 12'd0 ; assign n__read__h21850 = m_m_specBits_3_dummy2_1$Q_OUT ? IF_m_m_specBits_3_lat_0_whas__0_THEN_m_m_specB_ETC___d83 : 12'd0 ; assign upd__h10415 = m_m_specBits_1_lat_1$wget ; assign upd__h11344 = n__read__h21409 & specUpdate_correctSpeculation_mask ; assign upd__h12273 = n__read__h21850 & specUpdate_correctSpeculation_mask ; assign upd__h9486 = m_m_specBits_0_lat_1$wget ; always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_NOT_m_m_row_0_27_BIT_20_81_82_NOT_m_m__ETC___d190 = !m_m_row_0[20]; 2'd1: SEL_ARR_NOT_m_m_row_0_27_BIT_20_81_82_NOT_m_m__ETC___d190 = !m_m_row_1[20]; 2'd2: SEL_ARR_NOT_m_m_row_0_27_BIT_20_81_82_NOT_m_m__ETC___d190 = !m_m_row_2[20]; 2'd3: SEL_ARR_NOT_m_m_row_0_27_BIT_20_81_82_NOT_m_m__ETC___d190 = !m_m_row_3[20]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_24_55_m_m_row_1_29_BI_ETC___d160 = m_m_row_0[24]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_24_55_m_m_row_1_29_BI_ETC___d160 = m_m_row_1[24]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_24_55_m_m_row_1_29_BI_ETC___d160 = m_m_row_2[24]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_24_55_m_m_row_1_29_BI_ETC___d160 = m_m_row_3[24]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_23_61_m_m_row_1_29_BI_ETC___d166 = m_m_row_0[23]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_23_61_m_m_row_1_29_BI_ETC___d166 = m_m_row_1[23]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_23_61_m_m_row_1_29_BI_ETC___d166 = m_m_row_2[23]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_23_61_m_m_row_1_29_BI_ETC___d166 = m_m_row_3[23]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_26_43_m_m_row_1_29_BI_ETC___d148 = m_m_row_0[26]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_26_43_m_m_row_1_29_BI_ETC___d148 = m_m_row_1[26]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_26_43_m_m_row_1_29_BI_ETC___d148 = m_m_row_2[26]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_26_43_m_m_row_1_29_BI_ETC___d148 = m_m_row_3[26]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_22_67_m_m_row_1_29_BI_ETC___d172 = m_m_row_0[22]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_22_67_m_m_row_1_29_BI_ETC___d172 = m_m_row_1[22]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_22_67_m_m_row_1_29_BI_ETC___d172 = m_m_row_2[22]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_22_67_m_m_row_1_29_BI_ETC___d172 = m_m_row_3[22]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_25_49_m_m_row_1_29_BI_ETC___d154 = m_m_row_0[25]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_25_49_m_m_row_1_29_BI_ETC___d154 = m_m_row_1[25]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_25_49_m_m_row_1_29_BI_ETC___d154 = m_m_row_2[25]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_25_49_m_m_row_1_29_BI_ETC___d154 = m_m_row_3[25]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BITS_19_TO_13_92_m_m_row__ETC___d197 = m_m_row_0[19:13]; 2'd1: SEL_ARR_m_m_row_0_27_BITS_19_TO_13_92_m_m_row__ETC___d197 = m_m_row_1[19:13]; 2'd2: SEL_ARR_m_m_row_0_27_BITS_19_TO_13_92_m_m_row__ETC___d197 = m_m_row_2[19:13]; 2'd3: SEL_ARR_m_m_row_0_27_BITS_19_TO_13_92_m_m_row__ETC___d197 = m_m_row_3[19:13]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_12_98_m_m_row_1_29_BI_ETC___d203 = m_m_row_0[12]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_12_98_m_m_row_1_29_BI_ETC___d203 = m_m_row_1[12]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_12_98_m_m_row_1_29_BI_ETC___d203 = m_m_row_2[12]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_12_98_m_m_row_1_29_BI_ETC___d203 = m_m_row_3[12]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_11_07_m_m_row_1_29_BI_ETC___d212 = m_m_row_0[11]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_11_07_m_m_row_1_29_BI_ETC___d212 = m_m_row_1[11]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_11_07_m_m_row_1_29_BI_ETC___d212 = m_m_row_2[11]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_11_07_m_m_row_1_29_BI_ETC___d212 = m_m_row_3[11]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BITS_10_TO_6_13_m_m_row_1_ETC___d218 = m_m_row_0[10:6]; 2'd1: SEL_ARR_m_m_row_0_27_BITS_10_TO_6_13_m_m_row_1_ETC___d218 = m_m_row_1[10:6]; 2'd2: SEL_ARR_m_m_row_0_27_BITS_10_TO_6_13_m_m_row_1_ETC___d218 = m_m_row_2[10:6]; 2'd3: SEL_ARR_m_m_row_0_27_BITS_10_TO_6_13_m_m_row_1_ETC___d218 = m_m_row_3[10:6]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BITS_5_TO_0_19_m_m_row_1__ETC___d224 = m_m_row_0[5:0]; 2'd1: SEL_ARR_m_m_row_0_27_BITS_5_TO_0_19_m_m_row_1__ETC___d224 = m_m_row_1[5:0]; 2'd2: SEL_ARR_m_m_row_0_27_BITS_5_TO_0_19_m_m_row_1__ETC___d224 = m_m_row_2[5:0]; 2'd3: SEL_ARR_m_m_row_0_27_BITS_5_TO_0_19_m_m_row_1__ETC___d224 = m_m_row_3[5:0]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_21_75_m_m_row_1_29_BI_ETC___d180 = m_m_row_0[21]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_21_75_m_m_row_1_29_BI_ETC___d180 = m_m_row_1[21]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_21_75_m_m_row_1_29_BI_ETC___d180 = m_m_row_2[21]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_21_75_m_m_row_1_29_BI_ETC___d180 = m_m_row_3[21]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BIT_27_37_m_m_row_1_29_BI_ETC___d142 = m_m_row_0[27]; 2'd1: SEL_ARR_m_m_row_0_27_BIT_27_37_m_m_row_1_29_BI_ETC___d142 = m_m_row_1[27]; 2'd2: SEL_ARR_m_m_row_0_27_BIT_27_37_m_m_row_1_29_BI_ETC___d142 = m_m_row_2[27]; 2'd3: SEL_ARR_m_m_row_0_27_BIT_27_37_m_m_row_1_29_BI_ETC___d142 = m_m_row_3[27]; endcase end always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3) begin case (m_m_deqP) 2'd0: SEL_ARR_m_m_row_0_27_BITS_30_TO_28_28_m_m_row__ETC___d136 = m_m_row_0[30:28]; 2'd1: SEL_ARR_m_m_row_0_27_BITS_30_TO_28_28_m_m_row__ETC___d136 = m_m_row_1[30:28]; 2'd2: SEL_ARR_m_m_row_0_27_BITS_30_TO_28_28_m_m_row__ETC___d136 = m_m_row_2[30:28]; 2'd3: SEL_ARR_m_m_row_0_27_BITS_30_TO_28_28_m_m_row__ETC___d136 = m_m_row_3[30:28]; endcase end always@(m_m_deqP or bs__h19541 or bs__h19773 or bs__h20005 or bs__h20237) begin case (m_m_deqP) 2'd0: SEL_ARR_IF_m_m_specBits_0_dummy2_0_read__28_AN_ETC___d245 = bs__h19541; 2'd1: SEL_ARR_IF_m_m_specBits_0_dummy2_0_read__28_AN_ETC___d245 = bs__h19773; 2'd2: SEL_ARR_IF_m_m_specBits_0_dummy2_0_read__28_AN_ETC___d245 = bs__h20005; 2'd3: SEL_ARR_IF_m_m_specBits_0_dummy2_0_read__28_AN_ETC___d245 = bs__h20237; endcase end // handling of inlined registers always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin m_m_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0; m_m_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0; m_m_poisoned_0_rl <= `BSV_ASSIGNMENT_DELAY 1'h0; m_m_poisoned_1_rl <= `BSV_ASSIGNMENT_DELAY 1'h0; m_m_poisoned_2_rl <= `BSV_ASSIGNMENT_DELAY 1'h0; m_m_poisoned_3_rl <= `BSV_ASSIGNMENT_DELAY 1'h0; m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA; m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA; m_m_specBits_2_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA; m_m_specBits_3_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA; m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; m_m_valid_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; m_m_valid_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (m_m_deqP$EN) m_m_deqP <= `BSV_ASSIGNMENT_DELAY m_m_deqP$D_IN; if (m_m_enqP$EN) m_m_enqP <= `BSV_ASSIGNMENT_DELAY m_m_enqP$D_IN; if (m_m_poisoned_0_rl$EN) m_m_poisoned_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_0_rl$D_IN; if (m_m_poisoned_1_rl$EN) m_m_poisoned_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_1_rl$D_IN; if (m_m_poisoned_2_rl$EN) m_m_poisoned_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_2_rl$D_IN; if (m_m_poisoned_3_rl$EN) m_m_poisoned_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_3_rl$D_IN; if (m_m_specBits_0_rl$EN) m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN; if (m_m_specBits_1_rl$EN) m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_1_rl$D_IN; if (m_m_specBits_2_rl$EN) m_m_specBits_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_2_rl$D_IN; if (m_m_specBits_3_rl$EN) m_m_specBits_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_3_rl$D_IN; if (m_m_valid_0_rl$EN) m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN; if (m_m_valid_1_rl$EN) m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_1_rl$D_IN; if (m_m_valid_2_rl$EN) m_m_valid_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_2_rl$D_IN; if (m_m_valid_3_rl$EN) m_m_valid_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_3_rl$D_IN; end if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN; if (m_m_row_1$EN) m_m_row_1 <= `BSV_ASSIGNMENT_DELAY m_m_row_1$D_IN; if (m_m_row_2$EN) m_m_row_2 <= `BSV_ASSIGNMENT_DELAY m_m_row_2$D_IN; if (m_m_row_3$EN) m_m_row_3 <= `BSV_ASSIGNMENT_DELAY m_m_row_3$D_IN; end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin m_m_deqP = 2'h2; m_m_enqP = 2'h2; m_m_poisoned_0_rl = 1'h0; m_m_poisoned_1_rl = 1'h0; m_m_poisoned_2_rl = 1'h0; m_m_poisoned_3_rl = 1'h0; m_m_row_0 = 31'h2AAAAAAA; m_m_row_1 = 31'h2AAAAAAA; m_m_row_2 = 31'h2AAAAAAA; m_m_row_3 = 31'h2AAAAAAA; m_m_specBits_0_rl = 12'hAAA; m_m_specBits_1_rl = 12'hAAA; m_m_specBits_2_rl = 12'hAAA; m_m_specBits_3_rl = 12'hAAA; m_m_valid_0_rl = 1'h0; m_m_valid_1_rl = 1'h0; m_m_valid_2_rl = 1'h0; m_m_valid_3_rl = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on endmodule // mkFmaExecQ