146 lines
4.2 KiB
Verilog
146 lines
4.2 KiB
Verilog
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// Copyright (c) 2000-2012 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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// Bluespec primitive module which allows creation of clocks
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// with non-constant periods. The CLK_IN and COND_IN inputs
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// are registered and used to compute the CLK_OUT and
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// CLK_GATE_OUT outputs.
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module MakeClock ( CLK, RST,
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CLK_IN, CLK_IN_EN,
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COND_IN, COND_IN_EN,
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CLK_VAL_OUT, COND_OUT,
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CLK_OUT, CLK_GATE_OUT );
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parameter initVal = 0;
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parameter initGate = 1;
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input CLK;
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input RST;
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input CLK_IN;
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input CLK_IN_EN;
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input COND_IN;
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input COND_IN_EN;
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output CLK_VAL_OUT;
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output COND_OUT;
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output CLK_OUT;
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output CLK_GATE_OUT;
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reg current_clk;
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reg CLK_VAL_OUT;
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reg current_gate;
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reg new_gate;
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// The use of blocking assignment within this block insures
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// that the clock generated from the generate clock (current_clK) occurs before any
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// LHS of nonblocking assigments also from CLKoccur.
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// Basically, this insures that CLK_OUT and CLK occur within
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// the same phase of the execution cycle, before any state
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// updates occur. see
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// http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
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always @(posedge CLK or `BSV_RESET_EDGE RST)
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begin
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if (RST == `BSV_RESET_VALUE)
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begin
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current_clk = initVal;
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end
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else
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begin
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if (CLK_IN_EN)
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current_clk = CLK_IN;
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end
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end
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// Duplicate flop for DRC -- clocks cannot be used as data
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always @(posedge CLK or `BSV_RESET_EDGE RST)
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begin
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if (RST == `BSV_RESET_VALUE)
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begin
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CLK_VAL_OUT <= `BSV_ASSIGNMENT_DELAY initVal;
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end
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else
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begin
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if (CLK_IN_EN)
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CLK_VAL_OUT <= `BSV_ASSIGNMENT_DELAY CLK_IN;
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end
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end
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always @(posedge CLK or `BSV_RESET_EDGE RST)
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begin
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if (RST == `BSV_RESET_VALUE)
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new_gate <= `BSV_ASSIGNMENT_DELAY initGate;
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else
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begin
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if (COND_IN_EN)
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new_gate <= `BSV_ASSIGNMENT_DELAY COND_IN;
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end
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end
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// Use latch to avoid glitches
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// Gate can only change when clock is low
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// There remains a fundamental race condition in this design, which
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// is triggered when the current_clk rises and the the new_gate
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// changes. We recommend to avoid changing the gate in the same
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// cycle when the clock rises.
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always @( current_clk or new_gate )
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begin
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if (current_clk == 1'b0)
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current_gate <= `BSV_ASSIGNMENT_DELAY new_gate ;
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end
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assign CLK_OUT = current_clk && current_gate;
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assign CLK_GATE_OUT = current_gate;
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assign COND_OUT = new_gate;
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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// synopsys translate_off
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initial begin
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#0 ;
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current_clk = 1'b0 ;
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current_gate = 1'b1 ;
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new_gate = 1'b1 ;
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CLK_VAL_OUT = 1'b0;
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end
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// synopsys translate_on
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`endif // BSV_NO_INITIAL_BLOCKS
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endmodule
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