If DRAM latency is too high and the cache is performing frequent writes,
it would be possible to overflow this counter, which means we don't rate
limit, the cache could erroneously believe it's safe to do I/O
accesses/cache refills/page table walks, and the cache would block due
to the guard on decr when it finally gets enough write responses back.
We should block the incr method to automatically stall the cache until
it receives a new write response.
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