52 lines
1014 B
Plaintext
52 lines
1014 B
Plaintext
package PowerOnReset;
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import Clocks::*;
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UInt#(8) resetCycles = 10;
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import "BVI" RegUNInit =
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module mkRegUNInit#(parameter a init) (Reg#(a))
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provisos (Bits#(a,sa));
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parameter width = valueOf(sa);
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parameter init = pack(init);
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default_clock clk(CLK, (*unused*)CLK_GATE);
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no_reset;
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method Q_OUT _read();
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method _write(D_IN) enable(EN);
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schedule _read CF _read;
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schedule _write SBR _write;
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schedule _read SB _write;
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endmodule
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import "BVI" ASSIGN1 =
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module mkBoolToReset#(Bool xin) (ResetGenIfc);
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default_clock ();
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no_reset;
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port IN = xin;
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output_reset gen_rst(OUT);
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endmodule
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(*synthesize*)
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module mkPowerOnReset (ResetGenIfc);
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Reg#(UInt#(8)) ctr <- mkRegUNInit(resetCycles);
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Reg#(Bool) isInPowerOnReset <- mkRegUNInit(True);
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rule countDown(isInPowerOnReset);
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let n = ctr - 1;
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ctr <= n;
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if (n==0) isInPowerOnReset <= False;
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endrule
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let rst_ifc <- mkBoolToReset(!isInPowerOnReset);
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return rst_ifc;
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endmodule
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endpackage
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