Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
Files
master
Toooba/src_bsc_lib_RTL
History
Jessica Clarke 3add2cac5e Move MakeReset0.v to src_bsc_lib_RTL like Piccolo and Flute 
This ensures it's shared across all simulator builds.
2020-04-16 17:19:16 +01:00
..
BRAM2.v
Initial load of files
2019-03-26 14:49:40 -04:00
FIFO1.v
Initial load of files
2019-03-26 14:49:40 -04:00
FIFO2.v
Initial load of files
2019-03-26 14:49:40 -04:00
FIFO10.v
Initial load of files
2019-03-26 14:49:40 -04:00
FIFO20.v
Initial load of files
2019-03-26 14:49:40 -04:00
FIFOL1.v
Initial load of files
2019-03-26 14:49:40 -04:00
main.v
Initial load of files
2019-03-26 14:49:40 -04:00
MakeClock.v
Add support for external debug module.
2019-04-09 14:08:36 -04:00
MakeReset0.v
Move MakeReset0.v to src_bsc_lib_RTL like Piccolo and Flute
2020-04-16 17:19:16 +01:00
MakeResetA.v
Add support for external debug module.
2019-04-09 14:08:36 -04:00
README.txt
Initial load of files
2019-03-26 14:49:40 -04:00
RegFile.v
Initial load of files
2019-03-26 14:49:40 -04:00
RegFileLoad.v
Initial load of files
2019-03-26 14:49:40 -04:00
ResetEither.v
Add support for external debug module.
2019-04-09 14:08:36 -04:00
RevertReg.v
Initial load of files
2019-03-26 14:49:40 -04:00
SizedFIFO0.v
Initial load of files
2019-03-26 14:49:40 -04:00
SizedFIFO.v
Initial load of files
2019-03-26 14:49:40 -04:00
SyncHandshake.v
Add support for external debug module.
2019-04-09 14:08:36 -04:00
SyncRegister.v
Changes to support vectored RVFI_DII bridge directly, which enables us to successfully run memory tests with traps.
2019-12-09 16:34:27 +00:00
SyncResetA.v
Add support for external debug module.
2019-04-09 14:08:36 -04:00

README.txt 

These are copies of a few of the Verilog files that are found in any
standard Bluespec bsc distribution at $(BLUESPECDIR)/Verilog
Reference in New Issue View Git Blame Copy Permalink