49 lines
1.8 KiB
Plaintext
49 lines
1.8 KiB
Plaintext
Copyright (c) 2019 Bluespec, Inc. All Rights Reserved.
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This directory is intended for DARPA SSITH users; others may safely ignore it.
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This directory contains a wrapper and other resources that package up
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MIT's RISCY-OOO to fit into the "standard" core socket in the SSITH GFE
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("Government Furnished Equipment").
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>================================================================
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Context:
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The SSITH system is an SoC with a "socket" (placeholder) for a "Core"
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module (a RISC-V CPU). Various implementations are/will be plugged
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into this socket:
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- "P1"
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- Baseline Piccolo (BSV) based core
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- Baseline Rocket (Chisel) based core
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- Variations/alternatives by various SSITH project teams
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- "P2"
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- Baseline Flute (BSV) based core
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- Baseline Rocket (Chisel) based core
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- Variations/alternatives by various SSITH project teams
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- "P3"
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- Baseline Tooba (BSV) based core
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- Baseline BOOM (Chisel) based core
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- Variations/alternatives by various SSITH project teams
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>================================================================
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Extra dependencies:
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On top of the dependencies in the top project, you must have a build of bsc-contrib,
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which you can find here: https://github.com/B-Lang-org/bsc-contrib
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The Makefile expects the folder that is generated in bsc-contrib/inst/lib/Libraries/Bus
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to be located in the default bsc build at bsc/inst/lib/Libraries.
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>================================================================
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Whenever there are changes to the Toooba core, rerun:
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$ make compile
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(which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)
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The synthesis version (Verilog_RTL) uses Xilinx IP for the integer divider,
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while the simulation version (Verilog_RTL_sim) uses a model.
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>================================================================
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