219 lines
6.9 KiB
Plaintext
219 lines
6.9 KiB
Plaintext
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// Copyright (c) 2017 Massachusetts Institute of Technology
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// Portions Copyright (c) 2019-2020 Bluespec, Inc.
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// CHERI modifications:
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// Permission is hereby granted, free of charge, to any person
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// obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without
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// restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies
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// of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be
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// included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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`include "ProcConfig.bsv"
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import Types::*;
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import ProcTypes::*;
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import DefaultValue::*;
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import ConfigReg::*;
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import Ehr::*;
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import GetPut::*;
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import Vector::*;
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import CHERICap::*;
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import CHERICC_Fat::*;
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import ISA_Decls_CHERI::*;
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// ================================================================
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// BSV additional libs
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import Cur_Cycle::*;
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// ================================================================
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// Project imports from Toooba
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import SoC_Map::*;
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// ================================================================
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// Information returned on traps and mret/sret/uret
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typedef struct {
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CapMem new_pcc;
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} Scr_Trap_Updates
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deriving (Bits, FShow);
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typedef struct {
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CapMem new_pcc;
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} Scr_RET_Updates
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deriving (Bits, FShow);
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typedef struct {
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Addr top;
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Addr base;
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HardPerms perms;
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} ScrVMInfo
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deriving (Bits, FShow);
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typedef struct {
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Bool cap_mode;
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} ScrDecodeInfo
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deriving (Bits, FShow);
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// ================================================================
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interface ScrFile;
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// Read
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method CapReg rd(SCR csr);
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// normal write by RWSpecialCap inst to any SCR
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method Action scrInstWr(SCR csr, CapReg x);
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// The WARL transform performed during CSRRx writes to a CSR
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method CapReg warl_xform (SCR csr, CapReg x);
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// Methods for handling traps
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method ActionValue#(Scr_Trap_Updates) trap(CapPipe pc, Bit#(2) prv);
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method ActionValue#(Scr_RET_Updates) sret;
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method ActionValue#(Scr_RET_Updates) mret;
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// Outputs for CSRs that the rest of the processor needs to know about
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method ScrVMInfo ddcCheck;
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// terminate
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method ActionValue#(void) terminate;
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endinterface
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// same as EHR except that read port 0 is not ordered with other methods. Read
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// port 1 will still get bypassing from write port 0.
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module mkConfigEhr#(t init)(Ehr#(n, t)) provisos(Bits#(t, w));
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Ehr#(n, t) data <- mkEhr(init);
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Wire#(t) read <- mkBypassWire;
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(* fire_when_enabled, no_implicit_conditions *)
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rule setRead;
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read <= data[0];
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endrule
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Ehr#(n, t) ifc = ?;
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ifc[0] = (interface Reg;
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method _read = read._read;
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method _write = data[0]._write;
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endinterface);
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for(Integer i = 1; i < valueOf(n); i = i+1) begin
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ifc[i] = (interface Reg;
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method _read = data[i]._read;
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method _write = data[i]._write;
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endinterface);
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end
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return ifc;
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endmodule
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module mkScrFile (ScrFile);
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RiscVISASubset isa = defaultValue;
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let mkCsrReg = mkConfigReg;
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let mkCsrEhr = mkConfigEhr;
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// User level SCRs
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// PCC is implemented in the pipeline.
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Reg#(CapReg) ddc_reg <- mkCsrReg(defaultValue);
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// User level SCRs with accessSysRegs
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// Reg#(CapReg) utcc_reg <- mkCsrReg(defaultValue);
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// Reg#(CapReg) utdc_reg <- mkCsrReg(nullCap);
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// Reg#(CapReg) uScratchC_reg <- mkCsrReg(nullCap);
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// Reg#(CapReg) uepcc_reg <- mkCsrReg(defaultValue);
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// System level SCRs with accessSysRegs
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Reg#(CapReg) stcc_reg <- mkCsrReg(defaultValue);
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Reg#(CapReg) stdc_reg <- mkCsrReg(nullCap);
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Reg#(CapReg) sScratchC_reg <- mkCsrReg(nullCap);
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Ehr#(2, CapReg) sepcc_reg <- mkConfigEhr(defaultValue);
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// Machine level SCRs with accessSysRegs
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Reg#(CapReg) mtcc_reg <- mkCsrReg(defaultValue);
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Reg#(CapReg) mtdc_reg <- mkCsrReg(nullCap);
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Reg#(CapReg) mScratchC_reg <- mkCsrReg(nullCap);
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Ehr#(2, CapReg) mepcc_reg <- mkConfigEhr(defaultValue);
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// Function for getting a csr given an index
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function Reg#(CapReg) get_scr(SCR scr);
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return (case (scr)
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// User SCRs
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//SCR_PCC: $error("PCC does not actually live in the Special Capability Register File!");
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SCR_DDC: ddc_reg;
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// User CSRs with accessSysRegs
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// SCR_UTCC: utcc_reg;
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// SCR_UTDC: utdc_reg;
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// SCR_UScratchC: uScratchC_reg;
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// SCR_UEPCC: uepcc_reg;
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// System CSRs with accessSysRegs
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SCR_STCC: stcc_reg;
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SCR_STDC: stdc_reg;
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SCR_SScratchC: sScratchC_reg;
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SCR_SEPCC: sepcc_reg[1];
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// Machine CSRs with accessSysRegs
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SCR_MTCC: mtcc_reg;
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SCR_MTDC: mtdc_reg;
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SCR_MScratchC: mScratchC_reg;
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SCR_MEPCC: mepcc_reg[1];
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endcase);
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endfunction
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// ================================================================
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// INTERFACE
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method CapReg rd(SCR scr);
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return get_scr(scr)._read;
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endmethod
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method Action scrInstWr(SCR csr, CapReg x);
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get_scr(csr)._write(x);
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endmethod
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method ActionValue#(Scr_Trap_Updates) trap(CapPipe pc, Bit#(2) prv);
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case (prv)
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prvM: mepcc_reg[0] <= cast(pc);
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prvS: mepcc_reg[0] <= cast(pc);
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prvU: mepcc_reg[0] <= cast(pc);
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endcase
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return Scr_Trap_Updates{new_pcc: cast(mtcc_reg)};
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endmethod
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method ActionValue#(Scr_RET_Updates) mret;
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return Scr_RET_Updates{new_pcc: cast(mepcc_reg[0])};
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endmethod
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method ActionValue#(Scr_RET_Updates) sret;
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return Scr_RET_Updates{new_pcc: cast(sepcc_reg[0])};
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endmethod
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method ScrVMInfo ddcCheck;
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// for load/store, need to consider MPRV
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return ScrVMInfo {
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top: truncate(getTop(ddc_reg)),
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base: truncate(getBase(ddc_reg)),
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perms: getHardPerms(ddc_reg)
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};
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endmethod
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endmodule
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