140 lines
4.4 KiB
Plaintext
140 lines
4.4 KiB
Plaintext
// Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// Copyright (c) 2020 Peter Rugg
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package Proc_IFC;
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// ================================================================
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// BSV library imports
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import Vector :: *;
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import GetPut :: *;
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import ClientServer :: *;
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// ================================================================
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// Project imports
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import ProcTypes :: *;
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import ISA_Decls :: *;
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import AXI4 :: *;
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import Fabric_Defs :: *;
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import SoC_Map :: *;
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import CCTypes :: *;
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import ProcTypes :: *;
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`ifdef INCLUDE_GDB_CONTROL
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import DM_CPU_Req_Rsp :: *;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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import Trace_Data2 :: *;
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`endif
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// ================================================================
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// CPU interface
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// Note: this Proc_IFC is similar, but not identical to CPU_IFC for Piccolo and Flute
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// Specifically, it removes interfaces for software and timer,
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// because the RISCY-OOO mkProc contains those elements.
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interface Proc_IFC;
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// ----------------
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// Start the cores running
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// Use toHostAddr = 0 if not monitoring tohost
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method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr);
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// ----------------
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// SoC fabric connections
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// Fabric master interface for memory (from LLC)
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interface AXI4_Master #(Wd_MId, Wd_Addr, Wd_Data,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User) master0;
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// Fabric master interface for IO (from MMIOPlatform)
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interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User) master1;
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// ----------------
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// External interrupts
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(* always_ready, always_enabled *)
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method Action m_external_interrupt_req (Vector #(CoreNum, Bool) set_not_clear);
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(* always_ready, always_enabled *)
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method Action s_external_interrupt_req (Vector #(CoreNum, Bool) set_not_clear);
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// ----------------
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// Non-maskable interrupt
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(* always_ready, always_enabled *)
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method Action non_maskable_interrupt_req (Bool set_not_clear);
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// ----------------
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// Set core's verbosity
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method Action set_verbosity (Bit #(4) verbosity);
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// ----------------
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// Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory)
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interface AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User) debug_module_mem_server;
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`ifdef RVFI_DII
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interface Toooba_RVFI_DII_Server rvfi_dii_server;
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`endif
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// ----------------
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// Optional interface to Debug Module
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`ifdef INCLUDE_GDB_CONTROL
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interface Vector #(CoreNum, Server #(Bool, Bool)) harts_run_halt_server;
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interface Vector #(CoreNum, Server #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN))) harts_gpr_mem_server;
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`ifdef ISA_F
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interface Vector #(CoreNum, Server #(DM_CPU_Req #(5, FLEN), DM_CPU_Rsp #(FLEN))) harts_fpr_mem_server;
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`endif
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interface Vector #(CoreNum, Server #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN))) harts_csr_mem_server;
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// Non-standard
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interface Vector #(CoreNum, Put #(Bit #(4))) harts_put_other_req;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// Note: this is a SupSize vector of streams of Trace_Data2 structs,
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// each of which has a serialnum field. Each of the SupSize
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// streams has serialnums in increasing order. Each serialnum
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// appears exactly once in exactly one of the streams. Thus, the
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// channels can easily be merged into a single program-order stream.
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interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
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`endif
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`ifdef PERFORMANCE_MONITORING
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method Action events_tgc(EventsCache events);
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`endif
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endinterface
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// ================================================================
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endpackage
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