113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
4 lines
230 B
Tcl
4 lines
230 B
Tcl
set_property MARK_DEBUG true [get_nets jtagtap/CLK_jtag_tclk_out]
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create_clock -period 40.000 -name tck_internal -waveform {0.000 20.000} [get_nets jtagtap/CLK_jtag_tclk_out]
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set_clock_uncertainty 2.00 [get_clocks *tck_internal*]
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