Akilan 26b025b556 enabled performance counters

2026-04-09 13:17:48 +01:00

..

CCPipe.bsv

Request queues in L1 cache

2025-03-25 09:23:06 +00:00

CCTypes.bsv

CCTypes: Fix misleading bit width for MESI/Msi enum

2025-11-02 14:28:02 +00:00

CrossBar.bsv

Fix arbitration for non-power-of-two numbers of sources

2021-05-28 14:37:24 +01:00

IBank.bsv

enabled performance counters

2026-04-09 13:17:48 +01:00

ICRqMshr.bsv

Added license text

2023-05-23 13:37:43 +01:00

IPRqMshr.bsv

Prefetcher implementation in both L1 and LL and data logging

2023-02-13 11:59:26 +00:00

L1Bank.bsv

enabled performance counters

2026-04-09 13:17:48 +01:00

L1CRqMshr.bsv

Request queues in L1 cache

2025-03-25 09:23:06 +00:00

L1Pipe.bsv

merge fix in L1Pipe

2025-03-25 09:23:08 +00:00

L1PRqMshr.bsv

Prefetcher implementation in both L1 and LL and data logging

2023-02-13 11:59:26 +00:00

LLBank.bsv

enabled performance counters

2026-04-09 13:17:48 +01:00

LLCRqMshr.bsv

Add CHERI+RVFI_DII grant codes and copyrights

2020-07-06 17:39:25 +01:00

LLPipe.bsv

Request queues in L1 cache

2025-03-25 09:23:06 +00:00

MshrDeadlockChecker.bsv

Initial load of files

2019-03-26 14:49:40 -04:00

Prefetcher.bsv

Revert "Changes to make Prefetcher more deterministic, and also to report schedules."

2025-07-03 11:47:00 +01:00

RandomReplace.bsv

Add CHERI+RVFI_DII grant codes and copyrights

2020-07-06 17:39:25 +01:00

RWBramCore.bsv

Request queues in L1 cache

2025-03-25 09:23:06 +00:00

SelfInvIBank.bsv

enabled performance counters

2026-04-09 13:17:48 +01:00

SelfInvIPipe.bsv

Request queues in L1 cache

2025-03-25 09:23:06 +00:00

SelfInvL1Bank.bsv

enabled performance counters

2026-04-09 13:17:48 +01:00

SelfInvL1Pipe.bsv

Request queues in L1 cache

2025-03-25 09:23:06 +00:00

SelfInvLLBank.bsv

enabled performance counters

2026-04-09 13:17:48 +01:00

SelfInvLLPipe.bsv

Request queues in L1 cache

2025-03-25 09:23:06 +00:00