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0ac138b08f9db52ed991c2a889b1c08df00a5645
Toooba/src_SSITH_P3/xilinx_ip/hdl
History
rsnikhil 4bdbcbfd88 Additional fix to previous commit (75df204e) which only fixed MIP/MIE; this fixes SIP/SIE as well.
2020-03-04 13:14:31 -05:00
..
BRAM2.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
FIFO1.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO2.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO10.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
FIFO20.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFOL1.v
Add missing module (FIFOL1) to Xilinx import.
2019-04-24 21:34:52 -04:00
MakeClock.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
MakeResetA.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
mkAluDispToRegFifo.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkAluExeToFinFifo.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkAluRegToExeFifo.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkBht.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkCore.v
Additional fix to previous commit (75df204e) which only fixed MIP/MIE; this fixes SIP/SIE as well.
2020-03-04 13:14:31 -05:00
mkCoreW.v
Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values)
2020-03-04 09:50:39 -05:00
mkDCRqMshrWrapper.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkDebug_Module.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDirPredictor.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDivExecQ.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_Abstract_Commands.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_CSR_Tap.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_GPR_Tap.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_Mem_Tap.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_Run_Control.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_System_Bus.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDoubleDiv.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDoubleFMA.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDoubleSqrt.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDPipeline.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkDPRqMshrWrapper.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDTlbSynth.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkDummyStoreBuffer.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkEpochManager.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkFabric_2x3.v
Fixed a Tandem-Verification issue (report MIP change due to interrupts).
2020-03-03 18:34:00 -05:00
mkFetchStage.v
Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization
2020-03-03 13:56:31 -05:00
mkFmaExecQ.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkFpuMulDivDispToRegFifo.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkFpuMulDivRegToExeFifo.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkGSelectGHistReg.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkGSelectPred.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkGShareGHistReg.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkGSharePred.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkIBankWrapper.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkICoCache.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkICRqMshrWrapper.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkIPipeline.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkIPRqMshrWrapper.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkITlb.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkJtagTap.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkL2Tlb.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkLastLvCRqMshr.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkLLCache.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkLLPipeline.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkLSQIssueLdQ.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkMemDispToRegFifo.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkMemLoader.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkMemRegToExeFifo.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkMinimumExecQ.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkMMIOInst.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkMulExecQ.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkNullTransCache.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkP3_Core.v
Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values)
2020-03-04 09:50:39 -05:00
mkPLIC_16_2_7.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkProc.v
Fixed a Tandem-Verification issue (report MIP change due to interrupts).
2020-03-03 18:34:00 -05:00
mkRas.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkRegRenamingTable.v
Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization
2020-03-03 13:56:31 -05:00
mkReorderBufferSynth.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkReservationStationAlu.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkReservationStationFpuMulDiv.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkReservationStationMem.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkRFileSynth.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkRobRowSynth.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkScoreboardAggr.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkScoreboardCons.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkSimpleRespQ.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkSoC_Map.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkSpecTagManager.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkSplitLSQ.v
Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization
2020-03-03 13:56:31 -05:00
mkSplitTransCache.v
Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization
2020-03-03 13:56:31 -05:00
mkStoreBufferEhr.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkSyncBramFifo_w36_d512.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkSyncFifo_w32_d16.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkTourGHistReg.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkTourPred.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkTourPredSecure.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkTrace_Data2_to_Trace_Data.v
Fixed a Tandem-Verification issue (report MIP change due to interrupts).
2020-03-03 18:34:00 -05:00
mkTV_Encode.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkTV_Xactor.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkXilinxFpDiv.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkXilinxFpDivIP.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkXilinxFpDivSim.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkXilinxFpFma.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkXilinxFpFmaIP.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkXilinxFpFmaSim.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkXilinxFpSqrt.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkXilinxFpSqrtIP.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
mkXilinxFpSqrtSim.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_alu.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_aluBr.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_amoExec.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_basicExec.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_brAddrCalc.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_checkForException.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
module_decode.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
module_decodeBrPred.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_execFpuSimple.v
Modified synth and sim compile options in the Makefile
2020-02-22 17:51:13 +05:30
module_getControlFlow.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
RegFile.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
reset_guard.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
ResetEither.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
RevertReg.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
SizedFIFO0.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SizedFIFO.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
SyncFIFOLevel.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncHandshake.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncResetA.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00