50 lines
1.6 KiB
Verilog
50 lines
1.6 KiB
Verilog
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// Copyright (c) 2000-2019 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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// Basic register with initial value but without reset (not for ASIC synthesis).
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module RegUNInit(CLK, Q_OUT, D_IN, EN);
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parameter width = 1;
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parameter init = { width {1'b0} } ;
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input CLK;
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input EN;
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input [width - 1 : 0] D_IN;
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output [width - 1 : 0] Q_OUT;
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reg [width - 1 : 0] Q_OUT;
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initial Q_OUT = init;
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always@(posedge CLK)
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begin
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if (EN)
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Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
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end
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endmodule
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