85 lines
2.4 KiB
Verilog
85 lines
2.4 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// decodeBrPred O 65
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// decodeBrPred_pc I 64
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// decodeBrPred_dInst I 72
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// decodeBrPred_histTaken I 1
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// decodeBrPred_is_32b_inst I 1
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//
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// Combinational paths from inputs to outputs:
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// (decodeBrPred_pc,
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// decodeBrPred_dInst,
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// decodeBrPred_histTaken,
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// decodeBrPred_is_32b_inst) -> decodeBrPred
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_decodeBrPred(decodeBrPred_pc,
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decodeBrPred_dInst,
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decodeBrPred_histTaken,
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decodeBrPred_is_32b_inst,
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decodeBrPred);
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// value method decodeBrPred
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input [63 : 0] decodeBrPred_pc;
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input [71 : 0] decodeBrPred_dInst;
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input decodeBrPred_histTaken;
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input decodeBrPred_is_32b_inst;
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output [64 : 0] decodeBrPred;
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// signals for module outputs
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wire [64 : 0] decodeBrPred;
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// remaining internal signals
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reg [63 : 0] CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2;
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wire [63 : 0] imm_val__h25, jTarget__h45, pcPlusN__h24;
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wire [31 : 0] decodeBrPred_dInst_BITS_31_TO_0__q1;
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// value method decodeBrPred
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assign decodeBrPred =
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{ decodeBrPred_dInst[71:67] != 5'd9,
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CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 } ;
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// remaining internal signals
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assign decodeBrPred_dInst_BITS_31_TO_0__q1 = decodeBrPred_dInst[31:0] ;
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assign imm_val__h25 =
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{ {32{decodeBrPred_dInst_BITS_31_TO_0__q1[31]}},
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decodeBrPred_dInst_BITS_31_TO_0__q1 } ;
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assign jTarget__h45 = decodeBrPred_pc + imm_val__h25 ;
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assign pcPlusN__h24 =
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decodeBrPred_pc + (decodeBrPred_is_32b_inst ? 64'd4 : 64'd2) ;
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always@(decodeBrPred_dInst or
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pcPlusN__h24 or jTarget__h45 or decodeBrPred_histTaken)
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begin
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case (decodeBrPred_dInst[71:67])
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5'd8:
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CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
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jTarget__h45;
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5'd10:
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CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
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decodeBrPred_histTaken ? jTarget__h45 : pcPlusN__h24;
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default: CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
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pcPlusN__h24;
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endcase
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end
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endmodule // module_decodeBrPred
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