95 lines
2.3 KiB
Makefile
95 lines
2.3 KiB
Makefile
default: compile link
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all: compile link simulate
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TOP = Testbench
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TOPFILE = $(TOP).bsv
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TOPMODULE = mk$(TOP)
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# BSCFLAGS = -keep-fires -aggressive-conditions -no-warn-action-shadowing -no-inline-rwire
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# BSCFLAGS = -keep-fires -aggressive-conditions -no-inline-rwire -show-range-conflict -show-schedule
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BSCFLAGS = -D RV32 \
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-keep-fires \
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-aggressive-conditions \
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-suppress-warnings G0020 \
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-show-schedule
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# ----------------------------------------------------------------
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# FOR BLUESIM
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ISA_DECLS_DIR = $(HOME)/Projects/RISCV/Bluespec_RISCV/ISA
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TRX_DIR = $(HOME)/Projects/RISCV/Bluespec_RISCV/Fabrics/TRX
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ADDL_LIBS_DIR = $(HOME)/Projects/RISCV/Bluespec_RISCV/BSV_Additional_Libs/BSV
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BSCDIRS_BSIM = -simdir build_bsim -bdir build -info-dir build
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BSCPATH_BSIM = -p .:..:$(ISA_DECLS_DIR):$(TRX_DIR):$(ADDL_LIBS_DIR):%/Prelude:%/Libraries
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build_bsim:
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mkdir -p $@
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build:
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mkdir -p $@
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.PHONY: compile
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compile: build_bsim build
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@echo Compiling...
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bsc -u -sim $(BSCDIRS_BSIM) $(BSCFLAGS) $(BSCPATH_BSIM) $(TOPFILE)
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@echo Compilation finished
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.PHONY: link
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link:
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@echo Linking...
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bsc -e $(TOPMODULE) $(BSCFLAGS) -parallel-sim-link 8 -sim -o ./$(TOP)_bsim_exe $(BSCDIRS_BSIM) $(BSCPATH_BSIM)
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@echo Linking finished
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.PHONY: simulate
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simulate:
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@echo Simulation...
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logsave bsim.log ./$(TOP)_bsim_exe -V
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@echo Simulation finished
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# ----------------------------------------------------------------
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# FOR VERILOG
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BSCDIRS_V = -vdir verilog -bdir build_v -info-dir build_v
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BSCPATH_V = -p .:./$(SRC_BSV):%/Prelude:%/Libraries:%/Libraries/TLM3
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# Set VSIM to desired Verilog simulator
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# VSIM = modelsim
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VSIM ?= cvc
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# VSIM ?= iverilog
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build_v:
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mkdir -p $@
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verilog:
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mkdir -p $@
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.PHONY: rtl
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rtl: build_v verilog
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@echo Verilog generation ...
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bsc -u -elab -verilog $(BSCDIRS_V) $(BSCFLAGS) $(BSCPATH_V) $(TOPFILE)
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@echo Verilog generation finished
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.PHONY: vlink
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vlink:
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bsc -v -e $(TOPMODULE) -verilog -o ./out_v -vdir verilog -vsim $(VSIM) -keep-fires \
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verilog/$(TOPMODULE).v
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.PHONY: vsim
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vsim:
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@echo Simulation...
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./out_v
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@echo Simulation finished
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# ----------------------------------------------------------------
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.PHONY: clean
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clean:
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rm -f *~ src_*/*~ src_*/*.o build/* build_bsim/* build_v/* *.cxx *.h *.o
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.PHONY: full_clean
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full_clean: clean
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rm -r -f *_bsim_exe *.so out_v verilog build build_bsim dump.vcd bsim.log
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