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113f888d37da02fb4ba8b0e41b65a10e9b788571
Toooba/src_Core/RISCY_OOO/procs/lib
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rsnikhil 113f888d37 Added support for 'debug_external_interrupt_req' 
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00
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Amo.bsv
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Bht.bsv
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BrPred.bsv
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Btb.bsv
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Bypass.bsv
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CacheUtils.bsv
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ConcatReg.bsv
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Decode.bsv
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DirPredictor.bsv
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DTlb.bsv
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Ehr.bsv
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EpochManager.bsv
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Exec.bsv
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Fifo.bsv
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Fpu.bsv
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FullAssocTlb.bsv
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GlobalBrHistReg.bsv
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GlobalSpecUpdate.bsv
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GSelectPred.bsv
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GSharePred.bsv
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HasSpecBits.bsv
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ITlb.bsv
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L1CoCache.bsv
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L1LLConnect.bsv
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L2SetAssocTlb.bsv
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L2Tlb.bsv
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LatencyTimer.bsv
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LLCache.bsv
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LLCDmaConnect.bsv
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LLCRqMshrSecureModel.bsv
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MemLoader.bsv
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MemLoaderIF.bsv
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MemoryTypes.bsv
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MMIOAddrs.bsv
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MMIOCore.bsv
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MMIOInst.bsv
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MsgFifo.bsv
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MulDiv.bsv
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Performance.bsv
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PhysRFile.bsv
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ProcTypes.bsv
Added support for 'debug_external_interrupt_req'
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Ras.bsv
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RenameDebugIF.bsv
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RenamingTable.bsv
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ReorderBuffer.bsv
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ReservationStationEhr.bsv
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SafeCounter.bsv
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Scoreboard.bsv
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SetAssocTlb.bsv
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SpecFifo.bsv
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SpecPoisonFifo.bsv
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SpecTagManager.bsv
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SplitLSQ.bsv
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StoreBuffer.bsv
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TlbConnect.bsv
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TlbTypes.bsv
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TourPred.bsv
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TourPredSecure.bsv
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TranslationCache.bsv
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Types.bsv
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VerificationPacket.bsv
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