113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
132 lines
3.8 KiB
Verilog
132 lines
3.8 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// basicExec O 322
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// basicExec_dInst I 72
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// basicExec_rVal1 I 64
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// basicExec_rVal2 I 64
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// basicExec_pc I 64
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// basicExec_ppc I 64
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//
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// Combinational paths from inputs to outputs:
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// (basicExec_dInst,
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// basicExec_rVal1,
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// basicExec_rVal2,
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// basicExec_pc,
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// basicExec_ppc) -> basicExec
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_basicExec(basicExec_dInst,
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basicExec_rVal1,
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basicExec_rVal2,
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basicExec_pc,
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basicExec_ppc,
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basicExec);
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// value method basicExec
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input [71 : 0] basicExec_dInst;
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input [63 : 0] basicExec_rVal1;
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input [63 : 0] basicExec_rVal2;
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input [63 : 0] basicExec_pc;
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input [63 : 0] basicExec_ppc;
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output [321 : 0] basicExec;
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// signals for module outputs
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wire [321 : 0] basicExec;
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// remaining internal signals
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reg [63 : 0] x__h23, x__h263;
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wire [193 : 0] IF_basicExec_dInst_BITS_71_TO_67_EQ_4_8_OR_bas_ETC___d43;
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wire [63 : 0] SEXT_basicExec_dInst_BITS_31_TO_0_3___d14,
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aluVal2__h33,
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alu_result__h35,
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basicExec_pc_PLUS_4___d10,
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cf_nextPc__h294;
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wire [31 : 0] basicExec_dInst_BITS_31_TO_0__q1;
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wire aluBr___d37;
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// value method basicExec
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assign basicExec =
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{ x__h23,
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alu_result__h35,
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IF_basicExec_dInst_BITS_71_TO_67_EQ_4_8_OR_bas_ETC___d43 } ;
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// remaining internal signals
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module_alu instance_alu_1(.alu_a(basicExec_rVal1),
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.alu_b(aluVal2__h33),
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.alu_func((basicExec_dInst[66:64] == 3'd0) ?
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basicExec_dInst[50:46] :
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5'd0),
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.alu(alu_result__h35));
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module_aluBr instance_aluBr_0(.aluBr_a(basicExec_rVal1),
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.aluBr_b(basicExec_rVal2),
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.aluBr_brFunc((basicExec_dInst[66:64] ==
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3'd1) ?
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basicExec_dInst[48:46] :
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3'd7),
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.aluBr(aluBr___d37));
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module_brAddrCalc instance_brAddrCalc_2(.brAddrCalc_pc(basicExec_pc),
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.brAddrCalc_val(basicExec_rVal1),
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.brAddrCalc_iType(basicExec_dInst[71:67]),
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.brAddrCalc_imm(SEXT_basicExec_dInst_BITS_31_TO_0_3___d14),
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.brAddrCalc_taken(aluBr___d37),
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.brAddrCalc(cf_nextPc__h294));
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assign IF_basicExec_dInst_BITS_71_TO_67_EQ_4_8_OR_bas_ETC___d43 =
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{ x__h263,
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basicExec_pc,
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cf_nextPc__h294,
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aluBr___d37,
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cf_nextPc__h294 != basicExec_ppc } ;
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assign SEXT_basicExec_dInst_BITS_31_TO_0_3___d14 =
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{ {32{basicExec_dInst_BITS_31_TO_0__q1[31]}},
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basicExec_dInst_BITS_31_TO_0__q1 } ;
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assign aluVal2__h33 =
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basicExec_dInst[32] ?
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SEXT_basicExec_dInst_BITS_31_TO_0_3___d14 :
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basicExec_rVal2 ;
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assign basicExec_dInst_BITS_31_TO_0__q1 = basicExec_dInst[31:0] ;
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assign basicExec_pc_PLUS_4___d10 = basicExec_pc + 64'd4 ;
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always@(basicExec_dInst or
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alu_result__h35 or
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basicExec_rVal2 or
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basicExec_pc_PLUS_4___d10 or
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basicExec_pc or
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SEXT_basicExec_dInst_BITS_31_TO_0_3___d14 or basicExec_rVal1)
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begin
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case (basicExec_dInst[71:67])
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5'd2, 5'd5, 5'd7: x__h23 = basicExec_rVal2;
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5'd8, 5'd9: x__h23 = basicExec_pc_PLUS_4___d10;
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5'd11:
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x__h23 = basicExec_pc + SEXT_basicExec_dInst_BITS_31_TO_0_3___d14;
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5'd13: x__h23 = basicExec_rVal1;
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default: x__h23 = alu_result__h35;
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endcase
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end
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always@(basicExec_dInst or cf_nextPc__h294 or alu_result__h35)
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begin
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case (basicExec_dInst[71:67])
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5'd2, 5'd4, 5'd5, 5'd6, 5'd7: x__h263 = alu_result__h35;
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default: x__h263 = cf_nextPc__h294;
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endcase
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end
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endmodule // module_basicExec
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