179 lines
6.1 KiB
Makefile
179 lines
6.1 KiB
Makefile
### -*-Makefile-*-
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# ================================================================
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.PHONY: help
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help:
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@echo ' make compile Recompile Core (CPU, caches) into Verilog_RTL'
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@echo ' NOTE: needs Bluespec bsc compiler'
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@echo ' make tagsparams Generates the CHERI tag controller parameters source file'
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@echo ''
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@echo ' make clean Remove intermediate build-files'
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@echo ' make full_clean Restore this directory to pristine state'
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.PHONY: compile
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compile: compile_sim compile_synth
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# ================================================================
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REPO ?= ..
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ARCH ?= RV64ACDFIMSUxCHERI
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# ================================================================
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# RISC-V config macros passed into Bluespec 'bsc' compiler
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BSC_COMPILATION_FLAGS += \
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-D RV64 \
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-D ISA_PRIV_M -D ISA_PRIV_S -D ISA_PRIV_U \
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-D SV39 \
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-D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \
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-D CheriBusBytes=8 \
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-D CheriMasterIDWidth=1 \
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-D CheriTransactionIDWidth=5 \
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-D PERFORMANCE_MONITORING \
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-D SHIFT_BARREL \
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-D MULT_SERIAL \
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-D Near_Mem_Caches \
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-D FABRIC64 \
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-D CAP128 \
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-D MEM64 \
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-D RISCV \
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-D TSO_MM \
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-D NO_SPEC_TRAINING -D NO_SPEC_REDIRECT -D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL \
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-D NO_SPEC_STL \
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-D INCLUDE_GDB_CONTROL \
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-D BRVF_TRACE \
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-D XILINX_BSCAN -D JTAG_TAP
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#-D NO_SPEC_TRAINING -D NO_SPEC_REDIRECT -D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL \
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#-D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP \
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# Synth only BSC_COMPILATION_FLAGS
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SYNTH_BSC_OPTIONS = -D XILINX_XCVU9P
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# Sim only BSC_COMPILATION_FLAGS
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SIM_BSC_OPTIONS = -D BSIM
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# Set number of cores for RISCY config
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CORE_NUM = 2
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# Only used if we don't have INCLUDE_GDB_CONTROL
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# -D EXTERNAL_DEBUG_MODULE
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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# ================================================================
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# Path to RISCY-OOO sources
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RISCY_HOME ?= ../src_Core/RISCY_OOO
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RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib
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CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv
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CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib
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# ALL_RISCY_DIRS = $(RISCY_DIRS)
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ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS)
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# ================================================================
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# Search path for bsc for .bsv files
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CONTRIB_DIRS = %/Libraries/Bus
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CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/Core:$(REPO)/src_Core/PLIC:$(REPO)/src_Core/Debug_Module:$(REPO)/src_Core/BSV_Additional_Libs
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BLUESTUFF_DIRS = $(REPO)/libs/BlueStuff:$(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueUtils:$(REPO)/libs/BlueStuff/BlueBasics
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TAGCONTROLLER_DIRS = $(REPO)/libs/TagController/TagController:$(REPO)/libs/TagController/TagController/CacheCore
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RISCV_HPM_Events_DIR = $(REPO)/libs/RISCV_HPM_Events
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BSC_PATH = -p $(CONTRIB_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):src_BSV:$(BLUESTUFF_DIRS):$(TAGCONTROLLER_DIRS):$(RISCV_HPM_Events_DIR):+
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# ----------------
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# Top-level file and module
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TOPFILE = src_BSV/P3_Core.bsv
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TOPMODULE = mkP3_Core
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# ================================================================
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# More bsc compilation flags
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BSC_COMPILATION_FLAGS += \
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-keep-fires -aggressive-conditions \
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-no-warn-action-shadowing \
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-suppress-warnings G0020 \
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+RTS -K128M -RTS -show-range-conflict \
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-unspecified-to X -opt-undetermined-vals \
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-steps-max-intervals 10000000 \
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-steps-warn-interval 1000000
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# ================================================================
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# Generate Bluespec CHERI tag controller source file
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CAPSIZE = 128
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TAGS_STRUCT = 0 64
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TAGS_ALIGN = 32
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.PHONY: tagsparams
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tagsparams: src_BSV/TagTableStructure.bsv
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src_BSV/TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py
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@echo "INFO: Re-generating CHERI tag controller parameters"
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$^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --data-store-base-addr 0xc0000000 -b $@ 0xbfff8000 0x17ffff000
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@echo "INFO: Re-generated CHERI tag controller parameters"
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.PHONY: generate_hpm_vector
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generate_hpm_vector: GenerateHPMVector.bsv
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GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py
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@echo "INFO: Re-generating GenerateHPMVector bluespec file"
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$^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -b $@
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@echo "INFO: Re-generated GenerateHPMVector bluespec file"
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.PHONY: stat_counters
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stat_counters: StatCounters.bsv
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StatCounters.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py
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@echo "INFO: Re-generating HPM events struct bluepsec file"
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$^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -s $@
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@echo "INFO: Re-generated HPM events struct bluespec file"
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compile_sim: tagsparams stat_counters generate_hpm_vector
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compile_synth: tagsparams stat_counters generate_hpm_vector
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# ================================================================
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# Generate Verilog RTL from BSV sources (needs Bluespec 'bsc' compiler)
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BUILD_DIRS_SYNTH = -bdir build_dir_synth -info-dir build_dir_synth
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BUILD_DIRS_SIM = -bdir build_dir_sim -info-dir build_dir_sim
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build_dir_synth:
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mkdir -p $@
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build_dir_sim:
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mkdir -p $@
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Verilog_RTL:
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mkdir -p $@
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Verilog_RTL_sim:
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mkdir -p $@
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.PHONY: compile_synth
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compile_synth: | build_dir_synth Verilog_RTL
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@echo "INFO: Generating RTL into Verilog_RTL for synthesis ..."
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bsc -u -elab -verilog -vdir Verilog_RTL $(BUILD_DIRS_SYNTH) $(BSC_COMPILATION_FLAGS) $(SYNTH_BSC_OPTIONS) $(BSC_PATH) $(TOPFILE)
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@echo "INFO: Generated Synth RTL into Verilog_RTL"
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.PHONY: compile_sim
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compile_sim: | build_dir_sim Verilog_RTL_sim
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@echo "INFO: Generating RTL into Verilog_RTL_sim for simulation ..."
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bsc -u -elab -verilog -vdir Verilog_RTL_sim $(BUILD_DIRS_SIM) $(BSC_COMPILATION_FLAGS) $(SIM_BSC_OPTIONS) $(BSC_PATH) $(TOPFILE)
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# ================================================================
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.PHONY: clean
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clean:
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rm -r -f *~ Makefile_* build_dir_sim build_dir_synth src_BSV/TagTableStructure.bsv
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.PHONY: full_clean
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full_clean: clean
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rm -r -f *.log Verilog_RTL Verilog_RTL_sim
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# ================================================================
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