Peter Rugg 53eb073fb2 Don't track generated Verilog

2021-02-19 19:45:00 +00:00

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ASSIGN1.v

Fixes for synthesis

2020-06-05 17:40:28 +01:00

BRAM2.v

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FIFO1.v

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FIFO2.v

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FIFO10.v

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FIFO20.v

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FIFOL1.v

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MakeClock.v

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MakeReset0.v

Fixes for synthesis

2020-06-05 17:40:28 +01:00

MakeResetA.v

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RegFile.v

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RegUNInit.v

Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)

2020-03-13 16:38:54 -04:00

reset_guard.v

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ResetEither.v

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RevertReg.v

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SizedFIFO0.v

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SizedFIFO.v

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SyncFIFOLevel.v

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SyncHandshake.v

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SyncReset0.v

Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)

2020-03-13 16:38:54 -04:00

SyncResetA.v

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SyncWire.v

Fixes for synthesis

2020-06-05 17:40:28 +01:00