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25a728b6d363e6215f9eb53257d7144b95bde356
Toooba/src_Core/RISCY_OOO/procs/lib
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Jonathan Woodruff 25a728b6d3 Optimise timing of TLB translation, ensuring that the translated address 
proceeds with minimal conditions to the output.
2024-01-16 09:50:35 +00:00
..
Amo.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Bht.bsv
A timing optimisation for the direction predictor.
2022-01-18 11:05:09 +00:00
BrPred.bsv
A timing optimisation for the direction predictor.
2022-01-18 11:05:09 +00:00
Btb.bsv
Timing optimisation for Tournament Predictor.
2022-01-12 16:08:33 +00:00
Bypass.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
CacheUtils.bsv
Initial implementation CLoadTags
2021-04-08 17:08:15 +01:00
CapChecks.bsvi
Cleanup unused exception code
2023-06-20 16:46:39 +01:00
ConcatReg.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
CSRs.bsvi
CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING
2021-02-28 01:11:39 +00:00
Decode.bsv
Merge branch 'tag-clear' into CHERI
2023-06-27 11:38:42 +01:00
DirPredictor.bsv
Prefetcher implementation in both L1 and LL and data logging
2023-02-13 11:59:26 +00:00
DTlb.bsv
Optimise timing of TLB translation, ensuring that the translated address
2024-01-16 09:50:35 +00:00
Ehr.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
EpochManager.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Exceptions.bsvi
Merge branch 'mem_perm_checks' into CHERI
2020-07-23 16:53:14 +01:00
Exec.bsv
Fix CSetAddr tag clear bug
2023-06-26 18:01:56 +01:00
Fifos.bsv
Implemented overflow bypass fifo, required for double target table
2023-04-12 21:58:35 +03:00
FP_Utils.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Fpu.bsv
Use standard imports as the fixes have been upstreamed.
2022-08-15 16:18:23 +00:00
FullAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GlobalBrHistReg.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GlobalSpecUpdate.bsv
Simpelest strategy for making wrongSpec not conflict with loads of
2022-01-31 12:36:17 +00:00
GSelectPred.bsv
A timing optimisation for the direction predictor.
2022-01-18 11:05:09 +00:00
GSharePred.bsv
A timing optimisation for the direction predictor.
2022-01-18 11:05:09 +00:00
HasSpecBits.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
IndexedMultiset.bsv
Fix condition where Queue can remain "empty" when there were outstanding
2021-07-07 11:34:29 +01:00
Interrupts.bsvi
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
ITlb.bsv
Use an invalid virtual address when preventing prediction, and also
2021-10-08 11:00:11 +00:00
L1CoCache.bsv
"fix" non PERFORMANCE_MONITORING build
2021-09-29 18:09:06 +01:00
L1LLConnect.bsv
Implemented cross cache prefetching, fixed some coherence bugs in LLC
2023-02-13 11:59:26 +00:00
L2SetAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
L2Tlb.bsv
initial changes for HPM consistency
2021-09-02 14:50:17 +01:00
LatencyTimer.bsv
Improve scheduling for LatencyTimer to improve timing path discovered on
2022-01-07 09:52:43 +00:00
LLCache.bsv
"fix" non PERFORMANCE_MONITORING build
2021-09-29 18:09:06 +01:00
LLCDmaConnect.bsv
Fixes for the simplified debug unit DMA port
2023-02-28 14:55:20 +00:00
LLCRqMshrSecureModel.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Map.bsv
Optimise timing of TLB translation, ensuring that the translated address
2024-01-16 09:50:35 +00:00
MemLoader.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
MemLoaderIF.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
MemoryTypes.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
MMIOAddrs.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
MMIOCore.bsv
Initial implementation CLoadTags
2021-04-08 17:08:15 +01:00
MMIOInst.bsv
2-byte aligned instruction memory to simplify compressed instruction
2020-07-24 12:38:37 +01:00
MsgFifo.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
MulDiv.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Opcodes.bsvi
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
Performance.bsv
Prefetcher implementation in both L1 and LL and data logging
2023-02-13 11:59:26 +00:00
PhysRFile.bsv
Use mkRegOR in register file.
2022-01-25 20:42:16 +00:00
ProcTypes.bsv
Remove trap on CSetBounds*
2022-10-25 22:03:31 +01:00
Ras.bsv
commented out debug print statements in Ras.bsv
2022-07-29 15:41:28 +01:00
RenameDebugIF.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
RenamingTable.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ReorderBuffer.bsv
added do not cares for missing struct fields in ROB
2022-10-21 09:22:31 +00:00
ReservationStationEhr.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
RVRoundModes.bsvi
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
SafeCounter.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Scoreboard.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
SetAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SpecBuffer.bsv
Two modules (that build) that should be helpful in delaying the commit
2021-12-15 17:06:46 +00:00
SpecFifo.bsv
implemented missing notFull method in SpecFifo
2022-07-11 14:56:30 +01:00
SpecPoisonFifo.bsv
Roll back changes to SpecPoisonFifo which were accidentally committed.
2020-07-09 15:19:39 +01:00
SpecTagManager.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SplitLSQ.bsv
Revert "A scheduling experiment to try to get doRegReadMem and doExeMem"
2024-01-09 11:54:53 +00:00
STLPred.bsv
added typedefs to STLPred
2022-07-26 09:18:20 +01:00
StoreBuffer.bsv
Prefetcher implementation in both L1 and LL and data logging
2023-02-13 11:59:26 +00:00
TlbConnect.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TlbTypes.bsv
Use Matt's slightly cleaner version of the function.
2021-10-11 16:23:22 +00:00
TourPred.bsv
Swap poliarity of prediction for comparison with upstream.
2022-03-25 14:03:06 +00:00
TourPredSecure.bsv
A timing optimisation for the direction predictor.
2022-01-18 11:05:09 +00:00
TranslationCache.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Types.bsv
Initial implementation CLoadTags
2021-04-08 17:08:15 +01:00
VerificationPacket.bsv
Initial load of files
2019-03-26 14:49:40 -04:00