2c648eb1ed
are in Include_RISCY_Config.mk so that this can be included from an external repo without replicating Toooba branch-specific flags in that repo.
143 lines
5.2 KiB
Makefile
143 lines
5.2 KiB
Makefile
### -*-Makefile-*-
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# Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
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# This file is not a standalone Makefile, but 'include'd by other Makefiles
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# It contains common defs used by Makefiles generated for specific
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# RISC-V implementations that differ in RISC-V architectural-feature
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# choices, hardware implementation choices and simulator choices.
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# ================================================================
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.PHONY: help
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help:
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@echo ' make compile Recompile Core (CPU, caches)'
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@echo ' NOTE: needs Bluespec bsc compiler'
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@echo ' For Bluesim: generates Bluesim intermediate files'
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@echo ' For Verilog simulation: generates RTL'
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@echo ' make simulator Compiles and links intermediate files/RTL to create simulation executable'
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@echo ' make tagsparams Generates the CHERI tag controller parameters source file'
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@echo ' (Bluesim, verilator or iverilog)'
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@echo ' make all = make compile simulator'
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@echo ''
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@echo ' make run_example Runs simulation executable on ELF given by EXAMPLE'
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@echo ''
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@echo ' make test Runs simulation executable on rv32ui-p-add or rv64ui-p-add'
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@echo ' make isa_tests Runs simulation executable on all relevant standard RISC-V ISA tests'
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@echo ''
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@echo ' make clean Remove intermediate build-files unnecessary for execution'
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@echo ' make full_clean Restore to pristine state (pre-building anything)'
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.PHONY: all
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all: compile simulator
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# ================================================================
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# Search path for bsc for .bsv files
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TESTBENCH_DIRS = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC
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BSC_PATH += -p +:$(TESTBENCH_DIRS):$(EXTRA_DIRS)
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# ----------------
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# Top-level file and module
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TOPFILE ?= $(REPO)/src_Testbench/Top/Top_HW_Side.bsv
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TOPMODULE ?= mkTop_HW_Side
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# ================================================================
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# bsc compilation flags
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BSC_COMPILATION_FLAGS += \
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-D BSIM \
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-D MULT_SYNTH \
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-D Near_Mem_Caches \
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-D FABRIC64 \
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-D BLUESIM \
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-D PERFORMANCE_MONITORING \
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-D RAS_HIT_TRACING \
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-D NO_SPEC_TRAINING -D NO_SPEC_REDIRECT -D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP -D MELTDOWN_CF \
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-keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \
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-suppress-warnings G0020 -steps-max-intervals 10000000 \
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-steps-warn-interval 1000000 \
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-promote-warnings T0054 \
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+RTS -K128M -RTS -show-range-conflict -show-schedule
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# -D NO_SPEC_TRAINING -D NO_SPEC_REDIRECT -D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL -D RVFI
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# ================================================================
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# Runs simulation executable on ELF given by EXAMPLE
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EXAMPLE ?= PLEASE_DEFINE_EXAMPLE_PATH_TO_ELF
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.PHONY: run_example
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run_example:
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make -C $(TESTS_DIR)/elf_to_hex
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$(TESTS_DIR)/elf_to_hex/elf_to_hex $(EXAMPLE) Mem.hex
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./exe_HW_sim $(VERBOSITY) +exit
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# ================================================================
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# Test: run the executable on the standard RISCV ISA test specified in TEST
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TESTS_DIR ?= $(REPO)/Tests
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VERBOSITY ?= +v1
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.PHONY: test
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test:
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make -C $(TESTS_DIR)/elf_to_hex
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$(TESTS_DIR)/elf_to_hex/elf_to_hex $(TESTS_DIR)/isa/$(TEST) Mem.hex
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./exe_HW_sim $(VERBOSITY) +tohost
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# ================================================================
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# ISA Regression testing
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.PHONY: isa_tests
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isa_tests:
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@echo "Running regressions on ISA tests; saving logs in Logs/"
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$(REPO)/Tests/Run_regression.py ./exe_HW_sim $(REPO) ./Logs $(ARCH)
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@echo "Finished running regressions; saved logs in Logs/"
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# ================================================================
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# Generate Bluespec CHERI tag controller source file
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CAPSIZE = 128
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TAGS_STRUCT = 0 64
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TAGS_ALIGN = 32
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.PHONY: tagsparams
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tagsparams: TagTableStructure.bsv
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TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py
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@echo "INFO: Re-generating CHERI tag controller parameters"
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$^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --data-store-base-addr 0x80000000 -b $@ 0x3fffc000 0xbffff000
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@echo "INFO: Re-generated CHERI tag controller parameters"
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.PHONY: generate_hpm_vector
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generate_hpm_vector: GenerateHPMVector.bsv
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GenerateHPMVector.bsv: $(RISCVHPMEVENTSDIR)/parse_counters.py
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@echo "INFO: Re-generating GenerateHPMVector bluespec file"
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$^ $(RISCVHPMEVENTSDIR)/counters.yaml -m ProcTypes -b $@
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@echo "INFO: Re-generated GenerateHPMVector bluespec file"
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.PHONY: stat_counters
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stat_counters: StatCounters.bsv
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StatCounters.bsv: $(RISCVHPMEVENTSDIR)/parse_counters.py
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@echo "INFO: Re-generating HPM events struct bluepsec file"
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$^ $(RISCVHPMEVENTSDIR)/counters.yaml -m ProcTypes -s $@
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@echo "INFO: Re-generated HPM events struct bluespec file"
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compile: tagsparams #stat_counters generate_hpm_vector
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# ================================================================
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.PHONY: clean
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clean:
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rm -r -f *~ Makefile_* symbol_table.txt build_dir/* obj_dir Verilog_RTL/*
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rm -f TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv
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.PHONY: full_clean
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full_clean: clean
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rm -r -f $(SIM_EXE_FILE)* *.log *.vcd *.hex Logs/
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rm -f TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv .depends.mk
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# ================================================================
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