93 lines
3.7 KiB
Makefile
93 lines
3.7 KiB
Makefile
### -*-Makefile-*-
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# Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
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# This file is not a standalone Makefile, but 'include'd by other Makefiles
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# ================================================================
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# Generate Verilog RTL from BSV sources (needs Bluespec 'bsc' compiler)
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RTL_GEN_DIRS = -vdir Verilog_RTL -bdir build_dir -info-dir build_dir
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build_dir:
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mkdir -p $@
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Verilog_RTL:
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mkdir -p $@
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ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
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include .depends.mk
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.depends.mk: TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv | build_dir Verilog_RTL
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if ! bluetcl -exec makedepend -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
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endif
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%.bo:
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$(info building $@)
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bsc -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
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.PHONY: compile
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compile: build_dir/Top_HW_Side.bo | build_dir Verilog_RTL
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#Verilog_RTL/mkTop_HW_Side.v: build_dir Verilog_RTL /tmp/src_dir $(VERILOG_SUB_MODULES)
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#Verilog_RTL/mkTop_HW_Side.v: $(TOPFILE) build_dir/Top_HW_Side.bo build_dir Verilog_RTL
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# @echo "INFO: Verilog RTL generation ..."
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# bsc -u -verilog $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
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# @echo "INFO: Verilog RTL generation finished"
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# ================================================================
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# Compile and link Verilog RTL sources into an verilator executable
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SIM_EXE_FILE = exe_HW_sim
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# Verilator flags: notes
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# stats Dump stats on the design, in file {prefix}__stats.txt
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# -O3 Verilator optimization level
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# -CFLAGS -O3 C++ optimization level
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# --x-assign fast Optimize X value
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# --x-initial fast Optimize uninitialized value
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# --noassert Disable all assertions
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VERILATOR_FLAGS = --stats --x-assign fast --x-initial fast --noassert
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# VERILATOR_FLAGS = --stats -O3 -CFLAGS -O3 -LDFLAGS -static --x-assign fast --x-initial fast --noassert
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# XXX: Allow lint_off DEPRECATED for older Verilator versions.
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# This was added around the same time as -msg was deprecated, so we need
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# to suppress the deprecation messages without breaking older versions.
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# See verilator_config.vlt. Remove once 4.026 can be relied upon.
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VERILATOR_FLAGS += -Wfuture-DEPRECATED
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# Verilator flags: use the following to include code to generate VCDs
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# Select trace-depth according to your module hierarchy
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# VERILATOR_FLAGS += --trace --trace-depth 2 -CFLAGS -DVM_TRACE
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VTOP = V$(TOPMODULE)_edited
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VERILATOR_RESOURCES = $(REPO)/builds/Resources/Verilator_resources
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.PHONY: simulator
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simulator: build_dir/Top_HW_Side.bo
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@echo "INFO: Verilating Verilog files (in newly created obj_dir)"
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sed -f $(VERILATOR_RESOURCES)/sed_script.txt Verilog_RTL/$(TOPMODULE).v > tmp1.v
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cat $(VERILATOR_RESOURCES)/verilator_config.vlt \
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$(VERILATOR_RESOURCES)/import_DPI_C_decls.v \
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tmp1.v > Verilog_RTL/$(TOPMODULE)_edited.v
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rm -f tmp1.v
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verilator \
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-IVerilog_RTL \
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-I$(RISCY_HOME)/fpgautils/xilinx/fpu \
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-I$(RISCY_HOME)/fpgautils/xilinx/reset_regs \
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-I$(RISCY_HOME)/procs/asic/bluespec_verilog \
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-I$(REPO)/src_bsc_lib_RTL \
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$(VERILATOR_FLAGS) \
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--cc $(TOPMODULE)_edited.v \
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--exe sim_main.cpp \
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$(REPO)/src_Testbench/Top/C_Imported_Functions.c \
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$(REPO)/src_Verifier/BSV-RVFI-DII/SocketPacketUtils/socket_packet_utils.c
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@echo "INFO: Linking verilated files"
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cp -p $(VERILATOR_RESOURCES)/sim_main.cpp obj_dir/sim_main.cpp
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cd obj_dir; \
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make -j -f V$(TOPMODULE)_edited.mk $(VTOP); \
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cp -p $(VTOP) ../$(SIM_EXE_FILE)
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@echo "INFO: Created verilator executable: $(SIM_EXE_FILE)"
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# ================================================================
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