85 lines
2.1 KiB
C++
85 lines
2.1 KiB
C++
// Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
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// Top-level driver for "verilated" objects (Verilog compiled with verilator)
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#include <verilated.h>
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#include <sys/stat.h> // for 'mkdir'
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#include "VmkTop_HW_Side_edited.h"
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// If "verilator --trace" is used, include the tracing class
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#if VM_TRACE
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# include <verilated_vcd_c.h>
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#endif
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vluint64_t main_time = 0; // Current simulation time
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double sc_time_stamp () { // Called by $time in Verilog
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return main_time;
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}
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int main (int argc, char **argv, char **env) {
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Verilated::commandArgs (argc, argv); // remember args
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VmkTop_HW_Side_edited* mkTop_HW_Side = new VmkTop_HW_Side_edited; // create instance of model
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#if VM_TRACE
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// If verilator was invoked with --trace argument,
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// and if at run time passed the +trace argument, turn on tracing
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VerilatedVcdC* tfp = NULL;
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const char* flag = Verilated::commandArgsPlusMatch("trace");
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if (flag && 0==strcmp(flag, "+trace")) {
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Verilated::traceEverOn(true); // Verilator must compute traced signals
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VL_PRINTF("Enabling waves into vcd/vlt_dump.vcd...\n");
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tfp = new VerilatedVcdC;
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mkTop_HW_Side->trace(tfp, 99); // Trace 99 levels of hierarchy
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mkdir("vcd", 0777);
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tfp->open("vcd/vlt_dump.vcd"); // Open the dump file
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}
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#endif
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// initial conditions in order to generate appropriate edges on
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// reset
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mkTop_HW_Side->RST_N = 1;
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mkTop_HW_Side->CLK = 0;
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while (! Verilated::gotFinish ()) {
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if (main_time == 2) {
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mkTop_HW_Side->RST_N = 0; // assert reset
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}
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else if (main_time == 7) {
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mkTop_HW_Side->RST_N = 1; // Deassert reset
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}
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// Toggle clock
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if ((main_time % 10) == 5) {
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mkTop_HW_Side->CLK = 1;
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}
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else if ((main_time % 10) == 0) {
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mkTop_HW_Side->CLK = 0;
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}
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#if VM_TRACE
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if (tfp)
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tfp->dump(main_time);
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#endif
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mkTop_HW_Side->eval ();
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main_time++;
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}
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mkTop_HW_Side->final (); // Done simulating
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// Close trace if opened
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#if VM_TRACE
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if (tfp) { tfp->close(); }
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#endif
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delete mkTop_HW_Side;
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mkTop_HW_Side = NULL;
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exit (0);
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}
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