If DRAM latency is too high and the cache is performing frequent writes, it would be possible to overflow this counter, which means we don't rate limit, the cache could erroneously believe it's safe to do I/O accesses/cache refills/page table walks, and the cache would block due to the guard on decr when it finally gets enough write responses back. We should block the incr method to automatically stall the cache until it receives a new write response.
64 lines
1.6 KiB
Plaintext
64 lines
1.6 KiB
Plaintext
// Copyright (c) 2015-2019 Bluespec, Inc., All Rights Reserved
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// Author: Rishiyur S. Nikhil
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// A "credit counter" which can be incremented and decremented concurrently.
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package CreditCounter;
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// ================================================================
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// BSV library imports
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import Cur_Cycle :: *;
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// ================================================================
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// Interface
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interface CreditCounter_IFC #(numeric type w);
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// Current value of internal count
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method UInt #(w) value;
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// Increment internal count
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method Action incr;
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// Decrement internal count
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method Action decr;
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// Clear internal count to 0
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method Action clear;
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endinterface
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// ================================================================
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// Module implementation
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// Scheduling: value < incr < decr < clear
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module mkCreditCounter (CreditCounter_IFC #(w));
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Reg #(UInt #(w)) crg [3] <- mkCReg (3, 0);
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method UInt #(w) value = crg [1];
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method Action incr if (crg [0] != maxBound);
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if (crg [0] == maxBound) begin
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$display ("%0d: ERROR: CreditCounter: overflow", cur_cycle);
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$finish (1); // Assertion failure
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end
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crg [0] <= crg [0] + 1;
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endmethod
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method Action decr () if (crg [1] != 0);
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if (crg [1] == 0) begin
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$display ("%0d: ERROR: CreditCounter: underflow", cur_cycle);
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$finish (1); // Assertion failure
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end
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crg [1] <= crg [1] - 1;
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endmethod
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method Action clear;
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crg [2] <= 0;
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endmethod
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endmodule
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// ================================================================
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endpackage
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